(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 (cid:1) features Compact Converter Solution in UltraSmall (cid:1) 10-pin MSOP With Only Four External Regulated 3.3-V Output Voltage With up to Capacitors Required 100-mA Output Current From a 1.8-V to (cid:1) Evaluation Module Available 3.6-V Input Voltage (cid:1) (TPS60200EVM-145) Less Than 5-mV Output Voltage Ripple (PP) Achieved With Push-Pull Topology applications (cid:1) Integrated Low-Battery and Power-Good (cid:1) Replaces DC/DC Converters With Inductors Detector (cid:1) in Battery Powered Applications Like: Switching Frequency Can Be Synchronized − Two Battery Cells to 3.3-V Conversion to External Clock Signal − MP3 Portable Audio Players (cid:1) Extends Battery Usage With up to 90% − Battery-Powered Microprocessor Efficiency and 35-µA Quiescent Supply Systems Current − Backup-Battery Boost Converters (cid:1) Easy-to-Design, Low Cost, Low EMI Power − PDA’s, Organizers, and Cordless Phones Supply Since No Inductors Are Used − Handheld Instrumentation (cid:1) 0.05-µA Shutdown Current, Battery is − Glucose Meters and Other Medical Isolated From Load in Shutdown Mode Instruments · description The TPS6020x step-up, regulated charge pumps generate a 3.3-V ±4% output voltage from a 1.8-V to 3.6-V input voltage. The devices are typically powered by two Alkaline, NiCd, or NiMH battery cells and operate down to a minimum supply voltage of 1.6 V. Continuous output current is a minimum of 100 mA from a 2-V input. Only four external capacitors are needed to build a complete low-ripple dc/dc converter. The push-pull operating mode of two single-ended charge pumps assures the low output voltage ripple, as current is continuously transferred to the output. TPS60204 INPUT TPS60204 OUTPUT PEAK OUTPUT CURRENT 1.6 V to 3.6 V 7 5 3.3 V, 100 mA vs IN OUT INPUT VOLTAGE 2.C2i µF R1 1 LBI R3 2C.2o µF 350 10 LBO 300 R2 A Low Battery m 4 C1+ C2+ 6 Warning ent − 250 r 1C µ1F 39 C1− C2− 8 1C µ2F ut Cur 200 p EN ut 150 OFF/ON GND k O 2 ea 100 P − O 50 I Figure 1. Typical Application Circuit With Low-Battery Warning 0 1.6 2.0 2.4 2.8 3.2 3.6 VI − Input Voltage − V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:2)(cid:10)(cid:23)(cid:16)(cid:13)(cid:26)(cid:1)(cid:25)(cid:23)(cid:30) (cid:16)(cid:15)(cid:1)(cid:15) (cid:31)!"#$(cid:22)%&(cid:31)#! (cid:31)’ ()$$*!& %’ #" +),-(cid:31)(%&(cid:31)#! .%&*(cid:18) Copyright  2001, Texas Instruments Incorporated (cid:2)$#.)(&’ (#!"#$(cid:22) &# ’+*((cid:31)"(cid:31)(%&(cid:31)#!’ +*$ &/* &*$(cid:22)’ #" (cid:1)*0%’ (cid:25)!’&$)(cid:22)*!&’ ’&%!.%$. 1%$$%!&2(cid:18) (cid:2)$#.)(&(cid:31)#! +$#(*’’(cid:31)!3 .#*’ !#& !*(*’’%$(cid:31)-2 (cid:31)!(-).* &*’&(cid:31)!3 #" %-- +%$%(cid:22)*&*$’(cid:18) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 description (continued) The devices operate in the newly developed LinSkip mode. In this operating mode, the device switches seamlessly from the power saving pulse-skip mode at light loads to the low-noise constant-frequency, linear-regulation mode once the output current exceeds the LinSkip threshold of about 7 mA. Even in pulse-skip mode, the output ripple is maintained at a very low level because the output resistance of the charge pump is still regulated. Three operating modes can be programmed using the EN pin. EN = low disables the device, shuts down all internal circuits, and disconnects the output from the input. EN = high enables the device and programs it to run from the internal oscillator. The devices operate synchronized to an external clock signal if EN is clocked; thus, switching harmonics can be controlled and minimized. The devices include a low-battery detector that issues a warning if the battery voltage drops below a user-defined threshold voltage, or a power-good detector that goes active when the output voltage reaches about 90% of its nominal value. Device options with either a low-battery or power good detector are available. This dc/dc converter requires no inductors, therefore, EMI of the system is reduced to a minimum. It is available in the small 10-pin MSOP package (DGS). DGS PACKAGES TPS60204 TPS60205 LBI 1 10 LBO GND 1 10 PG GND 2 9 EN GND 2 9 EN C1− 3 8 C2− C1− 3 8 C2− C1+ 4 7 IN C1+ 4 7 IN OUT 5 6 C2+ OUT 5 6 C2+ ACTUAL SIZE 3,05 mm x 4,98 mm AVAILABLE OPTIONS MARKING OUTPUT OUTPUT TA PART NUMBER† DGS CURRENT VOLTAGE DEVICE FEATURES PACKAGE (mA) (V) TPS60204DGS AFB 100 3.3 Low-battery detector −−4400°°CC ttoo 8855°°CC TPS60205DGS AFC 100 3.3 Power-good detector †The DGS package is available taped and reeled. Add R suffix to device type (e.g., TPS60204DGSR) to order quantities of 2500 devices per reel. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 functional block diagrams TPS60204 with low-battery detector Charge Pump 1 0° IN Oscillator 180° C1+ C1 C1− EN Charge Pump 2 Control Circuit C2+ _ C2 C2− + + OUT VREF − Shutdown/ _ Start-Up _ LBI Control + + + − 0.8 x VI + VREF − GND LBO TPS60205 with power-good detector 0° Charge Pump 1 IN Oscillator 180° C1+ C1 C1− EN Charge Pump 2 Control Circuit C2+ _ C2− C2 + + OUT VREF − Shutdown/ _ Start-Up _ Control + + + − 0.8 x VI + VREF − GND PG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. C1+ 4 Positive terminal of the flying capacitor C1 C1− 3 Negative terminal of the flying capacitor C1 C2+ 6 Positive terminal of the flying capacitor C2 C2− 8 Negative terminal of the flying capacitor C2 Device-enable input. Three operating modes can be programmed with the EN pin. − EN = Low disables the device. Output and input are isolated in the shutdown. EN 9 I − EN = High lets the device run from the internal oscillator. − If an external clock signal is applied to the EN pin, the device is in syncmode and runs synchronized at the frequency of the external clock signal. GND 2 Ground IN 7 I Supply input. Bypass IN to GND with a capacitor of the same size as Co. Low-battery detector input for the TPS60204. A low-battery warning is generated at the LBO pin when the voltage LBI/GND 1 I on LBI drops below the threshold of 1.18 V. Connect LBI to GND if the low-battery detector function is not used. For the TPS60205, this pin has to be connected to ground (GND pin). Open-drain low-battery detector output for the TPS60204. This pin is pulled low if the voltage on LBI drops below the threshold of 1.18 V. A pullup resistor should be connected between LBO and OUT or any other logic supply rail that is lower than 3.6 V. LBO/PG 10 O Open-drain power-good detector output for the TPS60205. As soon as the voltage on OUT reaches about 90% of it is nominal value this pin goes active high. A pullup resistor should be connected between PG and OUT or any other logic supply rail that is lower than 3.6 V. OUT 5 O Regulated 3.3-V power output. Bypass OUT to GND with the output filter capacitor Co. detailed description operating principle The TPS6020x charge pumps provide a regulated 3.3-V output from a 1.8-V to 3.6-V input. They deliver up to 100-mA load current while maintaining the output at 3.3 V ±4%. Designed specifically for space critical battery powered applications, the complete converter requires only four external capacitors. The device is using the push-pull topology to achieve lowest output voltage ripple. The converter is also optimized for smallest board space. It makes use of small sized capacitors, with the highest output current rating per output capacitance and package size. The TPS6020x circuits consist of an oscillator, a 1.18-V voltage reference, an internal resistive feedback circuit, an error amplifier, two charge pump power stages with high current MOSFET switches, a shutdown/start-up circuit, and a control circuit (see functional block diagrams). push-pull operating mode The two single-ended charge pump power stages operate in the so-called push-pull operating mode, i.e., they operate with a 180°C phase shift. Each single-ended charge pump transfers charge into its transfer capacitor (C1 or C2) in one half of the period. During the other half of the period (transfer phase), the transfer capacitor is placed in series with the input to transfer its charge to C . While one single-ended charge pump is in the charge o phase, the other one is in the transfer phase. This operation assures an almost constant output current which ensures a low output ripple. If the clock were to run continuously, this process would eventually generate an output voltage equal to two times the input voltage (hence the name voltage doubler). In order to provide a regulated fixed output voltage of 3.3V, the TPS6020x devices use either pulse-skip or constant-frequency linear-regulation control mode. The mode is automatically selected based on the output current. If the load current is below the LinSkip current threshold, it switches into the power-saving pulse-skip mode to boost efficiency at low output power. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 detailed description (continued) constant-frequency mode When the output current is higher then the LinSkip current threshold, the charge pump runs continuously at the switching frequency f . The control circuit, fed from the error amplifier, controls the charge on C1 and C2 (OSC) by controlling the gates and hence the r of the integrated MOSFETs. When the output voltage decreases, DS(ON) the gate drive increases, resulting in a larger voltage across C1 and C2. This regulation scheme minimizes output ripple. Since the device switches continuously, the output signal contains well-defined frequency components, and the circuit requires smaller external capacitors for a given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light loads. For this reason, the device switches seamlessly into the pulse-skip mode when the output current drops below the LinSkip current threshold. pulse-skip mode The regulator enters the pulse-skip mode when the output current is lower than the LinSkip current threshold of 7 mA. In the pulse-skip mode, the error amplifier disables switching of the power stages when it detects an output voltage higher than 3.3 V. The controller skips switching cycles until the output voltage drops below 3.3V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again. A 30-mV output voltage offset is introduced in this mode. The pulse-skip regulation mode minimizes operating current because it does not switch continuously and deactivates all functions except the voltage reference and error amplifier when the output is higher than 3.3V. Even in pulse-skip mode the r of the MOSFETs is controlled. This way the energy per switching cycle that DS(ON) is transferred by the charge pump from the input to the output is limited to the minimum that is necessary to sustain a regulated output voltage, with the benefit that the output ripple is kept to a minimum. When switching is disabled from the error amplifier, the load is also isolated from the input. start up and shutdown During start-up, i.e. when EN is set from logic low to logic high, the output capacitor is directly connected to IN and charged up with a limited current until the output voltage V reaches 0.8 × V. When the start-up comparator O I detects this limit, the converter begins switching. This precharging of the output capacitor guarantees a short start-up time. In addition, the inrush current into an empty output capacitor is limited. The converter can start into a full load, which is defined by a 33-Ω or 66-Ω resistor, respectively. Driving EN low disables the converter. This disables all internal circuits and reduces the supply current to only 0.05 µA. The device exits shutdown once EN is set high. When the device is disabled, the load is isolated from the input. This is an important feature in battery operated products because it extends the products shelf life. synchronization to an external clock signal The operating frequency of the charge pump is limited to 400 kHz in order to avoid interference in the sensitive 455-kHz IF band. The device can either run from the integrated oscillator, or an external clock signal can be used to drive the charge pump. The maximum frequency of the external clock signal is 800 kHz. The switching frequency used internally to drive the charge pump power stages is half of the external clock frequency. The external clock signal is applied to the EN pin. The device will switch off if the signal on EN is hold low for more than 10 µs. When the load current drops below the LinSkip current threshold, the devices will enter the pulse-skip mode but stay synchronized to the external clock signal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 detailed description (continued) low-battery detector (TPS60204) The low-battery comparator trips at 1.18 V ±4% when the voltage on pin LBI ramps down. The voltage V (TRIP) at which the low-battery warning is issued can be adjusted with a resistive divider as shown in Figure 2. The sum of resistors R1 and R2 is recommended to be in the 100-kΩ to 1-MΩ range. When choosing R1 and R2, be aware of the input leakage current into the LBI pin. LBO is an open drain output. An external pullup resistor to OUT, or any other voltage rail in the appropriate range, in the 100-kΩ to 1-MΩ range is recommended. During start-up, the LBO output signal is invalid for the first 500µs. LBO is high impedance when the device is disabled. If the low-battery comparator function is not used, connect LBI to ground and leave LBO unconnected. The low-battery detector is disabled when the device is switched off. VO IN VBAT R3 R1 (cid:2) (cid:4) LBO _ LBI V(TRIP)(cid:1)1.18V 1(cid:3)RR12 + R2 + VREF − Figure 2. Programming of the Low-Battery Comparator Trip Voltage A 100-nF ceramic capacitor should be connected in parallel to R2 if large line transients are expected. These voltage drops can inadvertently trigger the low-battery comparator and produce a wrong low-battery warning signal at the LBO pin. Formulas to calculate the resistive divider for low-battery detection, with V = 1.13 V to 1.23 V and the sum LBI of resistors R1 and R2 equal 1 MΩ: V R2(cid:1)1M(cid:1)(cid:5) LBI (1) V Bat R1(cid:1)1M(cid:1)(cid:6)R2 (2) Formulas to calculate the minimum and maximum battery voltage: R1 (cid:3)R2 (min) (max) V (cid:1)V (cid:5) (3) Bat(min) LBI(min) R2 (max) R1 (cid:3)R2 (max) (min) V (cid:1)V (cid:5) (4) Bat(max) LBI(max) R2 (min) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 detailed description (continued) Table 1. Recommended Values for the Resistive Divider From the E96 Series (±1%) VIN/V R1/kΩ R2/kΩ VTRIP(MIN)/V VTRIP(MAX)/V 1.6 267 750 1.524 1.677 1.7 301 681 1.620 1.785 1.8 340 649 1.710 1.887 1.9 374 619 1.799 1.988 2.0 402 576 1.903 2.106 power-good detector (TPS60205) The power-good output is an open-drain output that pulls low when the output is out of regulation. When the output rises to within 90% of its nominal voltage, the power-good output is released. Power-good is high impedance in shutdown. In normal operation, an external pullup resistor must be connected between PG and OUT, or any other voltage rail in the appropriate range. The resistor should be in the 100-kΩ to 1-MΩ range. If the PG output is not used, it should remain unconnected. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range: IN, OUT, EN, LBI, LBO, PG to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.6 V C1+, C2+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (V + 0.3 V) O C1−, C2− to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (V + 0.3 V) I Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table Continuous output current TPS60204, TPS60205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C stg Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C J †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING DGS 424 mW 3.4 mW/(cid:2)C 187 mW 136 mW The thermal resistance junction to ambient of the DGS package is RTH−JA = 294°C/W. recommended operating conditions MIN NOM MAX UNIT Input voltage range, VI 1.6 3.6 V Input capacitor, Ci 2.2 µF Flying capacitors, C1, C2 1 µF Output capacitor, Co 2.2 µF Operating junction temperature, TJ −40 125 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 electrical characteristics at Ci = 2.2 µF, C1 = C2 = 1 µF, CO = 2.2 µF, TA = −40°C to 85°C, VI = 2.4 V, EN = V (unless otherwise noted) I PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO(MAX) Maximum continuous output current VI = 2 V 100 mA 1.6 V < VI < 1.8 V, 0 < IO < 0.25 × IO(MAX) 3 1.8 V < VI < 2 V, 0 < IO < 0.5 × IO(MAX) 3.17 3.43 VVOO OOuuttppuutt vvoollttaaggee VV 2 V < VI < 3.3 V, 0 < IO < IO(MAX) 3.17 3.43 3.3 V < VI < 3.6 V, 0 < IO < IO(MAX) 3.17 3.47 VPP Output voltage ripple IO = IO(MAX) 5 mVPP I(Q) Quiescent current (no-load input current) IO = 0 mA, VI = 1.8 V to 3.6 V 35 70 µµAA I(SD) Shutdown supply current EN = 0 V 0.05 1 f(OSC) Internal switching frequency 200 300 400 kkHHzz f(SYNC) External clock signal frequency 400 600 800 External clock signal duty cycle 30% 70% VIL EN input low voltage VI = 1.6 V to 3.6 V 0.3 × VI VV VIH EN input high voltage VI = 1.6 V to 3.6 V 0.7 × VI Ilkg(EN) EN input leakage current EN = 0 V or VI 0.01 0.1 µA EN is set from VI to GND, Output capacitor auto discharge time 0.6 ms Time until VO < 0.5 V OOuuttppuutt lleeaakkaaggee ccuurrrreenntt iinn sshhuuttddoowwnn EN = 0 V, TA = −40 to 85°C 5 µµAA EN = 0 V, TA ≤ 65°C 3 LinSkip threshold VI = 2.2 V 7 mA Output load regulation 10 mA < IO < IO(MAX); TA = 25°C 0.01 %/mA 2 V < VI < 3.3 V, IO = 0.5 xIO(MAX), Output line regulation 0.6 %/V TA = 25°C I(SC) Short circuit current VI = 2.4 V, VO = 0 V 60 mA electrical characteristics for low-battery comparator of devices TPS60204 at T = −40°C to 85°C, A V = 2.4 V and EN = V (unless otherwise noted) I I PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(LBI) LBI trip voltage VI = 1.6 V to 2.2 V, Tc = 0°C to 70°C 1.13 1.18 1.23 V LBI trip voltage hysteresis For rising voltage at LBI 10 mV II(LBI) LBI input current V(LBI) = 1.3 V 2 50 nA VO(LBO) LBO output voltage low V(LBI) = 0 V, I(LBO) = 1 mA 0.4 V Ilkg(LBO) LBO leakage current V(LBI) = 1.3 V, V(LBO) = 3.3 V 0.01 0.1 µA NOTE: During start-up of the converter the LBO output signal is invalid for the first 500 µs. electrical characteristics for power-good comparator of devices TPS60205 at T = −40°C to 85°C, A V = 2.4 V and EN = V (unless otherwise noted) I I PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(PG) Power-good trip voltage Tc = 0°C to 70°C 0.87 × VO 0.91 × VO 0.95 × VO V Vhys(PG) Power-good trip voltage hysteresis VO decreasing, Tc = 0°C to 70°C 1% VO(PG) Power-good output voltage Low VO = 0 V, I(PG) = 1 mA 0.4 V Ilkg(PG) Power-good leakage current VO = 3.3 V, V(PG) = 3.3 V 0.01 0.1 µA NOTE: During start-up of the converter the PG output signal is invalid for the first 500 µs. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 TYPICAL CHARACTERISTICS Table of Graphs FIGURES vs Output current (TPS60204, TPS60205) 3 η EEffffiicciieennccyy vs Input voltage 4 IQ Quiescent supply current vs Input voltage 5 vs Output current 6 VVOO OOuuttppuutt vvoollttaaggee vs Input voltage 7 VO Output voltage ripple vs Time 8, 9, 10 Start-up timing 11 Load transient response 12, 13 IO Peak output current vs Input voltage 14 NOTE: All typical characteristics were measured using the typical application circuit of Figure 14 (unless otherwise noted). TPS60204, TPS60205 EFFICIENCY EFFICIENCY vs vs OUTPUT CURRENT INPUT VOLTAGE 100 100 90 90 80 80 70 70 % % − 60 − 60 ncy 50 VI = 1.8 V ncy 50 cie VI = 2.4 V cie IO = 50 mA Effi 40 Effi 40 VI = 2.7 V 30 30 20 20 10 10 0 0 0.1 1 10 100 1000 1.6 2.0 2.4 2.8 3.2 3.6 IO − Output Current − mA VI − Input Voltage − V Figure 3 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 TYPICAL CHARACTERISTICS QUIESCENT SUPPLY CURRENT OUTPUT VOLTAGE vs vs INPUT VOLTAGE OUTPUT CURRENT 40 3.5 38 IO = 0 mA A 36 3.4 µ − VI = 3.6 V Current 3342 ge − V 3.3 pply 30 Volta 3.2 VI = 1.8 V Su ut cent 28 Outp 3.1 VI = 2.7 V es 26 − Qui VO VI = 2.4 V − Q) 24 3.0 ( 22 I 20 2.9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1 10 100 1000 VI − Input Voltage − V IO − Output Current − mA Figure 5 Figure 6 OUTPUT VOLTAGE OUTPUT VOLTAGE RIPPLE vs vs INPUT VOLTAGE TIME 3.4 3.38 3.36 VI = 2.4 V 3.3 V IO = 1 mA − ge − V 3.2 1 mA e Ripple 33..3342 a g Volt 3.1 100 mA 50 mA olta Output 3.0 utput V 33..3208 − VO 2.9 − OVO 3.26 2.8 3.24 2.7 3.22 1.6 2.0 2.4 2.8 3.2 3.6 0 5 10 15 20 25 30 35 40 45 50 VI − Input Voltage − V t − Time − µs Figure 7 Figure 8 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE RIPPLE OUTPUT VOLTAGE RIPPLE vs vs TIME TIME 3.38 3.38 VI = 2.4 V VI = 2.4 V 3.36 IO = 10 mA 3.36 IO = 100 mA V V ple − 3.34 ple − 3.34 p p Ri 3.32 Ri 3.32 ge ge Volta 3.30 Volta 3.30 ut ut utp 3.28 utp 3.28 O O − − O 3.26 O 3.26 V V 3.24 3.24 3.22 3.22 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 t − Time − µs t − Time − µs Figure 9 Figure 10 START-UP TIMING LOAD TRANSIENT RESPONSE 3.5 1400 V − e VI = 2.4 V 3 VO VI = 2.4 V 1200 oltag 3.30 V 2.5 1000 ut 3.28 V p oltage − 2 II 800 ent − mA V− OutO 3.26 V r − Output O1.51 EN 460000 − Input Cur ent − mA 3.24 V 0.5 200 II urr100 mA C ut p 0 0 ut O − O10 mA 0 50 100 150 200 250 300 350 400 450 500 I 0 50 100 150 200 250 300 350 400 450 500 t − Time − µs t − Time − µs Figure 11 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 TYPICAL CHARACTERISTICS PEAK OUTPUT CURRENT vs LINE TRANSIENT RESPONSE INPUT VOLTAGE V 350 e − IO = 50 mA g a 300 olt A V m utput 3.32 nt − 250 − O 3.30 urre O C 200 V 3.28 put V Out 150 − 3.26 k e ea oltag 2.8 V − PO 100 V I put 50 n − I VI2.2 V 0 0 1 2 3 4 5 6 7 8 9 10 1.6 2.0 2.4 2.8 3.2 3.6 t − Time − ms VI − Input Voltage − V Figure 13 Figure 14 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 APPLICATION INFORMATION capacitor selection The TPS6020x devices require only four external capacitors to achieve a very low output voltage ripple. The capacitor values are closely linked to the required output current. Low ESR (<0.1 Ω) capacitors should be used at input and output. In general, the transfer capacitors (C1 and C2) will be the smallest; a 1-µF value is recommended for maximum load operation. With smaller capacitor values, the maximum possible load current is reduced and the LinSkip threshold is lowered. The input capacitor improves system efficiency by reducing the input impedance. It also stabilizes the input current of the power source. The input capacitor should be chosen according to the power supply used and the distance from the power source to the converter IC. C is recommended to be about two to four times as large i as the flying capacitors C1 and C2. The output capacitor (C ) should be at minimum the size of the input capacitor. The minimum required o capacitance is 2.2 µF. Larger values will improve the load transient performance and will reduce the maximum output ripple voltage. Only ceramic capacitors are recommended for input, output, and flying capacitors. Depending on the material used to manufacture them, ceramic capacitors might lose their capacitance over temperature and voltage. Ceramic capacitors of type X7R or X5R material will keep their capacitance over temperature and voltage, whereas Z5U- or Y5V-type capacitors will decrease in capacitance. Table 2 lists the recommended capacitor values. Table 2. Recommended Capacitor Values (Ceramic X5R and X7R) FLYING INPUT OUTPUT OUTPUT VOLTAGE OUTPUT VOLTAGE LOAD CURRENT, CAPACITORS, CAPACITOR, CAPACITOR, RIPPLE IN LINEAR MODE, RIPPLE IN SKIP MODE, IL (mA) C1/C2 Ci Co V(P-P) V(P-P) (µF) (µF) (µF) (mV) (mV) 0−100 1 2.2 2.2 3 20 0−100 1 4.7 4.7 3 10 0−100 1 2.2 10 3 7 0−100 2.2 4.7 4.7 3 10 0−50 0.47 2.2 2.2 3 20 0−25 0.22 2.2 2.2 5 15 0−10 0.1 2.2 2.2 5 15 Table 3. Recommended Capacitor Types MANUFACTURER PART NUMBER SIZE CAPACITANCE TYPE TTaaiiyyoo YYuuddeenn UMK212BJ104MG 0805 0.1 µF Ceramic EMK212BJ224MG 0805 0.22 µF Ceramic EMK212BJ474MG 0805 0.47 µF Ceramic LMK212BJ105KG 0805 1 µF Ceramic LMK212BJ225MG 0805 2.2 µF Ceramic EMK316BJ225KL 1206 2.2 µF Ceramic LMK316BJ475KL 1206 4.7 µF Ceramic JMK316BJ106ML 1206 10 µF Ceramic AAVVXX 0805ZC105KAT2A 0805 1 µF Ceramic 1206ZC225KAT2A 1206 2.2 µF Ceramic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 APPLICATION INFORMATION Table 4. Recommended Capacitor Manufacturers MANUFACTURER CAPACITOR TYPE INTERNET SITE Taiyo Yuden X7R/X5R ceramic http://www.t−yuden.com/ AVX X7R/X5R ceramic http://www.avxcorp.com/ INPUT OUTPUT TPS60204 1.6 V to 3.6 V 7 5 3.3 V, 100 mA IN OUT 2.2µFCi R1 1 LBI R3 C2.o2µF 10 LBO R2 4 6 Low Battery C1+ C2+ Warning C1 1µF 3 C1− C2− 8 C2 9 1µF EN OFF/ON GND 2 Figure 15. Typical Operating Circuit TPS60204 With Low-Battery Detector INPUT OUTPUT TPS60205 1.6 V to 3.6 V 7 5 3.3 V, 100 mA IN OUT Co Ci R1 2.2µF 2.2µF 10 PG 4 6 Power-Good C1+ C2+ Signal C1 1µF 3 C1− C2− 8 C2 9 1µF EN OFF/ON GND 1,2 Figure 16. Typical Operating Circuit TPS60205 With Power-Good Detector 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 APPLICATION INFORMATION power dissipation The power dissipated in the TPS6020x devices depends mainly on input voltage and output current and is approximated by: (cid:2) (cid:4) P (cid:1) I x 2xV (cid:6) V forI (cid:7) I (5) (DISS) O I O (Q) O By observing equation 5, it can be seen that the power dissipation is worst for highest input voltage V and I highest output current I . For an input voltage of 3.6 V and an output current of 100 mA the calculated power O dissipation P is 390 mW. This is also the point where the charge pump operates with its lowest efficiency. (DISS) With the recommended maximum junction temperature of 125°C and an assumed maximum ambient operating temperature of 85°C, the maximum allowed thermal resistance junction to ambient of the system can be calculated. T (cid:6)T R (cid:1) J(MAX) A(cid:1)125°C(cid:6)85°C(cid:1)102°C(cid:8)W (6) (cid:2)JA(max) P 390mW DISS(max) P must be less than that allowed by the package rating. The thermal resistance junction to ambient of the DISS used 10-pin MSOP is 294°C/W for an unsoldered package. The thermal resistance junction to ambient with the IC soldered to a printed circuit using a board layout as described in the application information section, the RΘJA is typically 200°C/W, which is higher than the maximum value calculated above. However, in a battery powered application, both V and T will typically be lower than the worst case ratings used in equation 6 , and I A power dissipation should not be a problem in most applications. layout and board space Careful board layout is necessary due to the high transient currents and switching frequency of the converter. All capacitors should be placed in close proximity to the device. A PCB layout proposal for a one-layer board is given in Figure 17. There is no specific EVM available for the TPS60204. However, the TPS60200EVM−145 can be used to evaluate the device. The evaluation module for the TPS60200 can be ordered under product code TPS60200EVM−145. The EVM uses the layout shown in Figure 17. All components including the pins are shown. The EVM is built so that it can be connected to a 14-pin dual inline socket, therefore, the space needed for the IC, the external parts, and eight pins is 17,9 mm x 10,2 mm = 182,6 mm2. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 APPLICATION INFORMATION Figure 17. Recommended Component Placement and Board Layout Table 5. Component Identification IC1 TPS60204 C1, C2 Flying capacitors C3 Input capacitors C4 Output capacitors C5 Stabilization capacitor for LBI R1, R2 Resistive divider for LBI R3 Pullup resistor for LBO R4 Pullup resistor for EN Capacitor C5 should be included if large line transients are expected. This capacitor suppresses toggling of the LBO due to these line changes. device family products Other charge pump dc-dc converters in this family are: Table 6. Product Identification PART NUMBER DESCRIPTION TPS60100 2-cell to regulated 3.3 V, 200-mA low-noise charge pump TPS60101 2-cell to regulated 3.3 V, 100-mA low-noise charge pump TPS60110 3-cell to regulated 5.0 V, 300-mA low-noise charge pump TPS60111 3-cell to regulated 5.0 V, 150-mA low-noise charge pump TPS60120 2-cell to regulated 3.3 V, 200-mA high efficiency charge pump with low battery comparator TPS60121 2-cell to regulated 3.3 V, 200-mA high efficiency charge pump with power-good comparator TPS60122 2-cell to regulated 3.3 V, 100-mA high efficiency charge pump with low battery comparator TPS60123 2-cell to regulated 3.3 V, 100-mA high efficiency charge pump with power-good comparator TPS60130 3-cell to regulated 5.0 V, 300-mA high efficiency charge pump with low battery comparator TPS60131 3-cell to regulated 5.0 V, 300-mA high efficiency charge pump with power-good comparator TPS60132 3-cell to regulated 5.0 V, 150-mA high efficiency charge pump with low battery comparator TPS60133 3-cell to regulated 5.0 V, 150-mA high efficiency charge pump with power-good comparator TPS60140 2-cell to regulated 5.0 V, 100-mA charge pump voltage tripler with low battery comparator TPS60141 2-cell to regulated 5.0 V, 100-mA charge pump voltage tripler with power-good comparator 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:7)(cid:8) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:5)(cid:9) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:1)(cid:11)(cid:16) (cid:17)(cid:18)(cid:17)(cid:19)(cid:20)(cid:8) (cid:21)(cid:5)(cid:5)(cid:19)(cid:22)(cid:15) (cid:14)(cid:23)(cid:24)(cid:19)(cid:10)(cid:25)(cid:2)(cid:2)(cid:14)(cid:11) (cid:26)(cid:27)(cid:15)(cid:10)(cid:12)(cid:11) (cid:2)(cid:13)(cid:28)(cid:2) (cid:14)(cid:23)(cid:24) (cid:2)(cid:23)(cid:24)(cid:11)(cid:10) (cid:16)(cid:26)(cid:29)(cid:16)(cid:26) (cid:26)(cid:23)(cid:30)(cid:20)(cid:11)(cid:10)(cid:1)(cid:11)(cid:10)(cid:3) SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001 MECHANICAL DATA DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE 0,27 0,50 0,08 M 0,17 10 6 0,15 NOM 3,05 4,98 2,95 4,78 Gage Plane 0,25 1 5 0°−(cid:1)6° 0,69 3,05 0,41 2,95 Seating Plane 0,15 1,07 MAX 0,10 0,05 4073272/B 08/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-187 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty TPS60204DGS ACTIVE MSOP DGS 10 80 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60204DGSG4 ACTIVE MSOP DGS 10 80 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60204DGSR ACTIVE MSOP DGS 10 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60204DGSRG4 ACTIVE MSOP DGS 10 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60205DGS ACTIVE MSOP DGS 10 80 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60205DGSG4 ACTIVE MSOP DGS 10 80 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60205DGSR ACTIVE MSOP DGS 10 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) TPS60205DGSRG4 ACTIVE MSOP DGS 10 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) TPS60204DGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS60205DGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS60204DGSR MSOP DGS 10 2500 340.5 338.1 20.6 TPS60205DGSR MSOP DGS 10 2500 340.5 338.1 20.6 PackMaterials-Page2

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