Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 TPS54622 4.5-V to 17-V Input, 6-A Synchronous Step-Down SWIFT™ Converter With Hiccup Protection 1 Features 3 Description • Integrated26-mΩand19-mΩ MOSFETs The TPS54622 device in thermally enhanced 3.5-mm 1 × 3.5-mm VQFN package is a full-featured 17-V, 6-A • SplitPowerRail:1.6Vto17VonPVIN synchronous step-down converter optimized for small • 200-kHzto1.6-MHzSwitchingFrequency designs through high efficiency and integrating the • SynchronizestoExternalClock high-side and low-side MOSFETs. Further space savings are achieved through current mode control, • 0.6V±1%VoltageReferenceOvertemperature which reduces component count, and by selecting a • HiccupCurrentLimit high switching frequency, reducing the footprint of the • MonotonicStart-UpIntoPrebiasedOutputs inductor. • –40°Cto150°COperatingJunctionTemperature The output voltage start-up ramp is controlled by the Range SS/TR pin, which allows operation as either a stand- • AdjustableSlowStartandPowerSequencing alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring • PowerGoodOutputMonitorforUndervoltageand theenableandtheopen-drainpowergoodpins. Overvoltage Cycle-by-cycle current limiting on the high-side FET • AdjustableInputUndervoltageLockout protects the device in overload situations and is • ForSWIFT™Documentation,visit enhanced by a low-side sourcing current limit that http://www.ti.com/swift prevents current runaway. There is also a low-side • CreateaCustomDesignUsingtheTPS54622 sinking current limit that turns off the low-side WiththeWEBENCH®PowerDesigner MOSFET to prevent excessive reverse current. Hiccup protection is triggered if the overcurrent 2 Applications condition has persisted for longer than the preset time. Thermal hiccup protection disables the device • High-DensityDistributedPowerSystems when the die temperature exceeds the thermal • High-PerformancePoint-of-LoadRegulation shutdown temperature and enables the part again afterthebuilt-inthermalshutdownhiccuptime. • Broadband,Networking,andOptical CommunicationsInfrastructure DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) TPS54622 VQFN(14) 3.50mm×3.50mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic EfficiencyvsLoadCurrent TPS54622 VIN CBOOT 100 VIN BOOT 95 LO VOUT 90 EN PH 85 VIN = 8 V PWRGD VSENSE R1 Efficiency-% 778050 VIN = 1V2IN V = 17 V SS RT/CLK 65 R2 R3 COMP 60 GND 55 PowerPad CSS RRT C1 500 1 2 3 4 5 6 C2 Output Current -A Copyright ' 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 23 2 Applications........................................................... 1 8.1 ApplicationInformation............................................23 3 Description............................................................. 1 8.2 TypicalApplication .................................................23 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 32 5 PinConfigurationsandFunctions....................... 4 10 Layout................................................................... 32 6 Specifications......................................................... 5 10.1 LayoutGuidelines.................................................32 6.1 AbsoluteMaximumRatings .....................................5 10.2 LayoutExamples...................................................33 6.2 ESDRatings..............................................................5 10.3 EstimatedCircuitArea..........................................34 6.3 RecommendedOperatingConditions.......................5 11 DeviceandDocumentationSupport................. 35 6.4 ThermalInformation..................................................6 11.1 DeviceSupport......................................................35 6.5 ElectricalCharacteristics...........................................6 11.2 DocumentationSupport........................................35 6.6 TypicalCharacteristics..............................................8 11.3 ReceivingNotificationofDocumentationUpdates35 7 DetailedDescription............................................ 11 11.4 CommunityResources..........................................35 7.1 Overview.................................................................11 11.5 Trademarks...........................................................35 7.2 FunctionalBlockDiagram.......................................12 11.6 ElectrostaticDischargeCaution............................36 7.3 FeatureDescription.................................................12 11.7 Glossary................................................................36 7.4 DeviceFunctionalModes........................................20 12 Mechanical,Packaging,andOrderable Information........................................................... 36 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(December2016)toRevisionF Page • AddedtopnaviconforTIDesign .......................................................................................................................................... 1 • AddedlinksforWEBENCHonpage1andinApplicationandImplementationandDeviceandDocumentation Supportsections .................................................................................................................................................................... 1 • ChangedR valuefrom"47.2"to"40.1" ............................................................................................................................. 6 θJA • ChangedR valuefrom"64.8"to"34.4" .......................................................................................................................... 6 θJCtop • ChangedR valuefrom"14.4"to"11.4" ............................................................................................................................. 6 θJB • Changedψ valuefrom"14.7"to"11.4" ............................................................................................................................... 6 JB • ChangedR valuefrom"3.2"to"1.8" .............................................................................................................................. 6 θJCbot • AddednewparagraphtoendofSequencing(SS/TR)......................................................................................................... 22 ChangesfromRevisionD(August2016)toRevisionE Page • ChangedErroramplifierdcgainTestConditionFrom:VSENSE=0.8VTo:VSENSE=0.6VintheElectrical Characteristicstable............................................................................................................................................................... 6 • ChangedFrom:(Vref)is0.8VTo:(Vref)is0.6VinsectionSlowStart(SS/TR)................................................................ 15 • ChangedtextFrom:"voltagereferenceof0.8V.Above0.8V,.."To:"voltagereferenceof0.6V.Above0.6V,.."in theMinimumOutputVoltagesection.................................................................................................................................... 27 ChangesfromRevisionC(August2015)toRevisionD Page • Changedtextstringfrom"shouldbe0.1μF"to"shouldbebetween0.1μFand1.0μFinsectionBootstrapVoltage (BOOT)andLowDropoutOperation."................................................................................................................................. 21 • Changedtextstringfrom"A0.1μFceramiccapacitor"to"A0.1μFto1μFceramiccapacitor"insectionBootstrap CapacitorSelection............................................................................................................................................................... 26 2 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 ChangesfromRevisionB(January2014)toRevisionC Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • ChangedFromseparateRHLandRGYpackagesToacombinedRHLandRGYpackage................................................ 4 ChangesfromRevisionA(March2013)toRevisionB Page • ChangedFEATUREFrom:Low2µAShutdownQuiescentCurrentTo:HiccupCurrentLimit............................................. 1 ChangesfromOriginal(March2010)toRevisionA Page • AddedPH5nsTransienttotheABSOLUTEMAXIMUMRATINGStable.............................................................................. 5 Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 5 Pin Configurations and Functions RHLPackage 14-PinVQFNWithExposedThermalPad TopView RT/CLK PWRGD 1 14 GND 2 13 BOOT GND 3 12 PH Exposed PVIN 4 Thermal Pad 11 PH (15) PVIN 5 10 EN VIN 6 9 SS/TR 7 8 VSENSE COMP PinFunctions PIN I/O(1) DESCRIPTION NAME NO. AbootstrapcapisrequiredbetweenBOOTandPH.Thevoltageonthiscapcarriesthegatedrive BOOT 13 I voltageforthehigh-sideMOSFET. Erroramplifieroutput,andinputtotheoutputswitchcurrentcomparator.Connectfrequency COMP 8 O compensationtothispin. EN 10 I Enablepin.Floattoenable.Adjusttheinputundervoltagelockoutwithtworesistors. GND 2,3 G Returnforcontrolcircuitryandlow-sidepowerMOSFET. PH 11,12 O Theswitchnode. PVIN 4,5 P Powerinput.Suppliesthepowerswitchesofthepowerconverter. PowerGoodfaultpin.Assertslowifoutputvoltageislowduetothermalshutdown,dropout,over- PWRGD 14 G voltage,ENshutdownorduringslowstart. AutomaticallyselectsbetweenRTmodeandCLKmode.Anexternaltimingresistoradjuststhe RT/CLK 1 I switchingfrequencyofthedevice;InCLKmode,thedevicesynchronizestoanexternalclock. Slowstartandtracking.Anexternalcapacitorconnectedtothispinsetstheinternalvoltagereference SS/TR 9 O risetime.Thevoltageonthispinoverridestheinternalreference.Itcanbeusedfortrackingand sequencing. VIN 6 P Suppliesthecontrolcircuitryofthepowerconverter. VSENSE 7 I Invertinginputofthegmerroramplifier. Exposed Thermal 15 G Thermalpadofthepackageandsignalgroundanditmustbesoldereddownforproperoperation. PAD (1) I=input,O=output,G=GND,P=Power 4 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 6 Specifications 6.1 Absolute Maximum Ratings(1) MIN MAX UNIT VIN –0.3 20 PVIN –0.3 20 EN –0.3 6 BOOT –0.3 27 Inputvoltage VSENSE –0.3 3 V COMP –0.3 3 PWRGD –0.3 6 SS/TR –0.3 3 RT/CLK –0.3 6 BOOT-PH 0 7.5 PH –1 20 Outputvoltage V PH10-nstransient –3 20 PH5-nstransient –4 20 Vdiff(GNDtoexposedthermalpad) –0.2 0.2 V RT/CLK ±100 µA Sourcecurrent PH CurrentLimit A PH CurrentLimit A PVIN CurrentLimit A Sinkcurrent COMP ±200 µA PWRGD –0.1 5 mA Operatingjunctiontemperature –40 150 °C Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Inputvoltage VIN 4.5 17 V Powerstageinputvoltage PVIN 1.6 17 V Outputcurrent 0 6 A Operatingjunctiontemperature,T –40 150 °C J Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 6.4 Thermal Information TPS54622 THERMALMETRIC(1)(2) RHL(VQFN) UNIT 14PINS R Junction-to-ambientthermalresistance 40.1 °C/W θJA R Junction-to-ambientthermalresistance(3) 32 °C/W θJA R Junction-to-case(top)thermalresistance 34.4 °C/W θJCtop R Junction-to-boardthermalresistance 11.4 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.5 °C/W JT ψ Junction-to-boardcharacterizationparameter 11.4 °C/W JB R Junction-to-case(bottom)thermalresistance 1.8 °C/W θJCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) PowerratingataspecificambienttemperatureT shouldbedeterminedwithajunctiontemperatureof150°C.Thisisthepointwhere A distortionstartstosubstantiallyincrease.ThermalmanagementofthePCBshouldstrivetokeepthejunctiontemperatureatorbelow 150°Cforbestperformanceandlong-termreliability.Seethepowerdissipationestimateintheapplicationsectionofthisdatasheetfor moreinformation. (3) TestBoardConditions: (a)2.5inches×2.5inches,4layers,thickness:0.062inch (b)2oz.coppertraceslocatedonthetopofthePCB (c)2oz.coppergroundplanesonthe2internallayersofandthebottomlayer (d)40.010inchthermalviaslocatedunderthedevicepackage 6.5 Electrical Characteristics T =–40°Cto150°C,VIN=4.5Vto17V,PVIN=1.6Vto17V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINANDPVINPINS) PVINoperatinginputvoltage 1.6 17 V VINoperatinginputvoltage 4.5 17 V VINinternalUVLOthreshold VINrising 4 4.5 V VINinternalUVLOhysteresis 150 mV VINshutdownsupplyCurrent EN=0V 2 5 μA VINoperating–nonswitchingsupplycurrent VSENSE=810mV 600 800 μA ENABLEANDUVLO(ENPIN) Enablethreshold Rising 1.21 1.26 V Enablethreshold Falling 1.1 1.17 Inputcurrent EN=1.1V 1.15 μA Hysteresiscurrent EN=1.3V 3.3 μA VOLTAGEREFERENCE Voltagereference 0A≤I ≤6A 0.594 0.6 0.606 V OUT MOSFET High-sideswitchresistance BOOT-PH=3V 32 60 mΩ High-sideswitchresistance(1) BOOT-PH=6V 26 40 mΩ Low-sideswitchresistance(1) VIN=12V 19 30 mΩ ERRORAMPLIFIER Erroramplifiertransconductance(gm) –2μA<I <2μA,V =1V 1300 μMhos COMP (COMP) Erroramplifierdcgain VSENSE=0.6V 1000 3100 V/V V =1V,100mVinput Erroramplifiersource/sink (COMP) ±110 μA overdrive Startswitchingthreshold 0.25 V COMPtoIswitchgm 16 A/V (1) Measuredatpins. 6 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Electrical Characteristics (continued) T =–40°Cto150°C,VIN=4.5Vto17V,PVIN=1.6Vto17V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT High-sideswitchcurrentlimitthreshold 8 11 14 A Low-sideswitchsourcingcurrentlimit 6.5 10 15 A Low-sideswitchsinkingcurrentlimit 2 3 4 A Hiccupwaittime 512 Cycles Hiccuptimebeforere-start 16384 Cycles THERMALSHUTDOWN Thermalshutdown 160 175 °C Thermalshutdownhysteresis 10 °C Thermalshutdownhiccuptime 16384 Cycles TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) Minimumswitchingfrequency Rrt=240kΩ(1%) 160 200 240 kHz Switchingfrequency Rrt=100kΩ(1%) 400 480 560 kHz Maximumswitchingfrequency Rrt=29kΩ(1%) 1440 1600 1760 kHz Minimumpulsewidth 20 ns RT/CLKhighthreshold 2 V RT/CLKlowthreshold 0.8 V Measureat500kHzwithRTresistor RT/CLKfallingedgetoPHrisingedgedelay 66 ns inseries Switchingfrequencyrange(RTmodesetpoint 200 1600 kHz andPLLmode) PH(PHPIN) Measuredat90%to90%ofVIN, Minimumon-time 94 145 ns 25°C,I =2A PH Minimumoff-time BOOT-PH≥3V 0 ns BOOT(BOOTPIN) BOOT-PHUVLO 2.1 3 V SLOWSTARTANDTRACKING(SS/TRPIN) SSchargecurrent 2.3 μA SS/TRtoVSENSEmatching V =0.4V 20 60 mV (SS/TR) POWERGOOD(PWRGDPIN) VSENSEthreshold VSENSEfalling(Fault) 92 %Vref VSENSErising(Good) 94 %Vref VSENSErising(Fault) 106 %Vref VSENSEfalling(Good) 104 %Vref Outputhighleakage VSENSE=Vref,V =5.5V 30 100 nA (PWRGD) Outputlow I =2mA 0.3 V (PWRGD) MinimumVINforvalidoutput V <0.5Vat100μA 0.6 1 V (PWRGD) MinimumSS/TRvoltageforPWRGD 1.4 V Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 6.6 Typical Characteristics 40 30 VIN = 12 V VIN = 12 V W W m m 27 − 35 − e e nc nc esista 30 esista 24 R R On On 21 − − S(on) 25 S(on) 18 D D R R 20 15 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ−JunctionTemperature−°C TJ−JunctionTemperature -°C Figure1. High-SideR vsTemperature Figure2.Low-SideR vsTemperature DS(on) DS(on) 0.606 485 z V0.604 kH − − 480 erence0.602 uency Voltage Ref00..569080 cillator Freq 475 − Os 470 Vref0.596 − O f RT= 100 kΩ 0.594 465 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ−JunctionTemperature−°C TJ−JunctionTemperature−°C Figure3.VoltageReferencevsTemperature Figure4.OscillatorFrequencyvsTemperature A m – nt μ e urr C nt e c s e ui Q n w o d ut Sh N – Isd Figure5.ShutdownQuiescentCurrentvsInputVoltage Figure6.ENPinHysteresisCurrentvsTemperature 8 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Typical Characteristics (continued) 1.220 VIN = 12 V V μ −1.215 d ol h s e hr T1.210 O L V U n Pi1.205 n E 1.200 −50 −25 0 25 50 75 100 125 150 °C TJ−JunctionTemperature−°C Figure7.PinPullupCurrentvsTemperature Figure8.PinUVLOThresholdvsTemperature A 2.5 m − 800 Am nt − g Operating Quiescent Curre 567000000 TJ= 150°C TJ=−25°C TJ=−40°C −Slow Start Charge Current 222...234 Switchin 400 ISS 2.1−50 −25 0 25 50 75 100 125 150 Non- 3 6 9 12 15 TJ−JunctionTemperature−°C VI−Input Voltage−V Figure9.Non-SwitchingOperatingQuiescentCurrent(VIN) Figure10.SlowStartChargeCurrentvsTemperature vsInputVoltage 0.040 120 V Vin = 12 V − A set μ− 110 se Off0.030 urrent VSENSE Rising n C Vse ge 100 VSENSE Falling R to Char VSENSE Rising T0.020 S S/ S S − 90 − S VSENSE Falling Voff IS 0.010 80 −50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150 TJ−JunctionTemperature−°C TJ−JunctionTemperature−°C Figure11.(SS/TR-VSENSE)OffsetvsTemperature Figure12.PWRGDThresholdvsTemperature Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Typical Characteristics (continued) 13 140 s −A 12 e−n 130 hold 11 Tim Current LimitThres 17890 TJ=−40°C TJ= 25°C TJ= 150°C um Controllable On 111021000 − m IcI 6 Mini 90 VIN = 12 V 5 80 1 5 9 13 17 −50 −25 0 25 50 75 100 125 150 VI−Input Voltage−V TJ−JunctionTemperature−°C Figure13.High-SideCurrentLimitThresholdvsInput Figure14.MinimumControllableOn-TimevsTemperature Voltage 7.0 V – d ol h 6.0 s e hr T O L V U 5.0 H P T- O RT= 100 kΩ O VIN = 12 V B 4.0 °C Figure15.MinimumControllableDutyRatiovsJunction Figure16.BOOT-PHUVLOThresholdvsTemperature Temperature 10 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 7 Detailed Description 7.1 Overview The TPS54622 device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated N-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle tothefallingedgeofanexternalsystemclock. Thedevicehasbeendesignedforsafemonotonicstart-upintoprebiasedloads.Thedefaultstart-upiswhenVIN is typically 4 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal pullup current. The total operating current for the device is approximately 600 μA when notswitchingandundernoload.Whenthedeviceisdisabled,thesupplycurrentistypicallylessthan2 μA. The integrated MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 6 amperes.TheMOSFETshavebeensizedtooptimizeefficiencyforlowerdutycycleapplications. The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold which is typically 2.1 V. The output voltage can be stepped downtoaslowasthe0.6-Vvoltagereference(Vref). The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open-drain MOSFET which is pulled low when the VSENSE pin voltage is less than 92% or greater than 106% of the reference voltage Vref and asserts high when the VSENSE pin voltageis94%to104%oftheVref. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical powersupplysequencingrequirements. The device is protected from output overvoltage, overload, and thermal fault conditions. The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the VSENSE pin voltage is lower than 104% of the Vref. The device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections which help control the inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal shutdown trip point. The device is restarted under control of the slow start circuit automatically after the built-in thermalshutdownhiccuptime. Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 7.2 Functional Block Diagram PWRGD EN VIN PVIN UV Thermal i1 iHYS Shutdown UVLO Logic Enable Comparator OV Shutdown Boot Logic Charge Hiccup Voltage Shutdown Reference Enable Boot Threshold UVLO VSENSE + + BOOT SS Minimum OV Shutdown COMP Clamp Logic HS FET Dead Time COMP Current Logic and Comparator PWM Latch PH Slope Compensation VIN LS FET Regulator Current Overload Maximum OSC with Limit Recovery Clamp PLL Hiccup GND Shutdown RT/CLK Copyright ' 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Fixed-FrequencyPWMControl The device uses a adjustable fixed-frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output is converted into a current reference which compares to the high-side power switch current. When the power switch current reaches current reference generated by the COMP voltage level the high-side power switch is turnedoffandthelow-sidepowerswitchisturnedon. 7.3.2 ContinuousCurrentModeOperation(CCM) As a synchronous buck converter, the device normally works in continuous conduction mode (CCM) under all loadconditions. 7.3.3 VINandPowerVINPins(VINandPVIN) The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to thepowerconvertersystem. Iftiedtogether,theinputvoltageforVINandPVINcanrangefrom4.5Vto17V.IfusingtheVINseparatelyfrom PVIN, the VIN pin must be from 4.5 V to 17 V, and the PVIN pin can range from as low as 1.6 V to 17 V. A voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the inputvoltageUVLOonthePVINpinhelpstoprovideconsistentpower-upbehavior. 12 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Feature Description (continued) 7.3.4 VoltageReference The voltage reference system produces a precise ±1% voltage reference overtemperature by scaling the output ofatemperaturestablebandgapcircuit. 7.3.5 AdjustingtheOutputVoltage The output voltage is set with a resistor-divider from the output (VOUT) to the VSENSE pin. TI recommends using 1% tolerance or better divider resistors. Referring to the application schematic of Figure 29, start with a 10 kΩ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSEinputcurrentandarenoticeable. Vo-Vref R5= R6 Vref where • Vref=0.6V (1) The minimum output voltage and maximum output voltage can be limited by the minimum on-time of the high- side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum OutputVoltage andBootstrapVoltage(BOOT)andLowDropoutOperation. 7.3.6 SafeStart-UpIntoPrebiasedOutputs The device has been designed to prevent the low-side MOSFET from discharging a prebiased output. During monotonic prebiased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is higherthan1.4V. 7.3.7 ErrorAmplifier Thedeviceusesatransconductanceerroramplifier.TheerroramplifiercomparestheVSENSEpinvoltagetothe lower of the SS/TR pin voltage or the internal 0.6-V voltage reference. The transconductance of the error amplifier is 1300 μA/V during normal operation. The frequency compensation network is connected between the COMPpinandground. 7.3.8 SlopeCompensation The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub- harmonicoscillations.Theavailablepeakinductorcurrentremainsconstantoverthefulldutycyclerange. 7.3.9 EnableandAdjustingUndervoltageLockout The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stopsswitchingandenterslowIqstate. The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open-drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage fallsbelowtheinternalVINUVLOthreshold.TheinternalVINUVLOthresholdhasahysteresisof150mV. If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18, and Figure 19. When usingtheexternalUVLOfunction,TIrecommendssettingthehysteresistobegreaterthan500mV. The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function since it increases by I once the EN pin crosses the enable threshold. The UVLO thresholds can be h calculatedusingEquation2andEquation3. Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Feature Description (continued) VIN I I P H R1 EN + R2 Copyright ' 2016, Texas Instruments Incorporated Figure17. AdjustableVINUndervoltageLockout PVIN I I P H R1 EN + R2 Copyright ' 2016, Texas Instruments Incorporated Figure18. AdjustablePVINUndervoltageLockout,VIN ≥4.5V 14 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Feature Description (continued) VIN I I P H R1 EN + R2 Copyright ' 2016, Texas Instruments Incorporated Figure19. AdjustableVINandPVINUndervoltageLockout æV ö V ç ENFALLING ÷ - V START STOP è VENRISING ø R1= æ V ö I ç1- ENFALLING ÷+I p h è VENRISING ø (2) R1´V R2 = ENFALLING V -V +R1(I +I ) STOP ENFALLING p h where • I =3.4μA h • I =1.15μA p • V =1.21V ENRISING • V =1.17V (3) ENFALLING 7.3.10 AdjustableSwitchingFrequencyandSynchronization(RT/CLK) TheRT/CLKpincanbeusedtosettheswitchingfrequencyofthedeviceintwomodes. In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kΩ and minimum of 29 kΩ respectively.InCLKmode,anexternalclockisconnecteddirectlytotheRT/CLKpin.Thedeviceissynchronized totheexternalclockfrequencywithPLL. The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch fromtheRTmodetoCLKmode. 7.3.11 SlowStart(SS/TR) The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The device has an internal pullup current source of 2.3 μA that charges the external slow-start capacitor. Thecalculationsfortheslowstarttime(t ,10%to90%)andslow-startcapacitor(Css)areshowninEquation4. SS Thevoltagereference(Vref)is0.6Vandtheslowstartchargecurrent(Iss)is2.3 μA. Css(nF) ´ Vref (V) t (ms)= SS Iss(µA) (4) Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Feature Description (continued) When the input UVLO is triggered, the EN pin is pulled below 1.21 V, or a thermal shutdown event occurs the device stops switching and enters low current operation. At the subsequent power up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring propersoftstartbehavior. 7.3.12 PowerGood(PWRGD) The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 104% of the internal voltage reference the PWRGD pin pulldown is deasserted and the pin floats. TI recommends using a pullup resistor from the values of 10 kΩ to 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1 V but with reduced current sinking capability. The PWRGD achievesfullcurrentsinkingcapabilityoncetheVINinputvoltageisabove4.5V. The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 106% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN pinispulledlowortheSS/TRpinisbelow1.4V. 7.3.13 OutputOvervoltageProtection(OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP thresholdthehigh-sideMOSFETisturnedoffpreventingcurrentfromflowingtotheoutputandminimizingoutput overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turnonatthenextclockcycle. 7.3.14 OvercurrentProtection The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFETandthelow-sideMOSFET. 7.3.14.1 High-SideMOSFETOvercurrentProtection The device implements current mode control which uses the COMP pin voltage to control the turnoff of the high- side MOSFET and the turnon of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared, when the peak switch current intersectsthecurrentreferencethehigh-sideswitchisturnedoff. 7.3.14.2 Low-SideMOSFETOvercurrentProtection While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing currentlimitatthestartofacycle. The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are offuntilthestartofthenextcycle. Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severeovercurrentconditions. 16 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Feature Description (continued) 7.3.15 ThermalShutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will start to count. The device reinitiates the power-up sequence after the built-in thermal shutdown hiccup time (16384cycles)isover. 7.3.16 SmallSignalModelforLoopResponse Figure 20 shows an equivalent model for the device control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R (2.38 MΩ) and capacitor C (20.7 pF) model the open loop gain and frequency OUT(ea) OUT(ea) response of the error amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the R with a current source with the L appropriateloadstepamplitudeandsteprateinatimedomainanalysis. PH Power Stage VOUT 16 A/V a R ESR b R1 R LOAD VSENSE C COMP OUT c + 0.6 V R2 C2 R3 COUT(ea) R gM OUT(ea) 1300 µA/V C1 Copyright ' 2016, Texas Instruments Incorporated Figure20. SmallSignalModelforLoopResponse 7.3.17 SimpleSmallSignalModelforPeakCurrentModeControl Figure 21 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 5 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 20) is the power stage transconductance (gm ) which is 16 A/V for the device. The DC gain of the power stage is the product of gm ps ps and the load resistance ® ) as shown in Equation 6 with resistive loads. As the load current increases, the DC L gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 7). The combined effect is highlighted by the dashed line in Figure 22. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequencythesameforthevaryingloadconditionswhichmakesiteasiertodesignthefrequencycompensation. Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Feature Description (continued) VC RESR RLOAD gm(ps) COUT Copyright ' 2016, Texas Instruments Incorporated Figure21. SimplifiedSmallSignalModelforPeakCurrentModeControl Adc n ai G fP fZ Frequency Figure22. SimplifiedFrequencyResponseforPeakCurrentModeControl æ s ö ç1+ ÷ VOUT è 2p ´ ¦zø = Adc ´ VC æ s ö ç1+ ÷ è 2p ´ ¦pø (5) Adc = gm ´ R ps L (6) 1 ¦p = C ´ R ´ 2p O L (7) 1 ¦z= CO ´ RESR ´ 2p (8) where gm isthepowerstagegain(16A/V). ps R istheloadresistance. L C istheoutputcapacitance. O R istheequivalentseriesresistanceoftheoutputcapacitor. ESR 7.3.18 SmallSignalModelforFrequencyCompensation The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 23. In Type 2A, one additional high-frequency pole, C6, is added to attenuate high frequency noise. In Type III, one additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III CompensationforCurrentModeStep-DownConverters foracompleteexplanationofTypeIIIcompensation. 18 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Feature Description (continued) The design guidelines below are provided for advanced users who prefer to compensate using the general method. The following equations only apply to designs whose ESR zero is above the bandwidth of the control loop. This is usually true with ceramic output capacitors. See Application and Implementation for a step-by-step designprocedureusinghigherESRoutputcapacitorswithlowerESRzerofrequencies. V OUT R8 C11 VSENSE COMP g M(ea) Type III + V REF R9 R4 R4 C6 C4 C4 C R OUT(ea) OUT(ea) Type IIB Type IIA Copyright ' 2016, Texas Instruments Incorporated Figure23. TypesofFrequencyCompensation Thegeneraldesignguidelinesfordeviceloopcompensationareasfollows: 1. Determinethecrossoverfrequency,fc.Agoodstartingpointis1/10thoftheswitchingfrequency,fsw. 2. R4canbedeterminedby: 2p ´ ¦c ´ VOUT ´ Co R4= gm ´ Vref ´ gm ea ps where • gm istheGMamplifiergain(1300μA/V). ea • gm isthepowerstagegain(16A/V). ps • Vrefisthereferencevoltage(0.6V). (9) æ 1 ö ç¦p= ÷ 3. Placeacompensationzeroatthedominantpole: è CO ´ RL ´ 2p ø C4canbedeterminedby: R ´ Co C4= L R4 (10) 4. C6 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output capacitorC . O R ´ Co C6= ESR R4 (11) 5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly higherloopbandwidthsandhigherphasemargins.Ifused,C11iscalculatedfromEquation12. 1 C11= (2×p×R8×fc) (12) Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 7.4 Device Functional Modes 7.4.1 AdjustableSwitchingFrequency(RTMode) To determine the RT resistance for a given switching frequency, use Equation 13 or the curve in Figure 24. To reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiencyandminimumcontrollableon-timeshouldbeconsidered. Rrt(kW) = 48000×Fsw(kHz)-0.997 -2 (13) 250 200 W k − ce 150 n a st si Re 100 − T R 50 0 200 400 600 800 1000 1200 1400 1600 Fsw−Oscillator Frequency−kHz Figure24. RTSetResistorvsSwitchingFrequency 7.4.2 Synchronization(CLKMode) An internal phase locked loop (PLL) has been implemented to allow synchronization from 200 kHz to 1600 kHz, andtoeasilyswitchfromRTmodetoCLKmode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle from 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The startoftheswitchingcycleissynchronizedtothefallingedgeofRT/CLKpin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 25. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. TI does not recommended switching from the CLK mode back to the RT mode because the internal switchingfrequencydropsto100kHzfirstbeforereturningtotheswitchingfrequencysetbyRTresistor. RT/CLK Mode Select RT/CLK R RT Copyright ' 2016, Texas Instruments Incorporated Figure25. WorksWithBothRTModeandCLKMode 20 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 Device Functional Modes (continued) 7.4.3 BootstrapVoltage(BOOT)andLowDropoutOperation The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be between 0.1 μF and 1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric withavoltageratingof10Vorhigherbecauseofthestablecharacteristicsovertemperatureandvoltage. To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1 V. When the voltage between BOOT and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails 100%dutycycleoperationcanbeachievedaslongas(VIN –PVIN) >4V. 7.4.4 Sequencing(SS/TR) Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method is illustrated in Figure 26 using two TPS54622 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supplyreachesregulation. TPS54622 TPS54622 PWRGD EN EN PWRGD SS/TR SS/TR Copyright ' 2016, Texas Instruments Incorporated Figure26. SequentialStart-UpSequence Figure 27 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start timethepullupcurrentsourcemustbedoubledinEquation4. TPS54622 TPS54622 EN EN SS SS CSS PWRGD PWRGD Copyright ' 2016, Texas Instruments Incorporated Figure27. RatiometricStart-UpSequence Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 28 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 14 and Equation 15, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 16 is the voltage difference between Vout1 andVout2. Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Device Functional Modes (continued) To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 14 and Equation 15 for deltaV. Equation 16 results in a positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.. The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset, 29 mV) in the slow start circuit and the offset created by the pullup current source (Iss,2.3μA)andtrackingresistors,theVssoffsetandIssareincludedasvariablesintheequations. To ensure proper operation of the device, the calculated R1 value from Equation 14 must be greater than the valuecalculatedinEquation17. Vout2 + DV Vssoffset R1 = ´ Vref Iss (14) Vref ´ R1 R2= Vout2+DV - Vref (15) DV =Vout1 - Vout2 (16) R1>2800´Vout1-180´DV (17) TPS54622 V OUT(1) EN SS CSS PWRGD TPS54622 V OUT(2) EN R1 R3 SS R2 PWRGD R4 Copyright ' 2016, Texas Instruments Incorporated Figure28. RatiometricandSimultaneousStart-UpSequence There are two final considerations when using a resistor divider to the SS/TR pin for simultaneous start-up. First, as described in Power Good (PWRGD), for the PWRGD output to be active the SS/TR voltage must be above 1.4V.TheexternaldividermaypreventtheSS/TRvoltagefromchargingabovethethreshold.FortheSS/TRpin to charge above the threshold, an external MOSFET may be needed to disconnect the resistor divider or modify theresistordividerratioafterstart-upiscomplete.ThePWRGDpinoftheV convertercouldbeusedtoturn OUT(1) on or turn off the external MOSFET. Second, a pre-bias on V may prevent V from turning on. When OUT(1) OUT(2) the TPS54622 is enabled, an internal 700-Ω MOSFET at the SS/TR pin turns on to discharge the SS/TR voltage as described in Slow Start (SS/TR). The SS/TR pin voltage must discharge below 20 mV before the TPS54622 starts up. If the upper resistor at the SS/TR pin is too small, the SS/TR pin does not discharge below the threshold, and V does not ramp up. The upper resistor in the SS/TR divider may need to be increased to OUT(2) allowtheSS/TRpintodischargebelowthethreshold. 22 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54622 device is a highly integrated synchronous step-down DC-DC converter. This device is used to convertahigherDCinputvoltagetoalowerDCoutputvoltage,withamaximumoutputcurrentof6A. 8.2 Typical Application The application schematic of Figure 29 was developed to meet the requirements above. This circuit is available as the TPS54622EVM-012 evaluation module. The design procedure is given in this section. For more information about Type II and Type III frequency compensation circuits, see Designing Type III Compensation for CurrentModeStep-DownConverters anddesigncalculator(SLVC219). U1 R3 TPS54622RHL 100k C3 1 RT/CLK PWRGD 14 0.1 PF L1 2 GND BOOT 13 3.3 (cid:29)H VOUT = 3.3V, 6A VIN = 8-17V 43 GND PH 1121 VOUT PVIN PH 5 10 R5 C8 PVIN EN EN C7 10k Optional 6 VIN SS/TR 9 100 PF 10C 1PF VSNS 7 VSNS WPD COMP 8 VSNS R1 P 35.7k 15 R3 R7 EN 3.74k 2.21k C2 C5 C6 8.R026k 4.7 PF C4 47pF 0.022 PF 0.01 PF Copyright ' 2016, Texas Instruments Incorporated Figure29. TypicalApplicationCircuit 8.2.1 DesignRequirements This example details the design of a high-frequency switching regulator design using ceramic output capacitors. A few parameters must be known to start the design process. These parameters are typically determined at the systemlevel.Forthisexample,beginwiththeknownparameterslistedinTable1. Table1.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Outputvoltage 3.3V Outputcurrent 6A Transientresponse1-Aloadstep ΔV =5% OUT Inputvoltage 12Vnominal,8Vto17V Outputvoltageripple 33mVp-p Startinputvoltage(risingV ) 6.528V IN Stopinputvoltage(fallingV ) 6.190V IN Switchingfrequency 480kHz Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 8.2.2 DetailedDesignProcedures 8.2.2.1 CustomDesignWithWEBENCH® Tools ClickheretocreateacustomdesignusingtheTPS54622devicewiththeWEBENCH® PowerDesigner. 1. Startbyenteringtheinputvoltage(V ),outputvoltage(V ),andoutputcurrent(I )requirements. IN OUT OUT 2. Optimizethedesignforkeyparameterssuchasefficiency,footprint,andcostusingtheoptimizerdial. 3. ComparethegenerateddesignwithotherpossiblesolutionsfromTexasInstruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricingandcomponentavailability. Inmostcases,theseactionsareavailable: • Runelectricalsimulationstoseeimportantwaveformsandcircuitperformance • Runthermalsimulationstounderstandboardthermalperformance • ExportcustomizedschematicandlayoutintopopularCADformats • PrintPDFreportsforthedesign,andsharethedesignwithcolleagues GetmoreinformationaboutWEBENCHtoolsatwww.ti.com/WEBENCH. 8.2.2.2 OperatingFrequency The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both a smallsolutionsizeandahigh-efficiencyoperation. 8.2.2.3 OutputInductorSelection To calculate the value of the output inductor, use Equation 18. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 forthemajorityofapplications. Vinmax-Vout Vout L1= × Io×Kind Vinmax× fsw (18) For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 µH. For this design, a nearest standard value was chosen: 3.3 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation20andEquation21. Vinmax-Vout Vout Iripple= × L1 Vinmax× fsw (19) 2 1 æV ×(Vinmax-Vo)ö ILrms= Io2+ ×ç o ÷ 12 ç Vinmax×L1× fsw ÷ è ø (20) Iripple ILpeak=Iout+ 2 (21) For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.84 A. The chosen inductor is a Coilcraft MSS1048 series 3.3 µH. It has a saturation current rating of 7.38 A and a RMS current rating of 7.22A. 24 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitchcurrentlimitratherthanthepeakinductorcurrent. 8.2.2.4 OutputCapacitorSelection There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in loadcurrent.Theoutputcapacitanceneedstobeselectedbasedonthemorestringentofthesethreecriteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary toaccomplishthis. 2×DIout Co> fsw×DVout where • ΔIoutisthechangeinoutputcurrent. • f istheregulatorsswitchingfrequency. SW • ΔVoutistheallowablechangeintheoutputvoltage. (22) For this example, the transient load response is specified as a 5% change in Vout for a load step of 1 A. For this example, ΔIout = 3 A and ΔVout = 0.05 × 3.3 = 0.165 V. Using these numbers gives a minimum capacitance of 75.8 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramiccapacitors,theESRisusuallysmallenoughtoignoreinthiscalculation. Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 33 mV. Under this requirement, Equation23yields13.2 µF. 1 1 Co> × 8× fsw Voripple Iripple (23) Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 19.7 mΩ. In this case, the ESR of the ceramic capacitorsismuchsmallerthan19.7mΩ. Voripple Resr< Iripple (24) Additional capacitance deratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 100-μF, 6.3-V X5R ceramic capacitor with 3 mΩ of ESR is be used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRMS(RootMeanSquare)valueofthemaximumripplecurrent.Equation25 canbeused to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 485mA. Vout×(Vinmax-Vout) Icorms= 12×Vinmax×L1× fsw (25) Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 8.2.2.5 InputCapacitorSelection The TPS54622 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of effective capacitance on the PVIN input voltage pins and 4.7 µF on the Vin input voltage pin. In some applications, additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.Thecapacitormustalsohavearipplecurrentratinggreaterthanthemaximuminputcurrentrippleofthe TPS54622.TheinputripplecurrentcanbecalculatedusingEquation26. Vout (Vinmin-Vout) Icirms=Iout× × Vinmin Vinmin (26) The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and one 4.7 µF 25-V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the TPS54622 may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values, Ioutmax = 6 A, Cin = 14.7 μF, Fsw = 480 kHz, yields an input voltage ripple of 213 mV and a RMS input ripple currentof2.95A. Ioutmax×0.25 DVin= Cin× fsw (27) 8.2.2.6 Slow-StartCapacitorSelection The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54622 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start capacitor value can be calculated using Equation 28. For the example circuit, the soft-start time is not too critical since the outputcapacitorvalueis100μFwhichdoesnotrequiremuchcurrenttochargeto3.3V.Theexamplecircuithas the soft-start time set to an arbitrary value of 6 ms which requires a 22-nF capacitor. In TPS54622, Iss is 2.3 uA andVrefis0.6V. Tss(ms)×Iss(mA) C6(nF)= Vref(V) (28) 8.2.2.7 BootstrapCapacitorSelection A 0.1-µF to 1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or highervoltagerating. 8.2.2.8 UndervoltageLockoutSetpoint Theundervoltagelockout(UVLO)canbeadjustedusingtheexternalvoltagedividernetworkofR3andR4.R3is connected between VIN and the EN pin of the TPS54622 and R4 is connected between EN and GND . The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 6.528 V (UVLO start or enable). After the regulator starts switching,itshouldcontinuetodosountiltheinputvoltagefallsbelow6.19V(UVLOstopordisable).Equation2 andEquation3canbeusedtocalculatethevaluesfortheupperandlowerresistorvalues.Forthestopvoltages specified,theneareststandardresistorvalueforR3is35.7kΩandforR4is8.06kΩ. 26 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 8.2.2.9 OutputVoltageFeedbackResistorSelection The resistor-divider network R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was selectedforR5.UsingEquation29,R6iscalculatedas2.22kΩ.Theneareststandard1%resistoris2.21kΩ. R5×Vref R6= Vo-Vref (29) 8.2.2.9.1 MinimumOutputVoltage Due to the internal design of the TPS54622, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output voltage may be limited by the minimum controllable on-time. The minimum output voltage in this case is given by Equation30: Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Voutmin=Ontimemin×Fsmax(Vinmax+Ioutmin(RDS2min-RDS1min))-Ioutmin(RL+RDS2min) where • Voutmin=minimumachievableoutputvoltage • Ontimemin=minimumcontrollableon-time(135nsmaximum) • Fsmax=maximumswitchingfrequencyincludingtolerance • Vinmax=maximuminputvoltage • Ioutmin=minimumloadcurrent • RDS1min=minimumhigh-sideMOSFETON-resistance(36-32mΩtypical) • RDS2min=minimumlow-sideMOSFETON-resistance(19mΩtypical) • RL=seriesresistanceofoutputinductor (30) 8.2.2.10 CompensationComponentSelection There are several industry techniques used to compensate DC-DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin from 60 to 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54622. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the crossoverfrequencyusedinthecalculations. First, the modulator pole, fpmod, and the ESR zero, fzmod, must be calculated using Equation 31 and Equation 32. For Cout, use a derated value of 75 µF. Use Equation 33 and Equation 34 to estimate a starting point for the closed loop crossover frequency, fco. Then the required compensation components may be derived. For this design example, fpmod is 3.86 kHz and fzmod is 707.4 kHz. Equation 33 is the geometric mean of the modulator pole and the ESR zero and Equation 34 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency, fco. In this case Equation 33 yields 52.2 kHz and Equation 34 yields 30.4 kHz. The lower value is 30.4 kHz. A slightlyhigherfrequencyof30kHzischosenastheintendedcrossoverfrequency. Iout fpmod= 2×p×Vout×Cout (31) 1 fzmod= 2×p ×RESR×Cout (32) fco= fpmod× fzmod (33) fsw fco= fpmod× 2 (34) Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensatednetworkatthecrossoverfrequency.UseEquation35todeterminethevalueofR2. 2p× fc×Vout×Cout R4= gm ×Vref×gm ea ps (35) Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole frequency.Equation36todeterminethevalueofC3. Vout×Cout C4= Iout×R4 (36) UsingEquation35andEquation36thestandardvaluesforR4andC4are3.74kΩand0.01 µF. An additional high-frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R4 and C4. The pole frequency can be placed at the ESR zero frequency of the output capacitor asgivenbyEquation8.UseEquation37tocalculatetherequiredcapacitorvalueforC5. RESR×Cout C5= R4 (37) 28 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 8.2.2.11 FastTransientConsiderations In applications where fast transient responses are very important, Type III frequency compensation can be used insteadofthetraditionalTypeIIfrequencycompensation. For more information about Type II and Type III frequency compensation circuits, see Designing Type III CompensationforCurrentModeStep-DownConverters anddesigncalculator(SLVC219). 8.2.3 ApplicationCurves VOUT= 100 mV / div (dc coupled, -3.13 V offset) V = 5 V / div IN IOUT= 2A/ div Load step = 1.5Ato 4.5ASlew rate = 100 mA/ µsec VOUT= 1 V / div Time = 200 µsec / div Time = 2 msec / div Figure30.LoadTransient Figure31.Start-UpWithVIN V = 5 V / div IN V = 10 V / div IN V = 2 V / div OUT EN = 2 V / div VOUT= 2 V / div PH = 10 V / div Time = 2 msec / div Time = 2 msec / div Figure32.Start-UpWithEN Figure33.Start-UpWithPRE-BIAS Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com VOUT= 20 mV / div (ac coupled) VIN= 500 mV / div PH = 5 V / div PH = 5 V / div Time = 1 µsec / div Time = 1 µsec / div Figure34.OutputVoltageRippleWithNoLoad Figure35.InputVoltageRippleWithFullLoad 60 180 0.4 50 150 Phase 0.3 40 120 30 90 % 0.2 IOUT= 3A - Gain-dB--211200000 Gain --633600000 Phase-Degrees putVoltageDeviation -00..011 ut -30 -90 O -0.2 -40 -120 -0.3 -50 -150 -60 -180 -0.4 100 1000 10000 100000 1000000 8 9 10 11 12 13 14 15 16 17 Frequency - Hz Input Voltage - V Figure36.ClosedLoopResponse Figure37.LineRegulation 0.4 10 10 Vout 0.3 1 1 % 0.2 VIN= 12 V putVoltageDeviation- -00.01.1 Output Voltage - V 00.00.00.111 Ideal Vsense Vsense 000...001011 Vsense Voltage - V ut O -0.2 0.0001 0.0001 -0.3 0.00001 0.00001 -0.4 0 1 2 3 4 5 6 0.001 0.01 0.1 1 10 Output Current -A Track In Voltage - V Figure38.LoadRegulation Figure39.TrackingPerformance 30 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 150 150 mperature - °C 125 mperature - °C125 Tnojm aairx f=lo w150 °C, mbient Te 100 mbient Te100 A 75 A 75 m m mu VIN= 12 V, mu T- MaxiA 50 VFrosOowUm T= t e=4m 830p.3 ,k nVHo,z ,air flow T- MaxiA 50 25 25 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 Load Current -A PD- IC Power Dissipation - W Figure40.MaximumAmbientTemperaturevsLoad Figure41.MaximumAmbientTemperaturevsICPower Current Dissipation 150 100 T = room temperature, A 95 no air flow C e - ° 125 90 ur 85 at VIN = 8 V per 100 -% 80 VIN = 12 V m y c Te en 75 VIN = 17 V ction 75 Effici 70 n u 65 J - J 50 60 T 55 25 0 0.5 1 1.5 2 2.5 3 3.5 4 50 0 1 2 3 4 5 6 Pic - IC Power Dissipation - W Output Current -A Figure42.JunctionTemperaturevsICPowerDissipation Figure43.EfficiencyvsLoadCurrent 100 VIN = 12 V VIN = 17 V 90 80 VIN = 8 V VOUT= 2 V / div 70 % 60 - PH = 10 V / div ncy 50 Efficie 40 Inductor Current = 5A/ div 30 20 10 0 Time = 20 msec / div 0.01 0.1 1.0 10.0 Output Current -A Figure44.EfficiencyvsLoadCurrent Figure45.HiccupModeCurrentLimit Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 9 Power Supply Recommendations TheTPS54622isdesignedtooperatefromaninputvoltagesupplyrangefrom4.5Vto17V.Thissupplyvoltage must be well regulated. Power supplies must be well bypassed for proper electrical performance. This includes a minimumofone4.7-µF(afterderating)ceramiccapacitor,typeX5RorbetterfromPVINtoGND,andfromVINto GND. Additional local ceramic bypass capacitance may be required in systems with small input ripple specifications, in addition to bulk capacitance if the TPS54622 device is located more than a few inches away from its input power supply. In systems with an auxiliary power rail available, the power stage input, PVIN, and the analog power input, VIN, may operate from separate input supplies. See Figure 46 for recommended bypass capacitorplacement. 10 Layout 10.1 Layout Guidelines • Layoutisacriticalportionofgoodpowersupplydesign.SeeFigure46foraPCBlayoutexample. • The top layer contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connectionsfortheremainingpinsoftheTPS54622andalargetop-sideareafilledwithground. • Connect the top layer ground area to the internal ground layers using vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS54622 device to provide a thermal path from the exposed thermalpadlandtoground • TietheGNDpindirectlytothepowerpadundertheICandthepowerpad. • Foroperationatfullratedload,thetopsidegroundareatogetherwiththeinternalgroundplane,mustprovide adequateheatdissipatingarea. • There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductanceorparasiticcapacitancetogeneratenoiseordegradethepowersuppliesperformance. • To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypasscapacitorwithX5RorX7Rdielectric. • Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, andthegroundconnections. • TheVINpinmustalsobebypassedtogroundusingalowESRceramiccapacitorwithX5RorX7Rdielectric. • Make sure to connect this capacitor to the quite analog ground trace rather than the power ground trace of thePVInbypasscapacitor. • Since the PH connection is the switching node, the output inductor should be located close to the PH pins, andtheareaofthePCBconductorminimizedtopreventexcessivecapacitivecoupling. • The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. • Trytominimizethisconductorlengthwhilemaintainingadequatewidth. • Thesmallsignalcomponentsshouldbegroundedtotheanaloggroundpathasshown. • The RT/CLK pin is sensitive to noise so the RT resistor must be located as close as possible to the IC and routedwithminimallengthsoftrace. • Theadditionalexternalcomponentscanbeplacedapproximatelyasshown. • It may be possible to obtain acceptable performance with alternate PCB layouts, however, this layout has beenshowntoproducegoodresultsandismeantasaguideline. • Landpatternandstencilinformationisprovidedinthedatasheetaddendum. • ThedimensionandoutlineinformationisforthestandardRHL(S-PVQFN-N14)package. • TheremaybeslightdifferencesbetweentheprovideddataandactualleadframeusedontheTPS54622RHL package. 32 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 10.2 Layout Examples TOPSIDE GROUND AREA FREQUENCYSETRESISTOR OUTPUT FILTER CAPACITOR PVIN INPUT BYPASS CAPACITOR RT/CLK PWRGD BOOT CAPACITOR GND BOOT OUTPUT EPAXDPOASREEDATHERMAL INDUCTOR GND PH PVIN PH PH VOUT PVIN EN VIN SS/TR VSENSE COMP PVIN VIN SLOW START CAPACITOR UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR COMPENSATION FEEDBACK NETWORK RESISTORS ANALOG GROUNDTRACE 0.010 in. Diameter Thermal VIAto Ground Plane VIAto Ground Plane Etch Under Component Figure46. PCBLayout Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com Layout Examples (continued) Figure47. Ultra-SmallPCBLayoutUsingTPS54622(PMP4854-2) 10.3 Estimated Circuit Area The estimated printed-circuit-board area for the components used in the design of Figure 29 is 0.58 in2 (374mm2).Thisareadoesnotincludetestpointsorconnectors. 34 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

TPS54622 www.ti.com SLVSA70F–MARCH2011–REVISEDOCTOBER2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.1.2 DevelopmentSupport FortheDesignCalculator,seeSLVC219. 11.1.3 CustomDesignWithWEBENCH® Tools ClickheretocreateacustomdesignusingtheTPS54622devicewiththeWEBENCH® PowerDesigner. 1. Startbyenteringtheinputvoltage(V ),outputvoltage(V ),andoutputcurrent(I )requirements. IN OUT OUT 2. Optimizethedesignforkeyparameterssuchasefficiency,footprint,andcostusingtheoptimizerdial. 3. ComparethegenerateddesignwithotherpossiblesolutionsfromTexasInstruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricingandcomponentavailability. Inmostcases,theseactionsareavailable: • Runelectricalsimulationstoseeimportantwaveformsandcircuitperformance • Runthermalsimulationstounderstandboardthermalperformance • ExportcustomizedschematicandlayoutintopopularCADformats • PrintPDFreportsforthedesign,andsharethedesignwithcolleagues GetmoreinformationaboutWEBENCHtoolsatwww.ti.com/WEBENCH. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: DesigningTypeIIICompensationforCurrentModeStep-DownConverters,SLVA352 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Copyright©2011–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54622

TPS54622 SLVSA70F–MARCH2011–REVISEDOCTOBER2017 www.ti.com 11.5 Trademarks (continued) Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 36 SubmitDocumentationFeedback Copyright©2011–2017,TexasInstrumentsIncorporated ProductFolderLinks:TPS54622

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54622RHLR ACTIVE VQFN RHL 14 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 150 54622 & no Sb/Br) TPS54622RHLT ACTIVE VQFN RHL 14 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 150 54622 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54622RHLR VQFN RHL 14 3000 330.0 12.4 3.8 3.8 1.1 8.0 12.0 Q2 TPS54622RHLR VQFN RHL 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q2 TPS54622RHLT VQFN RHL 14 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54622RHLR VQFN RHL 14 3000 338.0 355.0 50.0 TPS54622RHLR VQFN RHL 14 3000 367.0 367.0 35.0 TPS54622RHLT VQFN RHL 14 250 210.0 185.0 35.0 PackMaterials-Page2

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