Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 TPS54427 4.5-V to 18-V Input, 4-A Output Single Synchronous Step-Down Switcher With Integrated FET 1 Features 3 Description • D-CAP2™ModeEnablesFastTransient The TPS54427 is an adaptive on-time D-CAP2™ 1 mode synchronous buck converter. The TPS54427 Response enables system designers to complete the suite of • LowOutputRippleandAllowsCeramicOutput various end equipment’s power bus regulators with a Capacitor cost effective, low component count, low standby • WideV InputVoltageRange:4.5Vto18V currentsolution. IN • OutputVoltageRange:0.76Vto7.0V The main control loop for the TPS54427 uses the D- • HighlyEfficientIntegratedFETsOptimized CAP2™ mode control which provides a fast transient forLowerDutyCycleApplications response with no external compensation –70mΩ(HighSide)and53mΩ (LowSide) components. • HighEfficiency,LessThan10μAatShutdown The TPS54427 also has a proprietary circuit that enables the device to adopt to both low equivalent • HighInitialBandgapReferenceAccuracy series resistance (ESR) output capacitors, such as • AdjustableSoftStart POSCAP or SP-CAP, and ultra-low ESR ceramic • Pre-BiasedSoftStart capacitors. • 650-kHzSwitchingFrequency(f ) SW The device operates from 4.5-V to 18-V VIN input. • CyclebyCycleOverCurrentLimit The output voltage can be programmed between 0.76Vand7V. 2 Applications Thedevicealsofeaturesanadjustablesoftstarttime. • WideRangeofApplicationsforLowVoltage The TPS54427 is available in the 8-pin DDA package System and 10-pin DRC, and is designed to operate from – DigitalTVPowerSupply –40°Cto85°C. – HighDefinitionBlu-rayDisc™Players DeviceInformation(1) – NetworkingHomeTerminal PARTNUMBER PACKAGE BODYSIZE(NOM) – DigitalSetTopBox(STB) SOPowerPAD™(8) 4.89mm×3.90mm TPS54427 VSON(10) 3.00mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic TPS54427TransientResponse TPA54427DDA V (50 mV/div) out I (2A/div) out 100 µs/div 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 11 2 Applications........................................................... 1 8.1 ApplicationInformation............................................11 3 Description............................................................. 1 8.2 TypicalApplication .................................................11 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 15 5 PinConfigurationandFunctions......................... 3 10 Layout................................................................... 15 6 Specifications......................................................... 4 10.1 LayoutGuidelines.................................................15 6.1 AbsoluteMaximumRatings......................................4 10.2 LayoutExamples...................................................16 6.2 ESDRatings..............................................................4 10.3 ThermalConsiderations........................................17 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 19 6.4 ThermalInformation..................................................5 11.1 DeviceSupport......................................................19 6.5 ElectricalCharacteristics...........................................5 11.2 DocumentationSupport .......................................19 6.6 TypicalCharacteristics..............................................6 11.3 CommunityResources..........................................19 7 DetailedDescription.............................................. 8 11.4 Trademarks...........................................................19 7.1 Overview...................................................................8 11.5 ElectrostaticDischargeCaution............................19 7.2 FunctionalBlockDiagram.........................................8 11.6 Glossary................................................................19 7.3 FeatureDescription...................................................8 12 Mechanical,Packaging,andOrderable Information........................................................... 19 7.4 DeviceFunctionalModes........................................10 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(October2015)toRevisionC Page • Deleted(SWIFT™)fromthedatasheettitle ......................................................................................................................... 1 ChangesfromRevisionA(June2013)toRevisionB Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • AddedtheDRC-10Pinpackagepinout................................................................................................................................ 3 ChangesfromOriginal(November2011)toRevisionA Page • Added"and10-pinDRC"totheDESCRIPTION.................................................................................................................... 1 • AddedtheDRC-10pinPackagetotheORDERINGINFORMATIONtable........................................................................... 1 • ChangedtheVBST(vsSW)MAXvalueFrom:5.7Vto6VintheROCtable......................................................................... 4 • ChangedV inputcurrentMAXvalueFrom:±0.15µATo:±0.1µA..................................................................................... 5 FB • AddedHighsideswitchresistance(DRC)............................................................................................................................. 5 • ChangedFigure9................................................................................................................................................................... 7 • AddedFigure9....................................................................................................................................................................... 7 • AddedFigure23................................................................................................................................................................... 17 2 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 5 Pin Configuration and Functions DDAPackage DRCPackage 8-PinSOPowerPAD 10-PinVSON TopView TopView 1 EN VIN 8 EN 1 10 VIN POWER VFB 2 Exposed 9 VIN 2 VFB VBST 7 Thermal PAD VREG5 3 Die PAD 8 VBST on TPS54427 Underside SS 4 PGND 7 SW 3 VREG5 DDA SW 6 GND 5 6 SW HSOP8 4 SS GND 5 PinFunctions PIN DESCRIPTION NAME DDA DRC EN 1 1 Enableinputcontrol.Activehighandmustbepulleduptoenablethedevice. VFB 2 2 Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider. 5.5Vpowersupplyoutput.Acapacitor(typical1µF)shouldbeconnectedtoGND.VREG5isnotactive VREG5 3 3 whenENislow. SS 4 4 Soft-startcontrol.AnexternalcapacitorshouldbeconnectedtoGND. Groundpin.Powergroundreturnforswitchingcircuit.ConnectsensitiveSSandVFBreturnstoGNData GND 5 5 singlepoint. SW 6 6,7 Switchnodeconnectionbetweenhigh-sideNFETandlow-sideNFET. Supplyinputforthehigh-sideFETgatedrivecircuit.Connect0.1µFcapacitorbetweenVBSTandSW VBST 7 8 pins.AninternaldiodeisconnectedbetweenVREG5andVBST. VIN 8 9,10 Inputvoltagesupplypin. Back Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Mustbeconnectedto Exposed side GND. Thermal Pad Back Thermalpadofthepackage.PGNDpowergroundreturnofinternallow-sideFET.Mustbesolderedto side achieveappropriatedissipation. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VIN,EN –0.3 20 V VBST –0.3 26 V VBST(10nstransient) –0.3 28 V Inputvoltage VBST(vsSW) –0.3 6.5 V VFB,SS –0.3 6.5 V SW –2 20 V SW(10nstransient) –3 22 V VREG5 –0.3 6.5 V Outputvoltage GND –0.3 0.3 V VoltagefromGNDtothermalpad,V –0.2 0.2 V diff Operatingjunctiontemperature,T –40 150 °C J Storagetemperature,T –55 150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyinputvoltage 4.5 18 V IN VBST –0.1 24 VBST(10nstransient) -0.1 27 VBST(vsSW) –0.1 6 SS –0.1 5.7 V Inputvoltage EN –0.1 18 V I VFB –0.1 5.5 SW –1.8 18 SW(10nstransient) –3 21 GND –0.1 0.1 V Outputvoltage VREG5 –0.1 5.7 V O I Outputcurrent I 0 10 mA O VREG5 T Operatingfree-airtemperature –40 85 °C A T Operatingjunctiontemperature –40 150 °C J 4 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 6.4 Thermal Information TPS54427 THERMALMETRIC(1) DDA[SOPowerPAD] DRC[VSON] UNIT 8PINS 10PINS R Junction-to-ambientthermalresistance 42.1 43.2 °C/W θJA R Junction-to-case(top)thermalresistance 50.9 53.8 °C/W θJC(top) R Junction-to-boardthermalresistance 31.8 18.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 5 0.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 13.5 18.3 °C/W JB R Junction-to-case(bottom)thermalresistance 7.1 4.7 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report(SPRA953). 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT V current,T =25°C,EN=5V, I Operating-non-switchingsupplycurrent IN A 950 1400 μA VIN V =0.8V FB I Shutdownsupplycurrent V current,T =25°C,EN=0V 3.0 10 μA VINSDN IN A LOGICTHRESHOLD V ENhigh-levelinputvoltage EN 1.6 V ENH V ENlow-levelinputvoltage EN 0.6 V ENL R ENpinresistancetoGND V =12V 225 450 900 kΩ EN EN V VOLTAGEANDDISCHARGERESISTANCE FB T =25°C,V =1.05V,continuousmode A O 757 765 773 mode V V thresholdvoltage mV FBTH FB T =–40°Cto85°C,V =1.05V, A O 751 765 779 continuousmodemode(1) I V inputcurrent V =0.8V,T =25°C 0 ±0.1 μA VFB FB FB A V OUTPUT REG5 T =25°C,6.0V<V <18V, V V outputvoltage A IN 5.2 5.5 5.7 V VREG5 REG5 0<I <5mA VREG5 V Lineregulation 6V<V <18V,I =5mA 25 mV LN5 IN VREG5 V Loadregulation 0mA<I <5mA 100 mV LD5 VREG5 I Outputcurrent V =6V,V =4.0V,T =25°C 60 mA VREG5 IN REG5 A MOSFET Highsideswitchresistance(DDA) 70 R 25°C,V -SW=5.5V mΩ DS(on)h BST Highsideswitchresistance(DRC) 74 R Lowsideswitchresistance 25°C 53 mΩ DS(on)l CURRENTLIMIT I Currentlimit Lout=1.5µH (1) 4.6 5.3 6.8 A ocl (1) Notproductiontested. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT THERMALSHUTDOWN Shutdowntemperature(1) 170 T Thermalshutdownthreshold °C SDN Hysteresis(1) 35 ON-TIMETIMERCONTROL t Ontime V =12V,V =1.05V 150 ns ON IN O t Minimumofftime T =25°C,V =0.7V 260 310 ns OFF(MIN) A FB SOFTSTART I SSchargecurrent V =1V 4.2 6.0 7.8 μA SSC SS I SSdischargecurrent V =0.5V 0.1 0.2 mA SSD SS UVLO WakeupV voltage 3.45 3.75 4.05 REG5 UVLO UVLOthreshold V HysteresisV voltage 0.19 0.32 0.45 REG5 6.6 Typical Characteristics VIN=12V,T =25°C(unlessotherwisenoted) A Figure1.VINCurrentvsJunctionTemperature Figure2.VINShutdownCurrentvsJunctionTemperature Figure3.ENCurrentvsENVoltage Figure4.1.05-VOutputVoltagevsOutputCurrent 6 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 Typical Characteristics (continued) VIN=12V,T =25°C(unlessotherwisenoted) A Figure5.1.05-VOutputVoltagevsVinVoltage Figure6.EfficiencyvsOutputCurrent Figure7.SwitchingFrequencyvsInputVoltage Figure8.SwitchingFrequencyvsOutputCurrent 0.780 0.775 0.770 0.765 0.760 0.755 0.750 -50 0 50 100 Figure9.VFBVoltagevsJunctionTemperature Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS54427 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESRoutputcapacitorsincludingceramicandspecialpolymertypes. 7.2 Functional Block Diagram VIN EN EN 1 VIN Logic 8 VREG5 VBST Control Logic 7 Ref SS 1 shot SW VO 2 6 VFB XCON VREG5 VREG5 Ceramic 3 Capacitor SGND SS 5 4 GND Softstart PGND SS SW SGND PGND VIN VREG5 UVLO Protection TSD Logic UVLO REF Ref 7.3 Feature Description 7.3.1 PWMOperation The main control loop of the TPS54427 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2™modecontrol. 8 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 Feature Description (continued) 7.3.2 PWMFrequencyandAdaptiveOn-TimeControl TPS54427 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54427 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the outputvoltage,therefore,whenthedutyratioisVOUT/VIN,thefrequencyisconstant. 7.3.3 SoftStartandPre-BiasedSoftStart The soft start function is adjustable. When the EN pin becomes high, 6-uA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 6-µA. C6(nF) ´ Vfb ´ 1.1 C6(nF) ´ 0.765 ´ 1.1 Tss(ms)= = Iss(mA) 6 (1) The TPS54427 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by- cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal modeoperation. 7.3.4 CurrentProtection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I . The TPS54427 constantly OUT monitorsthelow-sideFETswitchvoltage,whichisproportionaltotheswitchcurrent,duringthelow-sideon-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the highervalue. There are some important considerations for this type of over-current protection. The load current one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the over current condition is removed, the output voltagewillreturntotheregulatedvalue.Thisprotectionisnon-latching. 7.3.5 UVLOProtection Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lowerthanUVLOthresholdvoltage,theTPS54427isshutoff.Thisprotectionisnon-latching. 7.3.6 ThermalShutdown TPS54427 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 170°C), thedeviceisshutoff.Thisisnon-latchprotection. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com 7.4 Device Functional Modes 7.4.1 NormalOperation When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS54427 operates in normal switching mode. Normal continuous conduction mode(CCM) occurs when the minimumswitchcurrentisabove0A.InCMtheTPS54427operatesataquasi-fixedfrequencyof650kHz. 7.4.2 ForcedCCMOperation When the TPS54427 is in normal CCM operating mode and switch current falls below 0 A, the device begins operatinginforcedCCM. 10 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54427 is used as a step converter that convert an voltage of 4.5 V to 18 V to a lower voltage. WEBENCH®softwareisavailabletoaidinthedesignandanalysisofcircuits. 8.2 Typical Application VIN 4.5to18V VIN C1 C2 C3 10uF 10uF 0.1uF 1 U1 2 TPS54427DDA EN R3 10.0k 1 8 EN VIN VOUT 2 7 C7 0.1uF VOUT VFB VBST R1 8.25k 3 6 L1 1.05V4A VOUT R2 VREG5 SW C4 1 22.1k C5 4 SS GND 5 1.5uH C8 C9 1uF PwPd C6 9 22uF 22uF 8200pF 1 Not Installed Figure10. TypicalApplicationSchematic 8.2.1 DesignRequirements Table1showstheinputandoutputconnections. Table1.TPS54427PerformanceSpecificationsSummary SPECIFICATIONS TESTCONDITIONS MIN TYP MAX UNIT Inputvoltagerange,V 4.5 12 18 V IN Outputvoltage,V 1.05 V OUT Operatingfrequency V =12V,I =4A 650 kHz IN O Outputcurrentrange 0 4 A Outputripplevoltage V =12V,I =4A 15 mV IN O PP Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com 8.2.2 DetailedDesignProcedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent • Outputvoltageripple • Inputvoltageripple 8.2.2.1 OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1%toleranceorbetterdividerresistors.StartbyusingEquation2 tocalculateV . OUT To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptibletonoiseandvoltageerrorsfromtheVFBinputcurrentwillbemorenoticeable. æ R1ö V = 0.765 ´ 1+ OUT ç ÷ è R2ø (2) 8.2.2.2 OutputFilterSelection TheoutputfilterusedwiththeTPS54427isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L ´ C OUT OUT (3) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54427. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable2. Table2.RecommendedComponentValues OUTPUTVOLTAGE(V) R1(kΩ) R2(kΩ) C4(pF)(1) L1(µH) C8+C9(µF) 1 6.81 22.1 1.5 22-68 1.05 8.25 22.1 1.5 22-68 1.2 12.7 22.1 1.5 22-68 1.5 21.5 22.1 1.5 22-68 1.8 30.1 22.1 5-22 2.2 22-68 2.5 49.9 22.1 5-22 2.2 22-68 3.3 73.2 22.1 5-22 2.2 22-68 5 124 22.1 5-22 3.3 22-68 6.5 165 22.1 5-22 3.3 22-68 (1) Optional For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor(C4)inparallelwithR1. The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for f . SW Use 650 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS SW currentofEquation6. 12 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 Il = VOUT ´ VIN(MAX) - VOUT P-P V L ´ f IN(MAX) O SW (4) Il Il =I + P-P PEAK O 2 (5) 1 I = I 2 + Il 2 LO(RMS) O 12 P-P (6) For this design example, the calculated peak current is 4.51 A and the calculated RMS current is 4.01 A. The inductorusedisaTDKSPM6530-1R5M100withapeakcurrentratingof11.5AandanRMScurrentrating of11A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54427 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 7 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V ´ (V - V ) I = OUT IN OUT CO(RMS) 12 ´ V ´ L ´ f IN O SW (7) For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.286Aandeachoutputcapacitorisratedfor4A. 8.2.2.3 InputCapacitorSelection The TPS54427 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor(C3)frompin8togroundisoptionaltoprovideadditionalhighfrequencyfiltering.Thecapacitorvoltage ratingneedstobegreaterthanthemaximuminputvoltage. 8.2.2.4 BootstrapCapacitorSelection A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommendedtouseaceramiccapacitor. 8.2.2.5 VREG5CapacitorSelection A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommendedtouseaceramiccapacitor. 8.2.3 ApplicationCurves 100 100 90 90 80 80 70 70 %) 60 %) 60 Efficiency ( 4500 Efficiency ( 4500 30 30 20 20 10 VIN = 12 V 10 VIN = 12 V VIN = 5.0 V VIN = 5.0 V 00 500 1000 1500 2000 2500 3000 3500 4000 01 10 100 1000 4000 Output Current (mA) Output Current (mA) G000 G000 Figure11.TPS54427Efficiency Figure12.TPS54427Light-LoadEfficiency Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com 0.5 0.5 IOUT = 0 A 0.4 0.4 IOUT = 1 A IOUT = 2 A 0.3 0.3 IOUT = 4 A OUTP (%) 00..12 OUTP (%) 00..12 Output Voltage, −−00..021 Output Voltage, −−00..021 −0.3 −0.3 −0.4 VIN =12 V −0.4 VIN = 5.0 V −0.50 500 1000 1500 2000 2500 3000 3500 4000 −0.5 6 8 10 12 14 16 18 Output Current (mA) Input Voltage (V) G000 G000 Figure13.TPS54427LoadRegulation,V =5VandV = Figure14.TPS54427LineRegulation IN IN 12V. V 10 V/div SW V 100 mV/div (-0.85V offset) OUT V 20 mV/div (-1.05V offset) OUT I 1A/div OUT Load Step: 1Ato 3A IL2A/div Slew Rate: 1A/µs V = 12 V IN Time 100 µs/div Time 1 µs/div Figure15.TPS54427LoadTransientResponse Figure16.TPS54427OutputVoltageRipple V 50 mV/div (AC coupled) IN V 2 V/div IN VOUT50 mV/div (-1.05V offset) VREG5 2 V/div V 500 mV/div OUT VSW5 V/div IIN200 mA/div Time 2 ms/div Time 1 µs/div Figure18.TPS54427Start-UpRelativetoV Figure17.TPS54427InputVoltageRipple IN 14 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 V 2 V/div EN 2 V/div IN VREG5 2 V/div VREG5 2 V/div V 500 mV/div V 500 mV/div OUT OUT I 200 mA/div IN I 200 mA/div IN Time 2 ms/div Time 0.5 ms/div Figure19.TPS54427Shut-downRelativetoV Figure20.TPS54427Start-UpRelativetoEN IN EN 2 V/div VREG5 2 V/div V 500 mV/div OUT I 500 mA/div IN Time 0.5 s/div Figure21.TPS54427Shut-downRelativetoEN 9 Power Supply Recommendations The TPS54427 is designed to operate from input supply voltage in the range of 4.5 V to 18 V. Buck converters require the input voltage to be higher than the output voltage. in this case the maximum recommended operating dutycycleis65%.Usingthatcriteria,theminimumrecommendedinputvoltageisVo/0.65. 10 Layout 10.1 Layout Guidelines 1. The TPS54427 can supply relatively large current up to 4A. So heat dissipation may be a concern. The top sideareaadjacenttotheTPS54427shouldbefilledwithgroundasmuchaspossibletodissipateheat. 2. The bottom side area directly below the IC should a dedicated ground area. It should be directed connected to the thermal pad of the using vias as shown. The ground area should be as large as practical. Additional internallayerscanbededicatedasgroundplanesandconnectedtoviasaswell. 3. Keeptheinputswitchingcurrentloopassmallaspossible. 4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedbackpinofthedevice. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com Layout Guidelines (continued) 5. Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. 6. Makeasinglepointconnectionfromthesignalgroundtopowerground. 7. Donotallowswitchingcurrenttoflowunderthedevice. 8. KeepthepatternlinesforVINandPGNDbroad. 9. ExposedpadofdevicemustbeconnectedtoPGNDwithsolder. 10. VREG5capacitorshouldbeplacednearthedevice,andconnectedPGND. 11. OutputcapacitorshouldbeconnectedtoabroadpatternofthePGND. 12. Voltagefeedbackloopshouldbeasshortaspossible,andpreferablywithgroundshield. 13. LowerresistorofthevoltagedividerwhichisconnectedtotheVFBpinshouldbetiedtoSGND. 14. ProvidingsufficientviaispreferableforVIN,SWandPGNDconnection. 15. PCBpatternforVIN,SW,andPGNDshouldbeasbroadaspossible. 16. VINCapacitorshouldbeplacedasnearaspossibletothedevice. 10.2 Layout Examples Additional Thermal Vias VIN INPUT BYPASS TO ENABLE CAPACITOR CONTROL VIN INPUT BYPASS CAPACITOR VIN FEEDBACK RESISTORS EN VIN BOOST CAPACITOR VFB VBST VOUT VREG5 SW OUTPUT BIAS SS EXPOSED PGND INDUCTOR Connection to CAP POWERPAD POWER GROUND AREA OUTPUT on internal or bottom layer SOFT FILTER START CAPACITOR Additional CAP Thermal Vias POWER GROUND ANALOG GROUND TRACE Figure22. TPS54427Layout 16 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 Layout Examples (continued) VIN VIN INPUT BYPASS CAPACITOR VIN HIGH FREQUENCY FEEDBACK BYPASS RESISTORS TO ENABLE CAPACITOR CONTROL EN VIN VFB VIN BOOST VREG5 VBST CAPACITOR BIAS VOUT CAP SS SW SLOW START GND SW OUTPUT CAP INDUCTOR EXPOSED OUTPUT THERMALPAD FILTER ANALOG AREA CAPACITOR Connection to GROUND POWER GROUND TRACE on internal or POWER GROUND bottom layer VIAto Ground Plane Figure23. PCBLayoutfortheDRCPackage 10.3 Thermal Considerations This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, SLMA002 and Application Brief, PowerPAD™MadeEasy,SLMA004. Theexposedthermalpaddimensionsforthispackageareshowninthefollowingillustration. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54427

TPS54427 SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 www.ti.com Thermal Considerations (continued) 8 5 Exposed Thermal Pad 2,40 1,65 1 4 3,10 2,65 Figure24. ThermalPadDimensions 18 SubmitDocumentationFeedback Copyright©2011–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54427

TPS54427 www.ti.com SLVSB43C–NOVEMBER2011–REVISEDFEBRUARY2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.1.2 DesignSupport WEBENCH™ software uses an iterative design procedure and accesses comprehensive databases of components.Formoredetails,gotowww.ti.com/webench. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • PowerPAD™ThermallyEnhancedPackage,SLMA002 • PowerPAD™MadeEasy,SLMA004 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks D-CAP2,PowerPAD,E2EaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Blu-rayDiscisatrademarkofBlu-rayDiscAssociation. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54427

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54427DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54427 & no Sb/Br) TPS54427DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54427 & no Sb/Br) TPS54427DRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54427 & no Sb/Br) TPS54427DRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54427 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54427DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD TPS54427DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54427DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54427DDAR SOPowerPAD DDA 8 2500 366.0 364.0 50.0 TPS54427DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS54427DRCT VSON DRC 10 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4202561/G

None

None

None

GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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