TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 3A Dual Channel Synchronous Step-Down Switcher with Integrated FET CheckforSamples:TPS54395 FEATURES APPLICATIONS 1 • D-CAP2™ControlMode • Point-of-LoadRegulationinLowPower 2 – FastTransientResponse SystemsforWideRangeofApplications – NoExternalPartsRequiredForLoop – DigitalTVPowerSupply Compensation – NetworkingHomeTerminal – CompatiblewithCeramicOutput – DigitalSetTopBox(STB) Capacitors – DVDPlayer/Recorder • WideInputVoltageRange:4.5Vto18V – GamingConsolesandOther • OutputVoltageRange:0.76Vto7.0V DESCRIPTION • HighlyEfficientIntegratedFETsOptimizedfor LowDutyCycleApplications The TPS54395 is a dual, adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54395 – 90mΩ (HighSide)and60mΩ (LowSide) enables system designers to complete the suite of • HighInitialReferenceAccuracy various end equipment’s power bus regulators with a • SupportsConstant3AatBothChannels cost effective, low component count, and low standby current solution. The main control loops of the • Low-Sider Loss-LessCurrentSensing DS(on) TPS54395 use the D-CAP2™ mode control which • AdjustabelSoftStart provides a very fast transient response with no • Non-SinkingPre-BiasedSoftStart externalcompensationcomponents.Theadaptiveon- • 700kHzSwitchingFrequency time control supports seamless transition between PWM mode at higher load conditions and Eco- • Cycle-by-CycleOver-CurrentLimitControl mode™ operation at light loads. Eco-mode™ allows • OCL/UVLO/TSDProtections the TPS54395 to maintain high efficiency during • HiccupTimerforOverloadProtection lighter load conditions. The TPS54395 is able to adapt to both low equivalent series resistance (ESR) • AdaptiveGateDriverswithIntegratedBoost output capacitors such as POSCAP or SP-CAP, and PMOSSwitch ultra-low ESR, ceramic capacitors. The device • OCPConstantDueToThermallyCompensated provides convenient and efficient operation with input r with4000ppm/℃℃ voltagesfrom4.5Vto18V. DS(on) • 16-PinHTSSOP,16-PinVQFN The TPS54395 is available in a 4.4 mm × 5 mm 16- • Auto-SkipEco-mode™　　forHighEfficiencyat pin TSSOP (PWP) and 4 mm x 4 mm 16-pin VQFN LightLoad (RSA) package, and is specified for an ambient temperaturerangefrom–40°Cto85°C. Input Voltage Vout(50mV/div) 1 VIN1 VIN216 C11 2 VBST1 VBST215 C12 VO1 L11 C31 C32 L12 VO2 3 SW1 SW214 C21 C22 4PGND1 TPS54395 PGND213 PGND HTSSOP16 PGND 5 EN1 EN212 Iout(2A/div) C41 C42 6 SS1 SS211 R11 SGND SGND R12 R21 7 VFB1 VFB210 C5 R22 8 GND VREG59 100ms/div PGND SGND SGND 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. D-CAP2,Eco-mode,Eco-ModearetrademarksofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2012–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERINGINFORMATION(1) T PACKAGE(2) (3) ORDERINGPARTNUMBER PINS OUTPUTSUPPLY A TPS54395PWPR Tape-and-Reel PWP 16 TPS54395PWP Tube –40℃to85℃ TPS54395RSAR RSA 16 Tape-and-Reel TPS54395RSAT (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (3) AllpackagingoptionshaveCuNIPDAUlead/ballfinish. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) (2) VALUE UNIT VIN1,VIN2,EN1,EN2 –0.3to20 VBST1,VBST2 –0.3to26 VBST1,VBST2(10nstransient) –0.3to28 Inputvoltagerange VBST1–SW1,VBST2–SW2 –0.3to6.5 V VFB1,VFB2 –0.3to6.5 SW1,SW2 –2to20 SW1,SW2(10nstransient) –3to22 VREG5,SS1,SS2 –0.3to6.5 Outputvoltagerange V PGND1,PGND2 –0.3to0.3 HumanBodyModel(HBM) 2 kV Electrostaticdischarge ChargedDeviceModel(CDM) 500 V T Operatingambienttemperaturerange –40to85 °C A T Storagetemperaturerange –55to150 °C STG T Junctiontemperaturerange –40to150 °C J (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"arenotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoICGNDterminal. THERMAL INFORMATION TPS54395 THERMALMETRIC(1) UNITS PWP(16)PINS PWP(16)PINS θ Junction-to-ambientthermalresistance 41.4 32.8 JA θ Junction-to-case(top)thermalresistance 27.8 35.4 JCtop θ Junction-to-boardthermalresistance 23.2 9.9 JB °C/W ψ Junction-to-topcharacterizationparameter 0.9 0.4 JT ψ Junction-to-boardcharacterizationparameter 23.0 10.0 JB θ Junction-to-case(bottom)thermalresistance 3.5 1.6 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 2 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUES UNIT MIN MAX Supplyinputvoltagerange VIN1,VIN2 4.5 18 V VBST1,VBST2 –0.1 24 VBST1,VBST2(10nstransient) –0.1 27 VBST1–SW1,VBST2–SW2 –0.1 5.7 Inputvoltagerange VFB1,VFB2 –0.1 5.7 V EN1,EN2 –0.1 18 SW1,SW2 –1.0 18 SW1,SW2(10nstransient) –3 21 VREG5,SS1,SS2 –0.1 5.7 Outputvoltagerange PGND1,PGND2 –0.1 0.1 V VO1,VO2 0.76 7.0 T Operatingfree-airtemperature –40 85 °C A T OperatingJunctionTemperature –40 150 °C J ELECTRICAL CHARACTERISTICS(1) overrecommendedfree-airtemperaturerange,VIN=12V(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT T =25°C,EN1=EN2=5V, I VINsupplycurrent A 1200 2000 µA IN VFB1=VFB2=0.8V I VINshutdowncurrent T =25°C,EN1=EN2=LafterH 15 20 µA VINSDN A FEEDBACKVOLTAGE V VFBxthresholdvoltage T =25°C,CH1=3.3V,CH2=1.5V 758 765 773 mV VFBTHLx A TC Temperaturecoefficient Onthebasisof25°C(2) –115 115 ppm/℃ VFBx I VFBxInputCurrent VFBx=0.8V,T =25°C –0.4 0.2 0.4 µA VFBx A VREG5OUTPUT T =25°C,6V<VIN1<18V, V VREG5outputvoltage A 5.5 V VREG5 I =5mA VREG VIN1=6V,VREG5=4.0V, I Outputcurrent 75 mA VREG5 T =25°C(2) A MOSFETs r Highsideswitchresistance T =25℃,VBSTx-SWx=5.5V (2) 90 mΩ DS(on)H A r Lowsideswitchresistance T =25℃ (2) 60 mΩ DS(on)L A ON-TIMETIMERCONTROL T SW1OnTime SW1=12V,VO1=1.2V 165 ns ON1 T SW2OnTime SW2=12V,VO2=1.2V 165 ns ON2 T SW1Minofftime T =25℃,VFB1=0.7V(2) 220 ns OFF1 A T SW2Minofftime T =25℃,VFB2=0.7V(2) 220 ns OFF2 A SOFTSTART I SSxchargecurrent VSSx=0.5V,T =25℃ –8.4 –8.0 –7.6 µA SSC A TC I temperaturecoefficient Onthebasisof25°C(2) –5 4 nA/°C ISSC SSC I SSxdischargecurrent VSSx=0.5V 3 7 10 mA SSD (1) xmeanseither1or2,thatis,VFBxmeansVFB1orVFB2. (2) Specifiedbydesign.Notproductiontested. Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) overrecommendedfree-airtemperaturerange,VIN=12V(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT UVLO VREG5rising 3.83 V VREG5UVLOthreshold V UVREG5 Hysteresis 0.6 LOGICTHRESHOLDs V ENxH-levelthresholdvoltage 2.0 V ENxH V ENxL-levelthresholdvoltage 0.4 V ENxL R ENxinputresistance ENx=12V 225 450 900 kΩ ENx_IN CURRENTLIMITs I Currentlimit L =2.2µH(3) 3.5 4.7 6.5 A OCLx OUTx OUTPUTUNDERVOLTAGEANDOVERVOLTAGEPROTECTION(UVP,OVP) V OutputUVPtripthreshold measuredonVFBx 63% 68% 73% UVP T OutputUVPdelaytime 1.5 ms UVPDEL T OutputUVPenabledelay UVPenabledelay/softstarttime x1.4 x1.7 x2.0 UVPEN THERMALSHUTDOWN Shutdowntemperature(3) 155 T Thermalshutdownthreshold °C SD Hysteresis(3) 25 (3) Specifiedbydesign.Notproductiontested. 4 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 DEVICE INFORMATION HTSSOPPACKAGE (TOPVIEW) RSAPACKAGE(TOPVIEW) 2 D W2 GN N2 S2 1 VIN1 VIN2 16 S P E S 16 15 14 13 2 VBST1 VBST2 15 VBST2 1 12 VFB2 3 SW1 SW2 14 VIN2 2 11 VREG5 4 PGND1 TPS54395 PGND2 13 PowerPAD HTSSOP16 VIN1 3 10 GND 5 EN1 EN2 12 6 SS1 SS2 11 VBST1 4 9 VFB1 PowerPAD 7 VFB1 VFB2 10 5 6 7 8 W1 D1 N1 S1 S N E S G 8 GND VREG5 9 P PINFUNCTIONS(1) PIN I/O DESCRIPTION NAME PWP RSA VIN1 1 3 I PowerinputsandconnectstobothhighsideNFETdrains. VIN2 16 2 I SupplyInputfor5.5Vlinearregulator. VBST1 2 4 I Supplyinputforhigh-sideNFETgatedrivecircuit.Connect0.1µFceramiccapacitor betweenVBSTxandSWxpins.AninternaldiodeisconnectedbetweenVREG5and VBST2 15 1 I VBSTx SW1 3 5 I/O Switchnodeconnectionsforboththehigh-sideNFETsandlow–sideNFETs.Inputof SW2 14 16 I/O currentcomparator. PGND1 4 6 I/O Groundreturnsforlow-sideMOSFETs.Inputofcurrentcomparator. PGND2 13 15 I/O EN1 5 7 I Enable.PullHightoenableaccordingconverter. EN2 12 14 I SS1 6 8 O Soft-StartProgrammingPin.ConnectCapacitorfromSSxpintoGNDtoprogramSoft- SS2 11 13 O Starttime. VFB1 7 9 I D-CAP2feedbackinputs.Connecttooutputvoltagewithresistordivider. VFB2 10 12 I GND 8 10 I/O SignalGND.ConnectsensitiveSSxandVFBxreturnstoGNDatasinglepoint. Outputof5.5Vlinearregulator.BypasstoGNDwithahigh-qualityceramiccapacitorofat VREG5 9 11 O least1.0µF.VREG5isactivewhenENxishigh. ExposedThermal Back Back I/O Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Must Pad side side beconnectedtoGND. (1) xmeanseither1or2,thatis,VFBxmeansVFB1orVFB2. Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN1 VIN1 -32 UV1 VBST1 UV 0.1uF SW1 VO1 Ref1 Err PGND1 SS1 Comp PGND1 VFB1 Ref_OCL PGND1 SW1 SW1 EN1 OCP1 ZC1 EN EN2 EN Logic Logic VIN1 VREG5 GND CH1Min-off timer 5VREG 1.0uF CH2Min-off timer SS1 Ref1 REF Ref2 SS1 SS2 SoftStart SS2 UV1 UV2 UVLO Protection VIN2 CSS1 Logic VIN2 UVLO CSS2 TSD VBST2 -32 UV2 UV 0.1uF VO2 SW2 Ref2 SS2 Err PGND2 Comp PGND2 VFB2 Ref_OCL PGND2 SW2 SW2 OCP2 ZC2 6 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 OVERVIEW The TPS54395 is a 3A/3A dual synchronous step-down (buck) converter with two integrated N-channel MOSFETsforeachchannel.ItoperatesusingD-CAP2™controlmode.ThefasttransientresponseofD-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitryallowstheuseoflowESRoutputcapacitorsincludingceramicandspecialpolymertypes. DETAILED DESCRIPTION PWMOperation The main control loop of the TPS54395 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. Atthebeginningofeachcycle,thehigh-sideMOSFETisturnedon.ThisMOSFETisturnedoffwhentheinternal timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a pseudo-fixedfrequencyovertheinputvoltagerangehenceitiscalledadaptiveon-timecontrol.Thetimerisreset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. Aninternalrampisaddedtothereferencevoltagetosimulateoutputvoltageripple,eliminatingtheneedforESR inducedoutputripplefromD-CAP™control. PWMFrequencyandAdaptiveOn-TimeControl TPS54395 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54395 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set theon-timetimer.Theon-timeisinverselyproportionaltotheinputvoltageandproportionaltotheoutputvoltage, therefore,whenthedutyratioisVOx/VINx,thefrequencyisconstant. Auto-SkipEco-Mode™Control The TPS54395 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with smaller load current to the nominal output voltage. The transition point to the light load operation I current Ox(LL) canbeestimatedwithEquation1with700-kHzusedasf . SW 1 (V - V ) ´ V INx Ox Ox I = ´ Ox(LL) 2 ´ L1x ´ f V SW INx (1) SoftStartandPre-BiasedSoftStart The soft start time is adjustable. When the ENx pin becomes high, 8-µA current begins charging the capacitor which is connected from the SSx pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFBx voltage is 0.765-V and SSx pin source current is8-µA. C4x(nF) ´ VFBx(V) C4x(nF) ´ 0.765V T (ms)= = SS I (mA) 8mA SS (2) The TPS54395 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage VFBx), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx) startsandrampsupsmoothlyintoregulationfrompre-biasedstartuptonormalmodeoperation. Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com CurrentSensingandOver-CurrentProtection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the measurementaccuracy,thevoltagesensingistemperaturecompensated. During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx, VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I . If the sensed voltage on the Ox low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is monitoredinthesamemanner. Important considerations for this type of over-current protection: The load current is one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. When the over current condition is removed, the output voltage returns to the regulated value. This protection is non- latching. UndervoltageProtectionandHiccupMode Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition. If the OCL comparator circuit detects an over-current event the output voltage falls. When the feedback voltage falls below 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After counting UVP delay time, the TPS54395 shuts off the power supply for a given time (7x UVP Enable Delay Time) and then tries to re-start the power supply. If the over-load condition has been removed, the power supply starts and operates normally; otherwise, the TPS54395 detects another over-current event and shuts off the power supply again, repeating the previous cycle. Excess heat due to overload lasts for onlyashortdurationinthehiccupcycle,thereforethejunctiontemperatureofthepowerdeviceismuchlower. UVLOProtection Under-voltage lock out protection (UVLO) monitors the voltage of the V pin. When the V voltage is lower REG5 REG5 than the UVLO threshold, the TPS54395 shuts down. As soon as the voltage increases above the UVLO threshold,theconverterstartsagain. ThermalShutdown TPS54395 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device shutsdown.Whenthetemperaturefallsbelowthethreshold,theICstartsagain. When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is lowerthan155°C.AslongasVIN1rises,T mustbekeptbelow110°C. J 8 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 TYPICAL CHARACTERISTICS Oneoutputisenabledunlessotherwisenoted.V =VIN1orVIN2.VIN=12V,T =25°C(unlessotherwisenoted). I A 2000 20 VIN1 = VIN2 = 12 V, 1800 EN1 = EN2 = ON 18 1600 A 16 m Am1400 IIN ent - 14 IVINSDN ent -1200 Curr 12 y Curr1000 down 10 pl ut up 800 Sh 8 - SC 600 dn - 6 C s I c c 400 Iv 4 200 2 0 0 -50 0 50 100 150 -50 0 50 100 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure1.InputCurrentvsJunctionTemperature Figure2.InputShutdownCurrentvsJunctionTemperature 60 3.4 3.38 50 EN2 3.36 put Current -Am3400 EN1 utput Voltage - V 333.3..233.8324 VIN= 12 V VIN= 18 V n O EN I20 V- O3.26 VIN= 6 V 3.24 10 3.22 0 3.2 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 EN Input Voltage - V IO- Output Current -A Figure3.ENCurrentvsENVoltage(VEN=12V) Figure4.VO1=3.3VOutputVoltagevsOutputCurrent 1.55 3.4 1.54 3.38 1.53 3.36 V = 18 V V = 12 V IN Output Voltage - V 111...1455.9125 IN Output Voltage - V 333...3233.8243 IO= 10 mA V- O1.48 VIN= 5 V V- O3.26 IO= 1A 1.47 3.24 1.46 3.22 1.45 3.2 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 14 16 18 20 IO- Output Current -A VI- Input Voltage - V Figure5.VO2=1.5VOutputVoltagevsOutputCurrent Figure6.VO1=3.3VOutputVoltagevsInputVoltage Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Oneoutputisenabledunlessotherwisenoted.V =VIN1orVIN2.VIN=12V,T =25°C(unlessotherwisenoted). I A 1.55 1.54 1.53 IO= 10 mA Vout(50mV/div) V 1.52 e - g 1.51 a olt V 1.5 ut p - Out 1.49 IO= 1A Iout(2A/div) O1.48 V 1.47 1.46 100ms/div 1.45 0 2 4 6 8 10 12 14 16 18 20 VI- Input Voltage - V Figure7.VO2=1.5VOutputVoltagevsInputVoltage Figure8.VO1=3.3V,0Ato3ALoadTransientResponse EN1(10V/div) Vout(50mV/div) Vout(1V/div) Iout(2A/div) SS1(2V/div) 100ms/div 400ms/div Figure9.VO2=1.5V,0Ato3ALoadTransientResponse Figure10.VO1=3.3V,SoftStart 100 EN2(10V/div) 90 80 VIN= 6 V VIN= 12 V Vout2(0.5V/div) % VIN= 18 V y - nc 70 e ci Effi 60 SS2(2V/div) 50 400ms/div 40 0 0.5 1 1.5 2 2.5 3 IO- Output Current -A Figure11.VO2=1.5V,SoftStart Figure12.VO1=3.3V,EfficiencyvsOutputCurrent 10 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 TYPICAL CHARACTERISTICS (continued) Oneoutputisenabledunlessotherwisenoted.V =VIN1orVIN2.VIN=12V,T =25°C(unlessotherwisenoted). I A 100 100 90 VIN= 6 V VIN= 5 V 90 80 70 VIN= 18 V 80 Efficiency - % 456000 VIN= 12 V Efficiency - % 70 VIN= 12 V VIN= 18 V 60 30 20 50 10 0 40 0.001 0.01 0.1 1 10 0 0.5 1 1.5 2 2.5 3 IO- Output Current -A IO- Output Current -A Figure13.VO1=3.3V,EfficiencyvsOutputCurrent Figure14.VO2=1.5V,EfficiencyvsOutputCurrent 100 800 90 VIN= 6 V 750 7800 VIN= 18 V ncy - kHz 700 IO= 1A Efficiency - % 456000 VIN= 12 V witching Freque 566505000 30 S w - 500 20 fs 10 450 0 400 0.001 0.01 0.1 1 10 0 2 4 6 8 10 12 14 16 18 20 IO- Output Current -A VI- Input Voltage - V Figure15.VO2=1.5V,EfficiencyvsOutputCurrent Figure16.VO1=3.3V,SW-frequencyvsInputVoltage 800 800 750 700 z cy - kH 700 y - kHz600 VIN= 12 V en 650 nc500 u e q u e q ng Fr 600 IO= 1A g Fre400 Switchi 550 witchin300 sw - 500 w - S200 f s f 450 100 400 0 0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10 VI- Input Voltage - V IO- Output Current -A Figure17.VO2=1.5V,SW-frequencyvsInputVoltage Figure18.VO1=3.3V,SW-frequencyvsOutputCurrent Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Oneoutputisenabledunlessotherwisenoted.V =VIN1orVIN2.VIN=12V,T =25°C(unlessotherwisenoted). I A 800 700 VO= 3.3 V VO1(10mV/div) Hz600 k ncy - 500 VIN= 12 V e u q e Fr400 g SW1(5V/div) n chi300 wit S w - 200 s f 100 0 0.01 0.1 1 10 IO- Output Current -A Figure19.VO2=1.5V,SW-frequencyvsOutputCurrent Figure20.VO1=3.3V,VO1RippleVoltage(I =3A) O1 VO= 3.3 V VIN1(50mV/div) VO= 1.5 V VO2(10mV/div) SW2(5V/div) SW1(5V/div) Figure21.VO2=1.5V,RippleVoltage(I =3A) Figure22.VIN1InputVoltageRipple(I =3A) O2 O1 VO= 1.5 V VIN2(50mV/div) SW2(5V/div) Figure23.VIN2InputVoltageRipple(I =3A) O2 12 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 DESIGN GUIDE Step By Step Design Procedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated switchingfrequencyof700kHzisused. VINx 12V ± 10% 1 VIN1 VIN2 16 3V.O3 1V 10Cm1F1 2.L21m1H C0.311mF2 VBST1 VBST2150.1Cm3F2 1.L51m2H C1012mF 1V.O5 2V 3 SW1 SW214 C21 C22 22mF 22mF x2 4 PGND1 TPS54395 PGND213 x2 PGND HTSSOP16 PGND 5 EN1 EN212 C41 C42 R11 6 SS1 SS2 11 73.2 kW SGND 7 VFB1 VFB2 10 SGND R211.25 kW R21 C5 1uF R22 22.1 kW 8 GND VREG59 22.1 kW PGND SGND SGND Figure24. SchematicDiagramfortheDesignExample Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use 1%toleranceorbetterdividerresistors.StartbyusingEquation3tocalculateV . Ox To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values willbemoresusceptibletonoiseandvoltageerrorsduetotheVFBxinputcurrentwillbemorenoticeable. æ R1xö VOx =0.765V ´ çè1+R2x÷ø (3) Output Filter Selection TheoutputfilterusedwiththeTPS54395isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L1x ´ C1x (4) Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54395. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable1. Table1.RecommendedComponentValues OutputVoltage(V) R1x(kΩ) R2x(kΩ) Cffx(pF)(1) L1x(µH) C2x(µF) 1 6.81 22.1 1.5-2.2 20-68 1.05 8.25 22.1 1.5-2.2 20-68 1.2 12.7 22.1 1.5-2.2 20-68 1.5 21.5 22.1 1.5-2.2 20-68 1.8 30.1 22.1 5-22 2.2-3.3 20-68 2.5 49.9 22.1 5-22 2.2-3.3 20-68 3.3 73.2 22.1 5-22 2.2-3.3 20-68 5 124 22.1 5-22 4.7 20-68 6.5 165 22.1 5-22 4.7 20-68 (1) Optional For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor(Cffx)inparallelwithR1x. The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak currentandtheRMSorheatingcurrentratingmustbegreaterthanthecalculatedRMScurrent. For the calculations, use 700 kHz as the switching frequency, f . Make sure the chosen inductor is rated for the SW peakcurrentofEquation6andtheRMScurrentofEquation7. V V - V ΔI = Ox ´ INx(MAX) Ox L1x V L1x ´ f INx(MAX) SW (5) ΔI I =I + L1x L1xpeak Ox 2 (6) 1 I = I 2 + DI 2 L1x(RMS) Ox L1x 12 (7) For the above design example, the calculated peak current is 3.46 A and the calculated RMS current is 3.01 A for VO2. The inductor used is a TDK CLF7045T-2R2N with a rated current of 5.5A based on the inductance change,andof4.3Abasedonthetemperaturerise. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54395 is intended for use with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use Equation 8 todeterminetherequiredRMScurrentratingfortheoutputcapacitor(s). V ´ (V - V ) Ox INx Ox I = C2x(RMS) 12 ´ V ´ L1x ´ f INx SW (8) For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.19Aandeachoutputcapacitorisratedfor4A. 14 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 Input Capacitor Selection The TPS54395 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1 µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the SWxnodeovershoots.Thecapacitorsvoltageratingneedstobegreaterthanthemaximuminputvoltage. Bootstrap Capacitor Selection A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is recommendedtouseceramiccapacitorswithadielectricofX5Rorbetter. VREG5 Capacitor Selection A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is recommendedtouseaceramiccapacitorwithadielectricofX5Rorbetter. Thermal Information This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. Thisdesignoptimizestheheattransferfromtheintegratedcircuit(IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.SLMA002andApplicationBrief,PowerPAD™MadeEasy,TexasInstrumentsLiteratureNo.SLMA004. Theexposedthermalpaddimensionsforthispackageareshowninthefollowingillustration. Figure25. ThermalPadDimensions Layout Considerations 1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal pad. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductanceandtominimizeradiatedemissions. 3. Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. 4. Makeasinglepointconnectionfromthesignalgroundtopowerground. 5. Donotallowswitchingcurrentstoflowunderthedevice. 6. KeepthepatternlinesforVINxandPGNDxbroad. Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com 7. ExposedpadofdevicemustbesolderedtoPGND. 8. VREG5capacitorshouldbeplacednearthedevice,andconnectedtoGND. 9. OutputcapacitorsshouldbeconnectedwithabroadpatterntothePGND. 10. Voltagefeedbackloopsshouldbeasshortaspossible,andpreferablywithgroundshields. 11. Kelvinconnectionsshouldbebroughtfromtheoutputtothefeedbackpinofthedevice. 12. ProvidingsufficientviasispreferableforVIN,SWandPGNDconnections. 13. PCBpatternforVIN,SW,andPGNDshouldbeasbroadaspossible. 14. VINCapacitorshouldbeplacedasnearaspossibletothedevice. VIN2 VIN HIGH FREQUENCY VIN INPUT BYPASS BYPASS CAPACITOR CAPACITOR ～0.1µF 10µF x2 Switching noise VIN1 1 16 VIN2 flows through IC and C .It avoids the thIeNrmal Pad. OUTPUT VBST1 2 15 VBST2 FILTER VO2 CAPACITOR SW1 3 14 SW2 INODUUTCPTUOTR Recommend to keep PGND14 13PGND2 distance more than3-4mm. (to avoid noise scattering, EN1 5 12EN2 TO ENABLE especially GND plane.) CONTROL Keep SS1 6 11SS2 distance more than1inch POWERGND VFB17 10 VFB2 To feedback GND 8 9VREG5 Feedback resisters BIAS resisters Symmetrical Layout CAP for CH1 and CH2 GND PLANE 2,3or bottom layer Via to GND Plane - Blue parts can be placed on the bottom side - Connect the SWx pins through another layer with the inductor (yellow line) Figure26. TPS54395Layout 16 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

TPS54395 www.ti.com SLVSBC8A–JUNE2012–REVISEDMAY2013 VOUT2 KEEP VIAS > 3-4 mm FROM OUTPUT OUTPUT2 CAPACITORS FILTER CAPACITORS POWER GROUND OUTPUT2 KEEPOUTPUT INDUCTOR VIAS > 25 mm FROM INPUTVIAS TO ENABLE VIN INPUT CONTROL BYPASS CAPACITORS KEEP VIAS > 3-4 mm FROM INPUT CAPACITORS VIN HIGH 2 FBCRYAEPPAAQSCUSIETNOCRY W2 GND N2 G2 TGOO OPOD WPUERLL S P E P UP2 BOOST CAPACITOR 16 15 14 13 FEEDBACK RESISTORS VBST2 1 EXPOSEDTHERMAL 12 VFB2 PADAREA VIN2 2 11 VREG5 VIN BIAS ANALOG VIN1 3 10 GND CAP GROUND TRACE VBST1 4 9 VFB1 BOOST CAPACITOR FEEDBACK 5 6 7 8 RESISTORS W1 D1 1N G1 TO POWER VIN HIGH S N E P GOOD PULL FREQUENCY G UP1 BYPASS P CAPACITOR KEEP VIAS > 3-4 mm FROM INPUT CAPACITORS VIN INPUT VIAto Internal or BYPASS Bottom Layer Ground Plane CAPACITORS TO ENABLE VIAto internal or CONTROL Bottom Layer Etch KEEPOUTPUT OUTPUT1 VIAS > 25 mm Etch or Copper Fill INDUCTOR FROM INPUTVIAS onTop Layer Internal or Bottom POWER Layer Ground Plane GROUND Etch on Bottom Layer, OUTPUT1 Internal Layer or FILTER Under Component CAPACITORS KEEP VIAS > 3-4 mm NOTE: ITIS POSSIBLETO PLACE VOUT1 FCRAOPAMC OITUOTRPSUT INTERNALOR SOME COMPONENTS SUCHAS BOTTOM LAYER BOOSTCAPACITORAND FEEDBACK GROUND PLANE RESISTORS ON BOTTOM LAYER Figure27. RSAPackageLayout Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54395

TPS54395 SLVSBC8A–JUNE2012–REVISEDMAY2013 www.ti.com REVISION HISTORY ChangesfromOriginal(June2012)toRevisionA Page • Added16-pinVQFNtotheFeaturesandDescription .......................................................................................................... 1 • Addedthe16-pinpackagetotheOrderingInformationtable............................................................................................... 2 • AddedtheRSApackagetotheThermalInformationtable .................................................................................................. 2 • AddedtheRSA16pinpackagepinoutimage,pinnamesandfunctionstotheDEVICEINFORMATIONsection ............. 5 • AddedFigure27 ................................................................................................................................................................. 17 18 SubmitDocumentationFeedback Copyright©2012–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54395

PACKAGE OPTION ADDENDUM www.ti.com 4-Jul-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (3) (4/5) TPS54395PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54395 & no Sb/Br) TPS54395PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54395 & no Sb/Br) TPS54395RSAR ACTIVE QFN RSA 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS & no Sb/Br) 54395 TPS54395RSAT ACTIVE QFN RSA 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS & no Sb/Br) 54395 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 4-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54395PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS54395RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS54395RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54395PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 TPS54395RSAR QFN RSA 16 3000 367.0 367.0 35.0 TPS54395RSAT QFN RSA 16 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PWP0016J PowerPAD TM TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE 6.6 C SEATING TYP 6.2 PLANE A PIN 1 INDEX 0.1 C AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 4.5 16X B 0.19 4.3 0.1 C A B (0.15) TYP SEE DETAIL A 8 9 0.25 3.55 GAGE PLANE 1.2 MAX 2.68 0.75 0.15 0 -8 0.50 0.05 1 16 DETA 20AIL A TYPICAL 2.46 THERMAL 1.75 PAD 4223595/A 03/2017 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PWP0016J PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (3.4) NOTE 8 METAL COVERED (2.46) BY SOLDER MASK 16X (1.5) SYMM SEE DETAILS 16X (0.45) 1 16 (1.3) TYP (R0.05) TYP SYMM (0.65) (3.55) (5) NOTE 8 14X (0.65) ( 0.2) TYP VIA 8 9 (1.35) TYP SOLDER MASK DEFINED PAD (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDE15.000R MASK DETAILS 4223595/A 03/2017 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 8. Size of metal pad may vary due to creepage requirement. 9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN PWP0016J PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (2.46) 16X (1.5) BASED ON METAL COVERED 0.125 THICK BY SOLDER MASK STENCIL 16X (0.45) 1 16 (R0.05) TYP (3.55) SYMM BASED ON 0.125 THICK STENCIL 14X (0.65) 8 9 SYMM SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL (5.8) THICKNESSES SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.75 X 3.97 0.125 2.46 X 3.55 (SHOWN) 0.15 2.25 X 3.24 0.175 2.08 X 3.00 4223595/A 03/2017 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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