TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 3.5-V to 42-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™ CONTROL SCHEME CheckforSamples:TPS54240-Q1 FEATURES APPLICATIONS 1 • QualifiedforAutomotiveApplications • 12-Vand24-VIndustrialandCommercialLow- 2 • AECQ100QualifiedWiththeFollowing PowerSystems Results: • GSM,GPRSModulesinFleetManagement,E- – DeviceTemperatureGrade1: –40°Cto Meters,andSecuritySystems 125°CAmbientOperatingTemperature DESCRIPTION Range The TPS54240-Q1 device is a 42-V, 2.5-A, step- – DeviceHBMESDClassificationLevelH2 downregulatorwithanintegratedhigh-sideMOSFET. – DeviceCDMESDClassificationLevelC6 Current-mode control provides simple external • 3.5-Vto42-VInputVoltageRange compensation and flexible component selection. A • 200-mΩHigh-SideMOSFET low-ripple pulse-skip mode reduces the no-load, regulated-output supply current to 138 μA. Using the • HighEfficiencyatLightLoadsWithaPulse- enable pin, shutdown supply current is reduced to 1.3 Skipping Eco-mode™ControlScheme μAwhentheenablepinislow. • 138-μAOperatingQuiescentCurrent Undervoltage lockout is internally set at 2.5 V, but • 1.3-μAShutdownCurrent can be increased using the enable pin. The output • 100-kHzto2.5-MHzSwitchingFrequency voltage start-up ramp is controlled by the slow-start pin that can also be configured for • SynchronizestoExternalClock sequencing/tracking. An open-drain power-good • AdjustableSlowStart/Sequencing signal indicates the output is within 94% to 107% of • UVandOVPower-GoodOutput itsnominalvoltage. • AdjustableUVLOVoltageandHysteresis A wide switching-frequency range allows efficiency • 0.8-VInternalVoltageReference and external component size to be optimized. Frequency foldback and thermal shutdown protects • MSOP10PowerPAD™Package thepartduringanoverloadcondition. • SupportedbySwitcherPro™SoftwareTool (http://focus.ti.com/docs/toolsw/folders/print/s The TPS54240-Q1 is available in a 10-pin thermally witcherpro.html) enhancedMSOPPowerPADpackage. • For SWIFT™Documentation,SeetheTIWeb siteathttp://www.ti.com/swift SIMPLIFIEDSCHEMATIC EFFICIENCYvsLOADCURRENT 100 V VVIINN PWRGD IN 90 TPS54240 80 70 BOOT EN % 60 y - SS/TR PH VOUT Efficienc 4500 RT/CLK 30 VIN=12V COMP 20 VOUT=3.3V VSENSE fsw=300kHz 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 GND IO- Output Current -A 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Eco-mode,PowerPAD,SwitcherPro,SWIFTaretrademarksofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingtemperaturerange(unlessotherwisenoted). VALUE UNITS MIN MAX VIN –0.3 47 EN(2) –0.3 5 BOOT 55 Input VSENSE –0.3 3 voltage COMP –0.3 3 PWRGD –0.3 6 SS/TR –0.3 3 V RT/CLK –0.3 3.6 BOOT-PH 8 –0.6 47 Output 200ns –1 47 voltage PH 30ns –2 47 Maximumdcvoltage,T =–40°C –0.85 J Voltage PADtoGND ±200 mV difference EN 100 μA BOOT 100 mA Source VSENSE 10 μA current Current PH limit RT/CLK 100 μA Current VIN limit Sinkcurrent COMP 100 µA PWRGD 10 mA SS/TR 200 μA Operatingjunctiontemperature –40 150 °C Storagetemperature –65 150 Human-bodymodel(HBM)AEC-Q100ClassificationLevelH2 2 kV Electrostaticdischarge(ESD)rating Charged-devicemodel(CDM)AEC-Q100ClassificationLevelC6 1000 V (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) SeetheEnableandAdjustingUndervoltageLockoutsectionofthisdatasheetfordetails. RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT T Operatingambienttemperature –40 125 °C A 2 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 THERMAL INFORMATION TPS54240-Q1 THERMALMETRIC(1)(2) DGQ UNIT 10PINS θ Junction-to-ambientthermalresistance(standardboard) 62.5 JA θ Junction-to-ambientthermalresistance(customboard)(3) 57 JA θ Junction-to-case(top)thermalresistance 83 JCtop θ Junction-to-boardthermalresistance 28 °C/W JB ψ Junction-to-topcharacterizationparameter 1.7 JT ψ Junction-to-boardcharacterizationparameter 20.1 JB θ Junction-to-case(bottom)thermalresistance 21 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) PowerratingataspecificambienttemperatureT shouldbedeterminedwithajunctiontemperatureof150°C.Thisisthepointwhere A distortionstartstoincreasesubstantially.SeePower-DissipationEstimateintheApplicationInformationsectionofthisdatasheetfor moreinformation. (3) Testboardconditions: (a)3in×3in(7,62mm×7,62mm),2layers,thickness:0.062in(1,59mm) (b) 2-oz(0,071-mmthick)coppertraceslocatedonthetopofthePCB (c) 2-oz(0,071-mmthick)coppergroundplane,bottomlayer (d)613-mil(0,33-mm)thermalviaslocatedunderthedevicepackage ELECTRICAL CHARACTERISTICS T =–40°Cto150°C,VIN=3.5Vto42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage 3.5 42 V Internalundervoltagelockout Novoltagehysteresis,risingandfalling 2.5 V threshold Shutdownsupplycurrent EN=0V,25°C,3.5V≤VIN≤42V 1.3 4 Operating:nonswitchingsupply μA VSENSE=0.83V,VIN=12V,25°C 138 200 current ENABLEANDUVLO(ENPIN) Enablethresholdvoltage Novoltagehysteresis,risingandfalling,25°C 1.15 1.25 1.36 V Enablethreshold50mV –3.8 Inputcurrent μA Enablethreshold–50mV –0.9 Hysteresiscurrent –2.9 μA VOLTAGEREFERENCE T =25°C 0.792 0.8 0.808 J Voltagereference V 0.784 0.8 0.816 HIGH-SIDEMOSFET VIN=3.5V,BOOT-PH=3V 300 On-resistance mΩ VIN=12V,BOOT-PH=6V 200 410 ERRORAMPLIFIER Inputcurrent 50 nA Erroramplifiertransconductance(g ) –2μA<I <2μA,V =1V 310 μMhos m COMP COMP Erroramplifiertransconductance(gm) –2μA<ICOMP<2μA,VCOMP=1V, 70 μMhos duringslowstart V =0.4V VSENSE Erroramplifierdcgain V =0.8V 10,000 V/V VSENSE Erroramplifierbandwidth 2700 kHz Erroramplifiersource/sink V =1V,100mVoverdrive ±27 μA (COMP) COMPtoswitchcurrent 10.5 A/V transconductance Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) T =–40°Cto150°C,VIN=3.5Vto42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT Currentlimitthreshold VIN=12V,T =25°C 3.5 6.1 A J THERMALSHUTDOWN Thermalshutdown 182 °C TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) Switching-frequencyrangeusingRT 100 2500 kHz mode f Switchingfrequency R =200kΩ 450 581 720 kHz SW T Switchingfrequencyrangeusing 300 2200 kHz CLKmode MinimumCLKinputpulseduration 40 ns RT/CLKhighthreshold 1.9 2.2 V RT/CLKlowthreshold 0.5 0.7 V RT/CLKfallingedgetoPHrising Measuredat500kHzwithRTresistorinseries 60 ns edgedelay PLLlock-intime Measuredat500kHz 100 μs SLOWSTARTANDTRACKING(SS/TR) Chargecurrent V =0.4V 2 μA SS/TR SS/TR-to-VSENSEmatching V =0.4V 45 mV SS/TR SS/TR-to-referencecrossover 98%nominal 1.15 V SS/TRdischargecurrent(overload) VSENSE=0V,V(SS/TR)=0.4V 382 μA SS/TRdischargevoltage VSENSE=0V 54 mV POWERGOOD(PWRGDPIN) VSENSEfalling 92% VSENSErising 94% V VSENSEthreshold VSENSE VSENSErising 109% VSENSEfalling 107% Hysteresis VSENSEfalling 2% Output-highleakage VSENSE=VREF,V(PWRGD)=5.5V,25°C 10 nA On-resistance I(PWRGD)=3mA,VSENSE<0.79V 50 Ω MinimumVINfordefinedoutput V(PWRGD)<0.5V,II(PWRGD)=100μA 0.95 1.5 V 4 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DEVICE INFORMATION PIN CONFIGURATION DGQPACKAGE DRCPACKAGE (TOPVIEW) (TOPVIEW) BOOT 1 10 PH BOOT 1 10 PH VIN 2 9 GND Thermal VIN 2 9 GND Thermal EN 3 P(1a1d) 8 COMP EN 3 Pad 8 COMP (11) SS/TR 4 7 VSENSE SS/TR 4 7 VSENSE RT/CLK 5 6 PWRGD RT/CLK 5 6 PWRGD PINFUNCTIONS PIN I/O DESCRIPTION NAME NO. ConnectabootstrapcapacitorbetweenBOOTandPH.Ifthevoltageonthismandatorycapacitorisbelow BOOT 1 O theminimumrequiredbytheoutputdevice,theoutputisforcedtoswitchoffuntilthecapacitorisrefreshed. Erroramplifieroutput,andinputtotheoutputswitchcurrentcomparator.Connectfrequencycompensation COMP 8 O componentstothispin. Enablepin,internalpullupcurrentsource.Pullbelow1.2Vtodisable.Floattoenable.Adjusttheinput EN 3 I undervoltagelockoutwithtworesistors. GND 9 – Ground PH 10 I Thesourceoftheinternalhigh-sidepowerMOSFET Anopen-drainoutput,assertslowifoutputvoltageislowduetothermalshutdown,dropout,overvoltageor PWRGD 6 O ENshutdown. Resistortimingandexternalclock.Aninternalamplifierholdsthispinatafixedvoltagewhenusingan externalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLLupperthreshold, RT/CLK 5 I amodechangeoccursandthepinbecomesasynchronizationinput.Theinternalamplifierisdisabledand thepinisahigh-impedanceclockinputtotheinternalPLL.Ifclockingedgesstop,theinternalamplifierisre- enabledandthemodereturnstoaresistor-setfunction. Slow-startandtracking.Anexternalcapacitorconnectedtothispinsetstheoutputrisetime.Becausethe SS/TR 4 I voltageonthispinoverridestheinternalreference,itcanbeusedfortrackingandsequencing. VIN 2 I Inputsupplyvoltage,3.5Vto42V VSENSE 7 I Invertingnodeofthetransconductance(g )erroramplifier m Thermalpad (11) – GNDpinmustbeelectricallyconnectedtotheexposedpadontheprintedcircuitboardforproperoperation. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM PWRGD EN VIN 6 3 2 Shutdown Thermal Shutdown UVLO Enable UV Logic Comparator Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Minimum Boot Reference Clamp UVLO Current Pulse Sense ERROR Skip AMPLIFIER PWM VSENSE 7 Comparator 1 BOOT SS/TR 4 Logic And PWM Latch Shutdown Slope Compensation COMP 8 10PH 11 POWERPAD Frequency Shift Overload Maximum Recovery Clamp Oscillator TPS54240Block Diagram 9 GND with PLL 5 RT/CLK 6 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 TYPICAL CHARACTERISTICS ON-RESISTANCEvsJUNCTIONTEMPERATURE VOLTAGEREFERENCEvsJUNCTIONTEMPERATURE W 0.816 m 500 nce - VI= 12 V VI= 12 V a c Drain-Source On-State Resist 213527055 BOOT-PH = 3 V BOOT-PH = 6 V V- Voltage Reference - Vref 000...788900208 ati St N - O 0.784 DS 0 -50 -25 0 25 50 75 100 125 150 R -50 -25 0 25 50 75 100 125 150 T - Junction Temperature - °C TJ- Junction Temperature - °C J Figure1. Figure2. SWITCHCURRENTLIMITvsJUNCTIONTEMPERATURE SWITCHINGFREQUENCYvsJUNCTIONTEMPERATURE 7.0 610 VI= 12 V VRIT== 1 220 V0, kW 600 6.5 Hz k A cy - 590 nt - uen e q Switch Curr6.0 witching Fre 557800 5.5 - S fs 560 5.0 550 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure3. Figure4. SWITCHINGFREQUENCYvsRT/CLKRESISTANCE,HIGH- SWITCHINGFREQUENCYvsRT/CLKRESISTANCE,LOW- FREQUENCYRANGE FREQUENCYRANGE 2500 500 V= 12 V, I T = 25°C J V= 12 V, Hz 2000 Hz 400 TJI= 25°C witching Frequency - k 11050000 witching Frequency - k 230000 S S f- s 500 f- s 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK - Resistance - kW RT/CLK - Resistance - kW Figure5. Figure6. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EATRANSCONDUCTANCEDURINGSLOWSTARTvs JUNCTIONTEMPERATURE EATRANSCONDUCTANCEvsJUNCTIONTEMPERATURE 120 500 VI= 12 V VI= 12 V 450 100 400 80 V V A/ A/ m m350 m - m - g 60 g 300 40 250 20 200 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure7. Figure8. ENPINVOLTAGEvsJUNCTIONTEMPERATURE ENPINCURRENTvsJUNCTIONTEMPERATURE 1.40 -3.25 V= 12 V VI= 12 V, I VI(EN)=Threshold +50 mV -3.5 V 1.30 d - ol A h m EN - Thres 1.20 I-(EN)-3.75 -4 1.10 -4.25 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure9. Figure10. ENPINCURRENTvsJUNCTIONTEMPERATURE SS/TRCHARGECURRENTvsJUNCTIONTEMPERATURE -0.8 -1 VI= 12 V, VI= 12 V VI(EN)=Threshold -50 mV -0.85 -1.5 Am Am I-(EN)-0.9 -SS/TR) -2 I( -0.95 -2.5 -1 -3 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure11. Figure12. 8 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 TYPICAL CHARACTERISTICS (continued) SS/TRDISCHARGECURRENTvsJUNCTION TEMPERATURE SWITCHINGFREQUENCYvsVSENSE 575 100 VI= 12 V VI= 12 V, T = 25°C J 500 80 w Am 425 al fs 60 -R) min II(SS/T 350 of No 40 % 275 20 200 0 -50 0 50 100 150 0 0.2 0.4 0.6 0.8 TJ- Junction Temperature - °C VSENSE- V Figure13. Figure14. SHUTDOWNSUPPLYCURRENTvsJUNCTION TEMPERATURE SHUTDOWNSUPPLYCURRENTvsINPUTVOLTAGE(V ) IN 2 2 V= 12 V I T = 25°C J 1.5 1.5 A A m m I-(VIN) 1 I-(VIN) 1 0.5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 0 10 20 30 40 TJ- Junction Temperature - °C VI- Input Voltage - V Figure15. Figure16. VINSUPPLYCURRENTvsJUNCTIONTEMPERATURE VINSUPPLYCURRENTvsINPUTVOLTAGE 210 170 190 VVII(V=S 1E2N SVE,)= 0.83 V TVJI(V=S E2N5SoCE),= 0.83 V 170 150 A 150 A m m I-(VIN) 130 I-(VIN) 130 110 90 70 110 -50 0 50 100 150 0 20 40 TJ- Junction Temperature - °C VI- Input Voltage - V Figure17. Figure18. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGDON-RESISTANCEvsJUNCTIONTEMPERATURE PWRGDTHRESHOLDvsJUNCTIONTEMPERATURE 100 115 VI= 12 V VI= 12 V 80 ef110 VSENSE Rising Vr of % 105 VSENSE Falling WN - 60 old - RDSO 40 Thresh 100 GD 95 VSENSE Rising R W P 20 90 VSENSE Falling 0 85 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 T - Junction Temperature - °C T - Junction Temperature - °C J J Figure19. Figure20. BOOT-PHUVLOvsJUNCTIONTEMPERATURE INPUTVOLTAGE(UVLO)vsJUNCTIONTEMPERATURE 2.5 3 2.3 2.75 V V- I(BOOT-PH) 2 V- VI(VIN) 2.50 1.8 2.25 1.5 2 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure21. Figure22. SS/TR-TO-VSENSEOFFSETvsVSENSE SS/TR-TO-VSENSEOFFSETvsTEMPERATURE 600 60 V =12V mV) 500 TIJN=25°C 50 VV(IS=S/ T1R)2= V0.4 V ( d hol 400 40 res mV geTh 300 Offset - 30 a olt 20 V 200 et s 10 Off 100 0 -50 -25 0 25 50 75 100 125 150 0 0 200 400 600 800 TJ- Junction Temperature - °C VoltageSense(mV) Figure23. Figure24. 10 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 OVERVIEW The TPS54240-Q1 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant-frequency, current-mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output-filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switchturnontoafallingedgeofanexternalsystemclock. The TPS54240-Q1 has a default start-up voltage of approximately 2.5 V. The EN pin has an internal pullup current source that is used to adjust the input undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating the device operates. The operating current is 138 μA when not switching and under no load. When the device is disabled, the supply currentis1.3μA. The integrated 200-mΩ high-side MOSFET allows for high-efficiency power-supply designs capable of delivering 2.5 A of continuous current to a load. The TPS54240-Q1 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a UVLO circuit and turns the high- side MOSFET off when the boot voltage falls below a preset threshold. The TPS54240-Q1 operates at high duty cyclesbecauseofthebootUVLO.Theoutputvoltagecanbesteppeddowntoaslowasthe0.8Vreference. The TPS54240-Q1 has a power-good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open-drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage, allowingthepintotransitionhighwhenapullupresistorisused. The TPS54240-Q1 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power-good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked fromturningonuntiltheoutputvoltageislowerthan107%. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during power up. A small-value capacitor should be coupled to the pin to adjust the slow-start time. A resistor dividercanbecoupledtothepinforcriticalpower-supplysequencingrequirements.TheSS/TRpinisdischarged before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO faultoradisabledcondition. The TPS54240-Q1 also discharges the slow-start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit slow-starts the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startupandovercurrentfaultconditionstohelpcontroltheinductorcurrent. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION Fixed-Frequency PWM Control The TPS54240-Q1 uses an adjustable fixed-frequency, peak-current-mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The error amplifier output is compared to the high-side power-switch current. When the power-switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. The Eco-mode™ control scheme is implemented with a minimum clamp on the COMPpin. Slope Compensation Output Current The TPS54240-Q1 adds a compensating ramp to the switch-current signal. This slope compensation prevents sub-harmonicoscillations.Theavailablepeakinductorcurrentremainsconstantoverthefulldutycyclerange. Pulse-Skip Eco-mode Control Scheme The TPS54240-Q1 operates in a pulse-skip Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. The TPS54240-Q1 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. This current threshold is the current level corresponding to a nominal COMP voltage or 500mV. WheninEco-mode,theCOMPpinvoltageisclampedat500mVandthehigh-sideMOSFETisinhibited.Further decreasesinloadcurrentorinoutputvoltagecannotdrivetheCOMPpinbelowthisclampvoltagelevel. Because the device is not switching, the output voltage begins to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The output voltage recharges the regulated value, then the peak switch current starts to decrease,andeventuallyfallsbelowtheEco-modethreshold,atwhichtimethedeviceagainentersEco-mode. For Eco-mode operation, the TPS54240-Q1 senses peak current, not average or load current, so the load current where the device enters Eco-mode is dependent on the output inductor value. For example, the circuit in Figure 50 enters Eco-mode at about 5 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 138 μA of input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse-skip mode,theswitchingtransitionsoccursynchronouslywiththeexternalclocksignal. Low-Dropout Operation and Bootstrap Voltage (BOOT) The TPS54240-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommendedbecauseofthestablecharacteristicsovertemperatureandvoltage. To improve dropout, the TPS54240-Q1 is designed to operate at 100% duty cycle as long as the BOOT-to-PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET is turned off using an UVLO circuit, which allows the low side diode to conduct and refresh the charge on the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor; thus, the effective duty cycle oftheswitchingregulatorishigh. The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode, and printed circuit board resistance. During operating conditions in which the input voltage drops and the regulator is operating in continuous-conduction mode, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT- to PH-voltagefallsbelow2.1V. 12 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) Attention must be taken in maximum-duty-cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the high- sideMOSFETisturnedoff,buttheremaynotbeenoughinductorcurrenttopullthePHpindowntorechargethe BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. TI recommends to adjust the VIN stop voltage greater than the BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with resistorsontheENpin. The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26. The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching. During high-duty-cycle conditions, the inductor current ripple increases while the BOOT capacitor is being recharged, resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot capacitorbeinglongerthanthetypicalhigh-sideoff-time,whenswitchingoccurseverycycle. 4 5.6 VO= 3.3 V VO= 5 V 3.8 5.4 V V Voltage - 3.6 Start Voltage - 5.2 Start V- Input I 3.4 Stop V- Input I 5 Stop 3.2 4.8 3 4.6 0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20 IO- Output Current -A IO- Output Current -A Figure25.3.3-VStart/StopVoltage Figure26.5-VStart/StopVoltage Error Amplifier The TPS54240-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (g ) of the error amplifier is 310 μA/V during normal operation. During the slow-start operation, m the transconductance is a fraction of the normal operating g . When the voltage of the VSENSE pin is below 0.8 m VandthedeviceisregulatingusingtheSS/TRvoltage,theg is70μA/V. m The frequency-compensation components (capacitor, series resistor, and capacitor) are added from the COMP pintoground. Voltage Reference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output ofatemperature-stableband-gapcircuit. Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends to use 1% tolerance or better divider resistors. Start with 10 kΩ for the R2 resistor and use Equation 1 to calculate R1. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator ismoresusceptibletonoise,andvoltageerrorsfromtheVSENSEinputcurrentarenoticeable. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) æVout - 0.8Vö R1=R2 ´ ç ÷ è 0.8V ø (1) Enable and Adjusting Undervoltage Lockout The TPS54240-Q1 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly recommended to provide consistent power-up behavior. The EN pin has an internal pullup current source, I1, of 0.9 μA that provides the default condition of the TPS54240-Q1 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, I , is added. This additional current facilitates hys input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to settheinputstartvoltage. TPS54240 VIN Ihys I1 R1 0.9mA 2.9mA + R2 EN 1.25 V - Figure27. AdjustableUndervoltageLockout(UVLO) V -V R1= START STOP I HYS (2) V R2= ENA V -V START ENA +I R1 1 (3) Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used if the resistance values are high from the previous method and a wider voltage hysteresis is needed. Resistor R3 sourcesadditionalhysteresiscurrentintotheENpin. TPS54240 VIN Ihys R1 I1 2.9mA 0.9mA + R2 EN 1.25 V - VOUT R3 Figure28.AddingAdditionalHysteresis 14 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) V -V R1= START STOP V I + OUT HYS R3 (4) V R2= ENA V -V V START ENA +I - ENA R1 1 R3 (5) Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if V > 5 V when using a voltage divider to adjust the start and stop voltage. EN The node voltage, (see Figure 29) must remain equal to or less than 5.8 V. The Zener diode can sink up to 100 µA. The EN pin voltage can be greater than 5 V if the V voltage source has a high impedance and does not IN sourcemorethan100µAintotheENpin. VIN R1 ENA Node 10kohm R2 5.8V Figure29. NodeVoltage Slow Start/Tracking Pin (SS/TR) The TPS54240-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow-start time. The TPS54240-Q1 has an internal pullup current source of 2 μA that charges the external slow-start capacitor. The calculations for the slow-start time (10% to 90%) are shown in Equation6.Thevoltagereference(V )is0.8Vandtheslow-startcurrent(I )is2μA.Theslow-startcapacitor REF SS shouldremainlowerthan0.47μFandgreaterthan0.47nF. Tss(ms) ´ Iss(mA) Css(nF)= Vref(V) ´ 0.8 (6) At power up, the TPS54240-Q1 does not start switching until the slow start pin is discharged to less than 40 mV toensureaproperpowerup,seeFigure30. Also, during normal operation, the TPS54240-Q1 stops switching and the SS/TR must be discharged to 40 mV, whentheVINUVLOisexceeded,ENpinpulledbelow1.25V,orathermalshutdowneventoccurs. The VSENSE voltage follows the SS/TR pin voltage with a 45 mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure23).TheSS/TRvoltagerampslinearlyuntilclampedat1.7V. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) EN SS/TR V SENSE VOUT Figure30. OperationofSS/TRPinWhenStarting Overload Recovery Circuit The TPS54240-Q1 has an overload recovery (OLR) circuit. The OLR circuit slow starts the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of 382 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed,theoutputslowstartsfromthefaultvoltagetonominaloutputvoltage. Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 31 using two TPS54240-Q1 devices. The power good is coupled to the EN pin on the TPS54240-Q1 which enables the second power supply once the primary supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply provides a 1- msstart-updelay.Figure32showstheresultsofFigure31. 16 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) TPS54240 PWRGD EN EN EN1 SS/TR SS/TR PWRGD1 PWRGD VOUT1 VOUT2 Figure31.SchematicforSequentialStart-Up Figure32.SequentialStartupusingENand Sequence PWRGD TTPPSS5544126400 3 EN EN1, EN2 4 SS/TR 6 PWRGD VOUT1 TTPPSS5544126400 VOUT2 3 EN 4 SS/TR 6 PWRGD Figure33.SchematicforRatiometricStartupUsing Figure34.RatioMetricStartupUsingCoupled CoupledSS/TRPins SS/TRpins Figure33showsamethodforratiometricstartupsequencebyconnectingtheSS/TRpinstogether.Theregulator outputs ramps up and reaches regulation at the same time. When calculating the slow start time the pull up currentsourcemustbedoubledinEquation6.Figure34showstheresultsofFigure33. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) TPS54240 EN VOUT1 SS/TR PWRGD TPS54240 EN VOUT2 R1 SS/TR R2 PWRGD R3 R4 Figure35. SchematicforRatiometricandSimultaneousStart-UpSequence Ratiometric and simultaneous power supply sequencing is implemented by connecting the resistor network of R1 and R2 shown in Figure 35 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 9 is the voltage difference between Vout1 and Vout2 atthe95%ofnominaloutputregulation. The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and trackingresistors,theVssoffsetandIssareincludedasvariablesintheequations. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 7 through Equation 9 for deltaV. Equation 9 results in a positivenumberforapplicationswhichtheVout2isslightlylowerthanVout1whenVout2regulationisachieved. Because the SS/TR pin must be pulled below 40mV before starting after an EN, UVLO or thermal shutdown fault,carefulselectionofthetrackingresistorsisneededtoensurethedevicerestartsafterafault.Makesurethe calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can recoverfromafault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure23. Vout2+deltaV Vssoffset R1= ´ VREF Iss (7) VREF ´ R1 R2= Vout2+deltaV - VREF (8) deltaV=Vout1 - Vout2 (9) R1>2800 ´ Vout1 - 180 ´ deltaV (10) 18 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) EN EN VOUT1 VOUT1 VOUT2 VOUT2 Figure36.RatiometricStartupWithVOUT2 Figure37.RatiometricStartupWithVOUT1 LeadingVOUT1 LeadingVOUT2 EN VOUT1 VOUT2 Figure38.SimultaneousStartupWithTrackingResistor Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54240-Q1 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 11 or the curves in Figure 39 or Figure 40. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltageandminimumcontrollableontimeshouldbeconsidered. Theminimumcontrollableontimeistypically135nsandlimitsthemaximumoperatinginputvoltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of themaximumswitchingfrequencyislocatedbelow. 206033 RT (kOhm)= ¦sw (kHz)1.0888 (11) SWITCHINGFREQUENCY SWITCHINGFREQUENCY vs vs RT/CLKRESISTANCEHIGHFREQUENCYRANGE RT/CLKRESISTANCELOWFREQUENCYRANGE 2500 500 V= 12 V, I T = 25°C J V= 12 V, Hz 2000 Hz 400 TJI= 25°C witching Frequency - k 11050000 witching Frequency - k 230000 S S f- s 500 f- s 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK - Clock Resistance - kW RT/CLK - Resistance - kW Figure39.High-RangeRT Figure40.Low-RangeRT Overcurrent Protection and Frequency Shift The TPS54240-Q1 implements current mode control which uses the COMP pin voltage to turn off the high side MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing theswitchcurrent.Theerroramplifieroutputisclampedinternally,whichfunctionsasaswitchcurrentlimit. To increase the maximum operating switching frequency at high input voltages the TPS54240-Q1 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSEpin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Because the device can only divide the switching frequency by 8, there is a maximuminputvoltagelimitinwhichthedeviceoperatesandstillhavefrequencyshiftprotection. Duringshort-circuitevents(particularlywithhighinputvoltageapplications),thecontrolloophasafiniteminimum controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on time. During the switch off time, the inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp upamount.Thefrequencyshifteffectivelyincreasestheofftimeallowingthecurrenttorampdown. 20 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation13.Equation12isthemaximumswitchingfrequencylimitationsetbytheminimumcontrollableontime. Settingtheswitchingfrequencyabovethisvaluecausestheregulatortoskipswitchingpulses. Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the fsw(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 V, the ƒdiv integer increases from 1 to 8 correspondingtothefrequencyshift. In Figure 41, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.13 Ω, FET on resistance of 0.2 Ω and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switchingfrequency. fSW(maxskip)=æçt1 ö÷´æçç(I(LV´ -RIdc´+VROhUsT++VVdd))ö÷÷ è ONø è IN L ø (12) fdiv æ(I ´Rdc+V +Vd)ö fSW(shift)= t ´çç L(V -I xORUhTsSC+Vd) ÷÷ ON è IN L ø (13) I inductorcurrent L Rdc inductorresistance V maximuminputvoltage IN V outputvoltage OUT V outputvoltageduringshort OUTSC Vd diodevoltagedrop R switchonresistance DS(on) t controllableontime ON ƒ frequencydivideequals(1,2,4,or8) DIV 2500 V = 3.3 V O Hz 2000 y - k Shift c n ue 1500 q Fre Skip g n hi 1000 c wit S - fs 500 0 10 20 30 40 VI- Input Voltage - V Figure41. MaximumSwitchingFrequencyVersusInputVoltage Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin is used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 42. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device has the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommends to use a frequency set resistor connected as shown in Figure 42 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends to ac couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequencyuntilthePLLlocksontotheCLKfrequencywithin100ms. When the device transitions from the PLL to resistor mode the switching frequency slows down from the CLK frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor then sets the switching frequency. The switchingfrequencyisdividedby8,4,2,and1asthevoltagerampsfrom0to0.8VonVSENSEpin.Thedevice implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 43, Figure 44 and Figure 45 show the device synchronized to an external system clock in continuousconductionmode(CCM)discontinuousconduction(DCM)andpulseskipmode(psm). TPS54240 10 pF 4 kW PLL R fset EXT RT/CLK Clock 50W Source Figure42. SynchronizingtoaSystemClock 22 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure43.PlotofSynchronizinginCCM Figure44.PlotofSynchronizinginDCM PH EXT IL Figure45.PlotofSynchronizinginPSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. TI recommends to use a pull-up resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD achievesfullcurrentsinkingcapabilityasVINinputvoltageapproaches3V. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) ThePWRGDpinispulledlowwhentheVSENSEislowerthan92%orgreaterthan109%ofthenominalinternal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulledlow. Overvoltage Transient Protection The TPS54240-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high side MOSFET is allowed toturnonatthenextclockcycle. Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence bydischargingtheSS/TRpin. Small Signal Model for Loop Response Figure 46 shows an equivalent model for the TPS54240-Q1 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a g of 310 μA/V. The error amplifier can be modeled using an ideal voltage mEA controlled current source. The resistor R and capacitor C model the open loop gain and frequency response of o o the amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequencyresponsemeasurements.Plottingc/ashowsthesmallsignalresponseofthefrequencycompensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing R with a current source with the appropriate load step amplitude and step rate in a time domain L analysis.Thisequivalentmodelisonlyvalidforcontinuousconductionmodedesigns. 24 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) PH V Power Stage O gm 10.5A/V ps a b R1 RESR COMP RL c VSENSE C 0.8 V OUT CO RO R3 gm ea C2 350mA/V R2 C1 Figure46. Small-SignalModelforLoopResponse Simple Small Signal Model for Peak Current Mode Control Figure 47 describes a simple small signal model that can be used to understand how to design the frequency compensation.TheTPS54240-Q1powerstageisapproximatedtoavoltage-controlledcurrentsource(dutycycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 46) is the power stage transconductance. The g for the TPS54240-Q1 is 10.5 A/V. The low-frequency gain of the power stage mPS frequencyresponseistheproductofthetransconductanceandtheloadresistanceasshowninEquation15. Astheloadcurrentincreasesanddecreases,thelow-frequencygaindecreasesandincreases,respectively.This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 47. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases fromtheESRzeroatthelowerfrequencies(seeEquation17). V O VC Adc R ESR fp R L gm ps C OUT fz Figure47.SimpleSmall-SignalModelandFrequencyResponseforPeakCurrent-ModeControl Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com DETAILED DESCRIPTION (continued) æ s ö ç1+ ÷ VOUT = Adc´è 2p´fZ ø V æ s ö C ç1+ ÷ è 2p´fP ø (14) Adc=gm ´ R ps L (15) 1 f = P C ´R ´2p OUT L (16) 1 f = Z C ´R ´2p OUT ESR (17) Small-Signal Model for Frequency Compensation The TPS54240-Q1 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 48. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors.. Equation 18 and Equation 19 show how to relate the frequency response of theamplifiertothesmallsignalmodelinFigure48.Theopen-loopgainandbandwidtharemodeledusingtheR O and C shown in Figure 48. See the application section for a design example using a Type 2A network with a O lowESRoutputcapacitor. Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application sectionoruseswitchedinformation. V O R1 VSENSE gm Type 2A Type 2B Type 1 ea COMP Vref R3 C2 R3 R2 RO CO C2 C1 C1 Figure48. TypesofFrequencyCompensation 26 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 DETAILED DESCRIPTION (continued) Aol P1 A0 Z1 P2 A1 BW Figure49. FrequencyResponseoftheType2AandType2BFrequencyCompensation Aol(V/V) Ro= gm ea (18) gm C = ea O 2p ´ BW (Hz) (19) æ s ö ç1+ ÷ è 2p´fZ1ø EA = A0´ æ s ö æ s ö ç1+ ÷´ç1+ ÷ è 2p´fP1ø è 2p´fP2 ø (20) R2 A0=gm ´ Ro ´ ea R1+R2 (21) R2 A1=gm ´ Ro||R3 ´ ea R1+R2 (22) 1 P1= 2p´Ro´C1 (23) 1 Z1= 2p´R3´C1 (24) 1 P2= type2a 2p ´ R3||R ´ (C2+C ) O O (25) 1 P2= type2b 2p ´ R3||R ´ C O O (26) 1 P2 = type 1 2p ´ R ´ (C2 + C ) O O (27) Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. Afewparametersmustbeknowninordertostartthedesignprocess.Theseparametersaretypicallydetermined atthesystemlevel.Forthisexample,usethefollowingknownparameters: OutputVoltage 3.3V TransientResponse0-to1.5-Aloadstep ΔVout=3% MaximumOutputCurrent 2.5A InputVoltage 12V(nom)10.8Vto13.2V OutputVoltageRipple 1%ofVout StartInputVoltage(risingVIN) 6V StopInputVoltage(fallingVIN) 5.5V Selecting the Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, the user chooses the highest switching frequency possible because it produces the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch,theinputvoltageandtheoutputvoltageandthefrequencyshiftlimitation. Equation 12 and Equation 13 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values result in pulse skipping or thelackofovercurrentprotectionduringashortcircuit. Thetypicalminimumontime,t ,is135nsfortheTPS54240-Q1.Forthisexample,theoutputvoltageis3.3V onmin and the maximum input voltage is 13.2 V, which allows for a maximum switch frequency up to 2247 kHz when including the inductor resistance, on resistance output current and diode voltage in Equation 12. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 13 or the solid curve in Figure 41 to determine the maximum switching frequency. With a maximum input voltage of 13.2 V, assuming a diode voltage of 0.7 V, inductor resistance of 26 mΩ, switch resistance of 200 mΩ, a current limit value of 3.5 A andashortcircuitoutputvoltageof0.2V.Themaximumswitchingfrequencyisapproximately4449kHz. For this design, a much lower switching frequency of 300 kHz is used. To determine the timing resistance for a givenswitchingfrequency,useEquation11orthecurveinFigure40. The switching frequency is set by resistor R shown in Figure 50 For 300 kHz operation a 412 kΩ resistor is 3 required. 28 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 TPS54240DGQ Figure50. 3.3-VOutputTPS54240-Q1DesignExample. Output Inductor Selection (L ) O Tocalculatetheminimumvalueoftheoutputinductor,useEquation28. K isacoefficientthatrepresentstheamountofinductorripplecurrentrelativetothemaximumoutputcurrent. IND The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer;however,thefollowingguidelinesmaybeused. For designs using low ESR output capacitors such as ceramics, a value as high as K = 0.3 may be used. IND When using higher ESR output capacitors, K = 0.2 yields better results. Because the inductor ripple current is IND part of the PWM control system, the inductor ripple current should always be greater than 150 mA for dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use K = 0.3 and the minimum inductor value is calculated to be 11 μH. For this IND design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation30andEquation31. For this design, the RMS inductor current is 2.51 A and the peak inductor current is 2.913 A. The chosen inductor is a Coilcraft MSS1038-103NLB . It has a saturation current rating of 4.52 A and an RMS current rating of4.05A. As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the regulatorbutallowforalowerinductancevalue. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitchcurrentlimitratherthanthepeakinductorcurrent. Vinmax - Vout Vout Lomin= ´ Io ´ K Vinmax ´ ƒsw IND (28) Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com IRIPPLE = VOUVTin´ma(xVin´mLaOx ´-fSVWOUT) (29) 2 I = (I )2 + 1 ´æçVOUT ´ (Vinmax - VOUT)ö÷ L(rms) O 12 ç Vinmax ´ L ´ f ÷ è O SW ø (30) Iripple ILpeak = Iout+ 2 (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulators responds to a large change in loadcurrent.Theoutputcapacitanceneedstobeselectedbasedonthemorestringentofthesethreecriteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance necessarytoaccomplishthis. Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 3% changeinVoutforaloadstepfrom1.5Ato2.5A(fullload).Forthisexample, ΔIout=2.5 –1.5=1Aand ΔVout = 0.03 × 3.3 = 0.099 V. Using these numbers gives a minimum capacitance of 67 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESRthatshouldbetakenintoaccount. The catch diode of the regulator can not sink current so any stored energy in the inductor produces an output voltage overshoot when the load current rapidly decreases, see Figure 51. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is used to calculatetheminimumcapacitancetokeeptheoutputvoltageovershoottoadesiredvalue.WhereListhevalue of the inductor, I is the output current under heavy load, I is the output under light load, Vf is the final peak OH OL output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step is from 2.5 A to 1.5A.Theoutputvoltageincreasesduringthisloadtransitionandthestatedmaximuminourspecificationis3% of the output voltage. This makes Vf = 1.03 × 3.3 = 3.399. Vi is the initial capacitor voltage which is the nominal outputvoltageof3.3V.UsingthesenumbersinEquation33yieldsaminimumcapacitanceof60 μF. Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, V is the maximum allowable output voltage ripple, and I is the oripple ripple inductorripplecurrent.Equation34yields12 μF. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.Equation35indicatestheESRshouldbelessthan36mΩ. The most stringent criteria for the output capacitor is 67 μF of capacitance to keep the output voltage in regulationduringanloadtransient. Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which increases this minimum value. For this example, 2 × 47 μF, 10 V ceramic capacitors with 3 mΩ of ESR is used. The derated capacitanceis72.4µF,abovetheminimumrequiredcapacitanceof67µF. 30 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRootMeanSquare(RMS)valueofthemaximumripplecurrent.Equation36 canbeused to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields 238mA. 2 ´ DIout Cout= ¦sw ´ DVout (32) ((Ioh)2 - (Iol)2) Cout>Lo ´ ((V¦)2 -(Vi)2) (33) 1 1 Cout> ´ 8 ´¦sw VORIPPLE I RIPPLE (34) V R < ORIPPLE ESR I RIPPLE (35) Vout ´ (Vinmax - Vout) Icorms= 12 ´ Vinmax ´ Lo ´ ¦sw (36) Catch Diode The TPS54240-Q1 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of thediode,thehighertheefficiencyoftheregulator. Typically,thehigherthevoltageandcurrentratingsthediodehas,thehighertheforwardvoltageis.Althoughthe designexamplehasaninputvoltageupto13.2V,adiodewithaminimumof60-Vreversevoltageisselected. For the example design, the B360B-13-F Schottky diode is selected for its lower forward voltage and it comes in a larger package size which has good thermal characteristics over small devices. The typical forward voltage of theB360B-13-Fis0.70volts. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power dissipation,conductionlossesplusaclosses,ofthediode. The B360B-13-F has a junction capacitance of 200 pF. Using Equation 37, the selected diode dissipates 1.32 Watts. If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diodewhichhasalowleakagecurrentandslightlyhigherforwardvoltagedrop. 2 (Vinmax - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin+ Vƒd) Pd= + Vinmax 2 (37) Input Capacitor The TPS54240-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54240- Q1.TheinputripplecurrentcanbecalculatedusingEquation38. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreasesasthedcbiasacrossacapacitorincreases. For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V so a 100-V capacitor should be selected. For this example, two 2.2-μF 100-V capacitors in parallel have been selected. Table 1 shows a selection of high voltage capacitors. The input capacitance value determinestheinputripplevoltageoftheregulator.TheinputvoltageripplecanbecalculatedusingEquation39. Using the design example values, Ioutmax = 2.5 A, Cin = 4.4μF, ƒsw = 300 kHz, yields an input voltage ripple of 206mVandarmsinputripplecurrentof1.15A. Vout (Vinmin - Vout) Icirms=Iout ´ ´ Vinmin Vinmin (38) Ioutmax ´ 0.25 ΔVin= Cin ´ ¦sw (39) Table1.CapacitorTypes VENDOR VALUE(μF) EIASize VOLTAGE DIALECTRIC COMMENTS 1to2.2 100V 1210 GRM32series 1to4.7 50V Murata 1 100V 1206 GRM31series 1to2.2 50V 1101.8 50V 2220 1to1.2 100V Vishay VJX7Rseries 1to3.9 50V 2225 1to1.8 100V X7R 1to2.2 100V 1812 CseriesC4532 1.5to6.8 50V TDK 1to2.2 100V 1210 CseriesC3225 1to3.3 50V 1to4.7 50V 1210 1 100V AVX X7Rdielectricseries 1to4.7 50V 1812 1to2.2 100V Slow-Start Capacitor The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54240-Q1 reach the current limit or excessive current draw from the input power supply may cause the input voltagerailtosag.Limitingtheoutputvoltageslewratesolvesbothoftheseproblems. The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the effective output capacitance of 72.4 µF up to 3.3 V whileonlyallowingtheaverageoutputcurrenttobe1Awouldrequirea0.19msslowstarttime. 32 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical because the output capacitor value is 2 × 47μF which does not require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of 3.5 ms which requires a 8.75 nF slow start capacitor. For this design, the next larger standard value of 10 nF isused. Cout ´ Vout ´ 0.8 Tss> Issavg (40) Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10 V or highervoltagerating. Undervoltage Lockout Set Point The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54240-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 6 V (enabled). After the regulator starts switching, it shouldcontinuetodosountiltheinputvoltagefallsbelow5.5V(UVLOstop). The programmable UVLO and enable voltages are set using the resistor divider of R1 and R2 between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 124 kΩ between Vin and EN (R1) and a 30.1 kΩ between EN and ground (R2) arerequiredtoproducethe6and5.5voltstartandstopvoltages. Output Voltage and Feedback Resistors Selection The voltage divider of R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was selected for R6. Using Equation 1, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values decrease quiescent current and improve efficiency at low output currentsbutmayintroducenoiseimmunityproblems. Compensation There are several methods used to compensate DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more accurate design. To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and Equation44gives13.4kHz.UsethelowervalueofEquation43 orEquation44foraninitialcrossoverfrequency. For this example, a higher fco is desired to improve transient response. the target fco is 35.0 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero.Acapacitorinparalleltothesetwocomponentsformsthecompensatingpole. Ioutmax ¦pmod= 2×p ×Vout×Cout (41) 1 ¦zmod= 2 ´ p ´ Resr×Cout (42) f = f mod´ f mod co p z (43) Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com f f = f mod´ sw co p 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, g , mPS is 10.5 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, g , are 3.3 V, mEA 0.8 V and 310 μA/V, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 4740 pF for compensatingcapacitorC5,a4700pFisusedforthisdesign. æ2´p´ f ´C ö æ V ö R4=ç co out ÷´ç out ÷ è gmps ø èVref´gmeaø (45) 1 C5= 2´p´R4´ f mod p (46) A compensation pole can be implemented if desired using an additional capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensationpole.C8isnotusedforthisdesignexample. C ´Resr C8= o R4 (47) 1 C8= R4´ f ´p sw (48) Discontinuous Mode and Eco-mode Boundary With an input voltage of 12 V, the power supply enters discontinuous mode when the output current is less than 337mA.ThepowersupplyentersEco-modewhentheoutputcurrentislowerthan5mA. Theinputcurrentdrawatnoloadis392μA. 34 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 APPLICATION CURVES Vout = 50 mv / div (ac coupled) Vin = 10 V / div Vout = 2 V / div Output Current = 1A/ div (Load Step 1.5Ato 2.5A) EN = 2 V / div SS/TR = 2 V / div Time = 200 usec / div Time = 5 msec / div Figure51.LoadTransient Figure52.StartupWithVIN Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 2 usec / div Figure53.OutputRipple,CCM Figure54.OutputRipple,DCM Vin = 200 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 10 usec / div Time = 2 usec / div Figure55.OutputRipple,PSM Figure56.InputRipple,CCM Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com 100 90 Vin = 50 mV / div (ac coupled) 80 70 % 60 PH = 5 V / div y - nc 50 e ci Effi 40 30 VIN=12V 20 Time = 2 usec / div VOUT=3.3V fsw=300kHz 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 IO- Output Current -A Figure57.InputRipple,DCM Figure58.EfficiencyVersusLoadCurrent 100 60 180 90 80 40 120 Phase 70 20 60 % 60 Gain Efficiency - 4500 Gain - dB 0 0 oPhase - -20 -60 30 VIN=12V 20 VOUT=3.3V VIN=12 V fsw=300kHz -40 VOUT=3.3V -120 10 IOUT=2.5A 0 -60 -180 0.001 0.01 0.1 10 100 1-103 1-104 1-105 1-106 IO- Output Current -A f - Frequency - Hz Figure59.Light-LoadEfficiency Figure60.OverallLoop-FrequencyResponse 3.4 3.4 3.38 3.38 - Output Voltage - VO33..3346 -Output Voltage - V33..3346 V O V VIN=12V 3.32 3.32 VOUT=3.3V VIN=12V fsw=300kHz VOUT=3.3V IOUT=1.5A fsw=300kHz 3.3 3.3 0 0.5 1.0 1.5 2.0 2.5 3.0 10.8 11.2 11.6 12 12.4 12.8 13.2 IO- Output Current -A IO- Output Current -A Figure61.RegulationVersusLoadCurrent Figure62.RegulationVersusInputVoltage 36 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 Power-Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation.Theseequationsshouldnotbeusedifthedeviceisworkingindiscontinuousconductionmode(DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supplycurrent(Pq). Vout Pcon=Io2 ´ R ´ DS(on) Vin (49) Psw=Vin2 ´ ¦sw ´ lo ´ 0.25 ´ 10-9 (50) Pgd=Vin ´ 3 ´ 10-9´¦sw (51) Pq=116 ´ 10-6 ´Vin Where: • IOUTistheoutputcurrent(A) • R istheon-resistanceofthehigh-sideMOSFET(Ω) DS(on) • VOUTistheoutputvoltage(V) • VINistheinputvoltage(V) • ƒswistheswitchingfrequency(Hz) (52) So Ptot=Pcon+Psw +Pgd+Pq (53) ForgivenT , A TJ=TA+Rth ´ Ptot (54) ForgivenT =150°C JMAX TAmax=TJmax - Rth ´ Ptot Where: • Ptotisthetotaldevicepowerdissipation(W) • T istheambienttemperature(°C) A • T isthejunctiontemperature(°C) J • Rthisthethermalresistanceofthepackage(°C/W) • T ismaximumjunctiontemperature(°C) JMAX • T ismaximumambienttemperature(°C) (55) AMAX There is additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and traceresistancethatimpactstheoverallefficiencyoftheregulator. Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 63 for a PCB layout example. The GND pin should be tied directly to the power pad under the ICandthepowerpad. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, andtheareaofthePCBconductorminimizedtopreventexcessivecapacitivecoupling.Foroperationatfullrated load,thetopsidegroundareamustprovideadequateheatdissipatingarea.TheRT/CLKpinissensitivetonoise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meantasaguideline. Vout Output Capacitor Output Topside Inductor Ground Route Boot Capacitor Catch Area Trace on another layer to Diode provide wide path for topside ground Input Bypass Capacitor BOOT PH Vin VIN GND EN COMP UVLO Adjust SS/TR VSENSE Compensation Resistor Resistors Network RT/CLK PWRGD Divider Slow Start Frequency Thermal VIA Capacitor Set Resistor Signal VIA Figure63. PCBLayoutExample 38 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 EstimatedCircuitArea TheestimatedprintedcircuitboardareaforthecomponentsusedinthedesignofFigure50 is0.55in2.Thisarea doesnotincludetestpointsorconnectors. VIN + Cin Cboot Lo VIN BOOT PH GND Cd R1 GND + TPS54240 R2 Co VOUT VSENSE EN SS/TR COMP RT/CLK Rcomp Czero Cpole Css RT Figure64. TPS54240-Q1InvertingPowerSupplyfromApplicationNoteSLVA317 VOPOS + VIN Copos + Cin Cboot GND VIN BOOT PH Lo Cd R1 + GND Coneg TPS54240 R2 VONEG VSENSE EN SS/TR COMP RT/CLK Rcomp Czero Cpole Css RT Figure65. TPS54240-Q1SplitRailPowerSupplyBasedonApplicationNoteSLVA369 Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 www.ti.com TPS54240DGQ Figure66. 12-Vto3.8-VGSMPowerSupply TPS54240DGQ Figure67. 24-Vto4.2-VGSMPowerSupply 40 SubmitDocumentationFeedback Copyright©2010–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240-Q1

TPS54240-Q1 www.ti.com SLVSAQ4B–DECEMBER2010–REVISEDSEPTEMBER2013 REVISION HISTORY ChangesfromRevisionA(April2011)toRevisionB Page • AddedAECqualificationtextandresultsfortemperaturegradeandHBM/CDMclassificationstoFEATURES ................ 1 • ChangedABSOLUTEMAXIMUMRATINGStableandaddedHBM/CDMclassificationlevels........................................... 2 • AddedDRCpackagetoPINCONFIGURATION .................................................................................................................. 5 • ChangedPowerGoodresistancefrom10to1kΩinPowerGood(PWRGDPin)section ................................................ 23 Copyright©2010–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TPS54240-Q1

PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54240QDGQRQ1 ACTIVE MSOP- DGQ 10 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 5424Q PowerPAD & no Sb/Br) TPS54240QDRCRQ1 ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 5424Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54240-Q1 : •Catalog: TPS54240 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54240QDGQRQ1 MSOP- DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Power PAD PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54240QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 370.0 355.0 55.0 PackMaterials-Page2

None

None

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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