Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 TPS54227 4.5-V to 18-V Input, 2-A Synchronous Step-Down Converter 1 Features 3 Description • D-CAP2™ModeEnablesFastTransient The TPS54227 device is an adaptive ON-time D- 1 CAP2 mode synchronous buck converter. The Response TPS54227 enables system designers to complete the • LowOutputRippleandAllowsCeramicOutput bus regulators for a suite of various end equipment Capacitor with a cost-effective, low component count, low • WideV InputVoltageRange:4.5Vto18V standby current solution. The main control loop for IN the TPS54227 uses the D-CAP2 mode control which • OutputVoltageRange:0.76Vto7V provides a fast transient response with no external • Highly-EfficientIntegratedFETsOptimized compensation components. The TPS54227 also has forLowerDutyCycleApplications a proprietary circuit that enables the device to adopt – 155mΩ (High-Side)and108mΩ(Low-Side) to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra- • HighEfficiency,LessThan10μAatShutdown low ESR ceramic capacitors. The device operates • HighInitialBandgapReferenceAccuracy from 4.5-V to 18-V VIN input. The output voltage can • AdjustableSoft-Start be programmed between 0.76 V and 7 V. The device • PrebiasedSoft-Start also features an adjustable soft-start time. The TPS54227 is available in the 8-pin HSOP package • 700-kHzSwitchingFrequency(f ) SW and 10-pin VSON, and is designed to operate from • Cycle-By-CycleOvercurrentLimit –40°Cto85°C. 2 Applications DeviceInformation(1) • WideRangeofApplicationsforLow-Voltage PARTNUMBER PACKAGE BODYSIZE(NOM) System SOPowerPAD(8) 4.89mm×3.90mm TPS54227 – DigitalTVPowerSupply VSON(10) 3.00mm×3.00mm – High-DefinitionBlu-rayDisc™Players (1) For all available packages, see the orderable addendum at theendofthedatasheet. – NetworkingHomeTerminals – DigitalSetTopBoxes(STB) SimplifiedSchematic TPS54227TransientResponse TPS54227DDA Vout (50 mV/div) Iout (1A/div) 100ms/div 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................10 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 11 3 Description............................................................. 1 8.1 ApplicationInformation............................................11 4 RevisionHistory..................................................... 2 8.2 TypicalApplication..................................................11 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 15 6 Specifications......................................................... 4 10 Layout................................................................... 15 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines.................................................15 6.2 ESDRatings..............................................................4 10.2 LayoutExamples...................................................15 6.3 RecommendedOperatingConditions.......................4 10.3 ThermalConsiderations........................................16 6.4 ThermalInformation..................................................5 11 DeviceandDocumentationSupport................. 17 6.5 ElectricalCharacteristics...........................................5 11.1 DocumentationSupport........................................17 6.6 TypicalCharacteristics..............................................6 11.2 CommunityResources..........................................17 7 DetailedDescription.............................................. 8 11.3 Trademarks...........................................................17 7.1 Overview...................................................................8 11.4 ElectrostaticDischargeCaution............................17 7.2 FunctionalBlockDiagram.........................................8 11.5 Glossary................................................................17 7.3 FeatureDescription...................................................8 12 Mechanical,Packaging,andOrderable Information........................................................... 17 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(June2013)toRevisionC Page • DeletedOrderingInformationtable ....................................................................................................................................... 1 • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection............................... 1 ChangesfromRevisionA(October2011)toRevisionB Page • Removed(SWIFT™)fromthedatasheettitle....................................................................................................................... 1 • Added"and10-pinDRC"totheDESCRIPTION.................................................................................................................... 1 • AddedtheDRC-10Pinpackagepinout................................................................................................................................ 3 • ChangedtheVBST(vsSW)MAXvalueFrom:5.7Vto6VintheROCtable......................................................................... 4 • AddedHigh-sideswitchresistance(DRC)............................................................................................................................. 5 • Addedaconditionsstatement"VIN=12V,T =25°C"totheTYPICALCHARACTERISTICS .......................................... 6 A • ChangedFigure11titleFrom:1.05-V,50-mAto2-ALOADTRANSIENTRESPONSETo:1.05-V,0-Ato2-ALOAD TRANSIENTRESPONSE.................................................................................................................................................... 13 • AddedFigure18................................................................................................................................................................... 16 ChangesfromOriginal(May2010)toRevisionA Page • CorrectedthepinnumbersforPins5through8.................................................................................................................... 3 • AddedR -ENpinresistancetoGNDtotheLOGICTHRESHOLDsectionoftheELECTRICAL EN CHARACTERISTICStable..................................................................................................................................................... 5 2 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 5 Pin Configuration and Functions DDAPackage 8-PinHSOP DRCPackage TopView 10-PinVSON TopView 1 EN VIN 8 EN 1 10 VIN VFB 2 Exposed 9 VIN Thermal 2 VFB VBST 7 VREG5 3 Dieo PnAD 8 VBST TPS54227 Underside (HSOP8) SS 4 PGND 7 SW 3 VREG5 PowerPADTM SW 6 GND 5 6 SW 4 SS GND 5 PinFunctions PIN I/O DESCRIPTION NAME DDA DRC EN 1 1 I Enableinputcontrol.ENisactivehighandmustbepulleduptoenablethedevice. Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Must Exposed — beconnectedtoGND. Thermal G Pad — Thermalpadofthepackage.PGNDpowergroundreturnofinternallow-sideFET.Must besolderedtoachieveappropriatedissipation. Groundpin.Powergroundreturnforswitchingcircuit.ConnectsensitiveSSandVFB GND 5 5 G returnstoGNDatasinglepoint. SS 4 4 O Soft-startcontrol.AnexternalcapacitorshouldbeconnectedtoGND. SW 6 6,7 O Switchnodeconnectionbetweenhigh-sideNFETandlow-sideNFET. Supplyinputforthehigh-sideFETgatedrivecircuit.Connect0.1-µFcapacitorbetween VBST 7 8 I VBSTandSWpins.AninternaldiodeisconnectedbetweenVREG5andVBST. VFB 2 2 I Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider. VIN 8 9,10 P Inputvoltagesupplypin. 5.5-Vpowersupplyoutput.Acapacitor(typical1µF)shouldbeconnectedtoGND. VREG5 3 3 O VREG5isnotactivewhenENislow. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VIN,EN –0.3 20 V VBST –0.3 26 V VBST(10-nstransient) –0.3 28 V Inputvoltage VBST(vsSW) –0.3 6.5 V VFB,SS –0.3 6.5 V SW –2 20 V SW(10-nstransient) –3 22 V VREG5 –0.3 6.5 V Outputvoltage GND –0.3 0.3 V VoltagefromGNDtothermalpad,V –0.2 0.2 V diff Operatingjunctiontemperature,T –40 150 °C J Storagetemperature,T –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyinputvoltagerange 4.5 18 V IN VBST –0.1 24 VBST(10nstransient) -0.1 27 VBST(vsSW) –0.1 6 SS –0.1 5.7 V Inputvoltagerange EN –0.1 18 V I VFB –0.1 5.5 SW –1.8 18 SW(10nstransient) –3 21 GND –0.1 0.1 V Outputvoltagerange VREG5 –0.1 5.7 V O I OutputCurrentrange I 0 10 mA O VREG5 T Operatingfree-airtemperature –40 85 °C A T Operatingjunctiontemperature –40 150 °C J 4 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 6.4 Thermal Information TPS54227 THERMALMETRIC(1) DDA(HSOP) DRC(VSON) UNIT 8PINS 10PINS R Junction-to-ambientthermalresistance 45.3 43.9 °C/W θJA R Junction-to-case(top)thermalresistance 54.8 55.4 °C/W θJC(top) R Junction-to-boardthermalresistance 16.2 18.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 6.6 0.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 16 19.1 °C/W JB R Junction-to-case(bottom)thermalresistance 8.5 5.3 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT IVIN Operating-non-switchingsupplycurrent VINcurrent,TA=25°C,EN=5V,VFB=0.8V 800 1200 μA IVINSDN Shutdownsupplycurrent VINcurrent,TA=25°C,EN=0V 5 10 μA LOGICTHRESHOLD VENH ENhigh-levelinputvoltage EN 1.6 V VENL ENlow-levelinputvoltage EN 0.6 V REN ENpinresistancetoGND VEN=12V 220 440 880 kΩ VFBVOLTAGEANDDISCHARGERESISTANCE VFBTH VFBthresholdvoltage TA=25°C,VO=1.05V,continuousmode 749 765 781 mV IVFB VFBinputcurrent VFB=0.8V,TA=25°C 0 ±0.1 μA VREG5OUTPUT VVREG5 VREG5outputvoltage TA=25°C,6V<VIN<18V,0<IVREG5<5mA 5.2 5.5 5.7 V VLN5 Lineregulation 6V<VIN<18V,IVREG5=5mA 25 mV VLD5 Loadregulation 0mA<IVREG5<5mA 100 mV IVREG5 Outputcurrent VIN=6V,VREG5=4V,TA=25°C 60 mA MOSFET High-sideswitchresistance(DDA) 155 RDS(on)h 25°C,VBST-SW=5.5V mΩ High-sideswitchresistance(DRC) 165 RDS(on)l Low-sideswitchresistance 25°C 108 mΩ CURRENTLIMIT Iocl Currentlimit Lout=2.2μH(1) 2.5 3.3 4.7 A THERMALSHUTDOWN Shutdowntemperature(1) 165 TSDN Thermalshutdownthreshold Hysteresis(1) 35 °C ON-TIMETIMERCONTROL tON ON-time VIN=12V,VO=1.05V 150 ns tOFF(MIN) MinimumOFF-time TA=25°C,VFB=0.7V 260 310 ns SOFT-START ISSC SSchargecurrent VSS=1V 1.4 2 2.6 μA ISSD SSdischargecurrent VSS=0.5V 0.1 0.2 mA UVLO WakeupVREG5voltage 3.45 3.75 4.05 UVLO UVLOthreshold V HysteresisVREG5voltage 0.13 0.32 0.48 (1) Notproductiontested. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com 6.6 Typical Characteristics VIN=12V,T =25°C(unlessotherwisenoted) A 1200 14 12 1000 A m urrent -Am 800 n Current - 108 VIN= 12 V I- Supply CCC 460000 csdn - Shutdow 46 c 200 Iv 2 0 0 -50 0 50 100 150 -50 0 50 100 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure1.VINCurrentvsJunctionTemperature Figure2.VINShutdownCurrentvs JunctionTemperature 100 100 90 VO= 3.3 V 90 80 A70 m 80 Current -5600 ncy - %70 VO= 2.5 V VO= 1.8 V EN - Input 3400 VIN= 18 V Efficie60 20 50 10 0 40 0 5 10 15 20 0 0.5 1 1.5 2 VI- Input Voltage - V IO- Output Current -A Figure3.ENCurrentvsENVoltage Figure4.EfficiencyvsOutputCurrent 900 900 850 850 Switching Frequency - kHz 566778505050000000 VO= 5 VVO= 1.8 VVOV=VO O1=.5= 3 V1.3.2 V V VO= 2.5 V Switching Frequency - kHz 566778505050000000 VO=V O1.=0 51 .V8 V VO= 3.3 V w - VO= 1.05 V w - fs 500 fs 500 450 450 400 400 0 5 10 15 20 0 0.5 1 1.5 2 VI- Input Voltage - V IO- Output Current -A Figure5.SwitchingFrequencyvsInputVoltage Figure6.SwitchingFrequencyvs OutputCurrent 6 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 Typical Characteristics (continued) VIN=12V,T =25°C(unlessotherwisenoted) A 0.780 0.775 V e - 0.770 g a olt V b 0.765 Vf - H VFBT 0.760 0.755 0.750 -50 0 50 100 150 TJ- JunctionTemperature -oC Figure7.VfbVoltagevsJunctionTemperature Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com 7 Detailed Description 7.1 Overview The TPS54227 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESRoutputcapacitorsincludingceramicandspecialpolymertypes. 7.2 Functional Block Diagram EN1 EN VIN Logic VIN 8 VREG5 Control Logic 7 VBST Ref + SS +PWM VFB 1 shot SW VO 2 - 6 XCON ON VREG5 VREG5 Ceramic 3 Capacitor SGND SS 4 Softstart SS 5 GND PGND SGND + SW OCP - PGND VIN VREG5 UVLO Protection TSD Logic UVLO REF Ref 7.3 Feature Description 7.3.1 PWMOperation The main control loop of the TPS54227 is an adaptive ON-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant ON-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive ON-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2modecontrol. 8 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 Feature Description (continued) 7.3.2 PWMFrequencyandAdaptiveON-TimeControl TPS54227 uses an adaptive ON-time control scheme and does not have a dedicated on board oscillator. The TPS54227 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the ON-time one-shot timer. The ON-time is inversely proportional to the input voltage and proportional to the outputvoltage,therefore,whenthedutyratioisVOUT/VIN,thefrequencyisconstant. 7.3.3 Soft-StartandPrebiasdSoft-Start The soft-start function is adjustable. When the EN pin becomes high, 2-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start-up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 2μA. C6(nF)xVREF x1.1 C6(nF)x0.765x1.1 t (ms)= = SS I (mA) 2 SS (1) TheTPS54227containsauniquecircuittopreventcurrentfrombeingpulledfromtheoutputduringstart-upifthe output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft-start becomes greater than feedback voltage V ), the controller slowly activates synchronous rectification by starting FB the first low-side FET gate driver pulses with a narrow ON-time. It then increments that ON-time on a cycle-by- cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the prebias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal modeoperation. 7.3.4 CurrentProtection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the ON-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the ON-time and the output inductor value. During the ON-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I . The TPS54227 constantly OUT monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side ON-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching cycle begins. In subsequent switching cycles, the ON-time is set to a fixed value and the current is monitored in the same manner. If the overcurrent condition exists for 7 consecutive switching cycles, the internal OCLthresholdissettoalowerlevel,reducingtheavailableoutputcurrent.Whenaswitchingcycleoccurswhere the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the highervalue. There are some important considerations for this type of overcurrent protection. The load current one half of the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the overcurrent condition is removed, the output voltagereturnstotheregulatedvalue.Thisprotectionisnon-latching. 7.3.5 UVLOProtection Undervoltage lockout protection (UVLO) monitors the voltage of the V pin. When the V voltage is lower REG5 REG5 thanUVLOthresholdvoltage,theTPS54227isshutoff.Thisisprotectionisnon-latching. 7.3.6 ThermalShutdown TPS54227 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), thedeviceisshutoff.Thisisnon-latchprotection. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com 7.4 Device Functional Modes 7.4.1 NormalOperation When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS54227 operates in normal switching mode. Normal continuous conduction mode (CCM) occurs when the minimumswitchcurrentisabove0A.InCMtheTPS54227operatesataquasi-fixedfrequencyof650kHz. 7.4.2 ForcedCCMOperation When the TPS54227 is in normal CCM operating mode and the switch current falls below 0 A, the device begins operatinginforcedCCM. 10 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54227 is used as a step converter that converts a voltage of 4.5 to 18 V to a lower voltage. WEBENCH™softwareisavailabletoaidinthedesignandanalysisofcircuits. 8.2 Typical Application U1 TPS54227DDA Figure8. TypicalApplication 8.2.1 DesignRequirements Table1liststhedesignrequirementsforthisexample. Table1.DesignRequirements SPECIFICATIONS TESTCONDITIONS MIN TYP MAX UNIT Inputvoltage 4.5 12 18 V Outputvoltage 1.05 V Operatingfrequency V =12V,I =1A 700 kHz IN o Outputcurrentrange 0 12 A Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com 8.2.2 DetailedDesignProcedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent • Outputvoltageripple • Inputvoltageripple 8.2.2.1 OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1% toleranceorbetterdividerresistors.StartbyusingEquation2tocalculateV . OUT To improve efficiency at very light loads consider using larger value resistors, too high of resistance is more susceptibletonoiseandvoltageerrorsfromtheVFBinputcurrentismorenoticeable. æ R1ö VOUT =0.765x çççè1+ R2÷÷÷÷ø (2) 8.2.2.2 OutputFilterSelection TheoutputfilterusedwiththeTPS54227isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L xC OUT OUT (3) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54227. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable2. Table2.RecommendedComponentValues OutputVoltage(V) R1(kΩ) R2(kΩ) C4(pF)(1) L1(µH) C8+C9(µF) 1 6.81 22.1 1.5-2.2 22-68 1.05 8.25 22.1 1.5-2.2 22-68 1.2 12.7 22.1 2.2 22-68 1.5 21.5 22.1 2.2 22-68 1.8 30.1 22.1 5-22 3.3 22-68 2.5 49.9 22.1 5-22 3.3 22-68 3.3 73.2 22.1 5-22 3.3 22-68 5 124 22.1 5-22 4.7 22-68 6.5 165 22.1 5-22 4.7 22-68 (1) Optional Because the DC gain is dependent on the output voltage, the required inductor value increases as the output voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by addingafeedforwardcapacitor(C4)inparallelwithR1 The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for f . SW Use 700 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS SW currentofEquation6. 12 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 I = VOUT x VIN(max) -VOUT IPP V L x f IN(max) O SW (4) I lpp I =I + Ipeak O 2 (5) 1 I = I 2 + I 2 Lo(RMS) O 12 IPP (6) For this design example, the calculated peak current is 2.311 A and the calculated RMS current is 2.008 A. The inductorusedisaTDKCLF7045T-2R2Mwithapeakcurrentratingof5.5AandanRMScurrentratingof4.3A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54227 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 7 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V x(V -V ) I = OUT IN OUT Co(RMS) 12 xV xL x f IN O SW (7) For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.18Aandeachoutputcapacitorisratedfor4A. 8.2.2.3 InputCapacitorSelection The TPS54227 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1-µF capacitor(C3)frompin8togroundisoptionaltoprovideadditionalhighfrequencyfiltering.Thecapacitorvoltage ratingneedstobegreaterthanthemaximuminputvoltage. 8.2.2.4 BootstrapCapacitorSelection A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI recommendstouseaceramiccapacitor. 8.2.2.5 VREG5CapacitorSelection A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. TI recommendstouseaceramiccapacitor. 8.2.3 ApplicationCurves 1.1 1.08 V = 1.8 V 1.075 VI= 1.2 V I 1.07 - Output Voltage - V 1.05 VI= 5 V - Output Voltage - VO1.06 IO= 0A IO= 1A O V V1.025 1.05 1.04 1 0 5 10 15 20 0 0.5 1 1.5 2 IO- Output Current -A VI- Input Voltage - V Figure9.1.05-VOutputVoltagevsOutputCurrent Figure10.1.05-VOutputVoltagevsInputVoltage Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com EN (10 V/div) Vout (50 mV/div) VREG5 (5 V/div) Iout (1A/div) Vout (0.5 V/div) 100ms/div t - Time - 1 ms Figure11.1.05-V,0-Ato2-ALoadTransientResponse Figure12.Start-UpWaveform VO= 1.05 V VO= 1.05 V VO(10 mV/div) VIN (50 mV/div) SW (5 V/div) SW (5 V/div) t - Time - 400 ns t - Time - 400 ns Figure13.VoltageRippleatOutput(IO=2A) Figure14.VoltageRippleatOutput(IO=2A) 100 100 90 90 80 80 70 70 % % y - 60 y - 60 nc 50 nc 50 e e Effici 40 Effici 40 30 30 20 20 10 VIN = 5 V 10 VIN = 5 V VIN = 12 V VIN = 12 V 0 0 0 0.5 1 1.5 2 0.01 0.1 1 10 Output Current - A Output Current - A D001 D001 Figure15.TPS54227EVM-686Efficiency Figure16.TPS54227EVM-686LightLoadEfficiency 14 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 9 Power Supply Recommendations The TPS54227 is designed to operate from input supply voltage in the range of 4.5 V to 18 V. Buck converters requiretheinputvoltagetobehigherthantheoutputvoltage. 10 Layout 10.1 Layout Guidelines 1. Keeptheinputswitchingcurrentloopassmallaspossible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedbackpinofthedevice. 3. Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. 4. Makeasinglepointconnectionfromthesignalgroundtopowerground. 5. Donotallowswitchingcurrenttoflowunderthedevice. 6. KeepthepatternlinesforVINandPGNDbroad. 7. ExposedpadofdevicemustbeconnectedtoPGNDwithsolder. 8. VREG5capacitorshouldbeplacednearthedevice,andconnectedPGND. 9. OutputcapacitorshouldbeconnectedtoabroadpatternofthePGND. 10. Voltagefeedbackloopshouldbeasshortaspossible,andpreferablywithgroundshield. 11. LowerresistorofthevoltagedividerwhichisconnectedtotheVFBpinshouldbetiedtoSGND. 12. ProvidingsufficientviaispreferableforVIN,SWandPGNDconnection. 13. PCBpatternforVIN,SW,andPGNDshouldbeasbroadaspossible. 14. VINCapacitorshouldbeplacedasnearaspossibletothedevice. 10.2 Layout Examples VIN VIN INPUT BYPASS CAPACITOR VIN HIGH FREQENCY BYPASS FEEDBACK CAPACITOR RESISTORS TO ENABLE CONTROL EN VIN BOOST VFB VBST CAPACITOR VREG5 SW OUTPUT VOUT BCIAAPS SS GND INDUCTOR SLOW START CAP EXPOSED THERMALPAD AREA OUTPUT Connection to POWER GROUND FILTER on internal or CAPACITOR bottom layer ANALOG GROUND TRACE POWER GROUND VIAto Ground Plane Figure17. PCBLayoutfortheDDAPackage Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54227

TPS54227 SLVSAU2C–MAY2011–REVISEDDECEMBER2015 www.ti.com Layout Examples (continued) VIN VIN INPUT BYPASS CAPACITOR VIN HIGH FREQENCY FEEDBACK BYPASS RESISTORS TO ENABLE CAPACITOR CONTROL EN VIN VFB VIN BOOST VREG5 VBST CAPACITOR BIAS VOUT CAP SS SW SLOW START GND SW OUTPUT CAP INDUCTOR EXPOSED OUTPUT THERMALPAD FILTER ANALOG AREA CAPACITOR GROUND Connection to TRACE PonO iWntEerRn aGl RorOUND POWER GROUND bottom layer VIAto Ground Plane Figure18. PCBLayoutfortheDRCPackage 10.3 Thermal Considerations This 8-pin HSOP package incorporates an exposed thermal pad that is designed to be directly to an external heartsick. The thermal pad must be soldered directly to the printed-circuit-board (PCB). After soldering, the PCB can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integratedcircuit(IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SLMA004). TheexposedthermalpaddimensionsforthispackageareshowninFigure19. Figure19. ThermalPadDimensions(TopView) 16 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54227

TPS54227 www.ti.com SLVSAU2C–MAY2011–REVISEDDECEMBER2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • PowerPAD™ThermallyEnhancedPackage,SLMA002 • PowerPAD™MadeEasy,SLMA004 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks D-CAP2,WEBENCH,PowerPAD,E2EaretrademarksofTexasInstruments. Blu-rayDiscisatrademarkofBlu-rayDiscAssociation. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54227

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54227DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54227 & no Sb/Br) TPS54227DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54227 & no Sb/Br) TPS54227DRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54227 & no Sb/Br) TPS54227DRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54227 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54227DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD TPS54227DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54227DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54227DDAR SOPowerPAD DDA 8 2500 366.0 364.0 50.0 TPS54227DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS54227DRCT VSON DRC 10 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4202561/G

None

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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