TPS2112 Actual Size TPS2113 www.ti.com (3,10 mm x 4,50 mm) SLVS446 – DECEMBER 2002 AUTOSWITCHING POWER MUX FEATURES APPLICATIONS (cid:1) Two-Input, One-Output Power Multiplexer (cid:1) PCs With Low rDS(on) Switches: (cid:1) PDAs – 84 mΩ Typ (TPS2113) (cid:1) Digital Cameras – 120 mΩ Typ (TPS2112) (cid:1) (cid:1) Modems Reverse and Cross-Conduction Blocking (cid:1) (cid:1) Cell phones Wide Operating Voltage Range . . . .2.8 V to (cid:1) 5.5 V Digital Radios (cid:1) Low Standby Current . . . . 0.5-µA Typ (cid:1) MP3 Players (cid:1) Low Operating Current . . . . 55-µA Typ (cid:1) PW PACKAGE Adjustable Current Limit (TOP VIEW) (cid:1) Controlled Output Voltage Transition Times, Limits Inrush Current and Minimizes Output STAT 1 8 IN1 Voltage Hold-Up Capacitance EN 2 7 OUT (cid:1) VSNS 3 6 IN2 CMOS and TTL Compatible Control Inputs ILIM 4 5 GND (cid:1) Auto-Switching Operating Mode (cid:1) Thermal Shutdown (cid:1) Available in a TSSOP-8 Package DESCRIPTION The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as a battery and a wall adapter, each operating at 2.8–5.5 V and delivering up to 1 A. The TPS211x family includes extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power multiplexer applications. TYPICAL APPLICATION Switch Status IN1: 2.8 – 5.5 V R1 TPS2113PW 0.1 µF 1 8 STAT IN1 2 7 EN OUT 3 6 VSNS IN2 CL RL 4 5 ILIM GND RILIM IN2: 2.8 – 5.5 V 0.1 µF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products Copyright  2002, Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS FEATURE TPS2110 TPS2111 TPS2112 TPS2113 TPS2114 TPS2115 Current Limit Adjustment Range 0.31–0.75A 0.63–1.25A 0.31–0.75A 0.63–1.25A 0.31–0.75A 0.63–1.25A Manual Yes Yes No No Yes Yes SSwwiittcchhiinngg mmooddeess Automatic Yes Yes Yes Yes Yes Yes Switch Status Output No No Yes Yes Yes Yes Package TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 ORDERING INFORMATION TA PACKAGE ORDERING NUMBER(1) MARKINGS TPS2112PW 2112 –4400°°CC tto 8855°°CC TTSSSSOOPP-88 ((PPWW)) TPS2113PW 2113 (1)The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2112PWR) to indicate tape and reel. PACKAGE DISSIPATION RATINGS DERATING FACTOR ABOVE TA ≤ 25°C TA = 70°C TA = 85°C PACKAGE TA = 25°C POWER RATING POWER RATING POWER RATING TSSOP-8 (PW) 3.87 mW/°C 386.84 mW 212.76 mW 154.73 mW ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS2112, TPS2113 Input voltage range at pins IN1, IN2, EN, VSNS, ILIM(2) –0.3 V to 6 V Output voltage range, VO(OUT), VO(STAT)(2) –0.3 V to 6 V Output sink current, IO(STAT) 5 mA TPS2112 0.9 A CCoonnttiinnuuoouuss oouuttppuutt ccuurrrreenntt, IIOO TPS2113 1.5 A Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, TJ –40°C to 125°C Storage temperature range, Tstg –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)All voltages are with respect to GND. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VI(IN2) ≥ 2.8 V 1.5 5.5 IInnppuutt vvoollttaaggee aatt IINN11, VVI(IN1) VV VI(IN2) < 2.8 V 2.8 5.5 VI(IN1) ≥ 2.8 V 1.5 5.5 IInnppuutt vvoollttaaggee aatt IINN22, VVI(IN2) VV VI(IN1) < 2.8 V 2.8 5.5 Input voltage, VI(EN), VI(VSNS) 0 5.5 V TPS2112 0.31 0.75 CCuurrrreenntt lliimmiitt aaddjjuussttmmeenntt rraannggee, IIO(OUT) AA TPS2113 0.63 1.25 Operating virtual junction temperature, TJ –40 125 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX UNIT Human body model 2 kV CDM 500 V 2

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted) TPS2112 TPS2113 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX MIN TYP MAX POWER SWITCH VI(IN1) = VI(IN2) = 5.0 V 120 140 84 110 TTJ = 2255°°CC, VI(IN1) = VI(IN2) = 3.3 V 120 140 84 110 mmΩΩ DDraiin-source IILL == 550000 mmAA rrDDSS((on))((11)) oonn-ssttaattee rreessiissttaannccee VI(IN1) = VI(IN2) = 2.8 V 120 140 84 110 ((IINNxx––OOUUTT)) TTJ = 112255°°CC, VVII((IINN11)) == VVII((IINN22)) == 53..03 VV 222200 115500 mΩ IILL == 550000 mmAA VI(IN1) = VI(IN2) = 2.8 V 220 150 (1)The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUTS (EN) VIH High-level input voltage 2 V VIL Low-level input voltage 0.7 V EN = High, sink current 1 IInnppuutt ccuurrrreenntt µµAA EN = Low, source current 0.5 1.4 5 SUPPLY AND LEAKAGE CURRENTS VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V, 55 90 VI(IN2) = 3.3 V, IO(OUT) = 0 A VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 3.3 V, 1 12 SSuuppllyy ccuurrrreenntt ffrroomm IINN11 VI(IN2) = 5.5 V, IO(OUT) = 0 A µµAA (operating) VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V, 75 VI(IN2) = 3.3 V, IO(OUT) = 0 A VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 3.3 V, 1 VI(IN2) = 5.5 V, IO(OUT) = 0 A VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V, 1 VI(IN2) = 3.3 V, IO(OUT) = 0 A VI(VSNS) = 1.5 V, EN =Low (IN1 active), VI(IN1) = 3.3 V, 75 SSuuppllyy ccuurrrreenntt ffrroomm IINN22 VI(IN2) = 5.5 V, IO(OUT) = 0 A µµAA (operating) VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V, 1 12 VI(IN2)= 3.3 V, IO(OUT) = 0 A VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 3.3 V, 55 90 VI(IN2) =5.5 V, IO(OUT) = 0 A QQuuiieesscceenntt ccuurrrreenntt ffrroomm IINN11 EN = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 0.5 2 µµAA (STANDBY) EN = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 1 QQuuiieesscceenntt ccuurrrreenntt ffrroomm IINN22 EN = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V, IO(OUT) = 0 A 1 µµAA (STANDBY) EN = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A 0.5 2 Forward leakage current from IN1 EN = High (inactive), VI(IN1) = 5.5 V, IN2 open, 0.1 5 µA (measured from OUT to GND) VO(OUT) = 0 V (shorted), TJ = 25°C Forward leakage current from IN2 EN = High (inactive), VI(IN2) = 5.5 V, IN1 open, 0.1 5 µA (measured from OUT to GND) VO(OUT) = 0 V (shorted), TJ = 25°C Reverse leakage current to INx (measured from INx to GND) EN = High (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TJ = 25°C 0.3 5 µA STAT OUTPUT Leakage current VO(STAT) = 5.5 V 0.01 1 µA Saturation voltage II(STAT) = 2 mA, IN1 switch is on 0.13 0.4 V Deglitch time (falling edge only) 150 µs 3

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT CIRCUIT RILIM = 400 Ω 0.51 0.63 0.80 TTPPSS22111122 RILIM = 700 Ω 0.30 0.36 0.50 CCuurrrreenntt lliimmiitt aaccccuurraaccyy AA RILIM = 400 Ω 0.95 1.25 1.56 TTPPSS22111133 RILIM = 700 Ω 0.47 0.71 0.99 Time for short–circuit output current to td Current limit settling time(1) settle within 10% of its steady state value. 1 ms Input current at ILIM VI(ILIM) = 0 V, IO(OUT) = 0 A –15 0 µA (1)Not tested in production. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSNS COMPARATOR VI(VSNS) ↑ 0.78 0.8 0.82 VVSSNNSS tthhrreesshhoolldd vvoollttaaggee VV VI(VSNS) ↓ 0.735 0.755 0.775 VSNS comparator hysteresis(1) 30 60 mV Deglitch of VSNS comparator (both ↑↓)(1) 90 150 220 µs Input current 0 V≤ VI(VSNS)≤ 5.5 V –1 1 µA UVLO Falling edge 1.15 1.25 IINN11 aanndd IINN22 UUVVLLOO VV Rising edge 1.30 1.35 IN1 and IN2 UVLO hysteresis(1) 30 57 65 mV Falling edge 2.4 2.53 IInntteerrnnaall VVDD UUVVLLOO ((tthhee hhiigghheerr ooff IINN11 aanndd IINN22)) VV Rising edge 2.58 2.8 Internal VDD UVLO hysteresis(1) 30 50 75 mV UVLO deglitch for IN1, IN2(1) Falling edge 110 µs (1)Not tested in production. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REVERSE CONDUCTION BLOCKING EN = high, VI(IN1) = 3.3 V and VI(IN2) = VI(VSNS) = Minimum output-to-input voltage 0 V. Connect OUT to a 5 V supply through a series ∆VO(I_block) difference to block switching 1-kΩ resistor. Let EN = low. Slowly decrease the 80 100 120 mV supply voltage until OUT connects to IN1. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN Thermal shutdown threshold(1) TPS211x is in current limit. 135 Recovery from thermal shutdown(1) TPS211x is in current limit. 125 °CC Hysteresis(1) 10 IN2–IN1 COMPARATORS Hysteresis of IN2–IN1 comparator 0.1 0.2 V Deglitch of IN2–IN1 comparator, (both ↑↓)(1) 90 150 220 µs (1)Not tested in production. 4

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 SWITCHING CHARACTERISTICS over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted) TPS2112 TPS2113 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX MIN TYP MAX POWER SWITCH Output rise time from VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 1 µF, tr an enable(1) VI(VSNS) = 1.5 V IL = 500 mA, 0.5 1.0 1.5 1 1.8 3 ms See Figure 1(a) Output fall time from VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 1 µF, tf a disable(1) VI(VSNS) = 1.5 V IL = 500 mA, 0.35 0.5 0.7 0.5 1 2 ms See Figure 1(a) TJ = 125°C, CL = 10 µF, IN1 to IN2 transition, IL = 500 mA [Measure transition time tt Transition time(1) VVII((IINN12)) == 35. V3 ,V, as 10–90% rise time or 40 60 40 60 µs from 3.4 V to 4.8 V on VI(EN) = 0 V VO(OUT)], See Figure 1(b) Turn-on propagation VMIe(IaNs1u)r e=d V fIr(oINm2 e) n=a 5b leV to TJ = 25°C, CL = 10 µF, tPLH1 delay from enable(1) 10% of VO(OUT), ISLe =e 5F0ig0u mreA 1,(a) 0.5 1 ms VI(VSNS) = 1.5 V Turn-off propagation VI(IN1) = VI(IN2) = 5 V, TJ = 25°C, CL = 10 µF, Measured from disable tPHL1 delay from a IL = 500 mA, 3 5 ms disable(1) to 90% of VO(OUT), See Figure 1(a) VI(VSNS) = 1.5 V Logic 1 to Logic 0 transition on VSNS , Switch-over rising VI(IN1) = 1.5 V, TJ = 25°C, CL = 10 µF, tPLH2 propagation delay(1) VI(IN2) = 5 V, IL = 500 mA, 0.17 1 0.17 1 ms VI(EN) = 0 V, See Figure 1(c) Measured from VSNS to 10% of VO(OUT) Logic 0 to Logic 1 transition on VSNS Switch-over falling VI(IN1) = 1.5V, TJ = 25°C, CL = 10 µF, tPHL2 propagation delay(1) VI(IN2) = 5V, IL = 500 mA, 2 3 10 2 5 10 ms VI(EN) = 0 V, See Figure 1(c) Measured from VSNS to 90% of VO(OUT) (1)Not tested in production. 5

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TRUTH TABLE EN VI(VSNS) > 0.8V VI(IN2) > VI(IN1) STAT OUT(1) Yes X 0 IN1 00 No No 0 IN1 No Yes Hi-Z IN2 1 X X 0 Hi-Z (1)The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if neither of the supplies exceeds the internal VDD UVLO. Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. EN 2 I EN is a TTL and CMOS compatible input with a 1-µA pull-up. The truth table shown above illustrates the functionality of EN. GND 5 I Ground IN1 8 I Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. IN2 6 I Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO. ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2112 and TPS2113, respectively. OUT 7 O Power switch output STAT 1 O STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0) VSNS 3 I An internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT to the higher of IN1 and IN2. The truth table shown above illustrates the functionality of VSNS. 6

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 FUNCTIONAL BLOCK DIAGRAM Internal VDD 1 µA Vf = 0 V Vf = 0 V IO(OUT) Q1 8 7 IN1 OUT 6 Q2 Charge IN2 Pump k* IO(OUT) VDD TPS2112: k = 0.2% ULVO _ TPS2113: k = 0.1% 4 ILIM IN2 + 0.5 V ULVO Cross-Conduction UILNV1O Detector + 0.6 V + + _ _ EN2 EN1 Q2 is ON Q1 is ON 100 mV UVLO (VDD) + UVLO (IN2) VO(OUT) > VI(INx) + _ UVLO (IN1) EN1 2 Control Thermal EN Logic Sense 3 VSNS + VI(VSNS) >0.8 V VI(IN2) > VI(IN1) + IN2 _ _ 0.8 V IN1 5 GND 1 STAT Q2 is ON 7

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VO(OUT) 90% 90% 10% 10% 0 V tr tf tPLH1 tPHL1 EN Switch Off Switch Enabled Switch Off (a) 4.8 V 5 V VO(OUT) 3.4 V 3.3 V tt VSNS Switch #1 Enabled Switch #2 Enabled (b) 5 V 4.65 V VO(OUT) 1.85 V 1.5 V tPLH2 tPHL2 VSNS Switch #1 Enabled Switch #2 Enabled Switch #1 Enabled (c) Figure 1. Propagation Delays and Transition Timing Waveforms 8

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TYPICAL CHARACTERISTICS OUTPUT SWITCHOVER RESPONSE 3.3 V VI(VSNS) TPS2113PW 0.1 µF 1 8 NC STAT IN1 f = 28 Hz 2 7 2V/DIV 22% Duty Cycle EN OUT 3 6 1 µF VSNS IN2 50 Ω 4 5 ILIM GND 400 Ω 5 V VO(OUT) 0.1 µF 2V/DIV Output Switchover Response Test Circuit t – Time – 1 ms/div Figure 2 OUTPUT TURN-ON RESPONSE VI(EN) 2V/Div 5 V TPS2113PW 0.1 µF f = 28 Hz 1 8 78% Duty Cycle NC STAT IN1 2 7 EN OUT 3 6 1 µF VSNS IN2 50 Ω 4 5 ILIM GND 400 Ω VO(OUT) 2V/Div Output Turn-On Response Test Circuit t – Time – 2 ms/div Figure 3 9

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TYPICAL CHARACTERISTICS OUTPUT SWITCHOVER VOLTAGE DROOP VI(VSNS) 2V/Div CL = 1 µF VO(OUT) 2V/Div CL = 0 µF t – Time – 40 µs/div 5 V SW1 1 kΩ TPS2113PW 0.1 µF 1 8 NC STAT IN1 f = 580 Hz 2 7 90% Duty Cycle EN OUT 3 6 VSNS IN2 CL 50 Ω 4 5 ILIM GND 400 Ω 0.1 µF Output Switchover Voltage Droop Test Circuit Figure 4 NOTE: To initialize the TPS2113 for this test, set input VSNS equal to 0 V, turn on the 5 V supply, and then turn on switch SW1. 10

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TYPICAL CHARACTERISTICS OUTPUT SWITCHOVER VOLTAGE DROOP vs LOAD CAPACITANCE 5 VI = 5 V 4.5 V – 4 p o o 3.5 r D ge 3 RL = 10 Ω a olt V 2.5 ut p ut 2 O – 1.5 T) U O(O 1 RL = 50 Ω V ∆ 0.5 0 0.1 1 10 100 CL – Load Capacitance – µF VI SW1 1 kΩ TPS2113PW 0.1 µF 1 8 f = 28 Hz NC STAT IN1 2 7 50% Duty Cycle EN OUT 3 6 VSNS IN2 4 5 ILIM GND 400 Ω 50 Ω 10 Ω 0.1 µF 0.1 µF 1 µF 10 µF 47 µF 100 µF Output Switchover Voltage Droop Test Circuit Figure 5 NOTE: To initialize the TPS2113 for this test, set input VSNS equal to 0 V, turn on the supply Vi, and then turn on switch SW1. 11

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TYPICAL CHARACTERISTICS INRUSH CURRENT vs LOAD CAPACITANCE 300 250 A 200 m – VI = 5 V nt e rr 150 u C sh VI = 3.3 V u r 100 n I – I I 50 0 0 20 40 60 80 100 CL – Load Capacitance – µF VI TPS2113PW 90%f =D u2t8y HCzycle NC 1 STAT IN1 8 0.1 µF To Oscilloscope 2 7 EN OUT 3 6 VSNS IN2 4 ILIM GND 5 50 Ω 400 Ω 0.1 µF 1 µF 10 µF 47 µF 100 µF Output Capacitor Inrush Current Test Circuit Figure 6 12

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TYPICAL CHARACTERISTICS SWITCH ON-RESISTANCE SWITCH ON-RESISTANCE vs vs JUNCTION TEMPERATURE SUPPLY VOLTAGE 180 120 TPS2112 Ω 115 Ωm 160 – m e – ce 110 c TPS2112 n n a sta 140 sist 105 si e e R n-R 120 On- 100 O h h c witc TPS2113 Swit 95 S 100 – – n) on) 90 DS(o 80 rDS( 85 TPS2113 r 60 80 –50 0 50 100 150 2 3 4 5 6 TJ – Junction Temperature – °C VI(INx) – Supply Voltage – V Figure 7 Figure 8 IN1 SUPPLY CURRENT IN1 SUPPLY CURRENT vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 0.96 60 IN1 Switch is ON Device Disabled 58 VI(IN2) = 0 V, 0.94 VI(IN2) = 0 V IO(OUT) = 0 A A IO(OUT) = 0 A A 56 µ µ nt – 0.92 nt – 54 e e r r ur ur 52 C 0.90 C y y pl pl 50 p p Su 0.88 Su 1 1 48 N N – IN1) 0.86 – IN1) 46 I(I II(I 44 I 0.84 42 0.82 40 2 3 4 5 6 2 3 4 5 6 VI(IN1)– IN1 Supply Voltage – V VI(IN1) – Supply Voltage – V Figure 9 Figure 10 13

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT SUPPLY CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 1.2 80 Device Disabled IN1 Switch is ON VI(IN1) = 5.5 V 70 VI(IN1) = 5.5 V, 1 VI(IN2) = 3.3 V VI(IN2) = 3.3 V A IO(OUT) = 0 A A IO(OUT) = 0 A µSupply Current – 00..68 II(IN1) = 5.5 V µSupply Current – 456000 II(IN1) – 0.4 – 30 Nx) Nx) II(I 0.2 II(I 20 10 II(IN2) = 3.3 V II(IN2) 0 0 –50 0 50 100 150 –50 0 50 100 150 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 11 Figure 12 14

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 APPLICATION INFORMATION Some applications have two energy sources, one of which should be used in preference to another. Figure 13 shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified threshold. Once the voltage on IN1 falls below this threshold, the TPS2112/3 will select the higher of the two supplies. This usually means that the TPS2112/3 will swap to IN2. Switch Status IN1: 2.8 – 5.5 V TPS2113PW R3 0.1 µF 1 8 STAT IN1 R1 2 7 EN OUT 3 6 VSNS IN2 CL RL 4 5 ILIM GND R2 RILIM IN2: 2.8 – 5.5 V 0.1 µF Figure 13. Auto-Selecting for a Dual Power Supply Application In Figure 14, the multiplexer selects between two power supplies based upon the EN logic signal. OUT connects to IN1 if EN is logic 1, otherwise OUT connects to IN2. The logic thresholds for the EN terminal are compatible with both TTL and CMOS logic. Switch Status IN1: 2.8 – 5.5 V R1 TPS2113PW 0.1 µF 1 8 STAT IN1 2 7 EN OUT 3 6 VSNS IN2 CL RL 4 5 ILIM GND RILIM IN2: 2.8 – 5.5 V 0.1 µF Figure 14. Manually Switching Power Sources 15

TPS2112 TPS2113 www.ti.com SLVS446 – DECEMBER 2002 DETAILED DESCRIPTION AUTO-SWITCHING MODE The TPS2112/3 only supports the auto-switching mode. In this mode, OUT connects to IN1 if V is greater I(VSNS) than 0.8V, otherwise OUT connects to the higher of IN1 and IN2. The VSNS terminal includes hysteresis equal to 3.75–7.5% of the threshold selected for transition from the primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply to the other due to resistive drops. N-CHANNEL MOSFETs Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET switch if the output voltage is greater than the input voltage. CROSS-CONDUCTION BLOCKING The switching circuitry ensures that both power switches will never conduct at the same time. A comparator monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of the other FET is below the turn-on threshold voltage. REVERSE-CONDUCTION BLOCKING When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211x will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output voltage. CHARGE PUMP The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages. A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET. CURRENT LIMITING A resistor RILIM from ILIM to GND sets the current limit to 250/ RILIM and 500/RILIM for the TPS2112 and TPS2113, respectively. Setting resistor R equal to zero is not recommended as that disables current limiting. ILIM OUTPUT VOLTAGE SLEW-RATE CONTROL The TPS2112/3 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state (see Truth Table). ). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the connector power contacts, when hot plugging a load like a PCI card. The TPS2112/3 slews the output voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output voltage droop and reduces the output voltage hold-up capacitance requirement. 16

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS2112PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 2112 & no Sb/Br) TPS2112PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 2112 & no Sb/Br) TPS2112PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 2112 & no Sb/Br) TPS2113PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 2113 & no Sb/Br) TPS2113PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 2113 & no Sb/Br) TPS2113PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 2113 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS2112PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TPS2113PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS2112PWR TSSOP PW 8 2000 367.0 367.0 35.0 TPS2113PWR TSSOP PW 8 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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