TC7650 Chopper Stabilized Operational Amplifier Features Package Type • Low Input Offset Voltage: 0.7µV Typ 8-Pin DIP • Low Input Offset Voltage Drift: 0.05V/°C Max • Low Input Bias Current: 10pA Max CA 1 8 CB • High Impedance Differential CMOS Inputs: 1012 –INPUT 2 7 VDD • High Open Loop Voltage Gain: 120dB Min. • Low Input Noise Voltage: 2.0Vp-p +INPUT 3 TC7650CPA 6 OUTPUT • High Slew Rate: 2.5V/sec. VSS 4 5 OUTPUT CLAMP • Low Power Operation: 20mW • Output Clamp Speeds Recovery Time • Compensated Internally for Stable Unity Gain 14-Pin DIP Operation • Direct Replacement for ICL7650 CB 1 14 INT/EXT • Available in 8-Pin Plastic DIP and 14-Pin Plastic CA 2 13 EXT CLK IN DIP Packages NC 3 12 INT CLK OUT Applications –INPUT 4 TC7650CPD 11 VDD • Instrumentation +INPUT 5 10 OUTPUT • Medical Instrumentation • Embedded Control NC 6 9 OUTPUT CLAMP • Temperature Sensor Amplifier VSS 7 8 CRETN • Strain Gage Amplifier Device Selection Table NC = NO INTERNAL CONNECTION Part Temperature Package Max V Number Range OS TC7650CPA 8-Pin PDIP 0°C to +70°C 5V TC7650CPD 14-Pin PDIP 0°C to +70°C 5V  2001-2012 Microchip Technology Inc. DS21463C-page 1

TC7650 General Description The TC7650 nulling scheme corrects both DC V OS errors and V drift errors with temperature. A nulling The TC7650 CMOS chopper stabilized operational OS amplifier alternately corrects its own V errors and the amplifier practically removes offset voltage error terms OS main amplifier V error. Offset nulling voltages are from system error calculations. The 5V maximum V OS OS stored on two user supplied external capacitors. The specification, for example, represents a 15 times capacitors connect to the internal amplifier V null improvement over the industry standard OP07E. The OS points. The main amplifier input signal is never 50nV/°C offset drift specification is over 25 times lower switched. Switching spikes are not present at the than the OP07E. The increased performance elimi- TC7650 output. nates V trim procedures, periodic potentiometer OS adjustment and the reliability problems caused by dam- The 14-pin dual-in-line package (DIP) has an external aged trimmers. oscillator input to drive the nulling circuitry for optimum noise performance. Both the 8 and 14-pin DIPs have The TC7650 performance advantages are achieved an output voltage clamp circuit to minimize overload without the additional manufacturing complexity and recovery time. cost incurred with laser or "zener zap" V trim tech- OS niques. Functional Block Diagram Output 14-Pin DIP Only Clamp Output Clamp INT/EXT Circuit Oscillator EXT CLK IN CLK OUT Main Amplifier A B Inputs Output NULL CB Intermod Compensation B B B A CA Null Amplifier TC7650 A Null *CRETN *For 8-Pin DIP, connect to Vss DS21463C-page 2  2001-2012 Microchip Technology Inc.

TC7650 1.0 ELECTRICAL *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. CHARACTERISTICS These are stress ratings only and functional operation of the device at these or any other conditions above those indi- ABSOLUTE MAXIMUM RATINGS* cated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions Total Supply Voltage (V to V ).......................+18V DD SS for extended periods my affect device reliability. Input Voltage....................(V +0.3V) to (V – 0.3V) DD SS Storage Temperature Range..............-65°C to +150°C Voltage on Oscillator Control Pins...............V to V DD SS Duration of Output Short Circuit.....................Indefinite Current Into Any Pin............................................10mA While Operating (Note 3)............................100µA Package Power Dissipation (T  70°C) A 8-Pin Plastic DIP.......................................730mW 14-Pin Plastic DIP.....................................800mW Operating Temperature Range C Device..........................................0°C to +70°C TC7652 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = +5V, VSS = -5V, CA = CB = 0.1F, TA = +25°C, unless otherwise indicated. Symbol Parameter Min. Typ Max Units Test Conditions Input VOS Input Offset Voltage — ±0.7 ±5 — TA = +25°C — ±1.0 — V Over Operating Temp Range VOS/T Input Offset Voltage Average — 0.01 0.05 V/°C Operating Temperature Range Temperature Coefficient Offset Voltage vs. Time — 100 — nV/ month IBIAS Input Bias Current — 1.5 10 pA TA = +25°C — 35 150 pA 0°C  TA  +70°C — 100 400 pA -25°C  TA  +85°C IOS Input Offset Current — 0.5 — pA eNP-P Input Noise Voltage — 2 — VP-P RS = 100, 0 to 10Hz IN Input Noise Current — 0.01 — pA/Hz f = 10Hz RIN Input Resistance — 1012  CMVR Common Mode Voltage Range -5 -5.2 to +2 +1.6 V CMRR Common Mode Rejection Ratio 120 130 — dB CMVR = -5V to +1.5V Output A Large Signal Voltage Gain 120 130 — dB RL = 10k VOUT Output Voltage Swing (Note 2) ±4.7 ±4.85 — V RL = 10k — ±4.95 — V RL = 100k Clamp ON Current 25 70 200 A RL = 100k (Note 1) Clamp OFF Current — 1 — pA -4V < VOUT < +4V (Note 1) Dynamic BW Unity Gain Bandwidth — 2.0 — MHz Unity Gain (+1) SR Slew Rate — 2.5 — V/sec CL = 50pF, RL = 10k tR Rise Time — 0.2 — sec Overshoot — 20 — % fCH Internal Chopping Frequency 120 200 375 Hz Pins 12–14 Open (DIP) Supply VDD, VSS Operating Supply Range 4.5 — 16 V IS Supply Current — 2 3.5 mA No Load PSRR Power Supply Rejection Ratio 120 130 dB VS = ±3V to ±8V Note 1: See "Output Clamp" discussion. 2: Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics. 3: Limiting input current to 100A is recommended to avoid latch-up problems.  2001-2012 Microchip Technology Inc. DS21463C-page 3

TC7650 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number Symbol Description 8-pin DIP 14-pin DIP 1,8 2,1 C , C Nulling capacitor pins A B 2 4 -INPUT Inverting Input 3 5 +INPUT Non-inverting Input 4 7 V Negative Power Supply SS 5 9 OUTPUT Output Voltage Clamp CLAMP 6 10 OUTPUT Output 7 11 V Positive Power Supply DD — 3,6 NC No internal connection — 8 C Capacitor current return pin RETN — 12 INT CLK OUT Internal Clock Output — 13 EXT CLK IN External Clock Input — 14 INT/EXT Select Internal or External Clock 3.0 DETAILED DESCRIPTION After the nulling amplifier is zeroed, the main amplifier is zeroed; the A switches open and B switches close. 3.1 Theory of Operation The output voltage equation is: Figure 3-1 shows the major elements of the TC7650. EQUATION 3-2: There are two amplifiers (the main amplifier and the nulling amplifier), and both have offset null capability. The main amplifier is connected full-time from the input V = A V + (V+ - V-) + A (V+ - V-) + A V  OUT M OSM N N OSE to the output. The nulling amplifier, under the control of the chopping frequency oscillator and clock circuit, alternately nulls itself and the main amplifier. Two exter- EQUATION 3-3: nal capacitors provide the required storage of the null- ing potentials and the necessary nulling loop time + - VOSM+VOSN V = A A V –V +------------------------------------------- constants. The nulling arrangement operates over the OUT M N A N full common mode and power supply ranges, and is also independent of the output level, thus giving excep- As desired, the device offset voltages are reduced by tionally high CMRR, PSRR and A . VOL the high open loop gain of the nulling amplifier. Careful balancing of the input switches minimizes chopper frequency charge injection at the input termi- 3.2 Output Stage/Loading nals, and the feed forward type injection into the com- pensation capacitor that can cause output spikes in this The output circuit is a high impedance stage (approxi- type of circuit. mately 18k). With loads less than this, the chopper The circuit's offset voltage compensation is easily amplifier behaves in some ways like a trans-conduc- shown. With the nulling inputs shorted, a voltage tance amplifier whose open-loop gain is proportional to almost identical to the nulling amplifier offset voltage is load resistance. For example, the open loop gain will stored on C . The effective offset voltage at the null be 17dB lower with a 1k load than with a 10k load. A amplifier input is: If the amplifier is used strictly for DC, the lower gain is of little consequence, since the DC gain is typically greater than 120dB, even with a 1k load. In wideband EQUATION 3-1: applications, the best frequency response will be V = --------1----------V achieved with a load resistor of 10k or higher. This OSE A +1 OSN N results in a smooth 6dB/octave response from 0.1Hz to 2MHz, with phase shifts of less than 10° in the transi- DS21463C-page 4  2001-2012 Microchip Technology Inc.

TC7650 tion region, where the main amplifier takes over from ing sum and difference frequencies, and causing dis- the null amplifier. The clock frequency sets the transi- turbances to the gain and phase versus frequency tion region. characteristics near the chopping frequency. These effects are substantially reduced in the TC7650 by 3.3 Intermodulation feeding the nulling circuit with a dynamic current corre- sponding to the compensation capacitor current in such Previous chopper stabilized amplifiers have suffered a way as to cancel that portion of the input signal due from intermodulation effects between the chopper fre- to a finite AC gain. The intermodulation and gain/phase quency and input signals. These arise because the disturbances are held to very low values, and can gen- finite AC gain of the amplifier results in a small AC sig- erally be ignored. nal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus inject- FIGURE 3-1: TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS. V+ Main + Amplifier Analog Input Null VOUT - V- Gain = A M B TC7650 + B C B Null A - A Null C A Amplifier Gain = A , Offset = V N OSN FIGURE 3-2: NULLING CAPACITOR 3.5 Clock Operation CONNECTION The internal oscillator is set for a 200Hz nominal chop- VDD VSS VDD ping frequency on both the 8- and 14-pin DIPs. With the 14-pin DIP TC7650, the 200 Hz internal chopping fre- 4 11 2 7 quency is available at the internal clock output (Pin 12). - - 7 A 400Hz nominal signal will be present at the external 10 6 TC7650 TC7650 clock input pin (Pin 13) with INT/EXT high or open. This 5 + 1 3 + 4 is the internal clock signal before a divide-by-two oper- 8 CB ation. 8 2 1 VSS The 14-pin DIP device can be driven by an external clock. The INT/EXT input (Pin 14) has an internal pull- CA CB CA up and may be left open for internal clock operation. If an external clock is used, INT/EXT must be tied to V 14-PIN PACKAGE 8-PIN PACKAGE SS (Pin 7) to disable the internal clock. The external clock signal is applied to the external clock input (Pin 13). 3.4 Nulling Capacitor Connection The external clock amplitude should swing between The offset voltage correction capacitors are connected VDD and ground for power supplies up to ±6V and to C and C . The common capacitor connection is between V+ and V+ -6V for higher supply voltages. A B made to VSS (Pin 4) on the 8-pin packages and to At low frequencies the external clock duty cycle is not capacitor return (CRETN, Pin 8) on the 14-pin packages. critical, since an internal divide-by-two gives the The common connection should be made through a desired 50% switching duty cycle. The offset storage separate PC trace or wire to avoid voltage drops. The correction capacitors are charged only when the exter- capacitors outside foil, if possible, should be connected nal clock input is high. A 50% to 80% external clock to C or V . RETN SS  2001-2012 Microchip Technology Inc. DS21463C-page 5

TC7650 positive duty cycle is desired for frequencies above FIGURE 3-5: INVERTING AMPLIFIER WITH 500Hz to ensure transients settle before the internal OPTIONAL CLAMP switches open. R2 The external clock input can also be used as a strobe input. If a strobe signal is connected at the external Clamp clock input so that it is LOW during the time an overload R1 signal is applied, neither capacitor will be charged. The Input leakage currents at the capacitors pins are very low. At TC7650 C Output 25°C a typical TC7650 will drift less than 10V/sec. + R * C (R1 R2) ‡ 100 kΩ 3.6 Output Clamp For Full Clamp Effect Chopper-stabilized systems can show long recovery *Connect To VR– 0.1 µ F 0.1 µ F times from overloads. If the output is driven to either On 8-Pin DIP. supply rail, output saturation occurs. The inputs are no longer held at a "virtual ground." The V null circuit The output clamp circuit is shown in Figure 3-3, with OS treats the differential signal as an offset and tries to cor- typical inverting and non-inverting circuit connections rect it by charging the external capacitors. The nulling shown in Figures 3-4 and 3-5. Output voltage versus circuit also saturates. Once the input signal returns to clamp circuit current characteristics are shown in the normal, the response time is lengthened by the long typical operating curves. For the clamp to be fully effec- recovery time of the nulling amplifier and external tive, the impedance across the clamp output should be capacitors. greater than 100k. Through an external clamp connection, the TC7650 3.7 Latch-Up Avoidance eliminates the overload recovery problem by reducing the feedback network gain before the output voltage Junction-isolated CMOS circuits inherently include a reaches either supply rail. parasitic 4-layer (p-n-p-n) structure which has charac- teristics similar to an SCR. Under certain circum- FIGURE 3-3: INTERNAL CLAMP CIRCUIT stances this junction may be triggered into a low- Internal impedance state, resulting in excessive supply current. Positive Clamp Bias ≈ V+ - VT ≈ V+ - 0.7 To avoid this condition, no voltage greater than 0.3V P-Channel beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established Output either at the same time or before any input signals are Clamp Pin applied. If this is not possible, the drive circuits must N-Channel limit input current flow to under 0.1mA to avoid latch- up. 3.8 Thermoelectric Potentials FIGURE 3-4: NON-INVERTING AMPLIFIER WITH OPTIONAL CLAMP Precision DC measurements are ultimately limited by *Connect To VSS 0.1µF thermoelectric potentials developed in thermocouple On 8-Pin DIP. junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, ther- C * moelectric voltages, typically around 0.1V/°C, but up Input + R to tens of V/°C for some materials, will be generated. TC7650C Output In order to realize the benefits extremely-low offset volt- R2 ages provide, it is essential to take special precautions Clamp to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially R3 R3 + (R1/R2) ‡ 100 kΩ R1 ttehmos.e cLaouws edt hbeyr pmooweelerc dtrisics ipacotin-egf feicleiemnet ntcso innn theect sioynss- For Full Clamp Effect should be used where possible and power supply volt- ages and power dissipation should be kept to a mini- mum. High impedance loads are preferable, and separation from surrounding heat dissipating elements is advised. DS21463C-page 6  2001-2012 Microchip Technology Inc.

TC7650 3.9 Pin Compatibility FIGURE 3-6: INPUT GUARD CONNECTION On the 8-pin mini-DIP TC7650, the external null stor- Inverting Amplifier age capacitors are connected to pins 1 and 8. On most R1 R2 other operational amplifiers these are left open or are Input used for offset potentiometer or compensation capaci- tor connections. - For OP05 and OP07 operational amplifiers, the Output replacement of the offset null potentiometer between + pins 1 and 8 by two capacitors from the pins to V will SS convert the OP05/07 pin configurations for TC7650 R3* operation. For LM108 devices, the compensation capacitor is replaced by the external nulling capacitors. The LM101/748/709 pinouts are modified similarly by removing any circuit connections to Pin 5. On the Noninverting Amplifier TC7650, Pin 5 is the output clamp connection. Other operational amplifiers may use this pin as an off- R2 set or compensation point. The minor modifications needed to retrofit a TC7650 R3* - into existing sockets operating at reduced power sup- ply voltages make prototyping and circuit verification Output straightforward. + R1 3.10 Input Guarding High impedance, low leakage CMOS inputs allow the Input Should Be Low Impedence For TsoCu7r6ce5s0. tSot ramya kleea kmageea spuarethmse cnatsn oinfc rheigahse-i minppeudta cnucre- NOTE: R3 = R1 R2 Optimum Guarding R1 + R2 rents and decrease input resistance unless inputs are guarded. A guard is a conductive PC trace surrounding Follower the input terminals. The ring connects to a low imped- ance point at the same potential as the inputs. Stray leakages are absorbed by the low impedance ring. The R3* equal potential between ring and inputs prevents input leakage currents. Typical guard connections are shown - in Figure 3-6. Output The 14-pin DIP configuration has been specifically Input + designed to ease input guarding. The pins adjacent to the inputs are unused. In applications requiring low leakage currents, boards should be cleaned thoroughly and blown dry after sol- dering. Protective coatings will prevent future board contamination. 3.11 Component Selection The two required capacitors, C and C , have optimum A B values, depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1F. To maintain the same relationship between the chop- ping frequency and the nulling time constant, the capacitor values should be scaled in proportion to the external clock, if used. High quality film type capacitors (such as Mylar) are preferred; ceramic or other lower grade capacitors may be suitable in some applications. For fast settling on initial turn-on, low dielectric absorp- tion capacitors (such as polypropylene) should be used. With ceramic capacitors, several seconds may be required to settle to 1V.  2001-2012 Microchip Technology Inc. DS21463C-page 7

TC7650 4.0 TYPICAL CHARACTERISTICS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Positive Clamp Current Negative Clamp Current vs. Output Voltage vs. Output Voltage 1 mA 1 mA 0.1 mA TA = +25˚C 0.1 mA TA = +25˚C VS = ±5V VS = ±5V 0.01 mA 0.01 mA T 1m A T 1m A N N E E R 0.1m A R 0.1m A R R U U C 0.01m A C 0.01m A P P M M A 1 nA A 1 nA L L C C 0.1 nA 0.1 nA 0.01 nA 0.01 nA 1 pA 1 pA 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 -4.0 -4.1 -4.2 -4.3 -4.4 -4.5 -4.6 -4.7 -4.8-4.9 -5.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Supply Current vs. Gain/Phase vs. Frequency Supply Voltage 3.0 30 225 TA = +25˚C 20 180 A) 2.6 10 135 m RRENT ( 2.2 N (dB) –100 GAIN 9405 E (deg) LY CU 1.8 GAI ––3200 PHASE 0-45 PHAS P P SU 1.4 –40 -90 –50 CLOSED-LOOP -135 GAIN = 20 1.0 –60 -180 5 6 7 8 9 10 11 12 13 14 15 1k 10k 100k 1M 10M SUPPLY VOLTAGE (V) FREQUENCY (H z ) DS21463C-page 8  2001-2012 Microchip Technology Inc.

TC7650 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Package marking information not available at this time. 5.2 Package Dimensions Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 8-Pin Plastic DIP PIN 1 .260 (6.60) .240 (6.10) .045 (1.14) .070 (1.78) .030 (0.76) .040 (1.02) .310 (7.87) .400 (10.16) .290 (7.37) .348 (8.84) .200 (5.08) .140 (3.56) .040 (1.02) .020 (0.51) .015 (0.38) 3˚MIN. .150 (3.81) .008 (0.20) .115 (2.92) .400 (10.16) .310 (7.87) .110 (2.79) .022 (0.56) .090 (2.29) .015 (0.38) Dimensions: inches (mm) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14-Pin PDIP (Narrow) PIN 1 .260 (6.60) .240 (6.10) .310 (7.87) .770 (19.56) .290 (7.37) .745 (18.92) .200 (5.08) .140 (3.56) .040 (1.02) .150 (3.81) .020 (0.51) ..001058 ((00..3280)) 3˚MIN. .115 (2.92) .400 (10.16) .310 (7.87) .110 (2.79) .070 (1.78) .022 (0.56) .090 (2.29) .045 (1.14) .015 (0.38) Dimensions: inches (mm)  2001-2012 Microchip Technology Inc. DS21463C-page 9

TC7650 6.0 REVISION HISTORY Revision C (December 2012) Added a note to each package outline drawing. DS21463C-page 10  2001-2012 Microchip Technology Inc.

TC7650 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2001-2012 Microchip Technology Inc. DS21463C-page 11

TC7650 NOTES: DS21463C-page 12  2001-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2001-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620768402 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2001-2012 Microchip Technology Inc. DS21463C-page 13

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