ST1S41 4 A step-down switching regulator Datasheet - production data Applications • μP/ASIC/DSP/FPGA core and I/O supplies • Point of load for: STB, TVs, DVD • Optical storage, hard disk drive, printers, audio/graphic cards VFQFPN8 4x4 HSOP8 Description Features The ST1S41 is an internally compensated 850 kHz fixed-frequency PWM synchronous step- • 4 A output current down regulator. The ST1S41 operates from 4.0 V to 18 V input, while it regulates an output voltage • 4.0 V to 18 V input voltage as low as 0.8 V and up to V . IN • Output voltage adjustable from 0.8 V The ST1S41 integrates 95 mΩ high-side switch • 850 kHz switching frequency and 69 mΩ synchronous rectifier allowing very • Internal soft-start high efficiency with very low output voltages. • Integrated 95 mΩ and 69 mΩ power The peak current mode control with internal MOSFETs compensation delivers a very compact solution • All ceramic capacitor with a minimum component count. • Enable The ST1S41 is available in VFQFPN 4 mm x 4 • Cycle-by-cycle current limiting mm 8-lead package and HSOP-8. • Current foldback short-circuit protection • VFQFPN 4x4-8L and HSOP-8 packages Figure 1. Application circuit L VIN 6 7 VOUT VINSW SW 1 VINA 2 R1 EN ST1S41 Cin_a 3 FB Cout Cin_sw PGND ePAD/GND R2 8 9 4 AM15058v1 April 2013 DocID023654 Rev 2 1/27 This is information on a product in full production. www.st.com 27

Contents ST1S41 Contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 Internal soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.5 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 DocID023654 Rev 2

ST1S41 Pin settings 1 Pin settings 1.1 Pin connection Figure 2. Pin connection (top view) VINA 1 8 PGND 9 9 EN 2 6 SW EN FB 3 7 VINSW NC GND 4 5 NC VFQFPN HSOP8 AM15059v1 1.2 Pin description Table 1. Pin description N. Type Description 1 VINA Unregulated DC input voltage Enable input. With EN higher than 1.2 V the device in ON and with EN 2 EN lower than 0.4 V the device is OFF (ST1S41Ixx). Feedback input. Connecting the output voltage directly to this pin the 3 FB output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from Vout to FB pin. 4 AGND Ground 5 NC Can be connected to ground 6 VINSW Power input voltage 7 SW Regulator output switching pin 8 PGND Power ground 9 ePAD Ground DocID023654 Rev 2 3/27

Maximum ratings ST1S41 2 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V Power input voltage -0.3 to 20 INSW V Input voltage -0.3 to 20 INA V Enable voltage -0.3 to V EN INA V V Output switching voltage -1 to V SW IN V Power Good -0.3 to V PG IN V Feedback voltage -0.3 to 2.5 FB I FB current -1 to +1 mA FB P Power dissipation at T < 60 °C 2.25 W TOT A T Operating junction temperature range -40 to 150 °C OP T Storage temperature range -55 to 150 °C stg 3 Thermal data Table 3. Thermal data Symbol Parameter Value Unit Maximum thermal resistance VFQFPN 40 R °C/W thJA junction-ambient (1) HSOP8 40 1. Package mounted on demonstration board. 4/27 DocID023654 Rev 2

ST1S41 Electrical characteristics 4 Electrical characteristics T = 25 °C, V = 12 V, unless otherwise specified. J CC Table 4. Electrical characteristics Values Symbol Parameter Test condition Unit Min. Typ. Max. Operating input voltage V (1) 4 18 IN range V V Turn-on V threshold (1) 2.9 INON CC V Threshold hysteresis (1) 0.250 INHYS High-side switch on- R -P I =750 mA 95 mΩ DSON resistance SW Low-side switch on- R -N I =750 mA 69 mΩ DSON resistance SW I Maximum limiting current (2) 5.0 7.0 A LIM Oscillator F Switching frequency 0.7 0.85 1 MHz SW D Maximum duty cycle (2) 100 % MAX Dynamic characteristics 0.784 0.8 0.816 V Feedback voltage V FB (1) 0.776 0.8 0.824 %VOUT/ Reference load Isw=10 mA to I (2) 0.5 % ΔI regulation LIM OUT %V / OUT Reference line regulation V = 4.0 V to 18 V (2) 0.4 % ΔV IN IN DC characteristics Duty cycle=0, no load I Quiescent current 1.5 2.5 mA Q V =1.2 V FB Total standby quiescent OFF 2.4 4.5 I μA QST-BY current OFF (1) 6 IFB FB bias current 50 nA Enable Device ON level 1.2 V EN threshold voltage V EN Device OFF level 0.4 I EN current 2 μA EN Soft-start T Soft-start duration 1 ms SS DocID023654 Rev 2 5/27

Electrical characteristics ST1S41 Table 4. Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min. Typ. Max. Protection Thermal shutdown 150 T °C SHDN Hystereris 15 1. Specifications referred to T from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range J are assured by design, characterization and statistical correlation. 2. Guaranteed by design. 6/27 DocID023654 Rev 2

ST1S41 Functional description 5 Functional description The ST1S41 is based on a “peak current mode”, constant frequency control. The output voltage V is sensed by the feedback pin (FB) compared to an internal reference (0.8 V) OUT providing an error signal that, compared to the output of the current sense amplifier, controls the on and off-time of the power switch. The main internal blocks are shown in the block diagram in Figure3. They are: • A fully integrated oscillator that provides the internal clock and the ramp for the slope compensation avoiding sub-harmonic instability • The soft-start circuitry to limit inrush current during the startup phase • The transconductance error amplifier with integrated compensation network • The pulse width modulator and the relative logic circuitry necessary to drive the internal power switches • The drivers for embedded P-channel and N-channel power MOSFET switches • The high-side current sensing block • The low-side current sense to implement diode emulation • A voltage monitor circuitry (UVLO) that checks the input and internal voltages • A thermal shutdown block, to prevent thermal run-away. Figure 3. Block diagram VINA VINSW OSC OCP REF I2V I_SENSE RSENSE COMP REGULATOR UVLO OCP Vdrv_p DRIVER MOSFET Vsum CONTROL LOGIC COMP Vdrv_n Vc SW OTP DMD E/A SHUTDOWN DRIVER SOFT-START 0.8V FB EN GNDA GNDP AM15060v1 DocID023654 Rev 2 7/27

Functional description ST1S41 5.1 Internal soft-start The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monothonically. The soft-start is performed by ramping the non-inverting input (V ) of the error amplifier REF from 0 V to 0.8 V in around 1 ms. 5.2 Error amplifier and control loop stability The error amplifier compares the FB pin voltage with the internal 0.8 V reference and it provides the error signal to be compared with the output of the current sense circuitry, that is the high-side power MOSFET current. Comparing the output of the error amplifier and the peak inductor current implements the peak current mode control loop. The error amplifier is a transconductance amplifier (OTA). The uncompensated characteristics are listed in Table5: Table 5. Error amplifier characteristics DC gain 95 dB Gm 251 uA/V Ro 240 MΩ The ST1S41 embeds the compensation network that assures the stability of the loop in the whole operating range. Here below, all the tools needed to check the loop stability. In Figure4 the simple small signal model for the peak current mode control loop is shown. 8/27 DocID023654 Rev 2

ST1S41 Functional description Figure 4. Block diagram of the loop for the small signal analysis VIN Slope GCO(s) Compensation High side Switch L GDIV(s) Current sense VOUT Logic Cout and Low side Driver Switch PWM comparator 0.8V R1 VC VFB Rc Error Amp R2 Cc GEA(s) AM15061v1 Three main terms can be identified to obtain the loop transfer function: 1. from control (output of E/A) to output, G (s); CO 2. from output (Vout) to FB pin, G (s); DIV 3. from FB pin to control (output of E/A), G (s). EA The transfer function from control to output G (s) results: CO Equation 1 ⎛ s ⎞ G (s) = R-----L---O----A---D---⋅ --------------------------------------------------1---------------------------------------------------⋅ -⎝--1-----+-----ω------- ---z----⎠--⋅ F (s) CO R R ⋅ T ⎛ s ⎞ H i 1+-----o---u---t---L---------S----W---⋅ [mC⋅ (1–D)–0.5] ⎝1+-ω--- -p--⎠ where R represents the load resistance, R the equivalent sensing resistor of the LOAD i current sense circuitry, ω the single pole introduced by the LC filter and ω the zero given p z by the ESR of the output capacitor. F (s) accounts for the sampling effect performed by the PWM comparator on the output of H the error amplifier that introduces a double pole at one half of the switching frequency. Equation 2 ω = ----------------1------------------ Z ESR⋅ C OUT DocID023654 Rev 2 9/27

Functional description ST1S41 Equation 3 ω = -------------------1---------------------+m------C-----⋅-----(---1-----–----D-----)---–-----0---.--5-- p R ⋅ C L⋅ C ⋅ f LOAD OUT OUT SW where: Equation 4 ⎛ S ⎜m = 1+-----e- ⎜ C Sn ⎜ ⎜Se = Vpp⋅ fSW ⎜ ⎝⎜Sn = -V----I-N-----–---L--V----O----U----T--⋅ Ri S represents the ON time slope of the sensed inductor current, S the slope of the external n e ramp (V peak-to-peak amplitude) that implements the slope compensation to avoid sub- PP harmonic oscillations at duty cycle over 50%. The sampling effect contribution F (s) is: H Equation 5 F (s) = ----------------------1------------------------ H 2 s s 1+----------------------+------- ω n⋅ QP ω2 n where: Equation 6 1 Q = ---------------------------------------------------------------- P π⋅ [m ⋅ (1–D)–0.5] C and Equation 7 ω = π⋅ f n SW The resistor to adjust the output voltage gives the term from output voltage to the FB pin. G (s) is: DIV Equation 8 R G (s) = ------------2-------- DIV R +R 1 2 10/27 DocID023654 Rev 2

ST1S41 Functional description The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. Figure5 shows the small signal model of the error amplifier with the internal compensation network. Figure 5. Small signal model for the error amplifier V FB Ro Co Rc Cp Vd Gm*Vd Cc V REF AM15062v1 R and C introduce a pole and a zero in the open loop gain. C does not significantly affect C C P system stability and can be neglected. So G (s) results: EA Equation 9 G ⋅ (1+s⋅ R ⋅ C ) G (s) = ----------------------------------------------------------------------------E---A---0-------------------------------------c---------------c------------------------------------------------------------------------- EA s2⋅ R ⋅ (C +C )⋅ R ⋅ C +s⋅ (R ⋅ C +R ⋅ (C +C )+R ⋅ C )+1 0 0 p c c 0 c 0 0 p c c where G = G · R . EA m o The poles of this transfer function are (if C >> C +C ): c 0 P Equation 10 1 f = ------------------------------------------ P LF 2⋅ π⋅ R ⋅ C 0 c Equation 11 1 f = ------------------------------------------------------------ P HF 2⋅ π⋅ R ⋅ (C +C ) c 0 p whereas the zero is defined as: Equation 12 1 f = ------------------------------------------ Z 2⋅ π⋅ R ⋅ C c c The embedded compensation network is R =70 kΩ, C =195 pF while C and C can be C C P O considered as negligible. The error amplifier output resistance is 240 MΩ so the relevant singularities are: Equation 13 f = 11.6 kHz f =3.4 Hz Z PLF DocID023654 Rev 2 11/27

Functional description ST1S41 So closing the loop, the loop gain G (s) is: LOOP Equation 14 G (s) = G (s)⋅ G (s)⋅ G (s) LOOP CO DIV EA Example: VIN=12 V, VOUT=1.2 V, Iomax=4 A, L=1.5 uH, Cout=47 uF (MLCC), R1=10 kΩ, R2=20 kΩ (see Section6.2 and Section6.3 for inductor and output capacitor selection guidelines). The module and phase bode plot are reported in Figure 6. The bandwidth is 100 kHz and the phase margin is 45 degrees. 12/27 DocID023654 Rev 2

ST1S41 Functional description Figure 6. Module and phase bode plot 5.3 Overcurrent protection The ST1S41 implements the pulse-by-pulse overcurrent protection. The peak current is sensed through the high-side power MOSFET and when it exceeds the first overcurrent threshold (OCP1) the high-side is immediately turned off and the low-side conducts the inductor current for the rest of the clock period and the following high-side cycle is disabled. This implements a division by two of the switching frequency in case of overload to keep the output current limited below the current limit value. During overload condition, since the duty cycle is not set by the control loop but is limited by the overcurrent threshold, the output voltage drops out of regulation. If the feedback falls below 0.3 V, the switching frequency is reduced to one fourth and the current limit threshold is folded back to around 2 A. Thanks to the current and frequency foldback the stress on the device and on the external power components is reduced in case of severe overload or dead-short to ground of the output. DocID023654 Rev 2 13/27

Functional description ST1S41 The current foldback is disabled during the startup to allow the Vout to start up properly in case of a big output capacitor requiring high extra current to be charged. A further mechanism is protecting the device in case of short-circuit on the output and high input voltage. A further threshold (OCP2, 1 A higher than OCP1) is compared to the inductor current. If the inductor current exceeds OCP2, the device stops switching and it restarts with a soft-start cycle. 5.4 Enable function The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 15 uA. With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V compatible. IN 5.5 Hysteretic thermal shutdown The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. 14/27 DocID023654 Rev 2

ST1S41 Application information 6 Application information 6.1 Input capacitor selection The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 15 I = I ⋅ D–2-----⋅------D-----2-+D-----2-- RMS O η η2 where Io is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η =1, this function has a maximum at D=0.5 and is equal to Io/2. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 16 VPP = C------------⋅I--O---F-----------⋅ ⎝⎛1–D--η--⎠⎞ ⋅ D+D--η--⋅ (1–D) +ESR⋅ IO IN SW where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can meet well the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of C as a function of the target peak-to-peak voltage ripple (V ) can be IN PP written as follows: Equation 17 CIN = V-------------I⋅--O----F----------⋅ ⎝⎛1–D--η--⎠⎞ ⋅ D+D--η--⋅ (1–D) PP SW neglecting the small ESR of ceramic capacitors. Considering η =1, this function has its maximum in D=0.5, therefore, given the maximum peak-to-peak input voltage (V ), the minimum input capacitor (C ) value is: PP_MAX IN_MIN Equation 18 I C = --------------------------O--------------------------- IN_MIN 2⋅ V ⋅ F PP_MAX SW DocID023654 Rev 2 15/27

Application information ST1S41 Typically, C is dimensioned to keep the maximum peak-to-peak voltage ripple in the order IN of 1% of V . INMAX In Table6 some multi-layer ceramic capacitors suitable for this device are reported. Table 6. Input MLCC capacitors Manufacturer Series Cap value (μF) Rated voltage (V) GRM31 10 25 Murata GRM55 10 25 TDK C3225 10 25 A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 uF. 6.2 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. In continuous current mode (CCM), the inductance value can be calculated by the following equation: Equation 19 V –V V ΔI = -----I-N--------------O----U----T--⋅ T = -----O----U---T--⋅ T L L ON L OFF where T is the conduction time of the high-side switch and T is the conduction time of ON OFF the low-side switch (in CCM, F =1/(T + T )). The maximum current ripple, given the SW ON OFF Vout, is obtained at maximum T , that is at minimum duty cycle (see previous section to OFF calculate minimum duty). So, fixing ΔI =20% to 30% of the maximum output current, the L minimum inductance value can be calculated as: Equation 20 V 1–D L = ------O----U---T---⋅ --------------M-----I-N--- MIN ΔI F MAX SWMIN where F is the minimum switching frequency, according to Table4. SWMIN The peak current through the inductor is given by: Equation 21 ΔI IL, PK = IO+---2---L-- 16/27 DocID023654 Rev 2

ST1S41 Application information So, if the inductor value decreases, the peak current (that must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit. In Table7 some inductor part numbers are listed. Table 7. Inductors Manufacturer Series Inductor value (μH) Saturation current (A) XAL5030/6030 2.2 to 4.7 6.7 to 15.5 Coilcraft MSS1048 2.2 to 6.8 4.14 to 6.62 MSS1260 10 5.5 WE-HC/HCA 3.3 to 4.7 7 to 11 Wurth WE-TPC typ XLH 3.6 to 6.2 4.5 to 6.4 WE-PD type L 10 5.6 TDK RLF7030T 2.2 to 4.7 4 to 6 6.3 Output capacitor selection The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection. Equation 22 ΔI ΔV = ESR⋅ ΔI +-------------------M-----A---X--------------- OUT MAX 8⋅ C ⋅ f OUT SW For the ceramic capacitor (MLCC) the capacitive component of the ripple dominates the resistive one. While for the electrolythic capacitor the opposite is true. Since the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. The equations of Section5.2 help to check loop stability given the application conditions, the value of the inductor, and of the output capacitor. In Table8 some capacitor series are listed. Table 8. Output capacitors Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) GRM32 22 to 100 6.3 to 25 < 5 MURATA GRM31 10 to 47 6.3 to 25 < 5 DocID023654 Rev 2 17/27

Application information ST1S41 Table 8. Output capacitors (continued) Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) ECJ 10 to 22 6.3 < 5 PANASONIC EEFCD 10 to 68 6.3 15 to 55 SANYO TPA/B/C 100 to 470 4 to 16 40 to 80 TDK C3225 22 to 100 6.3 < 5 6.4 Thermal dissipation The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the on-resistance of the high-side switch (R ) and low- HS side switch (R ); these are equal to: LS Equation 23 P = R ⋅ I 2⋅ D+R ⋅ I 2⋅ (1–D) COND HS OUT LS OUT where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between V and V , but actually it is slightly higher to compensate the losses of OUT IN the regulator. b) switching losses due to high-side power MOSFET turn-on and off; these can be calculated as: Equation 24 (T +T ) P = V ⋅ I ⋅ -------R----I-S----E-------------F---A----L---L----⋅ Fsw = V ⋅ I ⋅ T ⋅ F SW IN OUT 2 IN OUT SW SW where T and T are the overlap times of the voltage across the high-side power RISE FALL switch (V ) and the current flowing into it during turn-on and turn-off phases, as shown in DS Figure7. T is the equivalent switching time. For this device the typical value for the SW equivalent switching time is 20 ns. c) Quiescent current losses, calculated as: Equation 25 P = V ⋅ I Q IN Q where I is the quiescent current (I =2.5 mA maximum). Q Q The junction temperature T can be calculated as: J 18/27 DocID023654 Rev 2

ST1S41 Application information Equation 26 T = T +Rth ⋅ P J A JA TOT where T is the ambient temperature and P is the sum of the power losses just seen. A TOT Rth is the equivalent thermal resistance junction-to-ambient of the device; it can be JA calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth measured on the demonstration board described in the following JA paragraph is about 40 °C/W for the VFQFPN and HSOP packages. Figure 7. Switching losses V IN V SW I SW,HS V DS,HS P SW P P COND,HS COND,LS T T FALL RISE AM15064v1 6.5 Layout considerations The PC board layout of switching DC-DC regulator is very important to minimize the noise injected in high impedance nodes, to reduce interference generated by the high switching current loops and to optimize the reliability of the device. In order to avoid EMC problems, the high switching current loops must be as short as possible. In the buck converter there are two high switching current loops: during the on- time, the pulsed current flows through the input capacitor, the high-side power switch, the inductor and the output capacitor; during the off-time, through the low-side power switch, the inductor and the output capacitor. DocID023654 Rev 2 19/27

Application information ST1S41 The input capacitor connected to VINSW must be placed as close as possible to the device, to avoid spikes on VINSW due to the stray inductance and the pulsed input current. In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the VINA pin to the input must be derived from VINSW. The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference can be minimized routing the feedback node with a very short trace and as far as possible from the high current paths. A single point connection from signal ground to power ground is suggested. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction-to-ambient; so a large ground plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion. Figure 8. Suggested PCB layout Via to connect the thermal pad Star center for common ground To bottom or inner ground plane Short high switching current loop Input cap as close as possible to VINSW pin Short FB trace VINA derived from Cin to avoid dynamic voltage drop between VINA and VINSW AM15065v1 20/27 DocID023654 Rev 2

ST1S41 Typical characteristics 7 Typical characteristics Figure 9. Efficiency vs. I @Vin=5 V Figure 10. Efficiency vs. I @Vin=12 V OUT OUT 100 100 90 90 %] cy [ 80 %] 80 cien 70 ency [ 70 Effi Effici VVino==152VV 60 Vin=5V 60 Vo=3.3V Vo=3.3V Vo=1.8V 50 50 Vo=1.2V 40 40 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 Iout [A] AM15066v1 Iout [A] AM15067v1 Figure 11. Start at full load 4 A Figure 12. Efficiency vs. I @ different Vo OUT values 90 85 80 75 Vout %] IL 200mV/div ency [ 6750 4A/div Effici 60 Vin=12V 55 Vo=1.8V 50 Vo=1.2V 200us/div 45 40 AM15068v1 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 Iout [A] AM15069v1 DocID023654 Rev 2 21/27

Typical characteristics ST1S41 Figure 13. Startup with output shorted 2A/div 200us/div 5V/div SW IL Vout 01us/div AM14070v1 22/27 DocID023654 Rev 2

ST1S41 Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. VFQFPN8 (4x4x1.08 mm) mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.02 0.05 A3 0.20 b 0.23 0.30 0.38 D 3.90 4.00 4.10 D2 2.82 3.00 3.23 E 3.90 4.00 4.10 E2 2.05 2.20 2.30 e 0.80 L 0.40 0.50 0.60 Figure 14. VFQFPN8 (4x4x1.08 mm) package dimensions DocID023654 Rev 2 23/27

Package mechanical data ST1S41 Table 10. HSOP8 mechanical data mm Dim. Min. Typ. Max. A 1.70 A1 0.00 0.15 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8 ccc 0.10 Figure 15. HSOP8 package dimensions 24/27 DocID023654 Rev 2

ST1S41 Ordering information 9 Ordering information Table 11. Ordering information Order code Package ST1S41PUR VFQFPN 4x4 8L ST1S41PHR HSOP8 DocID023654 Rev 2 25/27

Revision history ST1S41 10 Revision history Table 12. Document revision history Date Revision Changes 14-Sep-2012 1 Initial release. Updated Table4: Electrical characteristics and Table11: Ordering 24-Apr-2013 2 information. 26/27 DocID023654 Rev 2

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