Product Order Technical Tools & Support & Folder Now Documents Software Community SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output 1 Features 3 Description • Latch-upperformanceexceeds100mAPerJESD The SN74LVC1G38 device is designed for 1.65-V to 1 5.5-VV operation. 78,ClassII CC • ESDprotectionexceedsJESD22 This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean – 2000-VHuman-bodymodel(A114-A) functionY= A× BorY= A+Binpositivelogic. – 200-VMachinemodel(A115-A) This device is fully specified for partial-power-down – 1000-VCharged-devicemodel(C101) applications using I . The I circuitry disables the off off • AvailableintheTexasInstruments outputs when the device is powered down. This NanoStar™andNanoFree™Packages inhibits current backflow into the device which • Supports5-VV operation preventsdamagetothedevice. CC • Inputsacceptvoltagesto5.5V NanoStar™ and NanoFree™ package technology is • SupportsdowntranslationtoV a major breakthrough in IC packaging concepts, CC usingthedieasthepackage. • Maximumt of4.5nsat3.3V pd • Lowpowerconsumption,10-µAmaximumICC DeviceInformation(1) • ±24-mAOutputdriveat3.3V DEVICENAME PACKAGE BODYSIZE(NOM) • IoffSupportspartial-power-downmodeandback- SN74LVC1G38DBV SOT-23(5) 2.90mm×1.60mm driveprotection SN74LVC1G38DCK SC70(5) 2.00mm×1.25mm SN74LVC1G38DRY SON(6) 1.45mm×1.00mm 2 Applications SN74LVC1G38DSF SON(6) 1.00mm×1.00mm • AVreceivers SN74LVC1G38YZP DSBGA(5) 0.89mm×1.39mm • Blu-rayplayersandhometheaters SN74LVC1G38DPW X2SON(5) 0.80mm×0.80mm • DVDrecordersandplayers (1) For all available packages, see the orderable addendum at • DesktopornotebookPCs theendofthedatasheet. • Digitalradioorinternetradioplayers LogicDiagram(PositiveLogic) • Digitalvideocameras(DVC) 1 A • EmbeddedPCs • GPS:personalnavigationdevices 4 Y • Mobileinternetdevices • Networkprojectorfront-ends 2 • Portablemediaplayers B • Proaudiomixers • Smokedetectors • Soliddtatedrive(SSD):enterprise • High-definition(HDTV) • Tablets:enterprise • Audiodocks:portable • DLPfrontprojectionsystems • DVRandDVS • Digitalpictureframe(DPF) • Digitalstillcameras 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................10 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................10 3 Description............................................................. 1 8.3 FeatureDescription.................................................10 8.4 DeviceFunctionalModes........................................11 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 12 5 PinConfigurationandFunctions......................... 3 9.1 ApplicationInformation............................................12 6 Specifications......................................................... 4 9.2 TypicalApplication .................................................12 6.1 AbsoluteMaximumRatings......................................4 10 PowerSupplyRecommendations..................... 13 6.2 ESDRatings..............................................................4 11 Layout................................................................... 13 6.3 RecommendedOperatingConditions.......................5 6.4 ThermalInformation..................................................5 11.1 LayoutGuidelines.................................................13 6.5 ElectricalCharacteristics...........................................6 11.2 LayoutExample....................................................13 6.6 SwitchingCharacteristics,C =15pF......................6 12 DeviceandDocumentationSupport................. 14 L 6.7 SwitchingCharacteristics,C =30pFor50pF, 12.1 DocumentationSupport........................................14 L –40°Cto+85°C..........................................................6 12.2 ReceivingNotificationofDocumentationUpdates14 6.8 SwitchingCharacteristics,CL=30pFor50pF, 12.3 SupportResources...............................................14 –40°Cto+125°C........................................................7 12.4 Trademarks...........................................................14 6.9 OperatingCharacteristics..........................................7 12.5 ElectrostaticDischargeCaution............................14 6.10 TypicalCharacteristics............................................7 12.6 Glossary................................................................14 7 ParameterMeasurementInformation..................8 13 Mechanical,Packaging,andOrderable 8 DetailedDescription............................................ 10 Information........................................................... 14 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(October)toRevisionG Page • ChangedtheT high-endtempfrom+1255°Cto+125°CintheTestConditionsfieldoftheElectricalCharacteristics A table. ...................................................................................................................................................................................... 6 ChangesfromRevisionE(August2017)toRevisionF Page • AddedvaluesforDPW(X2SON)packageinThermalInformationtable. ............................................................................. 5 ChangesfromRevisionD(December2013)toRevisionE Page • AddedDPW(X2SON)package.............................................................................................................................................. 1 • AddedApplications,DeviceInformationtable,PinConfigurationandFunctionssection,ESDRatingstable,Thermal Informationtable,TypicalCharacteristics,DetailedDescriptionsection,ApplicationandImplementationsection, Layoutsection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section.................................................................................................................................................................................... 1 • AddedMaximumjunctiontemperature,T ............................................................................................................................. 4 J • ChangedvaluesintheThermalInformationtabletoalignwithJEDECstandards................................................................ 5 ChangesfromRevisionC(March2011)toRevisionD Page • UpdateddocumenttonewTIdatasheetformat.................................................................................................................... 1 • UpdatedI inFeatures.......................................................................................................................................................... 1 off • AddedESDwarning............................................................................................................................................................... 1 • Updatedoperatingtemperaturerange................................................................................................................................... 5 2 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 www.ti.com SCES538G–JANUARY2004–REVISEDFEBRUARY2020 5 Pin Configuration and Functions DBVPackage 5-PinSOT-23 DCKPackage TopView 5-PinSC70 TopView A 1 5 VCC A 1 5 VCC B 2 B 2 GND 3 4 Y GND 3 4 Y DRYPackage 6-PinSON DSFPackage TopView 6-PinSON TopView A 1 6 VCC A 1 6 VCC B 2 5 NC B 2 5 NC GND 3 4 Y GND 3 4 Y NC–Nointernalconnection. Seemechanicaldrawingsfordimensions YZPPackage 5-PinDSBGA BottomView DPWPackage 5-PinX2SON 1 2 TopView C GND Y A V GND CC B B B Y A A VCC Not to scale PinFunctions PIN DBV, DRY, I/O DESCRIPTION NAME DCK, YZP DSF DPW A 1 1,5 A1 I LogicInputA B 2 2 B1 I LogicInputB GND 3 3 C1 — Ground NC — 5 — — NoInternalConnection Y 4 4 C2 O OutputY V 5 6 A2 — PositiveSupply CC Copyright©2004–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltage –0.5 6.5 V CC V Inputvoltage(2) –0.5 6.5 V I V Voltagerangeappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 6.5 V O I Inputclampcurrent V <0 –50 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent ±50 mA O ContinuouscurrentthroughV orGND ±100 mA CC T Maximumjunctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 2000 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) 1000 V (ESD) MachineModel(MM),A115-A 200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 www.ti.com SCES538G–JANUARY2004–REVISEDFEBRUARY2020 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Operating 1.65 5.5 V Supplyvoltage V CC Dataretentiononly 1.5 V =1.65Vto1.95V 0.65×V CC CC V =2.3Vto2.7V 1.7 CC V High-levelinputvoltage V IH V =3Vto3.6V 2 CC V =4.5Vto5.5V 0.7×V CC CC V =1.65Vto1.95V 0.35×V CC CC V =2.3Vto2.7V 0.7 CC V Low-levelinputvoltage V IL V =3Vto3.6V 0.8 CC V =4.5Vto5.5V 0.3×V CC CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 5.5 V O V =1.65V 4 CC V =2.3V 8 CC I Low-leveloutputcurrent 16 mA OL V =3V CC 24 V =4.5V 32 CC V =1.8V±0.15V,2.5V±0.2V 20 CC Δt/Δv Inputtransitionriseandfallrate V =3.3V±0.3V 10 ns/V CC V =5V±0.5V 5 CC T Operatingfree-airtemperature –40 125 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeeImplicationsofSloworFloating CC CMOSInputs. 6.4 Thermal Information SN74LVC1G38 THERMALMETRIC(1) DBV DCK DRY DSF YZP DPW UNIT (SOT-23) (SC70) (SON) (SON) (DSBGA) (X2SON) 5PINS 5PINS 6PINS 6PINS 5PINS 5PINS RθJA Junction-to-ambientthermalresistance 247.2 276.1 366.9 406.2 146.2 511.0 °C/W Junction-to-case(top)thermal RθJC(top) resistance 154.5 178.9 253.8 201.0 1.4 241.9 °C/W RθJB Junction-to-boardthermalresistance 86.8 70.9 227.5 256.9 39.3 374.2 °C/W Junction-to-topcharacterization ψJT parameter 58.0 47.0 75.8 35.2 0.7 45.0 °C/W Junction-to-boardcharacterization ψJB parameter 86.4 69.3 227.7 256.6 39.8 373.3 °C/W Junction-to-case(bottom)thermal RθJC(bot) resistance N/A N/A N/A N/A N/A 168.0 °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. Copyright©2004–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com 6.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS VCC MIN TYP(1) MAX UNIT TA=–40°Cto+85°C 1.65Vto IOL=100µA TA=–40°Cto+125°C 5.5V 0.1 TA=–40°Cto+85°C IOL=4mA 1.65V 0.45 TA=–40°Cto+125°C TA=–40°Cto+85°C IOL=8mA 2.3V 0.3 TA=–40°Cto+125°C VOL V TA=–40°Cto+85°C IOL=16mA 0.4 TA=–40°Cto+125°C 3V TA=–40°Cto+85°C IOL=24mA 0.55 TA=–40°Cto+125°C TA=–40°Cto+85°C IOL=32mA 4.5V 0.55 TA=–40°Cto+125°C TA=–40°Cto+85°C 1.65Vto II AorBinputs VI=5.5VorGND TA=–40°Cto+125°C 5.5V ±1 µA TA=–40°Cto+85°C Ioff VIorVO=5.5V 0 ±10 µA TA=–40°Cto+125°C TA=–40°Cto+85°C 1.65Vto ICC VI=5.5VorGND,IO=0 TA=–40°Cto+125°C 5.5V 10 µA ΔICC OOntheerinipnuptuatstaVtCVCCC–o0r.6GVN,D TTAA==––4400°°CCttoo++81525°C°C 3Vto5.5V 500 µA Ci VI=VCCorGND 3.3V 3.5 pF Co VO=VCCorGND 3.3V 4.5 pF (1) AlltypicalvaluesareatV =3.3V,T =25°C. CC A 6.6 Switching Characteristics, C = 15 pF L overrecommendedoperatingfree-airtemperaturerange,C =15pF(unlessotherwisenoted)(seeFigure2) L FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) VCC=1.8V±0.15V 2.9 7.4 VCC=2.5V±0.2V 1.7 3.8 tpd AorB Y TA=–40°Cto+85°C ns VCC=3.3V±0.3V 1.5 4.9 VCC=5V±0.5V 0.9 2.4 6.7 Switching Characteristics, C = 30 pF or 50 pF, –40°C to +85°C L overrecommendedoperatingfree-airtemperaturerange,C =30pFor50pF(unlessotherwisenoted)(seeFigure3) L FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) VCC=1.8V±0.15V 2.8 10 VCC=2.5V±0.2V 1.6 6 tpd AorB Y TA=–40°Cto+85°C ns VCC=3.3V±0.3V 1.4 4.5 VCC=5V±0.5V 1 3.9 6 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 www.ti.com SCES538G–JANUARY2004–REVISEDFEBRUARY2020 6.8 Switching Characteristics, C = 30 pF or 50 pF, –40°C to +125°C L overrecommendedoperatingfree-airtemperaturerange,C =30pFor50pF(unlessotherwisenoted)(seeFigure3) L FROM TO PARAMETER TESTCONDITIONS MIN MAX UNIT (INPUT) (OUTPUT) VCC=1.8V±0.15V 2.8 11 VCC=2.5V±0.2V 1.6 6.5 tpd AorB Y TA=–40°Cto+125°C ns VCC=3.3V±0.3V 1.4 5 VCC=5V±0.5V 1 4.4 6.9 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS TYP UNIT V =1.8V 3 CC V =2.5V 3 CC C Powerdissipationcapacitance f=10MHz pF pd V =3.3V 4 CC V =5V 6 CC 6.10 Typical Characteristics 0.35 0.3 0.25 V) 0.2 (OL V 0.15 0.1 VCC = 1.8 V 0.05 VCC = 2.5 V VCC = 3.3 V VCC = 5 V 0 0 5 10 15 20 25 30 35 IOL (mA) VOL_ Figure1.TypicalI vs.V (T =25°C) OL OL A Copyright©2004–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com 7 Parameter Measurement Information (OpenDrain) V LOAD R S1 Open From Output L TEST S1 UnderTest GND t (see Notes E and F) V C PZL LOAD (see Note A)L RL tPLZ(see Notes E and G) VLOAD t /t V PHZ PZH LOAD LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L ∆ I r f 1.8V±0.15V V ≤2 ns V /2 2 ×V 15 pF 1 MΩ 0.15V CC CC CC 2.5V±0.2V V ≤2 ns V /2 2 ×V 15 pF 1 MΩ 0.15V CC CC CC 3.3V±0.3V 3V ≤2.5 ns 1.5V 6V 15 pF 1 MΩ 0.3V 5V±0.5V V ≤2.5 ns V /2 2 ×V 15 pF 1 MΩ 0.3V CC CC CC V I Timing Input V M 0V t W VI tsu th V Input V V I M M Data Input V V M M 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSE DURATION SETUP AND HOLDTIMES Input VM VM VI COounttpruotl VM VM VI 0V 0V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WaSv1e afotrVm 1 VM V +V LOAD VOL (see NoteL OBAD) OL ∆ VOL t t PHL PLH t t PZH PHZ Output VM VM VVOOHL (WseSae1v eNaOftoo uGtretmpN Bu D2t) VM VOH–V∆ ≈V0OHV VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATION DELAYTIMES ENABLE AND DISABLETIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics:PRR≤10 MHz, Z = 50Ω. O D. The outputs are measured one at a time, with one transition per measurement. E. Because this device has open-drain outputs, t and t are the same as t . PLZ PZL PD F. t is measured atV . PZL M G.t is measured atV +V. PLZ OL ∆ H. All parameters and waveforms are not applicable to all devices. Figure2. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 www.ti.com SCES538G–JANUARY2004–REVISEDFEBRUARY2020 Parameter Measurement Information (continued) (OpenDrain) V LOAD R S1 Open From Output L TEST S1 UnderTest GND t (see Notes E and F) V C PZL LOAD (see Note A)L RL tPLZ(see Notes E and G) VLOAD t /t V PHZ PZH LOAD LOAD CIRCUIT INPUTS V V V C R V CC V t/t M LOAD L L ∆ I r f 1.8V±0.15V V ≤2 ns V /2 2 ×V 30 pF 1 kΩ 0.15V CC CC CC 2.5V±0.2V V ≤2 ns V /2 2 ×V 30 pF 500Ω 0.15V CC CC CC 3.3V±0.3V 3V ≤2.5 ns 1.5V 6V 50 pF 500Ω 0.3V 5V±0.5V V ≤2.5 ns V /2 2 ×V 50 pF 500Ω 0.3V CC CC CC V I Timing Input V M 0V t W VI tsu th V Input V V I M M Data Input V V M M 0V 0V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSE DURATION SETUP AND HOLDTIMES Input VM VM VI COounttpruotl VM VM VI 0V 0V t t t t PLH PHL PZL PLZ V Output V /2 Output VM VM OH WaSv1e afotrVm 1 VM V +V LOAD VOL (see NoteL OBAD) OL ∆ VOL t t PHL PLH t t PZH PHZ Output VM VM VVOOHL (WseSae1v eNaOftoo uGtretmpN Bu D2t) VM VOH–V∆ ≈V0OHV VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATION DELAYTIMES ENABLE AND DISABLETIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. C includes probe and jig capacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics:PRR≤10 MHz, Z = 50Ω. O D. The outputs are measured one at a time, with one transition per measurement. E. Because this device has open-drain outputs, t and t are the same as t . PLZ PZL PD F. t is measured atV . PZL M G.t is measured atV +V. PLZ OL ∆ H. All parameters and waveforms are not applicable to all devices. Figure3. LoadCircuitandVoltageWaveforms Copyright©2004–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com 8 Detailed Description 8.1 Overview TheSN74LVC1G38deviceis a single two-input NAND gate with open-drain outputs designed for 1.65-V to 5.5-V Vccoperation.ItperformstheBooleanfunctionY= A× BorY= A+Binpositivelogic. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs off off when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. 8.2 Functional Block Diagram 1 A 4 Y 2 B Figure4. LogicDiagram(PositiveLogic) 8.3 Feature Description 8.3.1 High-DriveOpen-DrainOutput Theopen-drainoutputallowsthedevicetosinkcurrentwhen the output is LOW and maintains a high impedance state when the output is HIGH. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the poweroutputofthedevicetobelimitedtoavoid thermal runaway and damage due to over-current. The electrical andthermallimitsdefinedtheintheAbsoluteMaximumRatingsmustbefollowedatalltimes. 8.3.2 StandardCMOSInputs Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the ElectricalCharacteristics,usingohm'slaw(R=V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-triggerinputshouldbeusedtoconditiontheinputsignalpriortothestandardCMOSinput. 10 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 www.ti.com SCES538G–JANUARY2004–REVISEDFEBRUARY2020 Feature Description (continued) 8.3.3 ClampDiodes Theinputsandoutputstothisdevicehavenegativeclampingdiodes. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings maybeexceedediftheinputandoutputclamp-currentratingsareobserved. Device VCC Input Logic Output -IIK -IOK GND Figure5. ElectricalPlacementofClampingDiodesforEachInputandOutput 8.3.4 PartialPowerDown(I ) off The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximumleakageintooroutofanyinputoroutputpinonthedeviceisspecifiedbyI inthe. off 8.3.5 Over-VoltageTolerantInputs Input signals to this device can be driven above the supply voltage so long as they remain below the maximum inputvoltagevaluespecifiedintheAbsoluteMaximumRatings. 8.3.6 UpTranslationandDownTranslationCapableOutputs Outputsof this device can be driven above the supply voltage so long as they remain below the maximum output voltage value specified in the Absolute Maximum Ratings. When the device is not actively driving LOW, the output is in the high impedance state. If a pull-up resistor is connected from the output to a power supply (of any valid value), the output will be driven by this supply, and therefore can have a voltage that is either higher or lower than the V supply of the device. An application of this device performing up-translation is depicted in CC ApplicationandImplementation,whereadditionaldesigndetailsareprovided. 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheSN74LVC1G38device. Table1.FunctionTable INPUTS OUTPUT A B Y L L Hi-Z L H Hi-Z H L Hi-Z H H L Copyright©2004–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information Open-drain devices are intrinsically capable of voltage translation. In this application, a 1.8-V logic signal is inverted and up-translated to 5 V at the output when the EN signal input is driven high by a 3.3-V signal. The outputisheldat5Vinthisscenariowhentheoutputofthedeviceisinthehighimpedancestate. 9.2 Typical Application V V 1 2 R A Y EN Figure6. GatedVoltageTranslatingInverterSchematicUsingSN74LVC1G38 9.2.1 DesignRequirements The supply voltage at V must be set to provide input thresholds for the signals A and EN. This device uses 1 CMOS technology and has an open-drain output. Outputs of open-drain devices can be tied directly together to produce a wired-OR configuration. This device has high current drive that will create fast edges into light loads soroutingandloadconditionsshouldbeconsideredtopreventringing. 9.2.2 DetailedDesignProcedure 1. RecommendedInputConditions – Risetimeandfalltimespecs.See(Δt/ΔV)intheRecommendedOperatingConditionstable. – Specifiedhighandlowlevels.See(VIHandVIL)intheRecommendedOperatingConditions table. – Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating ConditionstableatanyvalidVCC. 2. RecommendedOutputConditions – Load currents should not exceed (IO max). These limits are located in the Absolute Maximum Ratings table. – Outputs can be pulled above VCC for up-translation applications as long as the maximum output voltage intheAbsoluteMaximumRatingstableisobserved. 9.2.3 ApplicationCurve A EN Y Figure7.ApplicationTimingDiagram 12 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 www.ti.com SCES538G–JANUARY2004–REVISEDFEBRUARY2020 10 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the RecommendedOperatingConditionstable. The V pin should have a good bypass capacitor to prevent power disturbance. It is ok to parallel multiple CC bypass caps to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. Thebypasscapacitorshouldbeinstalledasclosetothepowerpinaspossibleforbestresults. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefinedvoltagesattheoutsideconnectionsresultinundefinedoperationalstates. Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or V ,whichevermakesmoresenseorismoreconvenient. CC Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore sometracesmustturncorners.Figure9 showsprogressively better techniques of rounding corners. Only the last example(BEST)maintainsconstanttracewidthandminimizesreflections. 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure8. Propermulti-gateinputterminationdiagram WORST BETTER BEST W 2 1W min. W Figure9. TraceExample Copyright©2004–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LVC1G38

SN74LVC1G38 SCES538G–JANUARY2004–REVISEDFEBRUARY2020 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • TexasInstruments,DesigningandManufacturingwithTI'sX2SONPackages ApplicationNote • TexasInstruments,HowtoSelectLittleLogicApplicationNote • TexasInstruments,ImplicationsofSloworFloatingCMOSInputs ApplicationNote. • TexasInstruments,UnderstandingandInterpretingStandard-LogicDataSheets ApplicationNote • TexasInstruments,IntroductiontoLogicApplicationNote • TexasInstruments,SignalSwitchDataBookUser'sGuide • TexasInstruments,LVCandLVLow-VoltageCMOSLogicDataBook User'sGuide • TexasInstruments,Low-VoltageLogic(LVC)Designer'sGuideUser'sGuide 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight fromtheexperts.Searchexistinganswersoraskyourownquestiontogetthequickdesignhelpyouneed. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do notnecessarilyreflectTI'sviews;seeTI'sTermsofUse. 12.4 Trademarks NanoStar,NanoFree,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 14 SubmitDocumentationFeedback Copyright©2004–2020,TexasInstrumentsIncorporated ProductFolderLinks:SN74LVC1G38

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LVC1G38DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C385, C38F, C38J, & no Sb/Br) C38R) (C38H, C38P, C38S) SN74LVC1G38DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C385 & no Sb/Br) C38S SN74LVC1G38DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C385 & no Sb/Br) C38S SN74LVC1G38DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C385, C38J, C38R) & no Sb/Br) (C38H, C38S) SN74LVC1G38DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 C385 & no Sb/Br) C38S SN74LVC1G38DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (D75, D7F, D7J, D7 & no Sb/Br) R) (D7H, D7P, D7S) SN74LVC1G38DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 D75 & no Sb/Br) D7S SN74LVC1G38DCKT ACTIVE SC70 DCK 5 250 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (D75, D7J, D7R) & no Sb/Br) (D7H, D7S) SN74LVC1G38DPWR ACTIVE X2SON DPW 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 BP & no Sb/Br) SN74LVC1G38DRYR ACTIVE SON DRY 6 5000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 D7 & no Sb/Br) SN74LVC1G38DSFR ACTIVE SON DSF 6 5000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 D7 & no Sb/Br) SN74LVC1G38YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 D7N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LVC1G38DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1G38DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1G38DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G38DBVRG4 SOT-23 DBV 5 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G38DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G38DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 SN74LVC1G38DBVTG4 SOT-23 DBV 5 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3 SN74LVC1G38DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G38DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74LVC1G38DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G38DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G38DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1G38DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G38DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 SN74LVC1G38DPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q3 SN74LVC1G38DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC1G38DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1G38YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LVC1G38DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74LVC1G38DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G38DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G38DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G38DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G38DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G38DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G38DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G38DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74LVC1G38DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G38DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G38DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G38DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G38DCKT SC70 DCK 5 250 202.0 201.0 28.0 SN74LVC1G38DPWR X2SON DPW 5 3000 205.0 200.0 33.0 SN74LVC1G38DRYR SON DRY 6 5000 184.0 184.0 19.0 SN74LVC1G38DSFR SON DSF 6 5000 184.0 184.0 19.0 SN74LVC1G38YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DPW0005A X2SON - 0.4 mm max height SCALE 12.000 PLASTIC SMALL OUTLINE - NO LEAD B 0.85 A 0.75 PIN 1 INDEX AREA 0.85 0.75 0.4 MAX C SEATING PLANE NOTE 3 (0.1) 0.05 (0.25) 4X (0.05) 0.00 0.25 0.1 2 4 NOTE 3 2X 3 2X (0.26) 0.48 5 1 0.27 0.27 4X 0.17 0.17 0.1 C A B (0.06) 0.05 C 0.32 3X 0.23 4223102/B 09/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. www.ti.com

EXAMPLE BOARD LAYOUT DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.78) SYMM ( 0.1) 4X (0.42) VIA 0.05 MIN ALL AROUND 1 TYP 5 4X (0.22) SYMM 4X (0.26) (0.48) 3 2 4 (R0.05) TYP SOLDER MASK 4X (0.06) OPENING, TYP ( 0.25) (0.21) TYP METAL UNDER EXPOSED METAL SOLDER MASK CLEARANCE TYP LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X 4223102/B 09/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DPW0005A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42) 4X (0.06) 5 4X (0.22) 1 ( 0.24) 4X (0.26) SYMM (0.21) (0.48) TYP SOLDER MASK 3 EDGE 2 4 (R0.05) TYP SYMM (0.78) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X 4223102/B 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE YZP0005 DSBGA - 0.5 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.05 C 0.15 BALL TYP 0.5 TYP C SYMM 1 B D: Max = 1.418 mm, Min =1 .358 mm TYP 0.5 TYP E: Max = 0.918 mm, Min =0 .858 mm A 0.25 5X 1 2 0.21 0.015 C A B SYMM 4219492/A 05/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.23) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23) OPENING SOLDER MASK OPENING ( 0.23) METAL METAL UNDER SOLDER MASK NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219492/A 05/2017 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZP0005 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 5X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM C METAL SYMM TYP SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219492/A 05/2017 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

PACKAGE OUTLINE DSF0006A X2SON - 0.4 mm max height SCALE 10.000 PLASTIC SMALL OUTLINE - NO LEAD 1.05 B A 0.95 PIN 1 INDEX AREA 1.05 0.95 0.4 MAX C SEATING PLANE 0.05 C (0.11) TYP SYMM 0.05 0.00 3 4 2X SYMM 0.7 4X 0.35 6 1 0.22 6X 0.12 (0.1) PIN 1 ID 0.45 0.07 C B A 6X 0.35 0.05 C 4220597/A 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF. www.ti.com

EXAMPLE BOARD LAYOUT DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:40X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220597/A 06/2017 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DSF0006A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 6X (0.6) (R0.05) TYP 1 6X (0.17) 6 SYMM 4X (0.35) 4 3 SYMM (0.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:40X 4220597/A 06/2017 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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GENERIC PACKAGE VIEW DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4207181/G

PACKAGE OUTLINE DRY0006A USON - 0.6 mm max height SCALE 8.500 PLASTIC SMALL OUTLINE - NO LEAD B 1.05 A 0.95 PIN 1 INDEX AREA 1.5 1.4 0.6 MAX C SEATING PLANE 0.05 0.00 0.08 C 3X 0.6 SYMM (0.127) TYP (0.05) TYP 3 4 4X 0.5 SYMM 2X 1 6 1 0.25 6X 0.15 0.4 0.3 0.1 C A B 0.05 C PIN 1 ID (OPTIONAL) 0.35 5X 0.25 4222894/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4222894/A 01/2018 NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN DRY0006A USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM (0.35) 5X (0.3) 1 6 6X (0.2) SYMM 4X (0.5) 4 3 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X 4222894/A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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