Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 SN74LV4052A Dual 4-Channel Analog Multiplexers and Demultiplexers 1 Features 3 Description • 2-Vto5.5-VV Operation The SN74LV4052A device is a dual, 4-channel 1 CC CMOS analog multiplexer and demultiplexer that is • FastSwitching designedfor2-Vto5.5-VV operation. CC • HighOn-OffOutput-VoltageRatio The SN74LV4052A device handles both analog and • LowCrosstalkBetweenSwitches digital signals. Each channel permits signals with • ExtremelyLowInputCurrent amplitudes up to 5.5 V (peak) to be transmitted in • Latch-UpPerformanceExceeds100mAPer eitherdirection. JESD78,ClassII DeviceInformation(1) • ESDProtectionExceedsJESD22: PARTNUMBER PACKAGE BODYSIZE(NOM) – 2000-VHuman-BodyModel(A114-A) SN74LV4052AD SOIC(16) 9.90mm×3.91mm – 1000-VCharged-DeviceModel(C101) SN74LV4052ADB SSOP(16) 6.20mm×5.30mm SN74LV4052ADGV TVSOP(16) 3.60mm×4.40mm 2 Applications SN74LV4052ANS SO(16) 10.30mm×5.30mm • Telecomunications SN74LV4052AN PDIP(16) 19.30mm×6.35mm • Infotainment SN74LV4052APW TSSOP(16) 5.00mm×4.40mm • SignalGatingandIsolation SN74LV4052ARGY VQFN(16) 4.00mm×3.50mm • HomeAppliances (1) For all available packages, see the orderable addendum at • ProgrammableLogicCircuits theendofthedatasheet. • ModulationandDemodulation LogicDiagram(PositiveLogic) 13 1-COM 12 1Y0 10 A 14 1Y1 15 1Y2 9 11 B 1Y3 1 2Y0 5 2Y1 2 2Y2 6 INH 4 2Y3 3 2-COM Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.UNLESSOTHERWISENOTED,thisdocumentcontainsPRODUCTION DATA.

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................12 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................12 3 Description............................................................. 1 8.3 FeatureDescription.................................................12 8.4 DeviceFunctionalModes........................................12 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 13 5 PinConfigurationandFunctions......................... 3 9.1 ApplicationInformation............................................13 6 Specifications......................................................... 4 9.2 TypicalApplication..................................................13 6.1 AbsoluteMaximumRatings......................................4 10 PowerSupplyRecommendations..................... 15 6.2 ESDRatings..............................................................4 11 Layout................................................................... 15 6.3 RecommendedOperatingConditions.......................4 6.4 ThermalInformation..................................................5 11.1 LayoutGuidelines.................................................15 6.5 ElectricalCharacteristics...........................................5 11.2 LayoutExample....................................................15 6.6 SwitchingCharacteristics:V =2.5V±0.2V........6 12 DeviceandDocumentationSupport................. 16 CC 6.7 SwitchingCharacteristics:V =3.3V±0.3V........6 12.1 DocumentationSupport .......................................16 CC 6.8 SwitchingCharacteristics:V =5V±0.5V...........6 12.2 ReceivingNotificationofDocumentationUpdates16 CC 6.9 SwitchingCharacteristics:Analog.............................7 12.3 CommunityResource............................................16 6.10 OperatingCharacteristics........................................7 12.4 Trademarks...........................................................16 6.11 TypicalCharacteristics............................................7 12.5 ElectrostaticDischargeCaution............................16 7 ParameterMeasurementInformation..................8 12.6 Glossary................................................................16 8 DetailedDescription............................................ 12 13 Mechanical,Packaging,andOrderable Information........................................................... 16 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionJ(October2012)toRevisionK Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedOrderingInformationtable;seePackageOptionAddendumattheendofthedatasheet...................................... 1 • DeletedSN54LV4052Afromdatasheet................................................................................................................................ 1 • ChangedPackagethermalimpedance,R ,valuesintheThermalInformationtableFrom:73To:90.9(D),From: θJA 82To:102.8(DB),From:120To:125.7(DGV),From:67To:54.8(N),From:64To:89.7(NS),From:108To: 113.2(PW),andFrom:39To:48.9(RGY)............................................................................................................................ 5 2 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 5 Pin Configuration and Functions D,DB,DGV,N,NS,orPWPackage RGYPackage 16-PinSOIC,SSOP,TVSOP,SO,PDIP,orTSSOP 16-PinVQFNWithThermalPad TopView TopView Y0 CC 2 V 2Y0 1 16 VCC 2Y2 2 15 1Y2 1 6 1 2-COM 3 14 1Y1 2Y2 2 15 1Y2 2Y3 4 13 1-COM 2-COM 3 14 1Y1 2Y1 5 12 1Y0 2Y3 4 Thermal 13 1-COM Pad INH 6 11 1Y3 2Y1 5 12 1Y0 GND 7 10 A INH 6 11 1Y3 GND 8 9 B GND 7 10 A 8 9 Not to scale Not to scale D B N G PinFunctions PIN I/O DESCRIPTION NO. NAME 1 2Y0 I/O Port2channel0 2 2Y2 I/O Port2channel2 3 2-COM I/O Port2commonchannel 4 2Y3 I/O Port2channel3 5 2Y1 I/O Port2channel1 6 INH I Inhibitinput 7 GND — Deviceground 8 GND — Deviceground 9 B I LogicinputselectorB 10 A I LogicinputselectorA 11 1Y3 I/O Port1channel3 12 1Y0 I/O Port1channel0 13 1-COM I/O Port1commonchannel 14 1Y1 I/O Port1channel1 15 1Y2 I/O Port1channel2 16 V — Devicepower CC Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Supplyvoltage,V –0.5 7 V CC Inputvoltage,V(2) –0.5 7 V I SwitchI/Ovoltage,V (2)(3) –0.5 V +0.5 V IO CC Inputclampcurrent,I V <0 –20 mA IK I I/Odiodecurrent,I V <0andV >V 50 mA IOK IO IO CC Switchthroughcurrent,I V =0toV ±25 mA T IO CC ContinuouscurrentthroughV orGND ±50 mA CC Junctiontemperature,T 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thisvalueislimitedto5.5Vmaximum. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±4000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±2000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.TestedonD package 6.3 Recommended Operating Conditions see(1) MIN MAX UNIT V Supplyvoltage 2(2) 5.5 V CC V =2V 1.5 CC V =2.3Vto2.7V V ×0.7 CC CC V High-levelinputvoltage(controlinputs) V IH V =3Vto3.6V V ×0.7 CC CC V =4.5Vto5.5V V ×0.7 CC CC V =2V 0.5 CC V =2.3Vto2.7V V ×0.3 CC CC V Low-levelinputvoltage(controlinputs) V IL V =3Vto3.6V V ×0.3 CC CC V =4.5Vto5.5V V ×0.3 CC CC V Controlinputvoltage 0 5.5 V I V Inputoroutputvoltage 0 V V IO CC V =2.3Vto2.7V 200 CC Δt/Δv Inputtransitionriseorfallrate V =3Vto3.6V 100 ns/V CC V =4.5Vto5.5V 20 CC T Operatingfree-airtemperature –40 85 °C A (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeeImplicationsofSloworFloating CC CMOSInputs(SCBA004). (2) Withsupplyvoltagesatornear2V,theanalogswitchon-stateresistancebecomesverynonlinear.TIrecommendsthatonlydigital signalsbetransmittedattheselowsupplyvoltages. 4 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 6.4 Thermal Information SN74LV4052A THERMALMETRIC(1) D DB DGV N NS PW RGY UNIT (SOIC) (SSOP) (TVSOP) (PDIP) (SO) (TSSOP) (VQFN) 16PINS 16PINS 16PINS 16PINS 16PINS 16PINS 16PINS RθJA Junction-to-ambientthermalresistance 90.9 102.8 125.7 54.8 89.7 113.2 48.9 °C/W RθJC(top) Junction-to-case(top)thermalresistance 51.9 53.3 50.9 42.1 48.1 48.2 46.9 °C/W RθJB Junction-to-boardthermalresistance 48 53.4 57.5 34.8 50.1 58.3 25 °C/W ψJT Junction-to-topcharacterizationparameter 18.6 16.5 5.6 26.9 16.7 6.3 2 °C/W ψJB Junction-to-boardcharacterizationparameter 47.8 52.9 57 34.7 49.8 57.8 25 °C/W RθJC(bot) Junction-to-case(bottom)thermalresistance — — — — — — 11.7 °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T =25°C 43 180 A V =2.3V CC T =–40to85°C 225 A IT=2mA,VI=VCC TA=25°C 34 150 r On-stateswitchresistance orGND,V =V V =3V Ω on INH IL CC (seeFigure2) TA=–40to85°C 190 T =25°C 25 75 A V =4.5V CC T =–40to85°C 100 A T =25°C 133 500 A V =2.3V CC T =–40to85°C 600 A r Peakon-stateresistance IT=2mA,VI=VCC V =3V TA=25°C 63 180 Ω on(p) toGND,VINH=VIL CC TA=–40to85°C 225 T =25°C 35 100 A V =4.5V CC T =–40to85°C 125 A T =25°C 1.5 30 A V =2.3V CC T =–40to85°C 40 A Δr Differenceinon-state IT=2mA,VI=VCC V =3V TA=25°C 1.1 20 Ω on resistancebetweenswitches toGND,VINH=VIL CC TA=–40to85°C 30 T =25°C 0.7 15 A V =4.5V CC T =–40to85°C 20 A T =25°C ±0.1 A I Controlinputcurrent V =5.5VorGND,andV =0to5.5V µA I I CC T =–40to85°C ±1 A V =V andV =GND,orV =GND T =25°C ±0.1 OFF-stateswitchleakage I CC O I A I andV =V ,V =V ,and µA S(off) current VCC=O5.5VCC(seeINFHigureIH3) TA=–40to85°C ±1 I ON-stateswitchleakage VI=VCCorGND,VINH=VIL,and TA=25°C ±0.1 µA S(on) current VCC=5.5V(seeFigure4) TA=–40to85°C ±1 I Supplycurrent V =V orGND,V =5.5V,andT =–40to85°C 20 µA CC I CC CC A C Controlinputcapacitance f=10MHz,V =3.3V,andT =25°C 2.1 pF IC CC A Commonterminal C V =3.3VandT =25°C 13.1 pF IS capacitance CC A C Switchterminalcapacitance V =3.3VandT =25°C 5.6 pF OS CC A C Feedthroughcapacitance V =3.3VandT =25°C 0.5 pF F CC A Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com 6.6 Switching Characteristics: V = 2.5 V ± 0.2 V CC overrecommendedoperatingfree-airtemperaturerangeandV =2.5V±0.2V(unlessotherwisenoted) CC FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) tPLH Propagation COMorY YorCOM CL=15pF TA=25°C 1.9 10 ns tPHL delaytime (seeFigure5) TA=–40to85°C 16 tPZH Enabledelaytime INH COMorY CL=15pF TA=25°C 8 18 ns tPZL (seeFigure6) TA=–40to85°C 23 tPHZ Disabledelaytime INH COMorY CL=15pF TA=25°C 8.3 18 ns tPLZ (seeFigure6) TA=–40to85°C 23 tPLH Propagation COMorY YorCOM CL=50pF TA=25°C 3.8 12 ns tPHL delaytime (seeFigure5) TA=–40to85°C 18 tPZH Enabledelaytime INH COMorY CL=50pF TA=25°C 9.4 28 ns tPZL (seeFigure6) TA=–40to85°C 35 tPHZ Disabledelaytime INH COMorY CL=50pF TA=25°C 12.4 28 ns tPLZ (seeFigure6) TA=–40to85°C 35 6.7 Switching Characteristics: V = 3.3 V ± 0.3 V CC overrecommendedoperatingfree-airtemperaturerangeandV =3.3V±0.3V(unlessotherwisenoted) CC FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) tPLH Propagation COMorY YorCOM CL=15pF TA=25°C 1.2 6 ns tPHL delaytime (seeFigure5) TA=–40to85°C 10 tPZH Enabledelaytime INH COMorY CL=15pF TA=25°C 5.7 12 ns tPZL (seeFigure6) TA=–40to85°C 15 tPHZ Disabledelaytime INH COMorY CL=15pF TA=25°C 6.6 12 ns tPLZ (seeFigure6) TA=–40to85°C 15 tPLH Propagation COMorY YorCOM CL=50pF TA=25°C 2.5 9 ns tPHL delaytime (seeFigure5) TA=–40to85°C 12 tPZH Enabledelaytime INH COMorY CL=50pF TA=25°C 6.7 20 ns tPZL (seeFigure6) TA=–40to85°C 25 tPHZ Disabledelaytime INH COMorY CL=50pF TA=25°C 9.5 20 ns tPLZ (seeFigure6) TA=–40to85°C 25 6.8 Switching Characteristics: V = 5 V ± 0.5 V CC overrecommendedoperatingfree-airtemperaturerangeandV =5V±0.5V(unlessotherwisenoted) CC FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) tPLH Propagation COMorY YorCOM CL=15pF TA=25°C 0.7 4 ns tPHL delaytime (seeFigure5) TA=–40to85°C 7 tPZH Enabledelaytime INH COMorY CL=15pF TA=25°C 4 8 ns tPZL (seeFigure6) TA=–40to85°C 10 tPHZ Disabledelay INH COMorY CL=15pF TA=25°C 5 8 ns tPLZ time (seeFigure6) TA=–40to85°C 10 tPLH Propagation COMorY YorCOM CL=50pF TA=25°C 1.5 6 ns tPHL delaytime (seeFigure5) TA=–40to85°C 8 tPZH Enabledelaytime INH COMorY CL=50pF TA=25°C 4.7 14 ns tPZL (seeFigure6) TA=–40to85°C 18 6 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 Switching Characteristics: V = 5 V ± 0.5 V (continued) CC overrecommendedoperatingfree-airtemperaturerangeandV =5V±0.5V(unlessotherwisenoted) CC FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) tPHZ Disabledelay INH COMorY CL=50pF TA=25°C 6.9 14 ns tPLZ time (seeFigure6) TA=–40to85°C 18 6.9 Switching Characteristics: Analog overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) FROM TO PARAMETER TESTCONDITIONS MIN TYP MAX UNIT (INPUT) (OUTPUT) V =2.3V 30 C =50pF,R =600Ω, CC Frequencyresponse L L COMorY YorCOM f =1MHz(sinewave) V =3V 35 MHz (switchon) (isneeFigure7)(1) CC V =4.5V 50 CC V =2.3V –45 C =50pF,R =600Ω, CC Crosstalk(betweenany L L COMorY YorCOM f =1MHz(sinewave) V =3V –45 dB switches) (isneeFigure8)(2) CC V =4.5V –45 CC V =2.3V 20 C =50pF,R =600Ω, CC Crosstalk(controlinput L L INH COMorY f =1MHz(sinewave) V =3V 35 mV tosignaloutput) in CC (seeFigure9) V =4.5V 65 CC V =2.3V –45 Feedthrough C =50pF,R =600Ω, CC L L attenuation COMorY YorCOM f =1MHz(sinewave) V =3V –45 dB in CC (switchoff) (seeFigure10)(2) V =4.5V –45 CC V =2V and I p-p 0.1% CL=50pF, VCC=2.3V R =10kΩ, L V =2.5V and Sine-wavedistortion COMorY YorCOM f =1kHz I p-p 0.1% in V =3V (sinewave) CC (seeFigure11) VI=4Vp-pand 0.1% V =4.5V CC (1) Adjustf voltagetoobtain0dBmatoutput.IncreasefinfrequencyuntildBmeterreads–3dB. in (2) Adjustf voltagetoobtain0dBmatinput. in 6.10 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS TYP UNIT C Powerdissipationcapacitance C =50pFandf=10MHz 11.8 pF pd L 6.11 Typical Characteristics 3.9 3.6 CL =15pF CL= 50pF 3.3 3 s) 2.7 p (n 2.4 y tD 2.1 P T 1.8 1.5 1.2 0.9 0.6 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 Vcc (V) D001 Figure1.TypicalPropagationDelayvsV cc Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com 7 Parameter Measurement Information V CC V =V INH IL V CC VI=VCCorGND (ON) VO GND V –V r I O W on 2 10–3 2mA V V −V I O Figure2. ON-StateResistanceTestCircuit V CC V =V INH IH V CC VI A (OFF) VO GND Condition1:V =0,V =V I O CC Condition2:V =V ,V =0 I CC O Figure3. OFF-StateSwitchLeakage-CurrentTestCircuit V CC V =V INH IL V CC VI A (ON) Open GND V =V orGND I CC Figure4. ON-StateSwitchLeakage-CurrentTestCircuit 8 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 Parameter Measurement Information (continued) V CC V =V INH IL V CC Input (ON) Output 50Ω GND C L Figure5. PropagationDelayTime,SignalInputtoSignalOutput VCC 50Ω VINH TEST S1 S2 VCC tPLZ/tPZL GND VCC VI VO RL=1kΩ tPHZ/tPZH VCC GND S1 S2 GND CL TESTCIRCUIT VCC VCC VINH 50% VINH 50% 0 V 0 V tPZL tPZH ≈VCC VOH VO 50% VO 50% VOL ≈0V (tPZL,tPZH) VCC VCC VINH 50% VINH 50% 0 V 0V tPLZ tPHZ ≈VCC VOH VOH−0.3V VO VOL+0.3V VO VOL ≈0V (tPLZ,tPHZ) VOLTAGEWAVEFORMS Figure6. SwitchingTime(t ,t ,t ,t ),ControltoSignalOutput PZL PLZ PZH PHZ Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com Parameter Measurement Information (continued) V CC V =GND INH 0.1μF V V CC I fin (ON) VO GND 50Ω RL=600Ω CL=50pF V /2 CC NOTEA: f is a sine wave. in Figure7. FrequencyResponse(SwitchON) V CC V =GND INH 0.1μF V V CC I fin (ON) VO1 600Ω GND 50Ω RL=600Ω CL=50pF V /2 CC V CC V =V INH CC V CC (OFF) V O2 GND 600Ω RL=600Ω CL=50pF V /2 CC Figure8. CrosstalkBetweenAnyTwoSwitches 10 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 Parameter Measurement Information (continued) V 50Ω CC V INH V CC fin VO GND 600Ω RL=600Ω CL=50pF V /2 V /2 CC CC Figure9. CrosstalkBetweenControlInputandSwitchOutput V CC V =V INH CC 0.1μF V V CC fin I (OFF) VO GND 50Ω 600Ω RL=600Ω CL=50pF V /2 V /2 CC CC Figure10. FeedthroughAttenuation(SwitchOFF) V CC V =GND INH 10μF V CC V fin I (ON) VO GND 600Ω RL=10kΩ CL=50pF V /2 CC Figure11. Sine-WaveDistortion Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com 8 Detailed Description 8.1 Overview The SN74LV4052A device is a dual, 4-channel CMOS analog multiplexer and demultiplexer that is designed for 2-V to 5.5-V V operation. It has low input current consumption at the digital input pins and low crosstalk CC between switches. The active low Inhibit (INH) tri-state all the channels when high and when low, depending on the A and B inputs, one of the four independent input/outputs (nY0 - nY3) connects to the COM channel. The SN74LV4052AisavailableinmultiplepackageoptionsincludingTSSOP(PW)andQFN(RGY). 8.2 Functional Block Diagram 13 1-COM 12 1Y0 10 A 14 1Y1 15 1Y2 9 11 B 1Y3 1 2Y0 5 2Y1 2 2Y2 6 INH 4 2Y3 3 2-COM Copyright © 2016,Texas Instruments Incorporated Figure12. LogicDiagram(PositiveLogic) 8.3 Feature Description • The SN74LV4052A operates from 2-V to 5.5-V V with extremely low input current consumption at the CC CMOSinputpinsofA,BandINH. • The SN74LV4052A enables fast switching with low crosstalk between the switches. 5.5 V peak level bidirectionaltransmissionallowedwiththeeitheranalogordigitalsignals. 8.4 Device Functional Modes Table1liststhefunctionalmodesofSN74LV4052A. Table1.FunctionTable INPUTS ON INH B A CHANNELS L L L 1Y0,2Y0 L L H 1Y1,2Y1 L H L 1Y2,2Y2 L H H 1Y3,2Y3 H X X None 12 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information TypicalapplicationsfortheSN74LV4052Aincludesignalgating,chopping,modulationordemodulation(modem), andsignalmultiplexingforanalog-to-digitalanddigital-to-analogconversionsystems. 9.2 Typical Application 3.3V SN74LV4052A 4 4 4 4 4 4 4 4 .7 .7 .7 .7 .7 .7 .7 .7 k k k k k k k k (cid:13) (cid:13) (cid:13) (cid:13) (cid:13) (cid:13) (cid:13) (cid:13) 1Y0 SDA1 1Y1 SDA2 1Y2 SDAx 1COM SDA3 1Y3 SDA4 SCLx 2COM 2Y0 SCL1 2Y1 SCL2 2Y2 SCL3 2Y3 SCL4 A B INH MCU Copyright ' 2016, Texas Instruments Incorporated Figure13. TypicalI2CMultiplexingApplication 9.2.1 DesignRequirements Designing with the SN74LV4052A device requires a stable input voltage between 2 V and 5.5 V (see Recommended Operating Conditions for details). Another important design consideration are the characteristics of the signal being multiplexed which ensures no important information is lost due to timing or incompatibility with thisdevice. 9.2.2 DetailedDesignProcedure The SN74LV4052A dual 1- to 4-channel multiplexer is ideal for I2C selection. The I2C data and clock lines are selected using A,B select lines from the MCU. The pullup resistors are selected based on the capability of the driver. Low pullup resistor results in faster rise time; however, it generates additional current during the low state into the driver. See to the Recommended Operating Conditions of the datasheet for the input transition rates (V IH andV )oftheCMOSinputs. IL Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com Typical Application (continued) 9.2.3 ApplicationCurve 18 17 CL=15pF CL = 50pF 16 15 s) 14 n x ( 13 a m 12 D TP 11 10 9 8 7 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 Vcc(V) D001 Figure14.MaximumPropagationDelayvsV cc 14 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

SN74LV4052A www.ti.com SCLS429K–MAY1999–REVISEDNOVEMBER2016 10 Power Supply Recommendations Most systems have a common 3.3-V or 5-V rail that can supply the V pin of this device. If this rail is not CC available, a switched-mode power supply (SMPS) or a low dropout regulator (LDO) can supply this device from a higher-voltagerail. See the Recommended Operating Conditions for operating voltage range for this device. Having bypass capacitorsof0.1 µFishighlyrecommended. 11 Layout 11.1 Layout Guidelines TI recommends keeping the signal lines as short and as straight as possible (see Figure 15). Incorporation of microstriporstriplinetechniquesarealsorecommendedwhensignallinesaremorethan1in.long.Thesetraces must be designed with a characteristic impedance of either 50-Ω or 75-Ω as required by the application. Do not place this device too close to high-voltage switching components because they may cause interference. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 16 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. 11.2 Layout Example Figure15. LayoutSchematic WORST BETTER BEST W 2 1W min. W Figure16. TraceExample Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:SN74LV4052A

SN74LV4052A SCLS429K–MAY1999–REVISEDNOVEMBER2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: ImplicationsofSloworFloatingCMOSInputs (SCBA004) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 16 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:SN74LV4052A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV4052AD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LV4052A & no Sb/Br) SN74LV4052ADBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052ADR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LV4052A & no Sb/Br) SN74LV4052AN ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74LV4052AN & no Sb/Br) SN74LV4052ANSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 74LV4052A & no Sb/Br) SN74LV4052APW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052APWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052APWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 LW052A & no Sb/Br) SN74LV4052ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 LW052A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LV4052A : •Automotive: SN74LV4052A-Q1 •Enhanced Product: SN74LV4052A-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV4052ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV4052ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4052ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74LV4052ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV4052APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4052APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4052APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4052APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV4052ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV4052ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV4052ADR SOIC D 16 2500 333.2 345.9 28.6 SN74LV4052ADR SOIC D 16 2500 364.0 364.0 27.0 SN74LV4052ANSR SO NS 16 2000 367.0 367.0 38.0 SN74LV4052APWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV4052APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV4052APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74LV4052APWT TSSOP PW 16 250 367.0 367.0 35.0 SN74LV4052ARGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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