Product Sample & Technical Tools & Support & Folder Buy Documents Software Community SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 1 Features 3 Description • 2-Vto5.5-VV Operation The 'LV132A devices are quadruple positive-NAND 1 CC gatesdesignedfor2-Vto5.5-VV operation. • Maxt of9nsat5V CC pd The 'LV132A devices perform the Boolean function Y • TypicalV (OutputGroundBounce) <0.8Vat OLP =A•BorY= A+Binpositivelogic. V =3.3V,T =25°C CC A • TypicalV (OutputV Undershoot)>2.3Vat Each circuit functions as a NAND gate, but because OHV OH V =3.3V,T =25°C of the Schmitt trigger, it has different input threshold CC A levelsforpositive-andnegative-goingsignals. • SupportMixed-ModeVoltageOperationonAll Ports These circuits are temperature compensated and can be triggered from the slowest of input ramps and still • Latch-UpPerformanceExceeds250mAper givecleanjitter-freeoutputsignals. JESD17 • IoffSupportsLiveInsertion,PartialPower-Down DeviceInformation(1) Mode,andBackDriveProtection PARTNUMBER PACKAGE BODYSIZE(NOM) • ESDProtectionExceedsJESD22 SOIC(14) 8.65mm×3.91mm – 2000-VHuman-BodyModel(A114-A) 10.30mm×5.30 SOP(14) – 200-VMachineModel(A115-A) mm LV132A SSOP(14) 6.20mm×5.30mm – 1000-VCharged-DeviceModel(C101) TSSOP(14) 5.00mm×4.40mm 2 Applications TVSOP(14) 3.60mm×4.40mm • IndustrialPC:RuggedPCandLaptop (1) For all available packages, see the orderable addendum at theendofthedatasheet. • AccessControlandSecurity:Camera SurveillanceIPNetwork • Vending,PaymentandChangeMachines • PatientMonitoringSTB/DVR/StreamingMedia (Withdraw) • OtherMotorDrives(SuchasSwitchReluctance) 4 Logic Diagram (Positive Logic) A Y B 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9 DetailedDescription.............................................. 9 2 Applications........................................................... 1 9.1 Overview...................................................................9 3 Description............................................................. 1 9.2 FunctionalBlockDiagram.........................................9 4 LogicDiagram(PositiveLogic)............................ 1 9.3 FeatureDescription...................................................9 9.4 DeviceFunctionalModes..........................................9 5 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 10 6 PinConfigurationandFunctions......................... 3 10.1 ApplicationInformation..........................................10 7 Specifications......................................................... 4 10.2 TypicalApplication ...............................................10 7.1 AbsoluteMaximumRatings .....................................4 11 PowerSupplyRecommendations..................... 11 7.2 ESDRatings..............................................................4 12 Layout................................................................... 11 7.3 RecommendedOperatingConditions.......................4 7.4 ThermalInformation..................................................5 12.1 LayoutGuidelines.................................................11 7.5 ElectricalCharacteristics...........................................5 12.2 LayoutExample....................................................11 7.6 SwitchingCharacteristics..........................................6 13 DeviceandDocumentationSupport................. 12 7.7 SwitchingCharacteristics..........................................6 13.1 RelatedLinks........................................................12 7.8 SwitchingCharacteristics..........................................6 13.2 Trademarks...........................................................12 7.9 NoiseCharacteristicsforSN74LV132A....................6 13.3 ElectrostaticDischargeCaution............................12 7.10 OperatingCharacteristics........................................6 13.4 Glossary................................................................12 7.11 TypicalCharacteristics............................................7 14 Mechanical,Packaging,andOrderable Information........................................................... 12 8 ParameterMeasurementInformation..................8 5 Revision History ChangesfromRevisionI(June2010)toRevisionJ Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • Updatedoperatingfree-airtemperaturemaximumfrom85°Cto125°CforSN74LV126A ................................................... 4 2 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A www.ti.com SCLS394J–APRIL1999–REVISEDFEBRUARY2015 6 Pin Configuration and Functions SN54LV132A:JorWPackage SN74LV132A:D,DB,DGV,NS,orPWPackage SN54LV132A:FKPackage (TopView) (TopView) C B A C CB 1A 1 14 VCC 1 1 N V 4 1B 2 13 4B 3 2 1 20 19 1Y 3 12 4A 1Y 4 18 4A 2A 4 11 4Y NC 5 17 NC 2B 5 10 3B 2A 6 16 4Y 2Y 6 9 3A NC 7 15 NC GND 7 8 3Y 2B 8 14 3B 9 10 11 12 13 YD CY A 2N N3 3 G A. NC-Nointernalconnection PinFunctions PIN I/O DESCRIPTION NO. NAME 1 1A I 1Ainput 2 1B I 1B 3 1Y O 1Y 4 2A I 2A 5 2B I 2B 6 2Y O 2Y 7 GND — GND 8 3Y O 3Y 9 3A I 3A 10 3B I 3B 11 4Y O 4Y 12 4A I 4A 13 4B I 4B 14 V — V CC CC Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperature(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage –0.5 7 V CC V Inputvoltage(2) –0.5 7 V I V Voltageappliedtoanyoutputinthehigh-impedanceorpower-offstate(2) –0.5 7 V O V Outputvoltage(2) (3) –0.5 V +0.5 V O CC I Inputclampcurrent V <0 –20 mA IK I I Outputclampcurrent V <0 –50 mA OK O I Continuousoutputcurrent V =0toV –25 25 mA O O CC ContinuouscurrentthroughV orGND –50 50 mA CC T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputnegative-voltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) Thevalueislimitedto5.5-Vmaximum. 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostatic Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) discharge Machinemodel(A115-A) 200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions See (1)(2) MIN MAX UNIT V Supplyvoltage 2 5.5 V CC V Inputvoltage 0 5.5 V I V Outputvoltage 0 V V O CC V =2V –50 μA CC V =2.3Vto2.7V –2 CC I High-leveloutputcurrent OH V =3Vto3.6V –6 mA CC V =4.5Vto5.5V –12 CC V =2V 50 μA CC V =2.3Vto2.7V 2 CC I Low-leveloutputcurrent OL V =3Vto3.6V 6 mA CC V =4.5Vto5.5V 12 CC SN54LV132A –55 125 T Operatingfree-airtemperature °C A SN74LV132A –40 125 (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.SeetheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,SCBA004. (2) SN54LV132Aisinproductpreview 4 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A www.ti.com SCLS394J–APRIL1999–REVISEDFEBRUARY2015 7.4 Thermal Information overoperatingfree-airtemperaturerange(unlessotherwisenoted) D DB DGV NS PW THERMALMETRIC(1) UNIT 14PINS R Junction-to-ambientthermalresistance 90.6 107.1 129.0 90.7 122.6 θJA R Junction-to-case(top)thermalresistance 50.9 59.6 52.1 48.3 51.4 θJC(top) R Junction-to-boardthermalresistance 44.8 54.4 62.0 49.4 64.4 °C/W θJB ψ Junction-to-topcharacterizationparameter 14.7 20.5 6.5 14.6 6.7 JT ψ Junction-to-boardcharacterizationparameter 44.5 53.8 61.3 49.1 63.8 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 7.5 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) SN54LV132A(1) SN74LV132A PARAMETER TESTCONDITIONS V UNIT CC MIN TYP MAX MIN TYP MAX 2.5V 1 1.75 1 1.75 Positive-goinginput V 3.3V 1.31 2.31 1.31 2.31 V T+ thresholdvoltage 5V 1.95 3.5 1.95 3.5 2.5V 0.75 1.5 0.75 1.5 Negative-goinginput V 3.3V 0.99 2.07 0.99 2.07 V T– thresholdvoltage 5V 1.5 3.05 1.5 3.05 2.5V 0.25 1 0.25 1 Hysteresis ΔV 3.3V 0.33 1.32 0.33 1.32 V T (V −V ) T+ T− 5V 0.5 2 0.5 2 I =–50μA 2to5.5V V –0.1 V –0.1 OH CC CC I =–2mA 2.3V 2 2 OH V V OH I =–6mA 3V 2.48 2.48 OH I =–12mA 4.5V 3.8 3.8 OH I =50μA 2to5.5V 0.1 0.1 OL I =2mA 2.3V 0.4 0.4 OL V V OL I =6mA 3V 0.44 0.44 OL I =12mA 4.5V 0.55 0.55 OL I V =5.5VorGND 0to5.5V ±1 ±1 μA I I V =V orGND,I I I CC O 5.5V 20 20 μA CC =0 I V orV =0to5.5V 0V 5 5 μA off I O C V =V orGND 3.3V 1.9 1.9 pF i I CC (1) SN54LV132Aisinproductpreview Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 www.ti.com 7.6 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,V =2.5V±0.2V(unlessotherwisenoted)(seeFigure3) CC LOAD TA=25°C SN54LV132A(1) SN74LV132A PARAMETER FROM(INPUT) TO(OUTPUT) UNIT CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CL=15pF 7.9(2) 16.5(2) 1(2) 18.5(2) 1 18.5 tpd AorB Y ns CL=50pF 10.8 20.2 1 23 1 23 (1) SN54LV132Aisinproductpreview (2) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 7.7 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,V =3.3V±0.3V(unlessotherwisenoted)(seeFigure3) CC LOAD TA=25°C SN54LV132A(1) SN74LV132A PARAMETER FROM(INPUT) TO(OUTPUT) UNIT CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CL=15pF 5.6(2) 11.9(2) 1(2) 14(2) 1 14 tpd AorB Y ns CL=50pF 7.6 15.4 1 17.5 1 17.5 (1) SN54LV132Aisinproductpreview (2) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 7.8 Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,V =5V±0.5V(unlessotherwisenoted)(seeFigure3) CC FROM TO LOAD TA=25°C SN54LV132A(1) SN74LV132A PARAMETER UNIT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CL=15pF 3.9(2) 7.7(2) 1(2) 9(2) 1 9 tpd AorB Y ns CL=50pF 5.3 9.7 1 11 1 11 (1) SN54LV132Aisinproductpreview (2) OnproductscomplianttoMIL-PRF-38535,thisparameterisnotproductiontested. 7.9 Noise Characteristics for SN74LV132A V =3.3V,C =50pF,T =25°C(1) CC L A PARAMETER MIN TYP MAX UNIT VOL(P) Quietoutput,maximumdynamicVOL 0.21 0.8 VOL(V) Quietoutput,minimumdynamicVOL –0.09 –0.8 VOH(V) Quietoutput,minimumdynamicVOH 3.12 V VIH(D) High-leveldynamicinputvoltage 2.31 VIL(D) Low-leveldynamicinputvoltage 0.99 (1) Characteristicsareforsurface-mountpackagesonly. 7.10 Operating Characteristics T =25°C A PARAMETER TESTCONDITIONS VCC TYP UNIT 3.3V 7.5 Cpd Powerdissipationcapacitance CL=50pF,f=10MHz pF 5V 11.2 6 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A www.ti.com SCLS394J–APRIL1999–REVISEDFEBRUARY2015 7.11 Typical Characteristics 7 9 8 6 7 5 6 s) 4 s) 5 n n t (pd 3 t (pd 4 3 2 2 1 1 0 0 -100 -50 0 50 100 150 0 1 2 3 4 5 6 Temperature (°C) D001 VCC (V) D002 Figure1.SN74LV132At vsTemperature Figure2.SN74LV132At vsV pd pd CC Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 www.ti.com 8 Parameter Measurement Information VCC From Output Test From Output RL= 1 kΩ S1 Open TEST S1 UnderTest Point UnderTest GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see NoteA) (see NoteA) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATEAND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC tw 0 V th VCC tsu VCC Input 50% VCC 50% VCC Data Input 50% VCC 50% VCC 0 V 0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PULSEDURATION SETUPAND HOLD TIMES VCC VCC Output Input 50% VCC 50% VCC Control 50% VCC 50% VCC 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output ≈VCC In-Phase 50%VCC 50% VCC Waveform 1 50% VCC Output VOL S1 at VCC VOL+0.3VVOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Out-of-Phase 50% VCC 50% VCC Waveform 2 50% VCC VOH 0.3V Output VOL (seSe1 Nato GteN BD) ≈0 V VOLTAGEWAVEFORMS VOLTAGEWAVEFORMS PROPAGATIONDELAYTIMES ENABLEAND DISABLE TIMES INVERTINGAND NONINVERTING OUTPUTS LOW-AND HIGH-LEVELENABLING A. C includesprobeandjigcapacitance. L B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutput control.Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbythe outputcontrol. C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤1MHz,Z =50Ω,t ≤3ns,t O r f ≤3ns. D. Theoutputsaremeasuredoneatatime,withoneinputtransitionpermeasurement. E. t andt arethesameast . PLZ PHZ dis F. t andtPZHarethesameast . PZL en G. t andt arethesameast . PHL PLH pd H. Allparametersandwaveformsarenotapplicabletoalldevices. Figure3. LoadCircuitandVoltageWaveforms 8 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A www.ti.com SCLS394J–APRIL1999–REVISEDFEBRUARY2015 9 Detailed Description 9.1 Overview The SN74LV132A Is a quadruple 2-input positive NAND gate with low drive that produces slow rise and fall times. This reduces ringing on the output signal. Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free outputsignals. 9.2 Functional Block Diagram A Y B Figure4. LogicDiagram(PositiveLogic) 9.3 Feature Description • Wideoperatingvoltagerange,operatesfrom2to5.5V • Allowsdownvoltagetranslation,inputsacceptvoltagesto5.5V 9.4 Device Functional Modes Table1.FunctionTable INPUTS OUTPUT A B Y H H L L X H X L H Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information The SN74LV132A is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on theoutputs.Theinputscanacceptvoltagesto5.5VatanyvalidV makingitIdealfordowntranslation. CC 10.2 Typical Application 5-V Accessory 5-V Regulated 0.1 PF Figure5. TypicalApplicationSchematic 10.2.1 DesignRequirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. The Schmitt trigger inputsallowforslowornoisyinputswhileproducingcleanoutputs. 10.2.2 DetailedDesignProcedure 1. Recommendedinputconditions – Specifiedhighandlowlevels.See(V andV )inRecommendedOperatingConditions. IH IL – Inputsareovervoltagetolerantallowingthemtogoashighas5.5VatanyvalidV CC 2. Recommendoutputconditions – Loadcurrentsshouldnotexceed25mAperoutputand50mAtotalforthepart – OutputsshouldnotbepulledaboveV CC 10 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A www.ti.com SCLS394J–APRIL1999–REVISEDFEBRUARY2015 Typical Application (continued) 10.2.3 ApplicationCurve Figure6.SwitchingCharacteristicsComparison 11 Power Supply Recommendations The power supply can be any voltage between the min and max supply voltage rating located in Recommended OperatingConditions. Each V terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single CC supply, TI recommends 0.1 μF and if there are multiple V terminals then TI recommends .01 μF or .022 μF for CC each power terminal. It is okay to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal aspossibleforbestresults. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V whichever make more sense or is more CC convenient. It is generally okay to float outputs unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of theIOssotheyalsocannotfloatwhendisabled. 12.2 Layout Example V Input CC Unused Input Output Unused Input Output Input Figure7. LayoutRecommendation Copyright©1999–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN54LV132A SN74LV132A

SN54LV132A,SN74LV132A SCLS394J–APRIL1999–REVISEDFEBRUARY2015 www.ti.com 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY SN54LV132A Clickhere Clickhere Clickhere Clickhere Clickhere SN74LV132A Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 12 SubmitDocumentationFeedback Copyright©1999–2015,TexasInstrumentsIncorporated ProductFolderLinks:SN54LV132A SN74LV132A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74LV132AD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132ADBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132ADGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132ADR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132ANSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 74LV132A & no Sb/Br) SN74LV132APW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132APWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) SN74LV132APWT ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 LV132A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LV132ADGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV132ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV132ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LV132APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV132APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LV132ADGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LV132ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LV132ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LV132APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV132APWT TSSOP PW 14 250 367.0 367.0 35.0 PackMaterials-Page2

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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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