SN54HCT623, SN74HCT623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS016C – MARCH 1984 – REVISED MARCH 2003 (cid:0) (cid:0) Operating Voltage Range of 4.5 V to 5.5 V Inputs Are TTL-Voltage Compatible (cid:0) (cid:0) Low Power Consumption, 80-µA Max I Lock Bus-Latch Capability CC (cid:0) (cid:0) Typical tpd = 11 ns True Logic (cid:0) (cid:0) ±6-mA Output Drive at 5 V High-Current 3-State Outputs Can Drive Up (cid:0) Low Input Current of 1 µA Max To 15 LSTTL Loads SN54HCT623...J OR W PACKAGE SN54HCT623...FK PACKAGE SN74HCT623...DW OR N PACKAGE (TOP VIEW) (TOP VIEW) B A A CB 2 1 E CE OEAB 1 20 VCC A A OV O A1 2 19 OEBA 3 2 1 20 19 A2 3 18 B1 A3 4 18 B1 A3 4 17 B2 A4 5 17 B2 A4 5 16 B3 A5 6 16 B3 A5 6 15 B4 A6 7 15 B4 A6 7 14 B5 A7 8 14 B5 A7 8 13 B6 9 10 1112 13 A8 9 12 B7 8 D 8 7 6 GND 10 11 B8 A N B B B G description/ordering information These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. The ’HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and OEBA) inputs. The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA. Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states. The 8-bit codes appearing on the two sets of buses are identical. To ensure the high-impedance state during power up or power down, OEBA should be tied to V through a CC pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP – N Tube SN74HCT623N SN74HCT623N –4400°°CC ttoo 8855°°CC SOIC – DW Tube SN74HCT623DW HCT623 CDIP – J Tube SNJ54HCT623J SNJ54HCT623J –55°C to 125°C CFP – W Tube SNJ54HCT623W SNJ54HCT623W LCCC – FK Tube SNJ54HCT623FK SNJ54HCT623FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  2003, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54HCT623, SN74HCT623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS016C – MARCH 1984 – REVISED MARCH 2003 FUNCTION TABLE INPUTS OOPPEERRAATTIIOONN OEBA OEAB L L B data to A bus H H A data to B bus H L Isolation B data to A bus, L H A data to B bus logic diagram (positive logic) 19 OEBA 1 OEAB 2 18 A1 B1 To Seven Other Transceivers absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA CC Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54HCT623, SN74HCT623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS016C – MARCH 1984 – REVISED MARCH 2003 recommended operating conditions (see Note 3) SN54HCT623 SN74HCT623 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V tt Input transition (rise and fall) time 500 500 ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT623 SN74HCT623 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = –20 µA 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 44.55 VV VV IOH = –6 mA 3.98 4.3 3.7 3.84 IOL = 20 µA 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 44.55 VV VV IOL = 6 mA 0.17 0.26 0.4 0.33 OEAB or II OEBA VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA IOZ A or B VO = VCC or GND 5.5 V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA One input at 0.5 V or 2.4 V, ∆ICC† Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA OEAB or 4.5 V Ci OEBA to 5.5 V 3 10 10 10 pF †This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FROM TO TA = 25°C SN54HCT623 SN74HCT623 PPAARRAAMMEETTEERR VVCCCC UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX 4.5 V 15 22 33 28 ttpdd AA oorr BB BB oorr AA nnss 5.5 V 13 20 30 25 4.5 V 30 42 63 53 tten OOEEBBAA AA nnss 5.5 V 23 38 57 48 4.5 V 18 30 45 38 ttddiis OOEEBBAA AA nnss 5.5 V 16 28 42 35 4.5 V 30 42 63 53 tten OOEEAABB BB nnss 5.5 V 23 38 57 48 4.5 V 18 30 45 38 ttddiis OOEEAABB BB nnss 5.5 V 16 28 42 35 4.5 V 9 12 18 15 tttt AA oorr BB nnss 5.5 V 8 11 16 14 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54HCT623, SN74HCT623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS016C – MARCH 1984 – REVISED MARCH 2003 switching characteristics over recommended operating free-air temperature range, C = 150 pF L (unless otherwise noted) (see Figure 1) FROM TO TA = 25°C SN54HCT623 SN74HCT623 PPAARRAAMMEETTEERR VVCCCC UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX 4.5 V 18 38 58 47 ttpdd AA oorr BB BB oorr AA nnss 5.5 V 11 34 52 42 4.5 V 36 59 89 74 OOEEBBAA AA 5.5 V 30 53 80 67 tten nnss 4.5 V 36 59 89 74 OOEEAABB BB 5.5 V 30 53 80 67 4.5 V 17 42 63 53 tttt AA oorr BB nnss 5.5 V 14 38 57 48 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per transceiver No load 40 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54HCT623, SN74HCT623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS016C – MARCH 1984 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER RL CL S1 S2 S1 tPZH 50 pF Open Closed Test ten 1 kΩ or From Output Point RL tPZL 150 pF Closed Open Under Test tPHZ Open Closed CL tdis 1 kΩ 50 pF (see Note A) S2 tPLZ Closed Open 50 pF tpd or tt –– or Open Open 150 pF LOAD CIRCUIT 3 V Input 2.7 V 2.7 V 1.3 V 1.3 V 0.3 V 0.3 V 0 V tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3 V Output 3 V Input 1.3 V 1.3 V Control 1.3 V 1.3 V (Low-Level 0 V Enabling) 0 V tPLH tPHL tPZL tPLZ In-Phase 90% 90% VOH Output ≈VCC Output 1.3 V 1.3 V Waveform 1 1.3 V 10% 10% tr tfVOL (See Note B) 10% VOL tPHL tPLH tPZH tPHZ Out-of- 90% 90% VOH Output VOH Phase 1.3 V 1.3 V 90% Output 10% 10% Waveform 2 1.3 V VOL (See Note B) ≈0 V tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74HCT623N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -40 to 85 SN74HCT623N (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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