(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1) (cid:13)(cid:2)(cid:20) (cid:14)(cid:21)(cid:2)(cid:18) (cid:20)(cid:19)(cid:21)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:21)(cid:7)(cid:5) (cid:24)(cid:25)(cid:1)(cid:7)(cid:13)(cid:7)(cid:18) (cid:12)(cid:16)(cid:7)(cid:26)(cid:16)(cid:7)(cid:1) SCLS174E − MARCH 1984 − REVISED AUGUST 2003 (cid:1) Operating Voltage Range of 4.5 V to 5.5 V SN54HCT240...J OR W PACKAGE (cid:1) SN74HCT240...DW, N, NS, OR PW PACKAGE High-Current Outputs Drive Up To 15 (TOP VIEW) LSTTL Loads (cid:1) Low Power Consumption, 80-µA Max ICC 1OE 1 20 VCC (cid:1) Typical tpd = 12 ns 1A1 2 19 2OE (cid:1) ±6-mA Output Drive at 5 V 2Y4 3 18 1Y1 (cid:1) Low Input Current of 1 µA Max 1A2 4 17 2A4 2Y3 5 16 1Y2 (cid:1) Inputs Are TTL-Voltage Compatible 1A3 6 15 2A3 (cid:1) 3-State Outputs Drive Bus Lines or Buffer 2Y2 7 14 1Y3 Memory Address Registers 1A4 8 13 2A2 2Y1 9 12 1Y4 description/ordering information GND 10 11 2A1 These octal buffers and line drivers are designed specifically to improve both the performance and SN54HCT240...FK PACKAGE (TOP VIEW) density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and 4 1 E CE Y A O CO transmitters. The ’HCT240 devices are organized 2 1 1V 2 as two 4-bit buffers/drivers with separate 3 2 1 20 19 output-enable (OE) inputs. When OE is low, the 1A2 4 18 1Y1 device passes inverted data from the A inputs to 2Y3 5 17 2A4 the Y outputs. When OE is high, the outputs are 1A3 6 16 1Y2 in the high-impedance state. 2Y2 7 15 2A3 1A4 8 14 1Y3 9 10 11 12 13 1 D 14 2 Y N AY A 2 G 21 2 ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − N Tube of 20 SN74HCT240N SN74HCT240N Tube of 25 SN74HCT240DW SSOOIICC −− DDWW HHCCTT224400 Reel of 2000 SN74HCT240DWR −−4400°CC ttoo 8855°CC SOP − NS Reel of 2000 SN74HCT240NSR HCT240 Tube of 70 SN74HCT240PW TTSSSSOOPP −− PPWW Reel of 2000 SN74HCT240PWR HHTT224400 Reel of 250 SN74HCT240PWT CDIP − J Tube of 20 SNJ54HCT240J SNJ54HCT240J −−5555°CC ttoo 112255°CC CFP − W Tube of 85 SNJ54HCT240W SNJ54HCT240W LCCC − FK Tube of 55 SNJ54HCT240FK SNJ54HCT240FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:26)(cid:19)(cid:12)(cid:20)(cid:16)(cid:6)(cid:7)(cid:21)(cid:12)(cid:2) (cid:20)(cid:13)(cid:7)(cid:13) (cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"#(cid:27)(cid:30)(cid:28) (cid:27)$ %&(cid:31)(cid:31)’(cid:28)# "$ (cid:30)(cid:29) (&)*(cid:27)%"#(cid:27)(cid:30)(cid:28) +"#’, Copyright  2003, Texas Instruments Incorporated (cid:26)(cid:31)(cid:30)+&%#$ %(cid:30)(cid:28)(cid:29)(cid:30)(cid:31)! #(cid:30) $(’%(cid:27)(cid:29)(cid:27)%"#(cid:27)(cid:30)(cid:28)$ (’(cid:31) #-’ #’(cid:31)!$ (cid:30)(cid:29) (cid:7)’."$ (cid:21)(cid:28)$#(cid:31)&!’(cid:28)#$ (cid:12)(cid:28) ((cid:31)(cid:30)+&%#$ %(cid:30)!(*(cid:27)"(cid:28)# #(cid:30) 2(cid:21)(cid:14)(cid:25)(cid:26)(cid:19)(cid:17)(cid:25)(cid:24)3(cid:3)(cid:24)(cid:3)(cid:10) "** ("(cid:31)"!’#’(cid:31)$ "(cid:31)’ #’$#’+ $#"(cid:28)+"(cid:31)+ /"(cid:31)(cid:31)"(cid:28)#0, (cid:26)(cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ &(cid:28)*’$$ (cid:30)#-’(cid:31)/(cid:27)$’ (cid:28)(cid:30)#’+, (cid:12)(cid:28) "** (cid:30)#-’(cid:31) ((cid:31)(cid:30)+&%#$(cid:10) ((cid:31)(cid:30)+&%#(cid:27)(cid:30)(cid:28) #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, ((cid:31)(cid:30)%’$$(cid:27)(cid:28)1 +(cid:30)’$ (cid:28)(cid:30)# (cid:28)’%’$$"(cid:31)(cid:27)*0 (cid:27)(cid:28)%*&+’ #’$#(cid:27)(cid:28)1 (cid:30)(cid:29) "** ("(cid:31)"!’#’(cid:31)$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1) (cid:13)(cid:2)(cid:20) (cid:14)(cid:21)(cid:2)(cid:18) (cid:20)(cid:19)(cid:21)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:21)(cid:7)(cid:5) (cid:24)(cid:25)(cid:1)(cid:7)(cid:13)(cid:7)(cid:18) (cid:12)(cid:16)(cid:7)(cid:26)(cid:16)(cid:7)(cid:1) SCLS174E − MARCH 1984 − REVISED AUGUST 2003 FUNCTION TABLE (each buffer/driver) INPUTS OOUUTTPPUUTT OE A Y L H L L L H H X Z logic diagram (positive logic) 1 19 1OE 2OE 1A1 2 18 1Y1 2A1 11 9 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 1A4 8 12 1Y4 2A4 17 3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA CC Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1) (cid:13)(cid:2)(cid:20) (cid:14)(cid:21)(cid:2)(cid:18) (cid:20)(cid:19)(cid:21)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:21)(cid:7)(cid:5) (cid:24)(cid:25)(cid:1)(cid:7)(cid:13)(cid:7)(cid:18) (cid:12)(cid:16)(cid:7)(cid:26)(cid:16)(cid:7)(cid:1) SCLS174E − MARCH 1984 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HCT240 SN74HCT240 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V ∆t/∆v Input transition rise/fall time 500 500 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54HCT240 SN74HCT240 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = −20 µA 4.4 4.499 4.4 4.4 VVOOHH VVII == VVIIHH oorr VVIILL 44..55 VV VV IOH = −6 mA 3.98 4.3 3.7 3.84 IOL = 20 µA 0.001 0.1 0.1 0.1 VVOOLL VVII == VVIIHH oorr VVIILL 44..55 VV VV IOL = 6 mA 0.17 0.26 0.4 0.33 II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0, VI = VIH or VIL 5.5 V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA One input at 0.5 V or 2.4 V, ∆ICC† Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA 4.5 V Ci to 5.5 V 3 10 10 10 pF †This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, C = 50 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HCT240 SN74HCT240 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 4.5 V 13 25 37 32 ttppdd AA YY nnss 5.5 V 12 23 33 29 4.5 V 21 35 53 44 tteenn OOEE YY nnss 5.5 V 19 32 48 40 4.5 V 19 35 53 44 ttddiiss OOEE YY nnss 5.5 V 18 32 48 40 4.5 V 8 12 18 15 tttt YY nnss 5.5 V 7 11 16 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1) (cid:13)(cid:2)(cid:20) (cid:14)(cid:21)(cid:2)(cid:18) (cid:20)(cid:19)(cid:21)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:21)(cid:7)(cid:5) (cid:24)(cid:25)(cid:1)(cid:7)(cid:13)(cid:7)(cid:18) (cid:12)(cid:16)(cid:7)(cid:26)(cid:16)(cid:7)(cid:1) SCLS174E − MARCH 1984 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, C = 150 pF L (unless otherwise noted) (see Figure 1) FFRROOMM TTOO TA = 25°C SN54HCT240 SN74HCT240 PPAARRAAMMEETTEERR (INPUT) (OUTPUT) VVCCCC MIN TYP MAX MIN MAX MIN MAX UUNNIITT 4.5 V 20 42 63 53 ttppdd AA YY nnss 5.5 V 19 38 56 48 4.5 V 25 52 79 65 tteenn OOEE YY nnss 5.5 V 22 47 71 59 4.5 V 17 42 63 53 tttt YY nnss 5.5 V 14 38 57 48 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 40 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9)(cid:10) (cid:1)(cid:2)(cid:11)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:12)(cid:6)(cid:7)(cid:13)(cid:14) (cid:15)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1) (cid:13)(cid:2)(cid:20) (cid:14)(cid:21)(cid:2)(cid:18) (cid:20)(cid:19)(cid:21)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:21)(cid:7)(cid:5) (cid:24)(cid:25)(cid:1)(cid:7)(cid:13)(cid:7)(cid:18) (cid:12)(cid:16)(cid:7)(cid:26)(cid:16)(cid:7)(cid:1) SCLS174E − MARCH 1984 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER RL CL S1 S2 S1 tPZH 50 pF Open Closed Test ten 1 kΩ or From Output Point RL tPZL 150 pF Closed Open Under Test tPHZ Open Closed CL tdis 1 kΩ 50 pF (see Note A) S2 tPLZ Closed Open 50 pF tpd or tt −− or Open Open 150 pF LOAD CIRCUIT 3 V Input 2.7 V 2.7 V 1.3 V 1.3 V 0.3 V 0.3 V 0 V tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3 V Output 3 V Input 1.3 V 1.3 V Control 1.3 V 1.3 V (Low-Level 0 V Enabling) 0 V tPLH tPHL tPZL tPLZ In-Phase 90% 90% VOH Output ≈VCC Output 1.3 V 1.3 V Waveform 1 1.3 V 10% 10% tr tfVOL (See Note B) 10% VOL tPHL tPLH tPZH tPHZ OPuhta-osfe- 90% 1.3 V 1.3 V 90% VOH Output 90% VOH Output 10% 10% Waveform 2 1.3 V VOL (See Note B) ≈0 V tf tr VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 85505012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85505012A SNJ54HCT 240FK 8550501RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8550501RA SNJ54HCT240J JM38510/65753BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65753BRA M38510/65753BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65753BRA SN54HCT240J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HCT240J SN74HCT240DW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT240 & no Sb/Br) SN74HCT240DWG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT240 & no Sb/Br) SN74HCT240DWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT240 & no Sb/Br) SN74HCT240DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT240 & no Sb/Br) SN74HCT240N ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74HCT240N (RoHS) SN74HCT240NSR ACTIVE SO NS 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HCT240 & no Sb/Br) SN74HCT240PW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT240 & no Sb/Br) SN74HCT240PWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT240 & no Sb/Br) SN74HCT240PWT ACTIVE TSSOP PW 20 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HT240 & no Sb/Br) SNJ54HCT240FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85505012A SNJ54HCT 240FK SNJ54HCT240J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8550501RA SNJ54HCT240J Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HCT240, SN74HCT240 : •Catalog: SN74HCT240 •Military: SN54HCT240 Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74HCT240DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74HCT240NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74HCT240PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74HCT240DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74HCT240NSR SO NS 20 2000 367.0 367.0 45.0 SN74HCT240PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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