(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:13)(cid:14)(cid:6)(cid:15)(cid:7) (cid:6)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:20)(cid:21)(cid:19)(cid:15)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:15)(cid:7)(cid:24) (cid:25)(cid:14)(cid:1)(cid:7)(cid:5)(cid:7)(cid:18) (cid:26)(cid:16)(cid:7)(cid:27)(cid:16)(cid:7)(cid:1) SCBS159E − JANUARY 1991 − REVISED APRIL 2005 (cid:1) State-of-the-Art EPIC-ΙΙB BiCMOS Design SN54ABT827...JT PACKAGE Significantly Reduces Power Dissipation SN74ABT827...DB, DW, NT, OR PW PACKAGE (cid:1) (TOP VIEW) Flow-Through Architecture Optimizes PCB Layout OE1 1 24 VCC (cid:1) Latch-Up Performance Exceeds 500 mA Per A1 2 23 Y1 JEDEC Standard JESD-17 A2 3 22 Y2 (cid:1) Typical V (Output Ground Bounce) < 1 V A3 4 21 Y3 OLP at V = 5 V, T = 25°C A4 5 20 Y4 CC A (cid:1) A5 6 19 Y5 High-Impedance State During Power Up A6 7 18 Y6 and Power Down (cid:1) A7 8 17 Y7 High-Drive Outputs (−32-mA I , 64-mA I ) OH OL A8 9 16 Y8 (cid:1) Package Options Include Plastic A9 10 15 Y9 Small-Outline (DW), Shrink Small-Outline A10 11 14 Y10 (DB), and Thin Shrink Small-Outline (PW) GND 12 13 OE2 Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs SN54ABT827...FK PACKAGE description (TOP VIEW) 1 C These 10-bit buffers or bus drivers provide a 2 1E C C12 A AO N V YY high-performance bus interface for wide data paths or buses carrying parity. 4 3 2 1 28 27 26 A3 5 25 Y3 The 3-state control gate is a 2-input AND gate with A4 6 24 Y4 active-low inputs so that, if either output-enable A5 7 23 Y5 (OE1 or OE2) input is high, all ten outputs are in NC 8 22 NC the high-impedance state. The ’ABT827 provides A6 9 21 Y6 true data at the outputs. A7 10 20 Y7 A8 11 19 Y8 When V is between 0 and 2.1 V, the device CC 12 1314 15 16 1718 is in the high-impedance state during power up 9 0 DC 2 0 9 or power down. However, to ensure A 1 NN E 1 Y the high-impedance state above 2.1 V, OE should A G O Y be tied to VCC through a pullup resistor; the NC − No internal connection minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT827 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ABT827 is characterized for operation from −40°C to 85°C. FUNCTION TABLE INPUTS OOUUTTPPUUTT OE1 OE2 A Y L L L L L L H H H X X Z X H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments. (cid:27)(cid:19)(cid:26)(cid:21)(cid:16)(cid:28)(cid:7)(cid:15)(cid:26)(cid:2) (cid:21)(cid:5)(cid:7)(cid:5) (cid:29)(cid:30)(cid:31)!"#$%(cid:29)!(cid:30) (cid:29)& ’("")(cid:30)% $& !(cid:31) *(+,(cid:29)’$%(cid:29)!(cid:30) -$%). Copyright  2005, Texas Instruments Incorporated (cid:27)"!-(’%& ’!(cid:30)(cid:31)!"# %! &*)’(cid:29)(cid:31)(cid:29)’$%(cid:29)!(cid:30)& *)" %/) %)"#& !(cid:31) (cid:7))0$& (cid:15)(cid:30)&%"(#)(cid:30)%& &%$(cid:30)-$"- 1$""$(cid:30)%2. (cid:27)"!-(’%(cid:29)!(cid:30) *"!’)&&(cid:29)(cid:30)3 -!)& (cid:30)!% (cid:30))’)&&$"(cid:29),2 (cid:29)(cid:30)’,(-) %)&%(cid:29)(cid:30)3 !(cid:31) $,, *$"$#)%)"&. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:13)(cid:14)(cid:6)(cid:15)(cid:7) (cid:6)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:20)(cid:21)(cid:19)(cid:15)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:15)(cid:7)(cid:24) (cid:25)(cid:14)(cid:1)(cid:7)(cid:5)(cid:7)(cid:18) (cid:26)(cid:16)(cid:7)(cid:27)(cid:16)(cid:7)(cid:1) SCBS159E − JANUARY 1991 − REVISED APRIL 2005 logic symbol† logic diagram (positive logic) 1 1 & OE1 13 OE1 13 EN OE2 OE2 2 23 A1 Y1 2 23 A1 1 Y1 3 22 A2 Y2 4 21 To Nine Other Channels A3 Y3 5 20 A4 Y4 6 19 A5 Y5 7 18 A6 Y6 8 17 A7 Y7 9 16 A8 Y8 10 15 A9 Y9 11 14 A10 Y10 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and PW packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W JA DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:13)(cid:14)(cid:6)(cid:15)(cid:7) (cid:6)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:20)(cid:21)(cid:19)(cid:15)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:15)(cid:7)(cid:24) (cid:25)(cid:14)(cid:1)(cid:7)(cid:5)(cid:7)(cid:18) (cid:26)(cid:16)(cid:7)(cid:27)(cid:16)(cid:7)(cid:1) SCBS159E − JANUARY 1991 − REVISED APRIL 2005 recommended operating conditions (see Note 3) SN54ABT827 SN74ABT827 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current −24 −32 mA IOL Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 5 5 ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:13)(cid:14)(cid:6)(cid:15)(cid:7) (cid:6)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:20)(cid:21)(cid:19)(cid:15)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:15)(cid:7)(cid:24) (cid:25)(cid:14)(cid:1)(cid:7)(cid:5)(cid:7)(cid:18) (cid:26)(cid:16)(cid:7)(cid:27)(cid:16)(cid:7)(cid:1) SCBS159E − JANUARY 1991 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT827 SN74ABT827 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 −1.2 V VCC = 4.5 V, IOH = −3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = −3 mA 3 3 3 VVOOHH VV IOH = −24 mA 2 2 VVCCCC == 44..55 VV IOH = −32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44..55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV II VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA IOZPU‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±10 ±50 µA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±10 ±50 µA IOZH VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10§ 10 10§ µA IOZL VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V −10§ −10 −10§ µA Ioff VCC = 0, VI or VO ≤ 5.5 V ±100 ±100 µA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA IO¶ VCC = 5.5 V, VO = 2.5 V −50 −140 −225§ −50 −225§ −50 −225§ mA Outputs high 80 250 250 250 µA IICCCC VVVVCCII ==CC VV ==CC 55CC..55 oo VVrr ,,GG IIOONN DD== 00,, Outputs low 35 40§ 40§ 40§ mA Outputs disabled 80 250 250 250 µA Outputs enabled 1.5 1.5 1.5 mA VVCCCC == 55..55 VV,, ∆∆IICCCC## OOnnee iinnppuutt aatt 33..44 VV,, Outputs disabled 50 50 50 µA OOtthheerr iinnppuuttss aatt VVCC oorr GGNNDD Control inputs 1.5 1.5 1.5 mA Ci VI = 2.5 V or 0.5 V 4 pF Co VO = 2.5 V or 0.5 V 8 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡This parameter is characterized, but not production tested. §This data sheet limit may vary among suppliers. ¶Not more than one output should be tested at a time, and the duration of the test should not exceed one second. #This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L VCC = 5 V, PPAARRAAMMEETTEERR FROM TO TA = 25°C SN54ABT827 SN74ABT827 UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX MIN MAX tPLH 1.1 2.6 4.4 1.1 4.9 1.1 4.8 AA YY nnss tPHL 1.1 2.3 4.1 1.1 4.8 1.1 4.7 tPZH 1§ 3.2 5.1 1 6 1§ 5.9 OOEE YY nnss tPZL 1§ 3.3 5.9 1 7.1 1§ 6.9 tPHZ 2 4.9 6.3 2 7 2 6.8 OOEE YY nnss tPLZ 1.3§ 4.2 6.6 1.3 7.9 1.3§ 6.9 §This data sheet limit may vary among suppliers. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10) (cid:12)(cid:13)(cid:14)(cid:6)(cid:15)(cid:7) (cid:6)(cid:16)(cid:17)(cid:17)(cid:18)(cid:19)(cid:1)(cid:20)(cid:21)(cid:19)(cid:15)(cid:22)(cid:18)(cid:19)(cid:1) (cid:23)(cid:15)(cid:7)(cid:24) (cid:25)(cid:14)(cid:1)(cid:7)(cid:5)(cid:7)(cid:18) (cid:26)(cid:16)(cid:7)(cid:27)(cid:16)(cid:7)(cid:1) SCBS159E − JANUARY 1991 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 Ω S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL VOH Output tPLZ 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oart m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHZ tPHL tPLH tPZH Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH − 0.3 V VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9450901QKA ACTIVE CFP W 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9450901QK A SNJ54ABT827W 5962-9450901QLA ACTIVE CDIP JT 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9450901QL A SNJ54ABT827JT SN74ABT827DBR ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB827 & no Sb/Br) SN74ABT827DW ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT827 & no Sb/Br) SN74ABT827DWR ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT827 & no Sb/Br) SN74ABT827PW ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB827 & no Sb/Br) SN74ABT827PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB827 & no Sb/Br) SN74ABT827PWR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB827 & no Sb/Br) SNJ54ABT827JT ACTIVE CDIP JT 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9450901QL A SNJ54ABT827JT SNJ54ABT827W ACTIVE CFP W 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9450901QK A SNJ54ABT827W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT827, SN74ABT827 : •Catalog: SN74ABT827 •Military: SN54ABT827 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT827DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74ABT827DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74ABT827PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT827DBR SSOP DB 24 2000 367.0 367.0 38.0 SN74ABT827DWR SOIC DW 24 2000 350.0 350.0 43.0 SN74ABT827PWR TSSOP PW 24 2000 367.0 367.0 38.0 PackMaterials-Page2

MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN A PINS ** 24 28 DIM 24 13 1.280 1.460 A MAX (32,51) (37,08) B A MIN 1.240 1.440 (31,50) (36,58) 0.300 0.291 B MAX (7,62) (7,39) 1 12 0.070 (1,78) 0.245 0.285 B MIN 0.030 (0,76) (6,22) (7,24) 0.320 (8,13) 0.100 (2,54) MAX 0.015 (0,38) MIN 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.100 (2,54) 0.008 (0,20) 4040110/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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