(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 (cid:1) (cid:1) Typical V (Output Ground Bounce) Latch-Up Performance Exceeds 500 mA Per OLP <1 V at V = 5 V, T = 25°C JEDEC Standard JESD-17 CC A (cid:1) (cid:1) High-Drive Outputs (−32-mA I , 64-mA I ) ESD Protection Exceeds JESD 22 OH OL (cid:1) − 2000-V Human-Body Model (A114-A) I Supports Partial-Power-Down Mode off − 200-V Machine Model (A115-A) Operation SN54ABT646A...JT OR W PACKAGE SN54ABT646A...FK PACKAGE SN74ABT646A...DB, DGV, DW, NS, NT, OR PW PACKAGE (TOP VIEW) (TOP VIEW) B A A B CLKAB 1 24 VCC DIR SAB CLK NC VCCCLK SBA SAB 2 23 CLKBA DIR 3 22 SBA 4 3 2 1 28 27 26 A1 5 25 OE A1 4 21 OE A2 6 24 B1 A2 5 20 B1 A3 7 23 B2 A3 6 19 B2 NC 8 22 NC A4 7 18 B3 A4 9 21 B3 A5 8 17 B4 A5 10 20 B4 A6 9 16 B5 A6 11 19 B5 A7 10 15 B6 1213 14 15 16 1718 A8 11 14 B7 7 8 DC 8 7 6 GND 12 13 B8 A A NN B B B G NC − No internal connection description/ordering information These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’ABT646A devices. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP − NT Tube SN74ABT646ANT SN74ABT646ANT Tube SN74ABT646ADW SSOOIICC −− DDWW AABBTT664466AA Tape and reel SN74ABT646ADWR SOP − NS Tape and reel SN74ABT646ANSR ABT646A −−4400°°CC ttoo 8855°°CC SSOP − DB Tape and reel SN74ABT646ADBR AB646A Tube SN74ABT646APW TTSSSSOOPP −− PPWW AABB664466AA Tape and reel SN74ABT646APWR TVSOP − DGV Tape and reel SN74ABT646ADGVR AB646A CDIP − JT Tube SNJ54ABT646AJT SNJ54ABT646AJT −−5555°CC ttoo 112255°CC CFP − W Tube SNJ54ABT646AW SNJ54ABT646AW LCCC − FK Tube SNJ54ABT646AFK SNJ54ABT646AFK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:25)(cid:15)(cid:11)(cid:19)(cid:14)(cid:12)(cid:7)(cid:17)(cid:11)(cid:2) (cid:19)(cid:5)(cid:7)(cid:5) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2004, Texas Instruments Incorporated (cid:25)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:7)&-!# (cid:17)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# (cid:11)(cid:27) ’(cid:30)(cid:29)*%$"# $(cid:29)(cid:31)’)(cid:26)!(cid:27)" "(cid:29) 1(cid:17)(cid:13)(cid:24)(cid:25)(cid:15)2(cid:24)(cid:23)3(cid:3)(cid:23)(cid:3)(cid:9) !)) ’!(cid:30)!(cid:31)&"&(cid:30)# !(cid:30)& "&#"&* #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:25)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& %(cid:27))&## (cid:29)",&(cid:30).(cid:26)#& (cid:27)(cid:29)"&*+ (cid:11)(cid:27) !)) (cid:29)",&(cid:30) ’(cid:30)(cid:29)*%$"#(cid:9) ’(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 description/ordering information(continued) Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. These devices are fully specified for partial-power-down applications using I . The I circuitry disables the off off outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 A B A B S S S S U U U U B B B B 21 3 1 23 2 22 21 3 1 23 2 22 OE DIR CLKAB CLKBA SAB SBA OE DIR CLKAB CLKBA SAB SBA L L X X X L L H X X L X REAL-TIME TRANSFER REAL-TIME TRANSFER BUS B TO BUS A BUS A TO BUS B A B A B S S S S U U U U B B B B 21 3 1 23 2 22 21 3 1 23 2 22 OE DIR CLKAB CLKBA SAB SBA OE DIR CLKAB CLKBA SAB SBA X X ↑ X X X L L X H or L X H X X X ↑ X X L H H or L X H X H X ↑ ↑ X X STORAGE FROM TRANSFER STORED DATA A, B, OR A AND B TO A AND/OR B Pin numbers shown are for the DB, DGV, DW, JT, NS, NT, PW, and W packages. Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 FUNCTION TABLE INPUTS DATA I/Os OOPPEERRAATTIIOONN OORR FFUUNNCCTTIIOONN OE DIR CLKAB CLKBA SAB SBA A1−A8 B1−B8 X X ↑ X X X Input Unspecified† Store A, B unspecified† X X X ↑ X X Unspecified† Input Store B, A unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus †The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled, i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. logic diagram (positive logic) 21 OE 3 DIR 23 CLKBA 22 SBA 1 CLKAB 2 SAB One of Eight Channels 1D C1 4 A1 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, NS, NT, PW, and W packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT646A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT646A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W JA (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W (see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-3. recommended operating conditions (see Note 4) SN54ABT646A SN74ABT646A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current −24 −32 mA IOL Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 5 5 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT646A SN74ABT646A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 −1.2 V VCC = 4.5 V, IOH = −3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = −3 mA 3 3 3 VVOOHH VV IOH = −24 mA 2 2 VVCCCC == 44..55 VV IOH = −32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44..55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV Control inputs ±1 ±1 ±1 IIII A or B ports VVCCCC == 55..55 VV,, VVII == VVCCCC oorr GGNNDD ±100 ±100 ±100 µAA IOZH‡ VCC = 5.5 V, VO = 2.7 V 10§ 10§ 10§ µA IOZL‡ VCC = 5.5 V, VO = 0.5 V −10§ −10§ −10§ µA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 µA IO¶ VCC = 5.5 V, VO = 2.5 V −50 −100 −180 −50 −180 −50 −180 mA Outputs high 250 250 250 µA VVCCCC == 55..55 VV,, IICCCC IIOO == 00,, Outputs low 30 30 30 mA VVI == VVCC oorr GGNNDD Outputs disabled 250 250 250 µA ∆ICC# VOCthCe r= i n5p.5u tVs ,a Ot nVeC iCn pourt GaNt 3D.4 V, 1.5 1.5 1.5 mA Ci Control inputs VI = 2.5 V or 0.5 V 7 pF Cio A or B ports VO = 2.5 V or 0.5 V 12 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡The parameters IOZH and IOZL include the input leakage current. §This data-sheet limit may vary among suppliers. ¶Not more than one output should be tested at a time, and the duration of the test should not exceed one second. #This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) SN54ABT646A VCC = 5 V, TA = 25°C MMIINN MMAAXX UNIT MIN MAX fclock Clock frequency 125 125 MHz tw Pulse duration, CLK high or low 4 4 ns tsu Setup time, A or B before CLKAB↑ or CLKBA↑ 3 3.5 ns th Hold time, A or B after CLKAB↑ or CLKBA↑ 1.5 1.5 ns 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) SN74ABT646A VCC = 5 V, TA = 25°C MMIINN MMAAXX UNIT MIN MAX fclock Clock frequency 125 125 MHz tw Pulse duration, CLK high or low 4 4 ns tsu Setup time, A or B before CLKAB↑ or CLKBA↑ 3 3 ns th Hold time, A or B after CLKAB↑ or CLKBA↑ 0 0 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 2) L SN54ABT646A FROM TO VCC = 5 V, PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C MMIINN MMAAXX UNIT MIN TYP MAX fmax 125 125 MHz tPLH 2.2 4 5.1 2.2 6.7 CCLLKKBBAA oorr CCLLKKAABB AA oorr BB nnss tPHL 1.7 4 5.1 1.2 6.7 tPLH 1.5 3 4.3 1.5 5 AA oorr BB BB oorr AA nnss tPHL 1.5 3.3 4.6 1.5 5.6 tPLH 1.5 4 5.7 1.5 7.8 SSAABB oorr SSBBAA†† BB oorr AA nnss tPHL 1.5 3.6 4.9 1.5 6.2 tPZH 1.5 4.3 5.3 1.5 7 OOEE AA oorr BB nnss tPZL 3 5.8 8 3 10.5 tPHZ 1.5 3.5 5.8 1 7.3 OOEE AA oorr BB nnss tPLZ 1.5 3 4 1.5 5.7 tPZH 1.5 4.5 5.7 1.5 7.3 DDIIRR AA oorr BB nnss tPZL 2.5 6.5 9 2.5 11 tPHZ 1.5 3.8 6.5 1 9 DDIIRR AA oorr BB nnss tPLZ 1.5 3.8 4.7 1.2 6.7 †These parameters are measured with the internal output state of the storage register opposite that of the bus input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 2) L SN74ABT646A FROM TO VCC = 5 V, PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C MMIINN MMAAXX UNIT MIN TYP MAX fmax 125 125 MHz tPLH 2.2 4 5.1 2.2 5.6 CCLLKKBBAA oorr CCLLKKAABB AA oorr BB nnss tPHL 1.7 4 5.1 1.7 5.6 tPLH 1.5 3 4.3 1.5 4.8 AA oorr BB BB oorr AA nnss tPHL 1.5 3.3 4.6 1.5 5.4 tPLH 1.5 4 5.1 1.5 6.5 SSAABB oorr SSBBAA†† BB oorr AA nnss tPHL 1.5 3.6 4.9 1.5 5.9 tPZH 1.5 4.3 5.3 1.5 6.3 OOEE AA oorr BB nnss tPZL 3 5.8 7.4 3 8.8 tPHZ 1.5 3.5 4.5 1.5 5 OOEE AA oorr BB nnss tPLZ 1.5 3 4 1.5 4.5 tPZH 1.5 4.5 5.7 1.5 6.7 DDIIRR AA oorr BB nnss tPZL 2.5 6.5 9 2.5 9.5 tPHZ 1.5 3.8 5 1.5 5.7 DDIIRR AA oorr BB nnss tPLZ 1.5 3.8 4.7 1.5 6 †These parameters are measured with the internal output state of the storage register opposite that of the bus input. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5)(cid:9) (cid:1)(cid:2)(cid:10)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:8)(cid:5) (cid:11)(cid:12)(cid:7)(cid:5)(cid:13) (cid:6)(cid:14)(cid:1) (cid:7)(cid:15)(cid:5)(cid:2)(cid:1)(cid:12)(cid:16)(cid:17)(cid:18)(cid:16)(cid:15)(cid:1) (cid:5)(cid:2)(cid:19) (cid:15)(cid:16)(cid:20)(cid:17)(cid:1)(cid:7)(cid:16)(cid:15)(cid:1) (cid:21)(cid:17)(cid:7)(cid:22) (cid:23)(cid:24)(cid:1)(cid:7)(cid:5)(cid:7)(cid:16) (cid:11)(cid:14)(cid:7)(cid:25)(cid:14)(cid:7)(cid:1) SCBS069H − JULY 1991 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 Ω S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 Ω tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ VOH Output 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oart m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHL tPLH tPZH tPHZ Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH − 0.3 V VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9457702Q3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9457702Q3A SNJ54ABT 646AFK 5962-9457702QLA ACTIVE CDIP JT 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9457702QL A SNJ54ABT646AJT SN74ABT646ADBR ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB646A & no Sb/Br) SN74ABT646ADW ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT646A & no Sb/Br) SN74ABT646ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT646A & no Sb/Br) SN74ABT646ADWR ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT646A & no Sb/Br) SN74ABT646ANSR ACTIVE SO NS 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT646A & no Sb/Br) SN74ABT646APW ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB646A & no Sb/Br) SNJ54ABT646AFK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9457702Q3A SNJ54ABT 646AFK SNJ54ABT646AJT ACTIVE CDIP JT 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9457702QL A SNJ54ABT646AJT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT646A, SN74ABT646A : •Catalog: SN74ABT646A •Military: SN54ABT646A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT646ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74ABT646ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74ABT646ANSR SO NS 24 2000 330.0 24.4 8.3 15.4 2.6 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT646ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74ABT646ADWR SOIC DW 24 2000 350.0 350.0 43.0 SN74ABT646ANSR SO NS 24 2000 367.0 367.0 45.0 PackMaterials-Page2

None

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN A PINS ** 24 28 DIM 24 13 1.280 1.460 A MAX (32,51) (37,08) B A MIN 1.240 1.440 (31,50) (36,58) 0.300 0.291 B MAX (7,62) (7,39) 1 12 0.070 (1,78) 0.245 0.285 B MIN 0.030 (0,76) (6,22) (7,24) 0.320 (8,13) 0.100 (2,54) MAX 0.015 (0,38) MIN 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.100 (2,54) 0.008 (0,20) 4040110/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated