End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers DESCRIPTION FEATURES Si9122A is a half-bridge controller IC ideally suited to fixed • 28 V to 75 V input voltage range telecom applications where high efficiency is required at low (cid:129) Compatible with ETSI 300 132-2 output voltages (e.g. < 3.3 V). Designed to operate within the (cid:129) Integrated ± 1 A half-bridge primary drivers RoHS fixed telecom voltage range of 33 V to 75 V and withstand (cid:129) Secondary synchronous rectifier control COMPLIANT 100V, 100 ms transients, the IC is capable of controlling and signals with programmable deadtime delay driving both the low and high-side switching devices of a half bridge circuit and also controlling the switching devices on (cid:129) Voltage mode control the secondary side of the bridge. Due to the very low on- (cid:129) Voltage feedforward compensation resistance of the secondary MOSFETs, a significant (cid:129) High voltage pre-regulator operates during start-up increase in conversion efficiency can be achieved as (cid:129) Current sensing on low-side primary device compared with conventional Schottky diodes. Control of the (cid:129) Frequency foldback eliminates constant current tail secondary devices is by means of a pulse transformer and a (cid:129) Advanced maximum current control during start-up and pair of inverters. Such a system has efficiencies well in shorted load excess of 90 % even for low output voltages. On-chip control of the dead time delays between the primary and secondary (cid:129) Low input voltage detection synchronous signals keep efficiencies high and prevent (cid:129) Programmable soft-start function accidental destruction of the power transformer. An external (cid:129) Over temperature protection resistor sets the switching frequency from 200 kHz to 625kHz. APPLICATIONS Si9122A has advanced current monitoring and control (cid:129) Network cards circuitry which allow the user to set the maximum current in (cid:129) Power supply modules the primary circuit. Such a feature acts as protection against output shorting and also provides constant current into large capacitive loads during start-up or when paralleling power supplies. Current sensing is by means of a sense resistor on the low-side primary device. FUNCTIONAL BLOCK DIAGRAM 28 V to 75 V N P C BST VI MO VC Synchronous C Rectifiers _G DH E R LX 1 V to 12 V Typ. + Si9122A DL VOUT – CS2 VIN_DET CS1 CL_CONT SRH Error SRL VCC Amplifier+ S FER CSO BM DN DGN EP - VREF S V R B G P Opto Isolator Figure 1. Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 1

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TECHNICAL DESCRIPTION Si9122A is a voltage mode controller for the half-bridge A break-before-make function is included to prevent shoot topology. With 100 V depletion mode MOSFET capability, through current or transformer shorting. Adjustable Break- the Si9122A is capable of powering directly from the high Before-Make time is incorporated into the IC and is voltage bus to V through an external PNP pass transistor, programmable by an external resistor value. CC or may be powered through an external regulator directly through the V pin. With PWM control, Si9122A provides Si9122A is packaged in lead (Pb)-free TSSOP-20 and CC peak efficiency throughout the entire line and load range. In MLP65-20 packages. To satisfy stringent ambient order to simplify the design of efficient secondary temperature requirements, Si9122A is rated to handle the synchronous rectification circuitry, Si9122A provides industrial temperature range of - 40 °C to 85 °C. When a intelligent gate drive signals to control the secondary situation arises which results in a rapid increase in primary MOSFETs. With independent gate drive signals from the (or secondary current) such as output shorted or start-up controller, transformer design is no longer limited by the gate with a large output capacitor, control of the PWM generator to source rating of the secondary-side MOSFETs. Si9122A is handed over to the current loop. Monitoring of the load provides constant V voltage, independent of line voltage current is by means of an external current sense resistor in GS to minimize the gate charge loss as well as conduction loss. the source of the primary low-side switch. SI9122 BLOCK DIAGRAM VI N VC C RO SC High-Side 9.1 V Primary BST REG_COMP Pre-Regulator + VU VLO Driver - Int DH VR EF 8.8 V LX VI VNRD EETF -+ VU V VF F OSC LDoriwve-Sr ide VC C DL Ramp + VS D 132 kΩ - PGND 550 mV 60 kΩ EP Error A mplifier +- -+ CDornivtreorl VC C SRH and V REF PWM Timing 2 Comparator 20 µA SYNC IS S Driver High SS OTP 8 V VC C CS2 + Duty Cycle SRL Peak DET CS1 - Control Over Current Protection Si9122 SDYrivNeCr Low GND CL _CONT BBM Figure 2. www.vishay.com Document Number: 73492 2 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V Parameter Limit Unit VIN (Continuous) 80 VIN (100 ms) 100 VCC 14.5 Continuous 95 V BST 100 ms 113.2 V VLX 100 VBST - VLX 15 V , R - 0.3 to V + 0.3 REF OSC CC Logic Inputs - 0.3 to VCC + 0.3 Analog Inputs - 0.3 to VCC + 0.3 HV Pre-Regulator Input Current (Continuous) 5 mA Storage Temperature - 65 to 150 °C Operating Junction Temperature 150 TSSOP-20b 850 Power Dissipationa mW MLP65-20c 2500 TSSOP-20 75 Thermal Impedance (JA) MLP65-20 38 °C/W Notes: a. Device Mounted on JEDEC compliant 1S2P test board. b. Derate - 14 mW/°C above 25 °C. c. Derate - 26 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE All voltages referenced to GND = 0 V Parameter Limit Unit VIN 28 to 75 V VCC Operating 10.5 to 13.2 CVCC 4.7 µF fOSC 200 to 625 kHz ROSC 22.6 to 72 k RBBM 22 to 50 CREF 0.1 µF CBOOST 0.1 Analog Inputs 0 V to VCC - 2 V V Digital Inputs 0 V to VCC Reference Voltage Output Current 0 to 2.5 mA Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 3

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix SPECIFICATIONSa Test Conditions Limits Unless Otherwise Specified - 40 to 85 °C f = 500 kHz, V = 75 V NOM IN Parameter Symbol VINDET = 7.5 V; 10.5 V  VCC  13.2 V Min.b Typ.c Max.b Unit Reference (3.3 V) Output Voltage VREF VCC = 12 V, 25 °C Load = 0 mA 3.2 3.3 3.4 V Short Circuit Current ISREF VREF = 0 V - 50 mA Load Regulation dVr/dir IREF = 0 to - 2.5 mA - 30 - 75 mV Power Supply Rejection PSRR at 100 Hz 60 dB Oscillator Accuracy (1 % ROSC) ROSC = 30 k, fNOM = 500 kHz - 20 20 % Max Frequencyh FMAX ROSC = 22.6 k 500 625 750 kHz Foldback Frequencyd FFOBK fNOM = 500 kHz, VCS2 - VCS1 > 150 mV 100 Error Amplifier Input Bias Current IBIAS VEP = 0 V - 40 - 15 µA Gain AV - 2.2 V/V Bandwidth BW 5 MHz Power Supply Rejection PSRR at 100 Hz 60 dB Slew Rate SR 0.5 V/µs Current Sense Amplifier Input Voltage CM Range VCM VCS1 - GND, VCS2 - GND ± 150 mV Input Amplifier Gain AVOL 17.5 dB Input Amplifier Bandwidth BW 5 MHz Input Amplifier Offset Voltage VOS ± 5 mV dVCS = 0 120 µA CL_CONT Current ICL_CONT dVCS = 100 mV 0 dVCS = 170 mV > 2 mA I = I - I = 0 Lower Current Limit Threshold VTLCL PD PU CL_CONT 100 See Figure 6 mV Upper Current Limit Threshold VTHCL IPD > 2 mA 150 Hysteresis IPU < 500 µA - 50 CL_CONT Clamp Level CL_CONT(min) IPU = 500 µA 0.6 1.5 V PWM Operation DMAX VEP = 0 V 90 92 95 f = 500 kHz OSC Duty Cyclee VEP = 1.75 V < 15 % D MIN VCS2 - VCS1 > 150 mV 3 Pre-Regulator Input Voltage + VIN IIN = 10 µA 28 75 V Input Leakage Current ILKG VIN = 75 V, VCC > VREG 10 µA IREG1 VIN = 75 V, VINDET < VSD 86 200 Regulator Bias Current IREG2 VIN = 75 V, VINDET > VREF 8 14 mA ISOURCE - 29 - 19 - 9 Regulator_Comp VCC = 12 V µA ISINK 50 82 110 Pre-Regulator Drive Capacility ISTART VCC < VREG 20 mA www.vishay.com Document Number: 73492 4 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix SPECIFICATIONSa Test Conditions Limits Unless Otherwise Specified - 40 to 85 °C f = 500 kHz, V = 75 V NOM IN Parameter Symbol VINDET = 7.5 V; 10.5 V  VCC  13.2 V Min.b Typ.c Max.b Unit Pre-Regulator 7.4 9.1 10.4 VCC Pre-Regulator Turn Off VREG1 VINDET > VREF TA = 25 °C 8.5 9.1 9.7 Threshold Voltage VREG2 VINDET = 0 V 9.2 V 7.15 8.8 9.8 Undervoltage Lockout VUVLO VCC Rising TA = 25 °C 8.1 8.8 9.3 VUVLO Hysteresisg VUVLOHYS 0.5 Soft-Start Soft-Start Current Output ISS Start-Up Condition 12 20 28 µA Soft-Start Completion Voltage VSS_COMP Normal Operation 7.35 8.05 8.85 V Shutdown VINDET Shutdown VSD VINDET Rising 350 550 720 mV VSD Hysteresis VINDET 200 V Input Threshold Voltages INDET VINDET - VIN Under Voltage VUV VINDET Rising 3.13 3.3 3.46 V VUV Hysteresis VINDET 0.23 0.3 0.35 Over Temperature Protection Activating Temperature TJ Increasing 160 °C De-Activating Temperature TJ Decreasing 130 Converter Supply Current (V ) CC Shutdown ICC1 Shutdown, VINDET = 0 V 50 350 µA Switching Disabled ICC2 VINDET < VREF 4 8 12 Switching w/o Load ICC3 VINDET > VREF, fNOM = 500 kHz 5 10 15 mA V = 12 V, C = C = 3 nF Switching with CLOAD ICC4 CCC = CDH = 0D.3L nF 21 SRH SRL Output MOSFET DH Driver (High-Side) Output High Voltage VOH Sourcing 10 mA VBST - 0.3 V Output Low Voltage VOL Sinking 10 mA VLX + 0.3 Boost Current IBST VLX = 75 V, VBST = VLX + VCC 1.3 1.9 2.7 mA LX Current ILX VLX = 75 V, VBST = VLX + VCC - 1.3 - 0.7 - 0.4 Peak Output Source ISOURCE - 1.0 - 0.75 VCC = 10.5 V A Peak Output Sink ISINK 0.75 1.0 Rise Time tr 35 CDH = 3 nF ns Fall Time tf 35 Output MOSFET DL Driver (Low-Side) Output High Voltage VOH Sourcing 10 mA VCC - 0.3 V Output Low Voltage VOL Sinking 10 mA 0.3 Peak Output Source ISOURCE - 1.0 - 0.75 VCC = 10.5 V A Peak Output Sink ISINK 0.75 1.0 Rise Time tr 35 CDL = 3 nF ns Fall Time tf 35 Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 5

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix SPECIFICATIONSa Test Conditions Limits Unless Otherwise Specified - 40 to 85 °C f = 500 kHz, V = 75 V NOM IN Parameter Symbol VINDET = 7.5 V; 10.5 V  VCC  13.2 V Min.b Typ.c Max.b Unit Synchronous Rectifier (SRH, SRL) Drivers Output High Voltage VOH Sourcing 10 mA VCC - 0.4 V Output Low Voltage VOL Sinking 10 mA 0.4 tBBM1 55 T = 25 °C, R = 33 k, See Figure 3 A BBM tBBM2 40 Break-Before-Make Timef ns tBBM3 35 T = 25 °C, R = 33 k, L = 75 V A BBM X tBBM4 55 Peak Output Source ISOURCE - 100 VCC = 10.5 V mA Peak Output Sink ISINK 100 Rise Time tr 35 CSRH = CSRL = 0.3 nF ns Fall Time tf 35 Voltage Mode td1DH Input to High-Side Switch Off < 200 Error Amplifier ns td2DL Input to Low-Side Switch Off < 200 Current Mode td3DH Input to High-Side Switch Off < 200 Current Amplifier ns td4DL Input to Low-Side Switch Off < 200 Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. F when V at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature. MIN CL_CONT e. Measured on SRL or SRH outputs. f. See figure 3 for Break-Before-Make time definition. g. V tracks V by a diode drop. UVLO REG1 h. Guaranteed by design and characterization, not tested in production. www.vishay.com Document Number: 73492 6 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TIMING DIAGRAM FOR MOS DRIVERS VC C PWM PWM PWM PWM GND VC C DL DL GND VC C SRL SRL GND VB ST DH DH VM ID DH DH GND VC C SRH SRH GND Time DH tB BM1 tB BM2 tB BM3 tB BM4 BST = LX + VC C 50 % V LX LX DH , LX DH , LX VM ID SRH VC C 50 % DH , LX GND tB BM3 tB BM4 DL SRL SRL VC C GND Return to: Specification Table Rectification Timing Sequence tB BM1 tB BM2 Primary MOSFET Drivers Secondary MOSFET Drivers Figure 3. Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 7

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix PIN CONFIGURATION Si9122ADQ (TSSOP-20) VIN 1 20 BST Si9122ADLP (MLP65-20) REG_COMP 2 19 DH VCC 3 18 LX 1 20 VREF 4 17 DL VIN 2 19 BST GND 5 16 PGND REG_COMP 3 18 DH ROSC 6 15 SRH VCC 4 17 LX EP 7 14 SRL VREF 5 16 DL VINDET 8 13 SS GND 6 15 PGND 7 14 CS1 9 12 BBM ROSC SRH 8 13 CS2 10 11 CL_CONT EP 9 12 SRL VINDET 10 11 SS CS1 BBM Top View CS2 CL_CONT Top View ORDERING INFORMATION Part Number Temperature Range Package Si9122ADQ-T1-E3 TSSOP-20 - 40 °C to 85 °C Si9122ADLP-T1-E3 MLP65-20 Eval Board Temperature Range Board Type Contact Factory - 10 °C to 70 °C Surface Mount and Thru-Hole PIN DESCRIPTION Pin Number Name Function 1 VIN Input supply voltage for the start-up circuit 2 REG_COMP Control signal for an external pass transistor 3 VCC Supply voltage for internal circuitry 4 VREF 3.3 V reference 5 GND Ground 6 ROSC External resistor connection to oscillator 7 EP Voltage control input V under voltage detect and shutdown function input. Shuts down or disables switching when V 8 VINDET IN INDET falls below preset threshold voltages and provides the feed forward voltage. 9 CS1 Current limit amplifier negative input 10 CS2 Current limit amplifier positive input 11 CL_CONT Current limit compensation 12 BBM Programmable break-before-make time connection to an external resistor to set time delay 13 SS Soft-start control - external capacitor connection 14 SRL Signal transformer drive, sequenced with the primary side 15 SRH Signal transformer drive, sequenced with the primary side 16 PGND Power ground. 17 DL Low-side gate drive signal - primary 18 LX High-side source and transformer connection node 19 DH High-side gate drive signal - primary 20 BST Bootstrap voltage to drive the high-side N-Channel MOSFET switch www.vishay.com Document Number: 73492 8 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix VCC VIN Pre-Regulator 12 V + Bandgap - VR EF Reference VREG 9.1 V 3.3 V 9.1 V VU VLO + + - - VU V VI NDET VR EF 8.8 V HPigrihm-Sairdye CL _CONT Driver + VS D BST - Voltage Frequency 160 C Temp High Vo ltage Feedforward Foldback 550 mV Protection Interface DH RO SC OSC VS D VU V VU VLO LX Oscillator Clock OTP Clock Logic VC C 132 kΩ Low-Side Driver 60 kΩ DL EP - – + + Logic VR EF /2 PGND PWM Generator Current CS2 Control + Gain Loop Timer VC C Synchronous CS1 - Control Driver (High) 100 mV Blanking SRH VC C Synchronous CL _CONT Driver GND VC C BBM (Low) SRL 20 µA Si9122A 8 V Soft-Start SS SS Enable Figure 4. Detailed Si9122A Block Diagram DETAILED OPERATION Start-Up When V rises above 0 V, the internal pre-regulator capacitor, bootstrap capacitor and the soft-start capacitor. INEXT begins to charge up the V capacitor. Current into the The value of the V capacitor should therefore be chosen CC CC external V capacitor is limited to typically 40 mA by the to be capable of maintaining switch mode operation until the CC internal DMOS device. When V exceeds the UVLO required V current can be supplied from the external circuit CC CC voltage of 8.8 V a soft-start cycle of the switch mode supply (e.g via a power transformer winding and zener regulator). is initiated. The V supply continues to be charged by the Feedback from the output of the switch mode supply charges CC pre-regulator until V equals V . During this period, V above V and fully disconnects the pre-regulator, CC REG CC REG between V and V , excessive load current will result isolating V from V . V is then maintained above V UVLO REG CC IN CC REG in V falling below V and stopping switch mode for the duration of switch mode operation. In the event of an CC UVLO operation. This situation is avoided by the hysteresis over voltage condition on V , an internal voltage clamp CC between V and V and correct sizing of the V turns on at 14.5 V to shunt excessive current to GND. REG UVLO CC Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 9

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix Care needs to be taken if there is a delay prior to the external Half-Bridge and Synchronous Rectification Timing circuit feeding back to the V supply. To prevent excessive Sequence CC power dissipation within the IC it is advisable to use an The PWM signal generated within the Si9122A controls the external PNP device. A pin has been incorporated on the IC, low and high-side bridge drivers on alternative cycles. A (REG_COMP) to provide compensation when employing the period of inactivity always results after initiation of the soft- external device. In this case the V pin is connected to the IN start cycle until the soft-start voltage reaches approximately base of the PNP device and controls the current, while the 1.2 V and PWM controlled switching begins. The first bridge REG_COMP pin determines the frequency compensation of driver to switch is always the low-side (D ), as this allows the circuit. The value of the REG_COMP capacitor cannot be L charging of the high-side boost capacitor. too big, otherwise it will slow down the response of the pre-regulator in the case that fault situations occur and The timing and coordination of the drives to the primary and pre-regulator needs to be turned on again. To understand secondary stages is very important and shown in figure 3. It the operation please refer to Figure 5. is essential to avoid the situation where both of the secondary MOSFETs are on when either the high or the low- The soft-start circuit is designed for the dc-dc converter to side switch are active. In this situation the transformer would start-up in an orderly manner and reduce component stress effectively be presented with a short across the output. To on the IC. This feature is programmable by selecting an avoid this, a dedicated break-before-make circuit is included external C . An internal 20 µA current source charges C SS SS which will generate non overlapping waveforms for the from 0 V to the final clamped voltage of 8 V. In the event of primary and the secondary drive signals. This is achieved by UVLO or shutdown, V will be held low (< 1 V) disabling SS a programmable timer which delays the switching on of the driver switching. To prevent oscillations, a longer soft-start primary driver relative to the switching off of the related time may be needed for highly capacitive loads and/or high secondary and subsequently delays the switching on of the peak output current applications. secondary relative to the switching off of the related primary. Reference Typical variations of BBM times with respect to R and BBM The reference voltage of Si9122A is set at 3.3 V. The other operating parameters are shown on page 13 and 14. reference voltage should be de-coupled externally with Primary High- and Low-Side MOSFET Drivers 0.1 µF capacitor. The V voltage is 0 V in shutdown mode REF and has 50 mA source capability. The drive voltage for the low-side MOSFET switch is provided directly from V . The high-side MOSFET however Voltage Mode PWM Operation CC requires the gate voltage to be enhanced above V . This is IN Under normal load conditions, the IC operates in voltage achieved by bootstrapping the V voltage onto the L CC X mode and generates a fixed frequency pulse width voltage (the high-side MOSFET source). In order to provide modulated signal to the drivers. Duty cycle is controlled over the bootstrapping an external diode and capacitor are a wide range to maintain output voltage under line and load required as shown on the application schematic. The variation. Voltage feed forward is also included to take capacitor will charge up after the low-side driver has turned account of variations in supply voltage V . on. The switch gate drive signals D and D are shown in IN H L figure 3. In the half-bridge topology requiring isolation between output and input, the reference voltage and error amplifier must be Secondary MOSFET Drivers supplied externally, usually on the secondary side. The error The secondary side MOSFETs are driven from the Si9122A information is thus passed to the power controller through an via a center tapped pulse transformer and inverter drivers. opto-coupling device. This information is inverted, hence 0 V The waveforms from SRH and SRL are shown in figure 3. Of represents the maximum duty cycle, whilst 2 V represents importance is the relative voltage between SRH and SRL, minimum duty cycle. The error information enters the IC via i.e. that which is presented across the primary of the pulse pin EP, and is passed to the PWM generator via an inverting transformer. When both potentials of SRL and SRH are amplifier. The relationship between duty cycle and V is EP equal then by the action of the inverting drivers both shown in the typical characteristic Graph, duty cycle vs. secondary MOSFETs are turned on. V 25 °C , page 11. Voltage feedforward is implemented by EP taking the attenuated V signal at V and directly Oscillator IN INDET modulating the duty cycle. The oscillator is designed to operate at a nominal frequency At start-up, i.e., once V is greater than V , switching is of 500 kHz. The 500 kHz operating frequency allows the CC UVLO initiated under soft-start control which increases primary converter to minimize the inductor and capacitor size, switch on-times linearly from D to D over the soft-start improving the power density of the converter. The oscillator MIN MAX period. Start-up from a V power down is also initiated and therefore the switching frequency is programmable by INDET under soft-start control. attaching a resistor to the ROSC pin. Under overload conditions the oscillator frequency is reduced by the current overload protection to enable a constant current to be maintained into a low impedance circuit. www.vishay.com Document Number: 73492 10 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix Current Limit V Voltage Monitor - V IN INDET Current mode control providing constant current operation is The chip provides a means of sensing the voltage of V , and IN achieved by monitoring the differential voltage V between withholding operation of the output drivers until a minimum CS the CS1 and CS2 pins, which are connected to a current voltage of V (3.3 V, 300 mV hysteresis), is achieved. This REF sense resistor on the primary low-side MOSFET. In the is achieved by choosing an appropriate resistive tap between absence of an overcurrent condition, V is less than lower the ground and V , and comparing this voltage with the CS IN current limit threshold V (typical 100 mV); C is reference voltage. When the applied voltage is greater than TLCL L_CONT pulled up linearly via the 120 µA current source (I ) and V , the output drivers are activated as normal. V also PU REF INDET both DL and DH switch at half the oscillator set frequency. provides the input to the voltage feed forward function. When a moderate overcurrent condition occurs (V < V TLCL CS However, if the divided voltage applied to the V pin is < V ), the C capacitor will be discharged at a rate INDET THCL L_CONT greater than V - 0.3 V, the high-side driver, D , will stop that is proportional to V - 100 mV by the I current CC H CS PD switching until the voltage drops below V - 0.3 V. Thus, the source. Both driver outputs are in frequency fold-back mode CC resistive tap on the V divider must be set to accommodate and the switching frequency becomes roughly 20 % of IN the normal V operating voltage to avoid this condition. normal switching frequency. When a severe overcurrent CC Alternatively, a zener clamp diode from V to GND may condition occurs (V < V ), the NMOS discharges INDET THCL CS also be used. C capacitor immediately at 2 mA rate and the L_CONT C voltage will be clamped to 1.2 V disabling both DL Shutdown Mode L_CONT and DH outputs. If V is forced below the lower V threshold, the device INDET SD Before V reaches severe overcurrent condition, a lowering will enter SHUTDOWN mode. This powers down all CS of the C voltage results in PWM control of the output unnecessary functions of the controller, ensures that the L_CONT drive being taken over by the current limit control loop primary switches are off, and results in a low level current through CL_CONT. Current control initially reduces the demand from the VIN or VCC supplies. switching duty cycle toward the minimum the chip can reach (DMIN). If this duty cycle reduction still cannot lower the load VINEXT current, then the switching frequency will start to fold back to REXT minimum 1/5 of the nominal frequency. This prevents the VIN on-time of the primary drivers from being reduced to below 100 ns and avoids current tails. If V > V , the switching CS THCL will then stop. 12 V PNP Ext (Si9122A) Auxillary With constant current mode control and frequency foldback HVDMOS VCC protection of the MOSFET switches is increased. The VCC converter reverts to voltage mode operation immediately REG_COMP when the primary current falls below the limit level, and CVCC C capacitor is charged up and clamped to 6.5 V. The CEXT 0.5 µF L_CONT 2 nF 14.5 V soft-start function does not apply during current limit period, VREF as this would constitute hiccup mode operation. GND Figure 5. High-Voltage Pre-Regulator Circuit VC C AV OSC IP U 120 µA (nom) + GM Peak Detect - VO FFSET CL _CLAMP CL _CONT CS1 - AV CS2 + AV 150 mV RE XT Blank + GM IP D CE XT - 0 to 240 µA (nom) AV 100 mV Figure 6 . Current Limit Circuit Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 11

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TYPICAL CHARACTERISTICS 600 3.300 3.295 500 3.290 )zH )V k(CS 400 (FER 3.285 O V F 3.280 300 3.275 200 3.270 20 30 40 50 60 70 80 - 50 - 25 0 25 50 75 100 ROSC (kΩ) Temperature (°C) fOSC vs. ROSC at VCC = 12 V VREF vs. Temperature, VCC = 12 V 10.0 100 90 3.6 V = VINDET 9.5 80 )%( e 70 4.8 V lc V)(G 9.0 VINDET > VREF yC ytu 5600 7.2 V E D R TC = - 11 mV/C V 8.5 40 VCC = 12 V 30 8.0 20 10 7.5 0 - 50 - 25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 Temperature ( C) VEP (V) VREG vs. Temperature, VIN = 48 V SRL, SRH Duty Cycle vs. VEP 25 8.20 VC C = 13 V 8.15 23 TC = + 1.25 mV/C 8.10 ) A µI ( 1 S S 21 VC C = 12 V )V(VSS 8.05 VINDET > VREF 19 8.00 VC C = 10 V 17 7.95 15 7.90 - 50 - 25 0 25 50 75 100 125 - 50 - 25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) ISS vs. Temperature VSS vs. Temperature, VCC = 12 V www.vishay.com Document Number: 73492 12 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TYPICAL CHARACTERISTICS 11 13 10 12 9 11 )Am )A (2 8 m( 10 G 3 E C R C I I 7 9 6 8 5 7 - 50 - 25 0 25 50 75 100 - 50 - 25 0 25 50 75 100 Temperature (°C) Temperature (°C) IREG2 vs. Temperature ICC3 vs. Temperature 250 250 200 VCC = 12 V 200 VCC = 12 V )Am 150 )A 150 ( m E ( C K R N UOS 100 IIS 100 I 50 50 0 0 0 200 400 600 800 0 200 400 600 800 VOH (mV) VOL (mV) DH, DL ISOURCE vs. VOH DH, DL ISINK vs. VOL 35 35 30 30 VCC = 12 V VCC = 12 V 25 25 A)m 20 )A 20 ( m E ( C K R 15 N 15 UO IIS S I 10 10 5 5 0 0 0 200 400 600 800 0 200 400 600 800 VOH (mV) VOL (mV) SRL, SRH ISOURCE vs. VOH SRL, SRH ISINK vs. VOL Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 13

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TYPICAL CHARACTERISTICS 100 65 tBBM4 90 VCC = 12 V tBBM1 VCC = 12 V tBBM1 55 80 tBBM4 tBBM2 70 45 )s )s n(M 60 n(M tBBM3 BB tBBM3 BB t 50 tBBM2 t 35 40 25 30 20 15 25 30 35 40 45 25 30 35 40 45 RBBM (kΩ) RBBM (kΩ) tBBM vs. RBBM, VEP = 0 V tBBM vs. RBBM, VEP = 1.65 V 60 80 tBBM1,VCC = 1tB3B VM1,VCC = 12 V 55 VRE B PB M= =1 .3635 kVΩ tB BM1, VC C = 10 V 70 tBBM1,VCC = 10 V 50 ()sn,1MBB2 5600 VREBBPM = = 0 3 V3 kΩ t ) s n ( , M B B 2 1 45 tB BM1, VC C = 12 V tB BM1, VC C = 13 V t 40 tBBM2,VCC = 10 V tBBM2,VCC = 10 V tBBM2,VCC = 12 V tB BM2, VC C = 12 V 40 35 tB BM2, VC C = 13 V tBBM2,VCC = 13 V 30 30 - 50 - 25 0 25 50 75 100 125 - 50 - 25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) t vs. Temperature, V = 1.65 V t vs. Temperature, V = 0 V BBM1, 2 EP BBM1, 2 EP 70 80 65 RVEBPB M= =0 3V3 kΩ tBBM4,VCC = 10 V RVEBPB M= =1 .3635 kVΩ tBBM4,VCC = 13 V 70 60 t)sn(,3MBB14 455505 tBBM4t,BVBCMC3 ,=V 1C3C V=tB 1B3M 4V,VCC = 12 V t)sn(,3MB1B4 456000 tBBM4,VCC = 12 V ttBBBBMM43,,VVCCCC == 1102 VV 40 tBBM3,VCC = 12 V tBBM3,VCC = 10 V 30 35 tBBM3,VCC = 10 V tBBM3,VCC = 13 V 30 20 - 50 - 25 0 25 50 75 100 125 - 50 - 25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) tBBM3, 4 vs. Temperature, VEP = 0 V tBBM3, 4 vs. Temperature, VEP = 1.65 V www.vishay.com Document Number: 73492 14 S-80038-Rev. D, 14-Jan-08

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TYPICAL CHARACTERISTICS 80 55 tBBM1,VCC = 13 V tBBM1,VCC = 13 V 70 tBBM1,VCC = 12 V tBBM1,VCC = 10 V 50 tBBM1,VCC = 12 V )sn(,1M2 60 VEP = 0 V )sn(,1M2 45 tBBM1,VCC = 10 V tBB 50 tBB VEP = 1.65 V tBBM2,VCC = 10 V tBBM2,VCC= 12 V 40 40 tBBM2,VCC = 13 V tBBM2,VCC = 12 V tBBM2,VCC = 13 V 30 35 tBBM2,VCC = 10 V 3.5 4.5 5.5 6.5 7.5 3.5 4.5 5.5 6.5 7.5 VINDET (V) VINDET (V) tBBM1, 2 vs. VCC vs. VINDET tBBM1, 2 vs. VCC vs. VINDET 80 65 tBBM4,VCC = 10 V VEP = 0 V 60 70 tBBM4,VCC = 12 V tBBM4,VCC = 12 V tBBM4,VCC = 10 V 55 tBBM4,VCC = 13 V )sn 60 )sn 50 ( ( 3B4,1M 50 tBBM4,VCC = 13 V 3B4,1M 45 VEP = 1.65 V B B t tBBM3,VCC = 12 V t tBBM3,VCC = 10 V 40 tBBM3,VCC = 12 V 40 tBBM3,VCC = 10 V tBBM3,VCC = 13 V 35 tBBM3,VCC = 13 V 30 30 3.5 4.5 5.5 6.5 7.5 3.5 4.5 5.5 6.5 7.5 VINDET (V) VINDET (V) tBBM3, 4 vs. VCC vs. VINDET tBBM3, 4 vs. VCC vs. VINDET 60 500 50 500 Frequency )% 45 Frequency 50 400 ( e 40 400 T D% lcy D% U C V .% elcyC ytuD ,TUOO 234000 IOUT 230000 Hk)z(neqeF ycur V( F ,)Hk( ytuD ,)CCSO3 1223350505 DSRL DDL 230000 yc)zHk(neuqerF I 100 S 10 100 10 VOUT VOR 5 VROSC 0 0 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1 2 3 4 5 RLOAD (Ω) VCLCONT (V) I vs. R (V = 72 V) V , F , and Duty Cycle vs. V OUT LOAD IN ROSC OSC CLCONT Document Number: 73492 www.vishay.com S-80038-Rev. D, 14-Jan-08 15

End of Life. Last Available Purchase Date is 31-Dec-2014 Si9122A Vishay Siliconix TYPICAL WAVEFORMS SRL 10 V/div SRL 10 V/div IOUT 5 A /div IOUT 5 A /div DL 10 V/div DL 5 V/div CS2 5 V/div CS2 50 mV/div 2 µs/div 2 µs/div Figure 7. Foldback Mode, RL = 0.02  Figure 8. Normal Mode, RL = 0.1  VIN 2 V/div VCL 2 V/div VEP 2 V/div IOUT 10 A/div VOUT 2 V/div VCC 2 V/div 2 ms/div 200 µs/div Figure 9. V Ramp-Up Figure 10. Overload Recovery CC DH 5 V/div LX 20 V/div SRL 5 V/div DL 5 V/div SRH 2 V/div SRH 5 V/div SRL 2 V/div 500 ns/div 500 ns/div Figure 11. Effective BBM - Measured On Secondary Figure 12. Drive Waveforms Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73492. www.vishay.com Document Number: 73492 16 S-80038-Rev. D, 14-Jan-08

Package Information Vishay Siliconix TSSOP: 20-LEAD (POWER IC ONLY) B D N 4X 0.20 C A−B D 0.20 H A−B D 2X N/2 TIPS E1 E 0 b bbb M C A−B D 9 0 1. E/2 A2 (cid:1) 0.05 C A C 1 2 3 H aaa C 1.00 DIA. 1.00 A e A1 SEPALTAINNEG (14(cid:1)) D SIDE VIEW MILLIMETERS Dim Min Nom Max 0.25 A — — 1.10 + + PALRINTIENG A1 0.05 — 0.15 A2 0.85 0.90 0.95 H aaa 0.076 L 6 b 0.19 − 0.30 (∝) b1 0.19 0.22 0.25 c bbb 0.10 1.00 B B c 0.09 − 0.20 (14(cid:1)) c1 0.09 0.127 0.16 DETAIL ‘A’ (SCALE: 30/1) D 6.50 BSC (VIEW ROTATED 90(cid:1) C.W.) E 6.40 BSC E1 4.30 4.40 4.50 CL e 0.65 BSC L 0.50 0.60 0.70 N 20 P 4.2 P1 3.0 ∝ 0(cid:1) — 8(cid:1) e/2 SEE ECN: S-40082—Rev. A, 02-Feb-04 DETAIL ‘A’ DWG: 5923 X X = A and B END VIEW LEAD SIDES TOP VIEW Document Number: 72818 www.vishay.com 28-Jan-04 1

Package Information Vishay Siliconix PowerPAK(cid:1) MLP65-18/20 (POWER IC ONLY) B- - D D/2 NXb Index Area -A- D/2(cid:1)E/2 bbb M A B C NXb E/2 x 2 E2/2 E C 2.00 E2 a a a Index Area NXL Detail D D/2(cid:1)E/2 aaa C 2x D2/2 D2 TOP VIEW BOTTOM VIEW A // ccc C A3 SEATING NX 0.08 C PLANE -C- SIDE VIEW A1 # IDENTIFIER TYPE A Chamber e/2 e Terminal Tip Terminal Tip e 5 5 EVEN TERMINAL SIDE ODD TERMINAL SIDE DETAIL B Document Number: 73182 www.vishay.com 15-Oct-04 1

Package Information Vishay Siliconix PowerPAK MLP65-18/20 (POWER IC ONLY) N = 18/20 PITCH: 0.5 mm, BODY SIZE: 6.00 x 5.00 MILLIMETERS* INCHES Dim Min Nom Max Min Nom Max Notes A 0.80 0.90 1.00 0.031 0.035 0.039 1, 2 A1 0.00 0.02 0.05 0.000 0.001 0.002 1, 2 A2 0.00 0.65 1.00 0.000 0.003 0.004 1, 2 A3 0.20 REF 0.008 REF aaa − 0.15 − − 0.006 − b 0.18 0.25 0.30 0.007 0.010 0.012 8 bbb − 0.10 − − 0.004 − C’ − 0.225 − − 0.009 − 4, 10 ccc − 0.10 − − 0.004 − D 6.00 BSC 0.236 BSC 1, 2 D2 4.00 4.15 4.25 0.157 1.63 0.167 1, 2 E 5.00 BSC 0.197 BSC 1, 2 E2 3.00 3.15 3.25 0.118 0.124 0.128 1, 2 e − 0.50 − − 0.020 − L 0.45 0.55 0.65 0.018 0.022 0.026 1, 2 N 18, 20 18, 20 1, 2 ND(18) 9 9 1, 2 NE(18) 0 0 1, 2 ND(20) 10 10 1, 2 NE(20) 0 0 1, 2 * Use millimeters as the primary measurement. ECN: S-41946—Rev. A, 18-Oct-04 DWG: 5939 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. All angels are in degrees. 3. N is the total number of terminals. 4. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95 SSP-022. Details of terminal #1 identifier are optional, but must be located within the zone indicated. A dot can be marked on the top side by pin 1 to indicate orientation. 5. ND and NE refer to the number of terminals on the D and E side respectively. 6. Depopulation is possible in a symmetrical fashion. 7. NJR refers to NON JEDEC REGISTERED. 8. Dimension “b” applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has optional radius on the other end of the terminal, the dimension “b” should not be measured in that radius area. 9. Coplanarity applies to the exposed heat slug as well as the terminal. 10. The 45(cid:1) chamfer dimension C’ is located by pin 1 on the bottom side of the package. www.vishay.com Document Number: 73182 2 15-Oct-04

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