Si8439DB www.vishay.com Vishay Siliconix P-Channel 8 V (D-S) MOSFET FEATURES PRODUCT SUMMARY • TrenchFET® power MOSFET: 1.2 V rated VDS (V) RDS(on) () MAX. ID (A) a, e Qg (TYP.) • Ultra-small 1.6 mm x 1.6 mm maximum outline 0.025 at V = -4.5 V -9.2 GS • Ultra-thin 0.6 mm maximum height 0.030 at V = -2.5 V -8.4 GS -8 0.037 at V = -1.8 V -7.6 33 • Material categorization:  GS for definitions of compliance please see 0.061 at V = -1.5 V -5.9 GS www.vishay.com/doc?99912 0.125 at V = -1.2 V -1 GS APPLICATIONS S MICRO FOOT® 1.6 x 1.6 • Low threshold load switch for D 2 portable devices D 3 9 3 - Low power consumption 4 G 8 x xx - Increased battery life 1.6 mm 1 1.6 m m S4 G1 • Ultra low voltage load switch Backside View Bump Side View D Marking Code: 8439 P-Channel MOSFET Ordering Information: Si8439DB-T1-E1 (lead (Pb)-free and halogen-free) ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V -8 DS V Gate-Source Voltage V ± 5 GS T = 25 °C -9.2 a A T = 70 °C -7.4 a A Continuous Drain Current (T = 150 °C) I J T = 25 °C D -5.9 b A T = 70 °C -4.7 b A A Pulsed Drain Current (t = 300 μs) I -25 DM T = 25 °C -2.3 a A Continuous Source-Drain Diode Current I T = 25 °C S -0.92 b A T = 25 °C 2.7 a A T = 70 °C 1.8 a A Maximum Power Dissipation P W T = 25 °C D 1.1 b A T = 70 °C 0.73 b A Operating Junction and Storage Temperature Range T , T -55 to +150 J stg VPR 260 °C Package Reflow Conditions c IR / convection 260 Notes a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s. b. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s. c. Refer to IPC / JEDEC® (J-STD-020), no manual or hand soldering. d. In this document, any reference to case represents the body of the MICRO FOOT device and foot is the bump. e. Based on TA = 25 °C. S15-1692-Rev. C, 20-Jul-15 1 Document Number: 63839 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si8439DB www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM UNIT Maximum Junction-to-Ambient a, b t = 5 s R 35 45 thJA °C/W Maximum Junction-to-Ambient c, d t = 5 s R 85 110 thJA Notes a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s. b. Maximum under steady state conditions is 85 °C/W. c. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s. d. Maximum under steady state conditions is 175 °C/W. SPECIFICATIONS (T = 25 °C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage V V = 0 V, I = -250 μA -8 - - V DS GS D VDS Temperature Coefficient VDS/TJ - -3 - I = -250 μA mV/°C D VGS(th) Temperature Coefficient VGS(th)/TJ - 2.5 - Gate-Source Threshold Voltage V V = V , I = -250 μA -0.4 - -0.8 V GS(th) DS GS D Gate-Source Leakage I V = 0 V, V = ± 5 V - - ± 100 nA GSS DS GS V = -8 V, V = 0 V - - -1 DS GS Zero Gate Voltage Drain Current I μA DSS V = -8 V, V = 0 V, T = 70 °C - - -10 DS GS J On-State Drain Current a ID(on) VDS  -5 V, VGS = -4.5 V -5 - - A V = -4.5 V, I = -1.5 A - 0.020 0.025 GS D V = -2.5 V, I = -1 A - 0.023 0.030 GS D Drain-Source On-State Resistance a RDS(on) VGS = -1.8 V, ID = -1 A - 0.030 0.037  V = -1.5 V, I = -1 A - 0.036 0.061 GS D V = -1.2 V, I = -0.5 A - 0.070 0.125 GS D Forward Transconductance a g V = -4 V, I = -1.5 A - 14 - S fs DS D Dynamic b Total Gate Charge Q - 33 50 g V = -4 V, V = -4.5 V, Gate-Source Charge Q DS GS - 3.5 - nC gs I = -1.5 A D Gate-Drain Charge Q - 7.2 - gd Gate Resistance Rg VGS = -0.1 V, f = 1 MHz - 27 -  Turn-On Delay Time t - 30 60 d(on) Rise Time tr VDD = -4 V, RL = 2.7  - 25 50 ns Turn-Off Delay Time td(off) ID  -1.5 A, VGEN = -4.5 V, Rg = 1  - 330 660 Fall Time t - 210 420 f Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I T = 25 °C - - -2.3 c S A A Pulse Diode Forward Current I - - -25 SM Body Diode Voltage V I = -1.5 A, V = 0 V - -0.7 -1.2 V SD S GS Body Diode Reverse Recovery Time t - 365 730 ns rr Body Diode Reverse Recovery Charge Q - 1.2 2.3 μC rr I = -1.5 A, dI/dt = 100 A/μs, T = 25 °C F J Reverse Recovery Fall Time t - 125 - a ns Reverse Recovery Rise Time t - 240 - b Notes a. Pulse test; pulse width  300 μs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. c. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s.  Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S15-1692-Rev. C, 20-Jul-15 2 Document Number: 63839 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si8439DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 20 10 V = 5 V thru 2 V GS 8 15 I - Drain Current (A) D 10 VGS = 1.5 V - Drain Current (A) D 46 TC = 25 °C 5 I T = 125 °C C 2 VGS = 1 V T = - 55 °C 0 0 C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.3 0.6 0.9 1.2 1.5 V - Drain-to-Source Voltage (V) V - Gate-to-Source Voltage (V) DS GS Output Characteristics Transfer Characteristics 0.15 3000 VGS= 1.2 V V = 1.5 V 2500 0.12 GS Ω) Ciss sistance ( 0.09 nce (pF) 2000 n-Re acita1500 R - ODS(on)00..0036 VGS = 1.8 V VGS = 2.5 V C - Cap1000 Crss Coss 500 VGS= 4 .5 V 0.00 0 0 4 8 12 16 20 0 2 4 6 8 I - Drain Current (A) V - Drain-to-Source Voltage (V) D DS On-Resistance vs. Drain Current Capacitance 6 1.3 I = 1.5 A D ge (V) 5 VDS = 4 V malized) 1.2 VGVSG S= = 4 .15. 8V ,V 2; .I5D V=; 1ID A = 1.5 A ate-to-Source Volta 234 VDS = 2 V VDS = 6.4 V On-Resistance (Nor 11..01 VGS = 1.5 V; ID = 1 A V - GGS 1 R - DS(on) 0.9 VG S = 1.2 V; ID = 0. 5 A 0 0.8 0 10 20 30 40 50 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature S15-1692-Rev. C, 20-Jul-15 3 Document Number: 63839 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si8439DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 0.10 I = 1.5 A D 0.08 Current (A) 10 TJ= 1 50 °C esistance (Ω) 0.06 urce TJ = 25 °C On-R 0.04 I - SoS 1 - DS(on) TJ = 125 °C R 0.02 T = 25 °C J 0.1 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4 5 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 0.8 80 0.7 60 V) 0.6 W) V (GS(th) 0.5 I = 250 μA Power ( 40 D 20 0.4 0.3 0 - 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10 100 600 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 100 Limited by R * DS(on) 10 1 ms A) nt ( urre 10 ms C 1 n 100 ms - DraiD 11D 0Cs s I 0.1 T = 25 °C A BVDSS Limited 0.01 0.1 1 10 100 V - Drain-to-Source Voltage (V) DS * V > minimum V at which R is specified GS GS DS(on) Safe Operating Area, Junction-to-Ambient S15-1692-Rev. C, 20-Jul-15 4 Document Number: 63839 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si8439DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 8 1.5 1.2 6 A) nt ( W) 0.9 e Curr 4 wer( n o ai P 0.6 Dr - D I 2 0.3 0 0.0 0 25 50 75 100 125 150 25 50 75 100 125 150 TA - Ambient Temperature (°C) TA- AmbientTemperature(°C) Current Derating a Power Derating Notes • When mounted on 1" x 1" FR4 with full copper. a. The power dissipation P is based on T = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper D J (max.) dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S15-1692-Rev. C, 20-Jul-15 5 Document Number: 63839 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Si8439DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 1 ent Duty Cycle = 0.5 e Transiedance 0.2 ctivmp Notes: ed Effeermal I 0.1 0.1 PDM zh maliT 0.05 t1 Nor 0.02 1. Duty Cyclet,2 D = tt12 2. Per Unit Base = RthJA = 85 °C/W 3. TJM- TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient (1" x 1" FR4 Board with Full Copper) 1 DutyCycle=0.5 nt e Transiance 0.2 ectiveImped 0.1 Notes: Effmal 0.1 PDM eder 0.05 alizTh t1 Norm 0.02 1.DutyCyclet,2D= tt12 2.PerUnitBase=RthJA=175 °C/W 3.TJM - TA=PDMZthJA(t) SinglePulse 4.SurfaceMounted 0.01 10-3 10-2 10-1 1 10 100 1000 SquareWavePulseDuration(s) Normalized Thermal Transient Impedance, Junction-to-Ambient (1" x 1" FR4 Board with Minimum Copper)                     Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63839. S15-1692-Rev. C, 20-Jul-15 6 Document Number: 63839 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix MICRO FOOT®: 4-Bumps (1.6 mm x 1.6 mm, 0.8 mm Pitch, 0.290 mm Bump Height) Mark on backside of die 4x Ø b1 4x 0.30 to .31 S (Note 3) Solder mask-0.4 XXXX D D XXX E e e e S G S Recommended land pattern S e S D b b1 2 A A Note 5 1 K A Notes 1.Bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 2.Backside surface is coated with a Ti/Ni/Ag layer. 3.Non-solder mask defined copper landing pad. 4.Laser marks on the silicon die back. 5.“b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. 6.• is the location of pin 1 MILLIMETERS INCHES DIM. MIN. NOM. MAX. MIN. NOM. MAX. A 0.550 0.575 0.600 0.0217 0.0226 0.0236 A1 0.260 0.275 0.290 0.0102 0.0108 0.0114 A2 0.290 0.300 0.310 0.0114 0.0118 0.0122 b 0.370 0.390 0.410 0.0146 0.0153 0.0161 b1 0.300 0.0118 e 0.800 0.0314 s 0.360 0.380 0.400 0.0141 0.0150 0.0157 D 1.520 1.560 1.600 0.0598 0.0614 0.0630 E 1.520 1.560 1.600 0.0598 0.0614 0.0630 K 0.155 0.185 0.215 0.0061 0.0073 0.0085 Note • Use millimeters as the primary measurement. ECN: T15-0175-Rev. A, 27-Apr-15 DWG: 6038 Revision: 27-Apr-15 1 Document Number: 69378 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

AN824 Vishay Siliconix PCB Design and Assembly Guidelines (cid:1) For MICRO FOOT Products Johnson Zhao INTRODUCTION Vishay Siliconix’s MICRO FOOT product family is based on a wafer-level chip-scale packaging (WL-CSP) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. MICRO FOOT products include power MOSFETs, analog switches, and power ICs. For battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. For example, the 6−bump MICRO FOOT Si8902EDB common drain power MOSFET, which measures just 1.6 mm x 2.4 mm, achieves the same performance as TSSOP−8 devices in a footprint that is 80% smaller and with a 50% lower height profile (Figure 1). A MICRO FOOT analog switch, the 6−bump DG3000DB, offers low charge injection and 1.4 W on−resistance in a footprint measuring just 1.08 mm x 1.58 mm (Figure 2). Vishay Siliconix MICRO FOOT products can be handled with FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and the same process techniques used for high-volume assembly Si8900EDB of packaged surface-mount devices. With proper attention to PCB and stencil design, the device will achieve reliable 3 2 1 performance without underfill. The advantage of the device’s 0.18 ~ 0.25 small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as A battery packs, PDAs, cellular phones, and notebook computers. 0.5 1.08 B This application note discusses the mechanical design and 0.285 reliability of MICRO FOOT, and then provides guidelines for board layout, the assembly process, and the PCB rework 0.5 process. 0.285 1.58 FIGURE 2. Outline of MICRO FOOT CSP & Analog Switch DG3000DB Document Number: 71990 www.vishay.com 06-Jan-03 1

AN824 Vishay Siliconix TABLE 1 ÁÁÁÁÁÁÁÁMÁainÁÁ PaÁramÁeterÁs oÁf SoÁÁlderÁ BuÁmpÁs inÁ MICÁROÁÁ FOÁOT ÁDesÁignÁs ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁMÁÁICRÁÁO FÁÁOOTÁÁ CSÁÁP ÁÁÁÁÁÁÁÁBumÁÁp MÁÁateÁÁrialÁÁÁÁÁÁBÁÁumÁÁp PiÁÁtchÁÁ* ÁÁÁÁBÁÁumÁÁp DiÁÁameÁÁterÁÁÁÁ* ÁÁBuÁÁmpÁÁ HeÁÁightÁÁ* ÁÁ ÁÁÁÁMICÁÁRO FÁÁOOTÁÁ CSÁÁP MOÁÁSFEÁÁT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0.8ÁÁÁÁÁÁÁÁÁÁÁÁ0.37-ÁÁ0.41ÁÁÁÁÁÁÁÁÁÁ0.2ÁÁ6-0.2ÁÁ9 ÁÁÁÁ EEuutteeccttiicc SSoollddeerr:: MICRO FOOT CSP Analog Switch 0.5 0.18-0.25 0.14-0.19 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ66ÁÁ33SSmmÁÁ//3377PPbbÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MICRO FOOT UCSP Analog Switch 0.5 0.32-0.34 0.21-0.24 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ * All measurements in millimeters MICRO FOOT’S DESIGN AND RELIABILITY BOARD LAYOUT GUIDELINES As a mechanical, electrical, and thermal connection between Board materials. Vishay Siliconix MICRO FOOT products are the device and PCB, the solder bumps of MICRO FOOT designed to be reliable on most board types, including organic products are mounted on the top active surface of the die. boards such as FR-4 or polyamide boards. The package Table 1 shows the main parameters for solder bumps used in qualification information is based on the test on 0.5-oz. FR-4 MICRO FOOT products. A silicon nitride passivation layer is and polyamide boards with NSMD pad design. applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot Land patterns. Two types of land patterns are used for test. A green laser is used to mark the backside of the die surface-mount packages. Solder mask defined (SMD) pads without damaging it. Reliability results for MICRO FOOT have a solder mask opening smaller than the metal pad products mounted on a FR-4 board without underfill are shown (Figure 3), whereas on-solder mask defined (NSMD) pads in Table 2. have a metal pad smaller than the solder-mask opening (Figure 4). TABLE 2 MICRO FOOT Reliability Results NSMD is recommended for copper etch processes, since it ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Test Condition C: −65(cid:1) to 150(cid:1)C >500 Cycles provides a higher level of control compared to SMD etch ÁÁÁTÁÁÁest cÁÁÁonditÁÁÁion BÁÁÁ: −40ÁÁÁ(cid:1) to ÁÁÁ125(cid:1)ÁÁÁC ÁÁÁÁÁÁÁÁÁÁÁÁ>10ÁÁÁ00 CÁÁÁyclesÁÁÁÁÁÁ processes. A small-size NSMD pad definition provides more area (both lateral and vertical) for soldering and more room for Á1Á21(cid:1)CÁ @ 1Á5PSÁI 100Á% HuÁmiditÁy TesÁÁt ÁÁ9Á6 HouÁrs ÁÁ escape routing on the PCB. By contrast, SMD pad definition introduces a stress concentration point near the solder mask on the PCB side that may result in solder joint cracking under extreme fatigue conditions. The main failure mechanism associated with wafer-level chip-scale packaging is fatigue of the solder joint. The results Copper pads should be finished with an organic solderability shown in Table 2 demonstrate that a high level of reliability can preservative (OSP) coating. For electroplated be achieved with proper board design and assembly nickel-immersion gold finish pads, the gold thickness must be techniques. less than 0.5 (cid:1)m to avoid solder joint embrittlement. Solder Mask Solder Mask Copper Copper FIGURE 3. SMD FIGURE 4. NSMD www.vishay.com Document Number: 71990 2 06-Jan-03

AN824 Vishay Siliconix Board pad design. The landing-pad size for MICRO FOOT Chip pick-and-placement. MICRO FOOT products can be products is determined by the bump pitch as shown in Table 3. picked and placed with standard pick-and-place equipment. The pad pattern is circular to ensure a symmetric, The recommended pick-and-place force is 150 g. Though the barrel-shaped solder bump. part will self-center during solder reflow, the maximum placement offset is 0.02 mm. TABLE 3 Reflow Process. MICRO FOOT products can be assembled using standard SMT reflow processes. Similar to any other Dimensions of Copper Pad and Solder Mask package, the thermal profile at specific board locations must Opening in PCB and Stencil Aperture ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ be determined. Nitrogen purge is recommended during reflow Solder Mask Stencil operation. Figure 6 shows a typical reflow profile. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pitch Copper Pad Opening Aperture ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0.80 mm 0.30 (cid:1) 0.01 mm 0.41 (cid:1) 0.01 mm 0.33 (cid:1) 0.01 mm Thermal Profile ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁiÁn ciirÁÁcle aÁÁpertuÁÁre 250 Á0.5Á0 mmÁÁ0Á.17 (cid:1)Á 0.0Á1 mmÁÁ0Á.27 (cid:1)Á 0.0Á1 mmÁÁinÁ0 .s3q0u Á(cid:1)are 0 a.Á0p1e rmtuÁmre 200 ASSEMBLY PROCESS C) 150 (cid:1) e ( MICRO FOOT products’ surface-mount-assembly operations atur include solder paste printing, component placement, and er 100 p m solder reflow as shown in the process flow chart (Figure 5). e T 50 Stencil Design IIncoming Tape and Reel Inspection 0 0 100 200 300 400 Solder Paste Printing Time (Seconds Chip Placement FIGURE 6. Reflow Profile Reflow Solder Joint Inspection PCB REWORK Pack and Ship To replace MICRO FOOT products on PCB, the rework procedure is much like the rework process for a standard BGA FIGURE 5. SMT Assembly Process Flow or CSP, as long as the rework process duplicates the original reflow profile. The key steps are as follows: 1. Remove the MICRO FOOT device using a convection Stencil design. Stencil design is the key to ensuring nozzle to create localized heating similar to the original maximum solder paste deposition without compromising the reflow profile. Preheat from the bottom. assembly yield from solder joint defects (such as bridging and 2. Once the nozzle temperature is +190(cid:1)C, use tweezers to extraneous solder spheres). The stencil aperture is dependent remove the part to be replaced. on the copper pad size, the solder mask opening, and the quantity of solder paste. 3. Resurface the pads using a temperature-controlled soldering iron. In MICRO FOOT products, the stencil is 0.125-mm (5-mils) thick. The recommended apertures are shown in Table 3 and 4. Apply gel flux to the pad. are fabricated by laser cut. 5. Use a vacuum needle pick-up tip to pick up the Solder-paste printing. The solder-paste printing process replacement part, and use a placement jig to placed it involves transferring solder paste through pre-defined accurately. apertures via application of pressure. 6. Reflow the part using the same convection nozzle, and In MICRO FOOT products, the solder paste used is UP78 preheat from the bottom, matching the original reflow No-clean eutectic 63 Sn/37Pb type3 or finer solder paste. profile. Document Number: 71990 www.vishay.com 06-Jan-03 3

Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 08-Feb-17 1 Document Number: 91000