SG3524 ® REGULATING PULSE WIDTH MODULATORS COMPLETE PWM POWER CONTROL CIR- CUITRY UNCOMMITTED OUTPUTS FOR SINGLE- ENDED OR PUSH PULL APPLICATIONS LOW STANDBY CURRENT 8mA TYPICAL OPERATION UP TO 300KHz 1% MAXIMUM TEMPERATURE VARIATION OF REFERENCE VOLTAGE DESCRIPTION DIP16 SO16 The SG3524 incorporates on a single monolithic ORDERING NUMBERS: SG3524N (DIP16) chip all the function required for the construction SG3524P (SO16) of regulating power suppies inverters or switching regulators. They can also be used as the control element for high power-output applications. The SG3524 family was designed for switching regu- lators of either polarity, transformer-coupled dc- to-dc converters, transformerless voltage dou- Each device includes an on-ship reference, error blers and polarity converter applications amplifier, programmable oscillator, pulse-steering employing fixed-frequency, pulse-width modula- flip flop, two uncommitted output transistors, a tion techniques. The dual alternating outputs al- high-gain comparator, and current-limiting and lows either single-ended or push-pull applications. shut-down circuitry. BLOCK DIAGRAM July 2000 1/9 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

SG3524 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VIN Supply Voltage 40 V IC Collector Output Current 100 mA IR Reference Output Current 50 mA IT Current Through CT Terminal – 5 mA Ptot Total Power Dissipation at Tamb = 70(cid:176) C 1000 mW Tstg Storage Temperature Range – 65 to 150 (cid:176) C Top Operating Ambient Temperature Range: 0 to 70 (cid:176) C PIN CONNECTION (Top view) THERMAL DATA Symbol Parameter DIP16 SO16 Unit Rth j-amb Thermal Resistance Junction-ambient Max. 80 – (cid:176) C/W Rth j-alumina Thermal Resistance Junction-alumina (*) Max. – 50 (cid:176) C/W (*) Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20mm; 0.65mm thickness with infinite heatsink. 2/9

SG3524 ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for Tj = 0 to 70(cid:176) C, VIN = 20V, and f = 20KHz). Symbol Parameter Test Condition Min. Typ. Max. Unit REFERENCE SECTION VREF Output Voltage 4.6 5 5.4 V D VREF Line Regulation VIN = 8 to 40V 10 30 mV D VREF Load Regulation IL = 0 to 20mA 20 50 mV Ripple Rejection f = 120Hz, Tj = 25(cid:176) C 66 dB Short Circuit Current Limit VREF = 0, Tj = 25(cid:176) C 100 mA D VREF/D T Temperature Stability Over Operating Temperature range 0.3 1 % D VREF Long Term Stability Tj = 125(cid:176) C, t = 1000Hrs 20 mV OSCILLATOR SECTION fMAX Maximum Frequency CT = 0.001m F, RT = 2KW 300 KHz Initial Accuracy RT and CT Constant 5 % Voltage Stability VIN = 8 to 40V, Tj = 25(cid:176) C 1 % D f/D T Temperature Stability Over Operating Temperature Range 2 % Output Amplitude Pin 3, Tj = 25(cid:176) C 3.5 V Output Pulse Width CT = 0.01m F, Tj = 25(cid:176) C 0.5 m s ERROR AMPLIFIER SECTION VOS Input Offset Voltage VCM = 2.5V 2 10 mV Ib Input Bias Current 2 10 m A GV Open Loop Voltage Gain 60 80 dB CMV Common Mode Voltage Tj = 25(cid:176) C 1.8 3.4 V CMR Common Mode Rejection Tj = 25(cid:176) C 70 dB B Small Signal Bandwidth AV = 0dB, Tj = 25(cid:176) C 3 MHz VO Output Voltage Tj = 25(cid:176) C 0.5 3.8 V COMPARATOR SECTION Duty-cycle % Each Output On 0 45 % VIT Input Threshold Zero Duty-cycle 1 V Maximum Duty-cycle 3.5 V Ib Input Bias Current 1 m A CURRENT LIMITING SECTION Sense Voltage Pin 9 = 2V with Error Amp. Set for 180 200 220 mV Max. Out. Tj = 25(cid:176) C Sense Voltage T.C. 0.2 mV/(cid:176) C CMV Common Mode Voltage –1 1 OUTPUT SECTION(each output) Collector-emitter Voltage 40 V Collector Leackage Curr. VCE = 40V 0.1 50 m A Saturation Voltage IC = 50mA 1 2 V Emitter Output Voltage VIN = 20V 17 18 V tr Rise Time RC = 2KW , Tj = 25(cid:176) C 0.2 m s tf Fall Time RC = 2KW , Tj = 25(cid:176) C 0.1 m s Iq (*) Total Standby Current VIN = 40V 8 10 mA (*) Excluding oscillator charging current, error and current limit dividers, and with outputs open. 3/9

SG3524 Figure 1: Open-loop Voltage Amplification of Figure 2: Oscillator Frequency vs. Timing Error Amplifier vs. Frequency Components. Figure 3: Output Dead Time vs. Timing Figure 4: Output Saturation Voltage vs. load Capacitance Value. Current. Figure 5: Open Loop Test Circuit. 4/9

SG3524 cording to the approximate formula: PRINCIPLES OF OPERATION The SG3524 is a fixed frequency pulse-with- 1.18 modulation voltage regulator control circuit. The f = R C regulator operates at a frequency that is pro- T T grammed by one timing resistor (RT) and one tim- where: civnhogalt argcgiaenp gra accmiutoprrr e an(t CtC TfTo).,r wRChTTi c. heT shistia sfb elrdies hstoue ldttsh eai n c coaom nlpisnatearaanr-t RCTT iiss iinn Km FW f is in KHz tor providing linear control of the output pulse width by the error amplifier. the SG3524 contains, Pratical values of CT fall between 0.001 and an on-board 5V regulator that serves as a refer- 0.1m F. Pratical values of RT fall between 1.8 and ence as well as powering the SG3524’s internal 100KW . This results in a frequency range typically control circuitry and is also useful in supplying ex- from 120Hz to to 500KHz. ternal support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common mode range the BLANKING error amplifier or an external reference may be The output pulse of oscillator is used as a blank- used. The power supply output is sensed by a ing pulse at the output. This pulse width is con- second resistor divider network to generale a trolled by the value of CT.If small values of CT are feedback signal to error amplifier. The amplifier required for frequency control, the oscillator out- output voltage is then compared to the linear volt- put pulse width may still be increased by applying age ramp at CT. The resulting modulated pulse a shunt capacitance of up to 100pF from pin 3 to out of the high-gain comparator is then steered to ground. If still greater dead-time is required, it the appropriate output pass transistors (QA or QB) should be accomplished by limiting the maximum by the pulse-steering flip-flop, which is synchro- duty cycle by clamping the output of the error am- nously toggled by the oscillator output. The oscil- plifier. This can easily be done with the circuit be- lator output pulse also serves as a blanking pulse low: to assure both output are never on simultane- ously during the transition times. The width of the blanking pulse is controlled by the value of CT. Figure 6. The outputs may be applied in a push-pull con- figuration in which their frequency is half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error am- plifier shares a common input to the comparator with the current limiting at shutdown circuitry and can be overridden by signals from either of these inputs. This common point is also available exter- nally and may be employed to control the gain of, or to compensate, the error amplifier, or to pro- SYNCRONOUS OPERATION vide additional control to the regulator. When an external clock is desired, a clock pulse of approximately 3V can be applied directly to the RECOMMENDED OPERATING CONDITIONS oscillator output terminal. The impedance to ground at this point is approximately 2KW . In this Supply voltage VIN 8 to 40V configuration RT CT must be selected for a clock Reference Output Current 0 to 20mA period slightly greater than that the external clock. Current trough CT Terminal - 0.03 to -2mA If two more SG2524 regulators are to be operated TTiimmiinngg CRaepsiasctoitro, rR, CTT 01.0.80 1to t o1 000.1KmW F nssyhenocctuehlddro tnbooe au stsileiyn,dg letao ltlg imetoihnsegcr i,lcl aaatpolla r cCitoTo ur,tt peaurnmtd i nttiaemlrsmin gicn oarnels-- sistor connected to a single RT terminal. The TYPICAL APPLICATIONS DATA other RT terminals can be left open or shorted to VREF. Minimum lead lengths should be used be- OSCILLATOR tween the CT terminals. The oscillator controls the frequency of the SG3524 and is programmed by RT and CT ac- 5/9

SG3524 Figure 7: Flyback Converter Circuit. Figure 8: PUSH-PULL Transformer-coupled circuit. 6/9

SG3524 mm inch OUTLINE AND DIM. MECHANICAL DATA MIN. TYP. MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 DIP16 Z 1.27 0.050 7/9

SG3524 mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45˚ (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M 0.62 0.024 SO16 Narrow S 8˚(max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 8/9

SG3524 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9