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  • 型号: QT60160-ISG
  • 制造商: Atmel
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QT60160-ISG产品简介:

ICGOO电子元器件商城为您提供QT60160-ISG由Atmel设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 QT60160-ISG价格参考。AtmelQT60160-ISG封装/规格:接口 - 传感器,电容式触摸, Capacitive Touch Buttons 32-QFN (5x5)。您可以下载QT60160-ISG参考资料、Datasheet数据手册功能说明书,资料中有QT60160-ISG 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

传感器,变送器

描述

SENSOR IC MTRX TOUCH16KEY 32-QFN

产品分类

电容式触摸传感器,接近传感器 IC

品牌

Atmel

数据手册

点击此处下载产品Datasheet

产品图片

产品型号

QT60160-ISG

rohs

无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

QMatrix™

产品目录页面

点击此处下载产品Datasheet

供应商器件封装

32-QFN

其它名称

427-1125-1

分辨率(位)

10 b

包装

剪切带 (CT)

参考设计库

http://www.digikey.com/rdl/4294959886/4294959868/868

安装类型

表面贴装

封装/外壳

32-VFQFN

工作温度

-40°C ~ 85°C

数据接口

I²C, SPI

数据速率/采样率(SPS,BPS)

-

标准包装

1

电压-电源

1.8V,3.3V,5V

电压基准

外部

电流-电源

4.6mA

类型

电容性

触摸面板接口

-

评估工具

可供

输入/按键数

16 键

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PDF Datasheet 数据手册内容提取

QT60160, QT60240 lQ 16 24 K QM ™ T S IC AND EY ATRIX OUCH ENSOR s These devices are designed for low cost mobile and consumer electronics Y2 Y1 Y0 /RS SC SD SM Y2 A A A T L A P B applications. QMatrix™ technology employs transverse charge-transfer sensing electrode 323130 2928 272625 M_SYNC 1 24 Y1B designs which can be made very compact and are easily wired. Charge is CHANGE 2 23 Y0B forced from an emitting electrode into the overlying panel dielectric, and then VSS 3 QT60240 22 A0 collected on a receiver electrode which directs the charge into a sampling VDD 4 QT60160 21 VSS capacitor which is then converted directly to digital form without the use of VSS 5 20 VDD amplifiers. VDD 6 MLF-32 19 A1 Keys are configured in a matrix format that minimizes the number of required X6 7 18 VDD scan lines and device pins. The key electrodes can be designed into a X7 8 17 X5 conventional Printed Circuit Board (PCB) or Flexible Printed Circuit Board 9 10 11121314 1516 (FPCB) as a copper pattern, or as printed conductive ink on plastic film. L V S X X X X X A R _ 0 1 2 3 4 TCH EF SYN C AT A GLANCE Number of keys: 1 to 16 (QT60160), or 1 to 24 (QT60240) Technology: Patented spread-spectrum charge-transfer (transverse mode) Key outline sizes: 6mm x 6mm or larger (panel thickness dependent); widely different sizes and shapes possible Key spacings: 8mm or wider, center to center (panel thickness dependent) Electrode design: Two-part electrode shapes (drive-receive); wide variety of possible layouts Layers required: One layer (with jumpers), two layers (no jumpers) Electrode materials: PCB, FPCB, silver or carbon on film, ITO on film, Orgacon† ink on film Panel materials: Plastic, glass, composites, painted surfaces (low particle density metallic paints possible) Adjacent Metal: Compatible with grounded metal immediately next to keys Panel thickness: Up to 50mm glass, 20mm plastic (key size dependent) Key sensitivity: Individually settable via simple commands over serial interface Interface: I2C slave mode (100kHz), or parallel output via external shift registers Moisture tolerance: Best in class. Power: 1.8V ~ 5.5V, 40µA (16 keys at 1.8V, 2s Low Power mode). Guaranteed to 1.62V. Package: 32-pin 5 x 5mm MLF RoHS compliant Signal processing: Self-calibration, auto drift compensation, noise filtering, Adjacent Key SuppressionTM Applications: Mobile phones, remote controls, domestic appliances, PC peripherals, automotive †Orgacon is a registered trademark of Agfa-Gevaert N.V AVAILABLE OPTIONS Part Number Keys T A QT60160-ISG 16 -400C to +850C QT60240-ISG 24 -400C to +850C LQ Copyright © 2006 QRG Ltd QT60240-ISG R8.06/0906

Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Interface Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 Part Differences . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Transferring Data Bits . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 Enabling / Disabling Keys . . . . . . . . . . . . . . . . . . . . . 3 5.3 START and STOP Conditions . . . . . . . . . . . . . . . . . . . 15 2 Hardware and Functional . . . . . . . . . . . . . . . . . . . . . 3 5.4 Address Packet Format . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Matrix Scan Sequence . . . . . . . . . . . . . . . . . . . . . . . 3 5.5 Data Packet Format . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Burst Paring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.6 Combining Address and Data Packets Into a Transmission . . . . 16 2.3 Cs Sample Capacitor Operation . . . . . . . . . . . . . . . . . . 3 6 Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 Sample Capacitor Saturation . . . . . . . . . . . . . . . . . . . 4 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 Sample Resistors . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Negative Threshold - NTHR . . . . . . . . . . . . . . . . . . . . 17 2.6 Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.3 Positive Threshold - PTHR . . . . . . . . . . . . . . . . . . . . 17 2.7 Matrix Series Resistors . . . . . . . . . . . . . . . . . . . . . . 5 6.4 Drift Compensation - NDRIFT, PDRIFT . . . . . . . . . . . . . . 17 2.8 Key Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.5 Detect Integrators - NDIL, FDIL . . . . . . . . . . . . . . . . . . 18 2.9 PCB Layout, Construction . . . . . . . . . . . . . . . . . . . . . 6 6.6 Negative Recal Delay - NRD . . . . . . . . . . . . . . . . . . . . 18 2.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.7 Positive Recalibration Delay - PRD . . . . . . . . . . . . . . . . 18 2.9.2 LED Traces and Other Switching Signals . . . . . . . . . . . . . . 6 6.8 Burst Length - BL . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9.3 PCB Cleanliness . . . . . . . . . . . . . . . . . . . . . . . . 6 6.9 Adjacent Key Suppression - AKS . . . . . . . . . . . . . . . . . 19 2.10 Power Supply Considerations . . . . . . . . . . . . . . . . . . 6 6.10 Oscilloscope Sync - SSYNC . . . . . . . . . . . . . . . . . . . 19 2.11 Startup / Calibration Times . . . . . . . . . . . . . . . . . . . . 7 6.11 Mains Sync - MSYNC . . . . . . . . . . . . . . . . . . . . . . 19 2.12 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.12 Sleep Duration - SLEEP . . . . . . . . . . . . . . . . . . . . . 20 2.13 Spread Spectrum Acquisitions . . . . . . . . . . . . . . . . . . 7 6.13 Wake on Key Touch - WAKE . . . . . . . . . . . . . . . . . . . 20 2.14 Detection Integrators . . . . . . . . . . . . . . . . . . . . . . . 7 6.14 Awake Timeout - AWAKE . . . . . . . . . . . . . . . . . . . . 20 2.15 Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.15 Drift Hold Time - DHT . . . . . . . . . . . . . . . . . . . . . . 20 2.16 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.16 Setups Block . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1 Absolute Maximum Electrical Specifications . . . . . . . . . . . . 23 3.2 Shift Register Output Mode . . . . . . . . . . . . . . . . . . . . 10 7.2 Recommended Operating Conditions . . . . . . . . . . . . . . . 23 3.3 I2C Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 CHANGE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 23 4 Control Commands . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Writing Data to the Device . . . . . . . . . . . . . . . . . . . . . 12 7.7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 Reading Data From the Device . . . . . . . . . . . . . . . . . . 12 7.8 Moisture Sensitivity Level (MSL) . . . . . . . . . . . . . . . . . . 25 4.4 Report Detections for All Keys . . . . . . . . . . . . . . . . . . . 12 4.5 Raw Data Commands . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Cal All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 lQ 2 QT60240-ISG R8.06/0906

1.3 Enabling / Disabling Keys 1 Overview The NDIL parameter is used to enable and disable keys in the matrix. Setting NDIL = 0 for a key disables it (Section 6.5). At 1.1 Introduction no time can the number of enabled keys exceed the QT60xx0 devices are digital burst mode charge-transfer (QT) maximum specified for the device (see Section 1.2). sensors designed specifically for matrix layout touch controls; they include all signal processing functions necessary to On the QT60160, only the first 2 Y lines (Y0, Y1) are provide stable sensing under a wide variety of changing operational by default. On the QT60160, to use keys located conditions. Only a few external parts are required for on line Y2, one or more of the pre-enabled keys must be operation. The entire circuit can be built within a few square disabled simultaneously while enabling the desired new keys. centimeters of single-sided PCB area. CEM-1 and FR1 This can be done in one Setups block load operation. punched, single-sided materials can be used for the lowest possible cost. The PCB’s rear can be mounted flush on the back of a glass or plastic panel using a conventional 2 Hardware and Functional adhesive, such as 3M VHB two-sided adhesive acrylic film. 2.1 Matrix Scan Sequence Figure 1.1 Field Flow Between X and Y Elements The circuit operates by scanning each key sequentially, key by key. Key scanning begins with location X=0 / Y=0 (key 0). X axis keys are known as rows while Y axis keys are referred overlying panel to as columns although this has no reflection on actual wiring. Keys are scanned sequentially by row, for example the sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1... etc. Keys are X Y also numbered from 0...23. Key 0 is located at X0Y0. element element Table 2.1 shows the key numbering. Table 2.1 Key Numbers X7 X6 X5 X4 X3 X2 X1 X0 Y0 7 6 5 4 3 2 1 0 s Y1 15 14 13 12 11 10 9 8 Keymber Y2 23 22 21 20 19 18 17 16 nu QT60xx0 devices employ transverse charge-transfer ('QT') sensing, a technology that senses changes in electrical Each key is sampled in a burst of acquisition pulses whose charge forced across two electrode elements by a pulse edge length is determined by the Setups parameter BL (page 19); (Figure 1.1). QT60xx0 devices allow a wide range of key sizes this can be set on a per-key basis. A burst is completed and shapes to be mixed together in a single touch panel. entirely before the next key is sampled; at the end of each burst the resulting signal is converted to digital form and The devices use an I2C interface to allow key data to be processed. The burst length directly impacts key gain; each extracted and to permit individual key parameter setup. The key can have a unique burst length in order to allow tailoring command structure is designed to minimize the amount of of key sensitivity on a key-by-key basis. data traffic while maximizing the amount of information conveyed. 2.2 Burst Paring In addition to normal operating and setup functions the device Keys that are disabled by setting NDIL = 0 (Section 6.5, can also report back actual signal strengths. page 18) have their bursts removed from the scan sequence QmBtn™ software for the PC can be used to program the to save scan time. As a consequence, the fewer keys that are operation of the IC, as well as read back key status and used the faster the device can respond. All calibration times signal levels in real time. are reduced when keys are disabled. 1.2 Part Differences 2.3 Cs Sample Capacitor Operation There are two versions of the device; one is capable of a Cs capacitors absorb charge from the key electrodes on the maximum of 16 keys (QT60160), the other is capable of a rising edge of each X pulse. On each falling edge of X, the Y maximum of 24 keys (QT60240). matrix line is clamped to ground to allow the electrode and wiring charges to neutralize in preparation for the next pulse. These devices are identical in all respects, except for the With each X pulse charge accumulates on Cs causing a maximum number of keys specified. The keys can be located staircase increase in its differential voltage. anywhere within an electrical grid of 8 X and 3 Y scan lines. After the burst completes, the device clamps the Y line to Unused keys are always pared from the burst sequence in ground causing the opposite terminal to go negative. The order to optimize speed. Similarly, in a given part a lesser charge on Cs is then measured using an external resistor to number of enabled keys will cause any unused acquisition ramp the negative terminal upwards until a zero crossing is burst timeslots to be pared from the sampling sequence to achieved. The time required to zero cross becomes the optimize acquire speed. Thus, if only 14 keys are actually measurement result. enabled, only 14 timeslots are used for scanning. lQ 3 QT60240-ISG R8.06/0906

The Cs should be connected as shown in Figure 2.7, page 9. Figure 2.1 VCs - Nonlinear During Burst The value of these capacitors is not critical but 4.7nF is (Burst too long, or Cs too small, or X-Y transcapacitance too large) recommended for most cases. They should be 10 percent X7R ceramics. If the transverse capacitive coupling from X to Y is large enough the voltage on a Cs capacitor can saturate, X Drive destroying gain. In such cases the burst length should be reduced and/or the Cs value increased. See Section 2.4. If a Y line is not used its corresponding Cs capacitor may be omitted and the pins left floating. YnB 2.4 Sample Capacitor Saturation Cs voltage saturation at a pin YnB is shown in Figure 2.1 Saturation begins to occur when the voltage at a YnB pin Figure 2.2 VCs - Poor Gain, Nonlinear During Burst becomes more negative than -0.25V at the end of the burst. (Excess capacitance from Y line to Gnd) This nonlinearity is caused by excessive voltage accumulation on Cs inducing conduction in the pin protection X Drive diodes. This badly saturated signal destroys key gain and introduces a strong thermal coefficient which can cause 'phantom' detection. The cause of this is either from the burst length being too long, the Cs value being too small, or the X-Y transfer coupling being too large. Solutions include YnB loosening up the key structure interleaving, more separation of the X and Y lines on the PCB, increasing Cs, and decreasing the burst length. Figure 2.3 VCs - Correct Increasing Cs will make the part slower; decreasing burst length will make it less sensitive. A better PCB layout and a looser key structure (up to a point) have no negative effects. X Drive Cs voltages should be observed on an oscilloscope with the matrix layer bonded to the panel material; if the Rs side of any Cs ramps more negative than -0.25 volts during any burst (not counting overshoot spikes which are probe artifacts), there is a potential saturation problem. YnB Figure 2.2 shows a defective waveform similar to that of 2.1, but in this case the distortion is caused by excessive stray capacitance coupling from the Y line to AC ground; for example, from running too near and too far alongside a ground trace, ground plane, or other traces. The excess Figure 2.4 X-Drive Pulse Roll-off and Dwell Time coupling causes the charge-transfer effect to dissipate a The Dwell time is fixed at ~500ns - see Section 2.7 significant portion of the received charge from a key into the stray capacitance. This phenomenon is more subtle; it can be best detected by increasing BL to a high count and watching X drive Lost charge due to what the waveform does as it descends towards and below inadequate settling -0.25V. The waveform will appear deceptively straight, but it before end of dwell time will slowly start to flatten even before the -0.25V level is Dwell time reached. A correct waveform is shown in Figure 2.3. Note that the Y gate bottom edge of the bottom trace is substantially straight (ignoring the downward spikes). Unlike other QT circuits, the Cs capacitor values on QT60xx0 devices have no effect on conversion gain. However, they do affect conversion time. Unused Y lines should be left open. 2.6 Signal Levels Quantum’s QmBtn software makes it is easy to observe the 2.5 Sample Resistors absolute level of signal received by the sensor on each key. There are three sample resistors (Rs) used to perform The signal values should normally be in the range of 200 to single-slope ADC conversion of the acquired charge on each 750 counts with properly designed key shapes and values of Cs capacitor. These resistors directly control acquisition gain; Rs. However, long adjacent runs of X and Y lines can also larger values of Rs will proportionately increase signal gain. artificially boost the signal values, and induce signal For most applications Rs should be 1M✡. Unused Y lines do saturation; this is to be avoided. The X-to-Y coupling should not require an Rs resistor. come mostly from intra-key electrode coupling, not from stray X-to-Y trace coupling. lQ 4 QT60240-ISG R8.06/0906

Figure 2.5 Probing X-Drive Figure 2.6 Recommended Key Structure Waveforms With a Coin ‘T’ should ideally be similar to the complete thickness the fields need to penetrate to the touch surface. Smaller dimensions will also work but will give less signal strength. If in doubt, make the pattern coarser. The lower figure shows a simpler structure used for compact key layouts, for example for mobile phones. A layout with a common X drive and three receive electrodes is depicted. Y0 X0 QmBtn software is available free of charge on Quantum’s website www.qprox.com. The signal swing from the smallest finger touch should Y1 preferably exceed 8 counts, with 12 being a reasonable target. The signal threshold setting (NTHR) should be set to a value guaranteed to be less than the signal swing caused by the smallest touch. Y2 Increasing the burst length (BL) parameter will increase the signal strengths as will increasing the sampling resistor (Rs) values. 2.7 Matrix Series Resistors The upper limits of Rx and Ry are reached when the signal The X and Y matrix scan lines can use series resistors level and hence key sensitivity are clearly reduced. The limits (referred to as Rx and Ry respectively) for improved EMC of Rx and Ry will depend on key geometry and stray performance (Figure 2.7, page 9). capacitance, and thus an oscilloscope is required to X drive lines require Rx in most cases to reduce edge rates determine optimum values of both. and thus reduce RF emissions. Typical values range from Dwell time is the duration in which charge coupled from X to 1K✡ to 20K✡. Y is captured (Figure 2.4, page 4). Increasing Rx values will Y lines need Ry to reduce EMC susceptibility problems and in cause the leading edge of the X pulses to increasingly roll off, some extreme cases, ESD. Typical Y values are about 1K✡. causing the loss of captured charge (and hence loss of signal Y resistors act to reduce noise susceptibility problems by strength) from the keys. forming a natural low-pass filter with the Cs capacitors. The dwell time of these parts is fixed at 500ns. If the X pulses It is essential that the Rx and Ry resistors and Cs capacitors have not settled within 500ns, key gain will be reduced; if this be placed very close to the chip. Placing these parts more happens, either the stray capacitance on the X line(s) should than a few millimeters away opens the circuit up to high be reduced (by a layout change, for example by reducing X frequency interference problems (above 20MHz) as the trace line exposure to nearby ground planes or traces), or, the Rx lengths between the components and the chip start to act as resistor needs to be reduced in value (or a combination of RF antennae. both approaches). lQ 5 QT60240-ISG R8.06/0906

One way to determine X line settling time is to monitor the Ground planes, if used, should be placed under or around the fields using a patch of metal foil or a small coin over the key QT chip itself and the associated resistors and capacitors in (Figure 2.5). Only one key along a particular X line needs to the circuit, under or around the power supply, and back to a be observed, as each of the keys along that X line will be connector, but nowhere else. identical. The 500ns dwell time should exceed the observed 95 percent settling of the X-pulse by 25 percent or more. 2.9.2 LED Traces and Other Switching Signals In almost all cases, Ry should be set equal to Rx, which will Digital switching signals near the Y lines will induce transients ensure that the charge on the Y line is fully captured into the into the acquired signals, deteriorating the SNR perfomance Cs capacitor. of the device. Such signals should be routed away from the Y lines, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). 2.8 Key Design LED terminals which are multiplexed or switched into a Circuits can be constructed out of a variety of materials floating state and which are within or physically very near a including conventional FR-4, Flexible Printed Circuit Boards key structure (even if on another nearby PCB) should be (FPCB), silver silk-screened on PET plastic film, and even bypassed to either Vss or Vdd with at least a 10nF capacitor inexpensive punched single-sided CEM-1 and FR-2. to suppress capacitive coupling effects which can induce The actual internal pattern style is not as important as the false signal shifts. The bypass capacitor does not need to be need to achieve regular X and Y widths and spacings of next to the LED, in fact it can be quite distant. The bypass sufficient size to cover the desired graphical key area or a capacitor is noncritical and can be of any type. little bit more; ~3mm oversize is acceptable in most cases, LED terminals which are constantly connected to Vss or Vdd since the key’s electric fields drop off near the edges anyway. do not need further bypassing. The overall key size can range from 6mm x 6mm up to 100mm x 100mm but these are not hard limits. The keys can be any shape including round, rectangular, square, etc. The 2.9.3 PCB Cleanliness internal pattern can be interdigitated as shown in Figure 2.6. All capacitive sensors should be treated as highly sensitive circuits which can be influenced by stray conductive leakage For small, dense keypads, electrodes such as shown in the paths. QT devices have a basic resolution in the femtofarad lower half of Figure 2.6 can be used. Where the panels are range; in this region, there is no such thing as ‘no clean flux’. thin (usually mobile phones have panels under 2mm thick) Flux absorbs moisture and becomes conductive between the electrode density can be quite high. solder joints, causing signal drift and resultant false For better surface moisture suppression, the outer perimeter detections or transient losses of sensitivity or instability. of X should be as wide as possible, and there should be no Conformal coatings will trap in existing amounts of moisture ground planes near the keys. The variable ‘T’ in this drawing which will then become highly temperature sensitive. represents the total thickness of all materials that the keys The designer should specify ultrasonic cleaning as part of the must penetrate. manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after 2.9 PCB Layout, Construction cleaning to keep out moisture. 2.9.1 Overview 2.10 Power Supply Considerations It is best to place the chip near the touch keys on the same The power supply can range from +1.8V to +5V nominal. The PCB so as to reduce X and Y trace lengths, thereby reducing device can tolerate ±5mV/s short-term power supply the chances for EMC problems. Long connection traces act fluctuations. If the power supply fluctuates slowly with as RF antennae. The Y (receive) lines are much more temperature, the device will track and compensate for these susceptible to noise pickup than the X (drive) lines. changes automatically with only minor changes in sensitivity. Even more importantly, all signal related discrete parts If the supply voltage drifts or shifts quickly, the drift (resistors and capacitors) should be very close to the body of compensation mechanism will not be able to keep up, the chip. Wiring between the chip and the various resistors causing sensitivity anomalies or false detections. and capacitors should be as short and direct as possible to As these devices use the power supply itself as an analog suppress noise pickup. reference, the power should be very clean and come from a separate regulator. A standard inexpensive Low Dropout (LDO) type regulator should be used that is not also used to Ground planes and traces should NOT power other loads such as LEDs, relays, or other high current be used around the keys and the Y lines devices. Load shifts on the output of the LDO can cause Vdd from the keys. Ground areas, traces, and to fluctuate enough to cause false detection or sensitivity other adjacent signal conductors that act shifts. as AC ground (such as Vdd and LED drive lines etc.) will absorb the received key signals and Caution: A regulator IC shared with other logic can result in reduce signal-to-noise ratio (SNR) and thus will be erratic operation and is not advised. counterproductive. Ground planes around keys will also A regulator can be shared among two or more QT devices on make water film effects worse. one board. One such regulator known to work well with QT chips is the S-817 series from Seiko Instruments (Seiko Instruments - www.sii-ic.com). lQ 6 QT60240-ISG R8.06/0906

A single ceramic 0.1uF bypass capacitor, with short traces, The QT60xx0 uses a two-tier confirmation mechanism having should be placed very close to supply pins 3, 4, 5 and 6 of the two such counters for each key. These can be thought of as IC. Failure to do so can result in device oscillation, high ‘inner loop’ and ‘outer loop’ confirmation counters. current consumption, erratic operation etc. Pins 18, 20, and The ‘inner’ counter is referred to as the ‘fast-DI’; this acts to 21 do not require bypassing. attempt to confirm a detection via rapid successive acquisition bursts, at the expense of delaying the sampling of 2.11 Startup / Calibration Times the next key. Each key has its own fast-DI counter and limit The devices require initialization times of up to 20ms. A value; these limits can be changed via the Setups block on a calibration takes one matrix scan. per-key basis. Disabled keys are subtracted from the burst sequence and The ‘outer’ counter is referred to as the ‘normal-DI’; this DI thus the cal time is shortened. The scan time should be counter increments whenever the fast-DI counter has reached measured on an oscilloscope. its limit value. If a fast-DI counter failed to reach its terminal count, the corresponding normal-DI counter is also reset. The normal-DI counter also has a limit value which is settable on 2.12 Reset Input a per-key basis. If a normal-DI counter reaches its terminal The /RST pin can be used to reset the device to simulate a count, the corresponding key is declared to be touched and power-down cycle, in order to bring the device up into a becomes ‘active’. Note that the normal-DI can only be known state should communications with the device be lost. incremented once per complete keyscan cycle, i.e. more The pin is active low, and a low pulse lasting at least 10µs slowly, whereas the fast-DI is incremented ‘on the spot’ must be applied to this pin to cause a reset. without interruption. The reset pin has an internal 30K✡ - 60K✡ resistor. A 2.2µF The net effect of this mechanism is a multiplication of the capacitor plus a diode to Vdd can be connected to this pin as inner and outer counters and hence a highly noise-resistance a traditional reset circuit, but this is not required. sensing method. If the inner limit is set to 5, and the outer to If an external hardware reset is not used, the reset pin may 3, the net effect is 5x3=15 successive threshold crossings to be connected to Vdd or left floating. declare a key as active. 2.13 Spread Spectrum Acquisitions 2.15 Sleep QT60xx0 devices use spread-spectrum burst modulation. The device will sleep whenever possible to conserve power. This has the effect of drastically reducing the possibility of Periodically, the part will wake automatically, scan the matrix, EMI effects on the sensor keys, while simultaneously and return to sleep unless there is activity which demands spreading RF emissions. This feature is hard-wired into the further attention. The part will always return to sleep device and cannot be disabled or modified. automatically once all activity has ceased. The time for which the part will sleep before automatically awakening can be Spread spectrum is configured as a frequency chirp over a configured. wide range of frequencies for robust operation. A new communication with the device while it is asleep will cause it to wake up, service the communication and scan the 2.14 Detection Integrators matrix. At least one full matrix scan is always performed after See also Section 6.5, page 18. waking up and before returning to sleep. The devices feature a detection integration mechanism, which At the end of each matrix scan, the part will return to sleep acts to confirm a detection in a robust fashion. A per-key unless recent activity demands further attention. If there has counter is incremented each time the key has exceeded its been recent activity, the part will perform another complete threshold and stayed there for a number of acquisitions. matrix scan and then attempt to sleep once again. This When this counter reaches a preset limit the key is finally process is repeated indefinitely until the activity stops and the declared to be touched. part returns to sleep. For example, if the limit value is 10, then the device has to Key touch activity will prevent the part from sleeping. The part exceed its threshold and stay there for 10 acquisitions in will not sleep if any touch events were detected at any key in succession without going below the threshold level, before the most recent scan of the key matrix. the key is declared to be touched. If on any acquisition the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. lQ 7 QT60240-ISG R8.06/0906

2.16 Wiring Table 2.2 Pin Listing Pin Function I/O Comments If Unused, Connect To... 1 M_SYNC I Mains Sync input Vdd 2 CHANGE O State change notification Leave open 3 Vss P Supply ground - 4 Vdd P Power, +1.8V to +5V - 5 Vss P Supply ground - 6 Vdd P Power, +1.8V to +5V - 7 X6 O X matrix drive line Leave open 8 X7 O X matrix drive line Leave open 9 LATCH O Shift Register Latch Output Leave open 10 Vref I Ground - 11 S_SYNC O Oscilloscope sync Leave open 12 X0 O X matrix drive line Leave open 13 X1 O X matrix drive line Leave open 14 X2 O X matrix drive line Leave open 15 X3 O X matrix drive line Leave open 16 X4 O X matrix drive line Leave open 17 X5 O X matrix drive line Leave open 18 Vdd P Power, +1.8V to +5V - 19 A1 I Com port address 1 - 20 Vdd P Power, +1.8V to +5V - 21 Vss P Supply ground - 22 A0 I Com port address 0 - 23 Y0B I Y line connection Leave open 24 Y1B I Y line connection Leave open 25 Y2B I Y line connection Leave open 26 SMP O Sample output. - 27 SDA I/O Serial Interface Data - 28 SCL I/O Serial Interface Clock - 29 /RST I Reset low; has internal 30K - 60K pull-up Leave open or Vdd 30 Y0A I Y line connection Leave open 31 Y1A I Y line connection Leave open 32 Y2A I Y line connection Leave open I Input only O Output only, push-pull OD Open drain output I/O Input and output P Ground or power lQ 8 QT60240-ISG R8.06/0906

Figure 2.7 Wiring Diagram See Table 2.2 for further connection information. VDD Vunreg +1.8V to +5V VREG *RX7 r e cfoolmlomwe rnedgeudla vtoarl umeasn fuofra icntpuuret arsnd VDD 1K *RX6 VE output bypass capacitors; keep output 1K *RX5 RI capacitor close to QT60xx0 pins 4 and 6. QT60240 1K *RX4 X D Inf enxot tt op othssoisbele p, iandsd. a 100nF capacitor 10K 10K QT60160 *RX3 1K RIX 1K *RX2 AT SDA 1K *RX1 M I2C SCL 1K *RX0 1K CHANGE * optional - for emission suppression LATCH ** optional - for RF susceptibility improvement MAINS SYNC **RY0 SCOPE SYNC 1K N IN A CS0 4.7nF C **RY1 S Y 1K X RI CS1 4.7nF AT **RY2 M 1K CS2 4.7nF Note: Leave YnA, YnB unconnected RS2 RS1 RS0 if not used 1M 1M 1M Suggested regulator manufacturers: • Toko (XC6215 series) • Seiko (S817 series) • BCDSemi (AP2121 series) lQ 9 QT60240-ISG R8.06/0906

Figure 3.2, page 11 shows a full shift register cycle with keys 3 Interfaces 3, 10 and 15 activated. Key Scan represents the time when the chip is measuring signal from each key. SCL, SDA and 3.1 Introduction LATCH represent their respective signals from the chip. SCL The QT60xx0 can be configured to communicate either over is an active low clock output. SDA is the data output; high if an I2C bus or a shift register type Serial Peripheral Interface the key is in detect and low if it is not. LATCH pulses low (SPI). when the data transfer is complete. The pins A0, A1 are used to configure the type of interface Data output proceeds as soon as the key has been and the I2C address if this mode is used. The modes and I2C processed. Most keys do not get processed during the key addresses are available as shown in Table 3.1 below. scan. If so, these keys are processed and the data is output after the complete key scan. Table 3.1 Interface Details The internal settings of the device in Shift Register mode are A1 A0 Interface the default factory settings found in Table 6.2. This means the Vss Vss Shift Register Vss Vdd I2C Address 7 device will operate with a Burst Length of 48 on all keys, and Vdd Vss I2C Address 17 a Sleep time of 125ms for example. These settings cannot be Vdd Vdd I2C Address 117 changed in this mode. In Shift Register mode, the CHANGE pin is inactive and 3.2 Shift Register Output Mode should be left open. When the option jumpers are both set at Vss, the device disables the I2C interface and instead generates output 3.3 I2C Port suitable for driving a shift register. These devices use I2C communications, in slave mode only. The shift register data is output at pin 27 (SDA). The clock is The QT60160/QT60240 will only respond to the correct output at pin 28 (SCL). The data is clocked on the address match. I2C operating parameters are as follows: positive-going transition of SCL. Data is transferred from the shift registers to the latched outputs on the positive-going Max Data Transfer: 100KHz transition of LATCH. An example shift register connection is Address: 7-bit shown in Figure 3.1. The match address is selected via pins A0 and A1. Table 3.1 The shift register data is output over the duration of a matrix shows the address selections. scan, as each key is being processed, and it is latched at the The QT60160/QT60240 allows multiple byte transmissions to end of the scan. The overall communication time depends on provide a more efficient communication. This is particularly the matrix scan time. useful to retrieve several information bytes at once. Every time the host retrieves data from the QT60160/QT60240, an Table 3.2 Shift Register internal address pointer is incremented. Parameter Legend Units Therefore, the host only needs to write the initial address SCL low pulse width tSCL 500ns min pointer of interest (the lowest address), followed by read SCL high pulse width tSCH 125us min cycles for as many bytes as required. LATCH pulse width tLATCH 500ns min SDA data to SCL clock hold time tSDA-SCL 75us min Figure 3.1 Shift Register Output 74HC595 QT60160/60240 Q0 27 Q2 SDA 28 DS Q3 Outputs, keys 16 to 23 SCL SH_CP Q4 Latch 9 ST_CP Q5 Q6 Q7 /Q7 74HC595 Q0 Q2 DS Q3 Outputs, keys 8 to 15 SH_CP Q4 ST_CP Q5 Q6 Q7 /Q7 74HC595 Q0 Q2 DS Q3 Outputs, keys 0 to 7 SH_CP Q4 ST_CP Q5 Q6 Q7 /Q7 lQ 10 QT60240-ISG R8.06/0906

3.4 CHANGE Pin In Shift Register mode the CHANGE pin does not operate and should be left open. Pin 2 (CHANGE) is an active-high output that can be used to alert the host to key touches or key releases, thus reducing Every key can be individually configured to wake a host the need for wasteful I2C communications. Normally, the host microcontroller upon a touch change; so, a product can wake can simply not bother to communicate with the device, except from sleep when any key state changes, or only when certain when the CHANGE pin goes high. desired keys change state. The configuration is set in the Setups block (Section 6.13) on a key-by-key basis. CHANGE becomes active only when there is a change in key state (either touch or touch release); CHANGE goes low again only when the host performs a read from address 1, the detect status register for all keys on Y0. CHANGE does not self-clear; only an I2C read from location 1 will cause it to clear. It is important to read all three key state addresses to ensure the host has a complete picture of which keys have changed. Figure 3.2 Shift Register Cycle Key Scan Key 0 Key 1 Key 2 Key 21 Key 22 Key 23 Key 0 Key 3 Key 4 Key 23 SCL t t t SCL SCH SDA-SCL SDA LATCH t LATCH lQ 11 QT60240-ISG R8.06/0906

The host initiates the transfer by sending the START 4 Control Commands condition, and follows this by sending the slave address of the device together with the Write-bit. The device sends an 4.1 Introduction ACK. The host then sends the memory address within the The devices feature a set of commands which are used for device it wishes to write to. The device sends an ACK. The control and status reporting. host transmits one or more data bytes; each will be acknowledged by the device. As well as Table 4.1 refer to Table 6.1, page 21 for further details. If the host sends more than one data byte, they will be written to consecutive memory addresses. The device automatically Table 4.1 Memory Map increments the target memory address after writing each data Address Use Access byte. After writing the last data byte, the host should send the STOP condition. 0 Reserved Read 1 Detect status for keys 0 to 7, one bit Read The host should not try to write beyond address 255 because per key the device will not increment the internal memory address Detect status for keys 8 to 15, one bit 2 Read beyond this. per key Detect status for keys 16 to 23, one 3 Read 4.3 Reading Data From the Device bit per key Data for keys 0 to 23, in sequence. The sequence of events required to read data from the device 4 to 123 Read Refer to Table 4.3 for details is shown next. Recalibrate all keys. Write 0x55 to 125 this address location to recalibrate all Write the keys Host to Device Device to Host Setups write-unlock. Write 0x55 130 Write S SLA+W A MemAddress A P S SLA+R A immediately before writing setups 131 to Setups - refer to Table 5.2 for details Read/Write Data 1 A Data 2 A Data n /A P 253 Poll rate: The host can make use of the CHANGE pin output Key to initiate a communication; this will guarantee the optimal S Start condition polling rate. SLA+W Slave address plus write bit A Acknowledge bit If the host cannot make use of the CHANGE pin the poll rate Target memory address within in normal ‘run’ operation should be no faster than once per MemAddress device matrix scan (see Section 7.4, page 23). Typically 10 to 20ms Data Data from device is more than fast enough to extract the key status. Anything P Stop condition faster will not provide new information and will slow down the SLA+R Slave address plus read bit chip operation. Not Acknowledge bit/indicates /A last byte transmission Sending or reading the setup block is an exception, in this case the host can send the data at the maximum possible The host initiates the transfer by sending the START rate. condition, and follows this by sending the slave address of the device together with the Write-bit. The device sends an Run Poll Sequence: In normal run mode the host should ACK. The host then sends the memory address within the limit traffic with a minimalist control structure. The host should device it wishes to read from. The device sends an ACK. just read the three detect status registers (see Figure 4.1, page 14). The host must then send a STOP and a START condition followed by the slave address again but this time Repeated Start: Using repeated start is not allowed and can accompanied by the Read-bit. The device will return an ACK, cause communication failure. followed by a data byte. The host must return either an ACK 4.2 Writing Data to the Device or NACK. If the host returns an ACK, the device will subsequently transmit the data byte from the next address. The sequence of events required to write data to the device is Each time a data byte is transmitted, the device automatically shown next. increments the internal address. The device will continue to return data bytes until the host responds with a NACK. The Host to Device Device to Host host should terminate the transfer by issuing the STOP condition. S SLA+W A MemAddress A Data A P 4.4 Report Detections for All Keys Key S Start condition Address 1: detect status for keys 0 to 7 SLA+W Slave address plus write bit Address 2: detect status for keys 8 to 15 A Acknowledge bit Address 3: detect status for keys 16 to 23 Target memory address within MemAddress Each location indicates all keys in detection, if any, as a device Data Data to be written bitfield; touched keys report as 1’s, untouched or disabled P Stop condition keys report as 0’s. Note: the change pin is cleared on reading address 1. lQ 12 QT60240-ISG R8.06/0906

Table 4.2 Bits for Key Reporting and Numbering There are five bytes of data for each key. The first two are the key’s 16-bit signal, and the second two are the key’s 16-bit Bit Number Address reference. These are followed by the Detect Integrator Count, 7 6 5 4 3 2 1 0 which is a 4-bit value stored in the lower nibble. In the case of 1 7 6 5 4 3 2 1 0 both the signal and reference, the 16-bit values are accessed 2 15 14 13 12 11 10 9 8 as two 8-bit bytes, stored LSB first. 3 23 22 21 20 19 18 17 16 Note: the device should be reset after disabling keys 4.6 Cal All because, if a key was in detect when it was disabled, it could A value of 0x55 must be written to address 125. Upon incorrectly report detect. receiving this command the QT60xx0 will recalibrate all of the 4.5 Raw Data Commands keys. Recalibration will start at the beginning of the next full Addresses 4 to 123 allow data to be read for each key. There matrix scan and last for one scan cycle. are a total of 24 keys and 5 bytes of data per key, yielding a total of 120 addresses. These addresses are read-only. 4.7 Setups The data for the keys is mapped in sequence, starting with The location “Setups write-unlock”, address 130, allows write key 0 at addresses 4 to 8. The data for key 15 is located at access to the setups. Normally the setups are write-protected; addresses 79 to 83, and that for key 23 is located at the write-protection is engaged as soon as a read operation is addresses 119 to 123. Table 4.3 summarizes this. performed at any address. By writing a value of 0x55 to this address, the write-protection is disengaged. This address is located conveniently immediately before the setups so that Table 4.3 Key Data the write protection may be disengaged and the setups written in a single I2C communication sequence. Reading this Address Key # Use address is undefined. 4 0 Signal LSB Addresses 131 to 252 provide read/write access to the 5 0 Signal MSB setups. Details of different setups can be found in Section 6, 6 0 Reference LSB page 17. 7 0 Reference MSB 8 0 DetectCount (lower nibble) When the host is writing a new setup block the values are 9 1 Signal LSB being recorded into EEPROM as they arrive from the host. 10 1 Signal MSB 11 1 Reference LSB 12 1 Reference MSB 13 1 DetectCount (lower nibble) 14 2 Signal LSB 15 2 Signal MSB 16 2 Reference LSB 17 2 Reference MSB 18 2 DetectCount (lower nibble) 19 to 118 3 to 22 Range of values 119 23 Signal LSB 120 23 Signal MSB 121 23 Reference LSB 122 23 Reference MSB 123 23 DetectCount (lower nibble) lQ 13 QT60240-ISG R8.06/0906

Figure 4.1 Power-on or Hardware Reset Flow Chart Power-on or Hardware Reset Recalibrate All Verify Setup Send Correct Send 0x55 to Block Setup Block Incorrect Addr 125 Setup Data Correct Setup Block 'CHANGE' output set Read key status registers Host main Addr: 1, 2 Process and 3 Keys OK Legend Internal Host Processes Key Detection(s) / End of Detection Processing Recalibrate All Comms with QT Send 0x55 to Addr 125 Stuck Key Detected lQ 14 QT60240-ISG R8.06/0906

5 I2C Operation 5.3 START and STOP Conditions The host initiates and terminates a data transmission. The 5.1 Interface Bus transmission is initiated when the host issues a START More detailed information about I2C is available from condition on the bus, and is terminated when the host issues www.i2C-bus.org. Devices are connected onto the I2C bus as a STOP condition. Between START and STOP conditions, the shown in Figure 5.1. Both bus lines are connected to Vdd via bus is considered busy. As shown below, START and STOP pull-up resistors. The bus drivers of all I2C devices must be conditions are signaled by changing the level of the SDA line open-drain type. This implements a wired-AND function which when the SCL line is high. allows any and all devices to drive the bus, one at a time. A low level on the bus is generated when a device outputs a Figure 5.3 START and STOP Conditions zero. Figure 5.1 I2C Interface Bus SDA Vcc SCL Device 1 Device 2 Device 3 Device n R1 R2 START STOP SDA 5.4 Address Packet Format SCL All address packets are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a write operation is performed. When the device Table 5.1 I2C Bus Specifications recognizes that it is being addressed, it will acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address Parameter Unit packet consisting of a slave address and a READ or a Address space 7-bit WRITE bit is called SLA+R or SLA+W, respectively. Maximum bus speed (SCL) 100 kHz Hold time START condition 4µs minimum The most significant bit of the address byte is transmitted Setup time for STOP condition 4µs minimum first. The address sent by the host must be consistent with Bus free time between a STOP and START that selected with the option jumpers. 4.7µs minimum condition Figure 5.4 Address Packet Format 5.2 Transferring Data Bits Each data bit transferred on the bus is accompanied by a Addr MSB Addr LSB R/W ACK pulse on the clock line. The level of the data line must be SDA stable when the clock line is high; The only exception to this rule is for generating START and STOP conditions. SCL Figure 5.2 Data Transfer 1 2 7 8 9 START 5.5 Data Packet Format SDA All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the host generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the SCL reception. An acknowledge (ACK) is signaled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Data Stable Data Stable Receiver leaves the SDA line high, a NACK is signaled. Data Change lQ 15 QT60240-ISG R8.06/0906

5.6 Combining Address and Data Packets Figure 5.6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W Into a Transmission and the STOP. A transmission consists of a START condition, an SLA+R/W, one or more data packets and a STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between the host and the device. The device extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the data transmissions. Figure 5.5 Data Packet Format Data MSB Data LSB ACK Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 7 8 9 STOP, SLA+R/W Data Byte or Next Data Byte Figure 5.6 Packet Transmission Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK SDA SCL 1 2 7 8 9 1 2 7 8 9 START SLA+R/W Data Byte STOP lQ 16 QT60240-ISG R8.06/0906

6.3 Positive Threshold - PTHR 6 Setups The positive threshold is used to provide a mechanism for 6.1 Introduction recalibration of the reference point when a key's signal moves abruptly to the positive. This condition is not The devices calibrate and process all signals using a normal, and usually occurs only after a recalibration when number of algorithms specifically designed to provide for an object is touching the key and is subsequently removed. high survivability in the face of adverse environmental The desire is normally to recover from these events challenges. They provide a large number of processing quickly. options which can be user-selected to implement very flexible, robust keypanel solutions. Positive hysteresis: PHYST is fixed at 12.5 percent of the positive threshold value and cannot be altered. User-defined Setups are employed to alter these algorithms to suit each application. These setups are Positive threshold levels are all fixed at six counts of signal loaded into the device over the I2C serial interfaces. The and cannot be modified. Setups are stored in an onboard EEPROM array. Many setups employ lookup-table value translation. 6.4 Drift Compensation - NDRIFT, PDRIFT Table 6.2, the Setups Lookup Table on page 22 shows all Signals can drift because of changes in Cx and Cs over translation values. The default values are the factory time and temperature. It is crucial that such drift be defaults. compensated, else false detections and sensitivity shifts can occur. Refer to Table 6.1 for all Setups. Drift compensation (Figure 6.1) is performed by making the 6.2 Negative Threshold - NTHR reference level track the raw signal at a slow rate, but only while there is no detection in effect. The rate of adjustment The negative threshold value is established relative to a must be performed slowly, otherwise legitimate detections key’s signal reference value. The threshold is used to could be ignored. The devices drift compensate using a determine key touch when crossed by a negative-going slew-rate limited change to the reference level; the signal swing after having been filtered by the detection threshold and hysteresis values are slaved to this integrator. Larger absolute values of threshold desensitize reference. keys since the signal must travel farther in order to cross the threshold level. Conversely, lower thresholds make When a finger is sensed, the signal falls since the human keys more sensitive. body acts to absorb charge from the cross-coupling between X and Y lines. An isolated, untouched foreign As Cx and Cs drift, the reference point drift-compensates object (a coin, or a water film) will cause the signal to rise for these changes at a user-settable rate; the threshold very slightly due to an enhancement of coupling. This is level is recomputed whenever the reference point moves, contrary to the way most capacitive sensors operate. and thus it also is drift compensated. Once a finger is sensed, the drift compensation The amount of NTHR required depends on the amount of mechanism ceases since the signal is legitimately signal swing that occurs when a key is touched. Thicker detecting an object. Drift compensation only works when panels or smaller key geometries reduce ‘key gain’, i.e. the signal in question has not crossed the negative signal swing from touch, thus requiring smaller NTHR threshold level. values to detect touch. The drift compensation mechanism can be asymmetric; the The negative threshold is programmed on a per-key basis drift-compensation can be made to occur in one direction using the Setup process. See Table 6.2, page 22. faster than it does in the other simply by changing the NDRIFT and PDRIFT Setup parameters. This can be done Negative hysteresis: NHYST is fixed at 12.5 percent of on a per-key basis. the negative threshold value and cannot be altered. Typical values: 3 to 8 (7 to 12 counts of threshold; 4 is internally added to NTHR to generate the threshold). Default value: 6 (10 counts of threshold) Figure 6.1 Thresholds and Drift Compensation Reference Hysteresis Threshold Signal Output lQ 17 QT60240-ISG R8.06/0906

Specifically, drift compensation should be set to compensate If FDIL = 5 and NDIL = 2, the total detection confirmations faster for increasing signals than for decreasing signals. required is 10, even though the device only scanned Decreasing signals should not be compensated quickly, through all keys only twice. since an approaching finger could be compensated for The DI is extremely effective at reducing false detections at partially or entirely before even touching the touch pad. the expense of slower reaction times. In some applications However, an obstruction over the sense pad, for which the a slow reaction time is desirable. The DI can be used to sensor has already made full allowance, could suddenly be intentionally slow down touch response in order to require removed leaving the sensor with an artificially suppressed the user to touch longer to operate the key. reference level and thus become insensitive to touch. In this latter case, the sensor should compensate for the If FDIL = 1, the device functions conventionally. Each object's removal by raising the reference level relatively channel acquires only once in rotation, and the normal quickly. detect integrator counter (NDIL) operates to confirm a detection. Fast-DI is in essence not operational. Drift compensation and the detection time-outs work together to provide for robust, adaptive sensing. The If FDIL m 2, then the fast-DI counter also operates in time-outs provide abrupt changes in reference calibration addition to the NDIL counter. depending on the duration of the signal 'event'. If Signal [ NTHR: The fast-DI counter is incremented NDRIFT Typical values: 9 to 11 towards FDIL due to touch. (2 to 3.3 seconds per count of drift compensation) If Signal >NTHR then the fast-DI counter is cleared due to NDRIFT Default value: 10 lack of touch. (2.5s / count of drift compensation) PDRIFT Typical values: 3 to 5 Disabling a key: If NDIL =0, the key becomes disabled. (0.4 to 0.8 seconds per count of drift compensation; Keys disabled in this way are pared from the burst translation via LUT, page ) sequence in order to improve sampling rates and thus PDRIFT Default value: 4 response time. See Section 2.2, page 3. (0.6s / count of drift compensation) NDIL Typical values: 2, 3 NDIL Default value: 2 6.5 Detect Integrators - NDIL, FDIL FDIL Typical values: 4 to 6 NDIL is used to enable or disable keys and to provide FDIL Default value: 5 signal filtering. To enable a key, its NDIL parameter should be nonzero (ie NDIL=0 disables a key). See Section 2.2. 6.6 Negative Recal Delay - NRD To suppress false detections caused by spurious events If an object unintentionally contacts a key resulting in a like electrical noise, the devices incorporate a 'detection detection for a prolonged interval it is usually desirable to integrator' or DI counter mechanism. A per-key counter is recalibrate the key in order to restore its function, perhaps incremented each time the key has exceeded its threshold after a time delay of some seconds. and stayed there for a number of acquisitions in succession, without going below the threshold level. When The Negative Recal Delay timer monitors such detections; this counter reaches a preset limit the key is finally if a detection event exceeds the timer's setting, the key will declared to be touched. be automatically recalibrated. After a recalibration has taken place, the affected key will once again function If on any acquisition the signal is not seen to exceed the normally even if it is still being contacted by the foreign threshold level, the counter is cleared and the process has object. This feature is set on a per-key basis using the to start from the beginning. NRD setup parameter. The DI mechanism uses two counters. The first is the ‘fast NRD can be disabled by setting it to zero (infinite timeout) DI’ counter FDIL. When a key’s signal is first noted to be in which case the key will never auto-recalibrate during a below the negative threshold, the key enters ‘fast burst’ continuous detection (but the host could still command it). mode. In this mode the burst is rapidly repeated for up to the specified limit count of the fast DI counter. Each key NRD is set using one byte per key, which can range in has its own counter and its own specified fast-DI limit value from 0...254. NRD above 0 is expressed in 0.5s (FDIL), which can range from 1 to 15. When fast-burst is increments. Thus if NRD =120, the timeout value will entered the QT device locks onto the key and repeats the actually be 60 seconds. 255 is not a legal number to use. acquire burst until the fast-DI counter reaches FDIL, or, the NRD Typical values: 20 to 60 (10 to 30 seconds) detection fails beforehand. After this the device resumes NRD Default value: 20 (10 seconds) normal keyscanning and goes on to the next key. NRD Range: 0..254 (∞, 0.5...127s) The ‘Normal DI’ counter counts the number of times the NRD Accuracy: to within ± 250ms fast-DI counter reached its FDIL value. The Normal DI counter can only increment once per complete scan of all 6.7 Positive Recalibration Delay - PRD keys. Only when the Normal DI counter reaches NDIL does the key become formally ‘active’. A recalibration occurs automatically if the signal swings more positive than the positive threshold level. This The net effect of this is that the sensor can rapidly lock condition can occur if there is positive drift but insufficient onto and confirm a detection with many confirmations, positive drift compensation, or, if the reference moved while still scanning other keys. The ratio of ‘fast’ to ‘normal’ negative due to a NRD auto-recalibration, and thereafter counts is completely user-settable via the Setups process. the signal rapidly returned to normal (positive excursion). The total number of required confirmations is equal to FDIL times NDIL. lQ 18 QT60240-ISG R8.06/0906

As an example of the latter, if a foreign object or a finger AKS works for keys that are AKS-enabled anywhere in the contacts a key for period longer than the Negative Recal matrix and is not restricted to physically adjacent keys; the Delay (NRD), the key is by recalibrated to a new lower device has no knowledge of which keys are actually reference level. Then, when the condition causing the physically adjacent. When enabled for a key, adjacent key negative swing ceases to exist (e.g. the object is removed) suppression causes detections on that key to be the signal suddenly swings positive to its normal reference. suppressed if any other AKS-enabled key in the panel has a more negative signal deviation from its reference. It is almost always desirable in these cases to cause the key to recalibrate quickly so as to restore normal touch This feature does not account for varying key gains (burst operation. The time required to do this is governed by length) but ignores the actual negative detection threshold PRD. In order for this to work, the signal must rise through setting for the key. If AKS-enabled keys in a panel have the positive threshold level PTHR continuously for the PRD different sizes, it may be necessary to reduce the gains of period. larger keys relative to smaller ones to equalize the effects of AKS. The signal threshold of the larger keys can be After the PRD interval has expired and the altered to compensate for this without causing problems autorecalibration has taken place, the affected key will with key suppression. once again function normally. Adjacent key suppression works to augment the natural PRD Accuracy: to within ± 50ms moisture suppression of narrow gated transfer switches Delay: PRD is fixed at 200ms for all keys, creating a more robust sensing method. and cannot be altered. AKS Default value: 0 (Off) 6.8 Burst Length - BL 6.10 Oscilloscope Sync - SSYNC The signal gain for each key is controlled by circuit parameters as well as the burst length. Pin 11 (S_SYNC) can output a positive pulse oscilloscope sync that brackets the burst of a selected key. More than The burst length is simply the number of times the one burst can output a sync pulse as determined by the charge-transfer (‘QT’) process is performed on a given key. Setups parameter SSYNC for each key. Each QT process is simply the pulsing of an X line once, with a corresponding Y line enabled to capture the This feature is invaluable for diagnostics; without it, resulting charge passed through the key’s capacitance Cx. observing signals clearly on an oscilloscope for a particular burst is very difficult. QT60xx0 devices use a fixed number of QT cycles which are executed in burst mode. There can be up to 64 QT This function is supported in Quantum’s QmBtn PC cycles in a burst, in accordance with the list of permitted software. values shown in Table 6.2, page 22. SSYNC Default value: 0 (Off) Increasing burst length directly affects key sensitivity. This occurs because the accumulation of charge in the charge 6.11 Mains Sync - MSYNC integrator is directly linked to the burst length. The burst The Mains Sync feature uses M_SYNC pin 1. length of each key can be set individually, allowing for direct digital control over the signal gains of each key External fields can cause interference leading to false individually. detections or sensitivity shifts. Most fields come from AC power sources. RFI noise sources are heavily suppressed Apparent touch sensitivity is also controlled by the by the low impedance nature of the QT circuitry itself. Negative Threshold level (NTHR). Burst length and NTHR interact; normally burst lengths should be kept as short as Noise such as from 50Hz or 60Hz fields becomes a possible to limit RF emissions, but NTHR should be kept problem if it is uncorrelated with acquisition signal above 6 to reduce false detections due to external noise. sampling; uncorrelated noise can cause aliasing effects in The detection integrator mechanism also helps to prevent the key signals. To suppress this problem the M_SYNC false detections. input allows bursts to synchronize to the noise source. BL Typical values: 1, 2 (32, 48 pulses / burst) The noise synchronization operating mode is set by BL Default value: 2 (48 pulses / burst) parameter MSYNC in Setups. BL Possible values: 0, 1, 2, 3 (16, 32, 48, 64 The synchronization occurs only at the burst for the lowest pulses/burst) numbered enabled key in the matrix. The device waits for the synchronization signal for up to 100ms after the end of 6.9 Adjacent Key Suppression - AKS a preceding full matrix scan, then when a negative These devices incorporate adjacent key suppression synchronization edge is received, the matrix is scanned in (‘AKS’ - patent pending) that can be selected on a per-key its entirety again. basis. AKS permits the suppression of multiple key The sync signal drive should be a buffered logic signal, or presses based on relative signal strength. This feature perhaps a diode-clamped signal, but never a raw AC signal assists in solving the problem of surface moisture which from the mains. The device will synchronize to the falling can bridge a key touch to an adjacent key, causing multiple edge. key presses. This feature is also useful for panels with tightly spaced keys, where a fingertip might inadvertently activate an adjacent key. lQ 19 QT60240-ISG R8.06/0906

Since noise synchronization is highly effective and In Shift Register mode, the WAKE function is enabled for inexpensive to implement, it is strongly advised to take all keys, however the CHANGE pin does not function in advantage of it anywhere there is a possibility of this mode. The AWAKE timeout in Shift Register mode is encountering low frequency (i.e. 50/60Hz) electric fields. 2.5s (note default setting of AWAKE parameter in Table Quantum’s QmBtn software can show such noise effects 6.2). on signals, and will hence assist in determining the need to WAKE Default value: 1 (On) make use of this feature. WAKE Possible range: 0, 1 (Off, On) If the synchronization feature is enabled but no 6.14 Awake Timeout - AWAKE synchronization signal exists, the sensor will continue to operate but with a delay of 100ms before the start of each After each matrix scan, the part will automatically go to matrix scan, and hence will have a slow response time. sleep whenever possible to conserve power, unless there has been a key state change on a key with the WAKE SYNC Default value: 0 (Off) feature enabled (Section 6.13), in which case the part will SYNC Possible range: 0, 1 (Off, On) wake up into ‘fast mode’ which has no sleep states and operates at the fastest possible speed. The AWAKE 6.12 Sleep Duration - SLEEP timeout feature determines how long the device will remain The QT60xx0 is designed to sleep as much as possible to in this mode from the last key state change. conserve power. Periodically, the part wakes automatically, Subsequent key state changes further prolong the AWAKE scans the keyboard matrix and then returns to sleep. The interval. In other words, once the part has been awakened length of time the part sleeps before automatically waking by a change on a WAKE enabled key, the key response up can be configured to one of eight different values, via a time will be fast for as long as the keyboard remains in look-up table. The look-up table index must be written to use. Once key activity lapses for a period longer than the the setups (see Table 6.2, page 22). AWAKE timeout, the part will return to sleep mode. Note that when a key changes state, the CHANGE pin can The AWAKE period can be configured to a value between be made to go active and the device can go into ‘fast 100ms and 25.5s, in increments of 100ms. mode’ automatically if the WAKE feature is enabled on that key (next section). AWAKE default value: 25 (2.5s) AWAKE range: 1...255 (100ms...25.5s) SLEEP default value: 3 (125ms) AWAKE Timeout accuracy: to within ±50ms SLEEP range: 0...7 (16ms...2s) 6.15 Drift Hold Time - DHT 6.13 Wake on Key Touch - WAKE Drift Hold Time (DHT) is used to restrict drift on all keys The device can be configured for full time wake-up from while one or more keys are activated. DHT defines the Sleep mode when specific keys are touched or released length of time the drift is halted after a key detection. using this feature, in order to improve response time after each key state change. Once awake the key will remain This feature is particularly useful in cases of high-density awake until the AWAKE function times out (Section 6.14). keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore Also this feature makes the CHANGE pin go active on a create a sensitivity shift, and ultimately inhibit any touch key touch or key release (Section 3.4). detection. Each key has its own WAKE configuration bit so that any DHT can be configured to a value of between 100ms and combination of keys can be configured for this function. 25.5s, in increments of 100ms. Setting this parameter to 0 The time the part will remain awake after any key state will disable this feature and the drift compensation on any change can also be configured in the Setup block (AWAKE key will not be dependent on the state of other keys. feature, next section). DHT default value: 10 (1s) Any key, even one where the WAKE feature is not DHT range: 0...255 (Off, 100ms...25.5s) enabled, will prolong the time the part remains awake once the part is awake lQ 20 QT60240-ISG R8.06/0906

6.16 Setups Block Table 6.1 Setups Table Setups data is sent from the host to the QT using the I2C interface. The setups block is memory mapped onto this interface. Thus each setup can be accessed by reading/writing the appropriate address. Setups can be accessed individually or as a block. Before writing to any setup, an unlock code (value 0x55) must be written to the setups write unlock address (130). Refer also to Table 6.2, page 22 for further details, and all of Section 6. Key Default Item Address Bytes Parameter Symbol Valid Range Bits Description Page Scope Value Neg thresh NTHR NTHR = 0...15 4 1 6 Lower nibble = Neg Threshold - take operand and add 4 to get value 17 1 131...154 24 Neg Drift Comp NDRIFT NDRIFT = 0...15 4 1 10 Upper nibble = Neg Drift comp - via Lookup Table (LUT) (Table 6.2, page 22) 17 2 155...178 24 Pos Drift Comp PDRIFT PDRIFT = 0...15 4 1 4 Upper nibble = Pos Drift comp - via LUT (Table 6.2, page 22) 17 Lower nibble = Normal DI Limit, values same as operand (0 = disabled burst) Normal DI Limit NDIL NDIL = 0...15 4 1 2 3 179...202 24 For QT60160, only the first 16 locations are set to 2, the last eight are set to 0 18 Fast DI Limit FDIL FDIL = 0...15 4 1 5 Upper nibble = Fast DI Limit, values same as operand (0 does not work) Range is in 0.5 sec increments; 0 = infinite, default = 10s 4 203...226 24 Neg recal delay NRD 0...254 8 1 20 18 Range is {infinite, 0.5...127s}; 255 is illegal to use Wake On Touch WAKE WAKE = 0,1 1 1 1 Bit 3 = WAKE, 1 - enabled 20 Burst Length BL BL = 0...3 2 1 2 Bits 5, 4 = BL, via LUT (Table 6.2 page 22), default = 48 19 5 227...250 24 AKS AKS AKS = 0,1 1 1 0 Bit 6 = AKS, 1 - enabled 19 Scope Sync SSYNC SSYNC = 0,1 1 1 0 Bit 7 = Scope sync, 1 = enabled 19 Sleep Duration SLEEP SLEEP = 0...7 3 24 3 Bits 2,1,0 = Sleep Duration, 8 values via LUT, default = 125ms 20 6 251 1 Mains Sync MSYNC MSYNC = 0,1 1 24 0 Bits 6 = Mains sync, negative edge, 1 = enabled, default = off 19 7 252 1 Awake Timeout AWAKE 1...255 8 24 25 Range is in 100ms increments; 1 = 100ms. Default = 2.5s. 0 is illegal to use 20 8 253 1 Drift Hold Time DHT 0...255 8 24 10 Range is in 100ms increments; 0 = disable, 1 = 100ms, default = 1s 20 lQ 21 QT60240-ISG R8.06/0906

Table 6.2 Setups Lookup Table Typical values: For most touch applications, use the values shown in the outlined cells. Bold text items indicate default settings. The number to send to the QT is the number in the leftmost column (0...15), not numbers from within the table. The QT uses lookup tables to translate the 0...15 to the parameters for each function. NRD is an exception: it can range from 0...254 which is translated from 1 = 0.5s to 254 = 127s, in increments of 0.5s, with zero = infinity. 255 is illegal. AWAKE is an exception: it can range from 1...255 which is translated from 1 = 0.1s to 255 = 25.5s, in increments of 0.1s. Zero is illegal. DHT is an exception: it can range from 0...255 which is translated from 1 = 0.1s to 255 = 25.5s, in increments of 0.1s. Zero will disable DHT. Parameter Index Number NTHR NDRIFT PDRIFT NDIL FDIL NRD BL SLEEP AWAKE DHT WAKE AKS SSYNC MSYNC counts secs secs counts counts secs Pulses ms secs secs (Page 17) (Page 17) (Page 17) (Page 18) (Page 18) (Page 18) (Page 20) (Page 19) (Page 19) (Page 19) (Page 20) (Page 19) (Page 20) (Page 20) Per key Per key Per key Per key Per key Per key Per key Per key Per key Per key Global Global Global Global 0 4 0.1 0.1 Key off unused 0 (Infinite) Off 16 - Off - - Off - 16 - Off - unused Off 1 5 0.2 0.2 1 1 0.5 .. 127s - On - 32 On On 32 On 0.1...25.5s 0.1...25.5s 2 6 0.3 0.3 - 2 - 2 Default= - 48 - 64 Default= Default= 3 7 0.4 0.4 3 3 10s 64 -125- 2.5s 1s 4 8 0.6 - 0.6 - 4 4 250 5 9 0.8 0.8 5 - 5 - 500 6 - 10 - 1 1 6 6 1,000 7 11 1.2 1.2 7 7 2,000 8 12 1.5 1.5 8 8 9 13 2 2 9 9 10 14 - 2.5 - 2.5 10 10 11 15 3.3 3.3 11 11 12 16 4.5 4.5 12 12 13 17 6 6 13 13 14 18 7.5 7.5 14 14 15 19 10 10 15 15 lQ 22 QT60240-ISG R8.06/0906

7 Specifications 7.1 Absolute Maximum Electrical Specifications Operating temp................................................................................... -40OC to +85OC Storage temp.................................................................................... -55OC to +125OC Vdd.................................................................................................-0.5 to +5.5V Max continuous pin current, any control or drive pin.......................................................... ±10mA Short circuit duration to ground, any pin......................................................................infinite Short circuit duration to Vdd, any pin........................................................................ infinite Voltage forced onto any pin............................................................... -0.6V to (Vdd + 0.6) Volts EEPROM setups maximum writes.............................................................. 100,000 write cycles 7.2 Recommended Operating Conditions Vdd...............................................................................................+1.8V to 5.25V Note: the devices will run at a minimum of 1.62V. Supply ripple+noise........................................................................................ ±5mV Cx transverse load capacitance per key................................................................... 2 to 20pF 7.3 DC Specifications Vdd = 5.0V, Cs = 4.7nF, Rs = 470K; Ta = recommended range, unless otherwise noted Parameter Description Min Typ Max Units Notes 1.02 Vdd = 1.8V Average supply current, Iddr 2.34 mA Vdd = 3.3V running 4.60 Vdd = 5.0V 3 Vdd = 1.8V Average supply current, Idds 4 µA Vdd = 3.3V sleeping 6 Vdd = 5.0V Vil Low input logic level 0.2Vdd V 1.8V <Vdd <5V Vhl High input logic level 0.6Vdd V 1.8V <Vdd <5V Vol Low output voltage 0.2 V Voh High output voltage 4.2 V Iil Input leakage current 1 µA Ar Acquisition resolution 10 bits Rrst Internal /RST pullup resistor 60 k✡ 7.4 Timing Specifications Parameter Description Min Typ Max Units Notes 270 µs BL = 16 380 BL = 32 TBS Burst spacing 490 BL = 48 600 BL = 64 Fc Burst center frequency 155 kHz Fm Burst modulation, percentage ±10 % lQ 23 QT60240-ISG R8.06/0906

7.5 Power Consumption Table 7.1 Average Current Consumption Test condition: BL = 48, 16 or 24 keys enabled (see appropriate column) Sleep Idd Typical (mA) Voltage (V) Setting (ms) 24 keys 16 keys 1.8 0.480 0.360 3.3 16 1.050 0.840 5.0 1.900 1.550 1.8 0.300 0.250 3.3 32 0.670 0.540 5.0 1.220 0.910 1.8 0.170 0.150 3.3 64 0.350 0.310 5.0 0.730 0.550 1.8 0.090 0.080 3.3 125 0.220 0.170 5.0 0.400 0.300 1.8 0.050 0.048 3.3 250 0.120 0.100 5.0 0.240 0.160 1.8 0.043 0.040 3.3 500 0.090 0.060 5.0 0.160 0.110 1.8 0.040 0.038 3.3 1000 0.080 0.053 5.0 0.130 0.100 1.8 0.039 0.037 3.3 2000 0.075 0.050 5.0 0.120 0.095 The formula to find the average current is: Idd = (current sleeping x sleep period) + (current running x (burst spacing x number of keys enabled)) sleep period + (burst spacing x number of keys enabled) Idd = (Idds x Tsleep) + (Iddr x (TBS x KE)) Note: there may be more than one instance of (TBS x KE) Tsleep + (TBS x KE) (see example below) Where: Idd = average current (mA) Idds = current when sleeping (mA) (Section 7.3) Tsleep = sleep period (ms) (Table 6.2) Iddr = current when running (mA) (Section 7.3) TBS = burst spacing1 (ms) (Section 7.4) KE = number of keys enabled1 1 if more than one burst spacing is used then each must be included in the calculation. Example: Conditions: Vdd = 1.8V, 10 keys BL = 32, 14 keys BL = 16, Tsleep = 125ms Idd = (0.003 x 125) + (1.02 x ((0.38 x 10) + (0.27 x 14))) = 0.06115mA = 61.15µA 125 + ((0.38 x 10) + (0.27 x 14)) lQ 24 QT60240-ISG R8.06/0906

7.6 Mechanical Dimensions B F PIN 1 e C G DimensionsinMillimeters D E Symbol Minimum Nominal Maximum A 0.80 0.90 1.00 A1 0.02 0.05 A2 0.65 1.00 A3 0.20REF B 5.00BSC C 5.00BSC D 0.18 0.23 0.30 A2 E 0.30 0.40 0.50 A A3 F 2.95 3.10 3.25 G 2.95 3.10 3.25 e 0.50BSC A1 7.7 Marking MLF Part Number Keys Marking QT60160-ISG 16 6160 QT60240-ISG 24 6240 7.8 Moisture Sensitivity Level (MSL) MSL Rating Peak Body Temperature Specifications MSL3 260OC IPC/JEDEC J-STD-020C lQ 25 QT60240-ISG R8.06/0906

lQ Copyright © 2006 QRG Ltd. All rights reserved Patented and patents pending Corporate Headquarters 1 Mitchell Point Ensign Way, Hamble SO31 4RF Great Britain Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939 www.qprox.com North America 651 Holiday Drive Bldg. 5 / 300 Pittsburgh, PA 15220 USA Tel: 412-391-7367 Fax: 412-291-1015 This device is covered under one or more United States and corresponding international patents. QRG patent numbers can be found online at www.qprox.com. Numerous further patents are pending, which may apply to this device or the applications thereof. The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order acknowledgement. QRG trademarks can be found online at www.qprox.com. QRG products are not suitable for medical (including lifesaving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customers are entirely responsible for their products and applications which incorporate QRG's products. Development Team: Samuel Brunet, Dr. Tim Ingersoll, Matthew Trend

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