18F8680.book Page 1 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module High-Performance RISC CPU: Analog Features: • Source code compatible with the PIC16 and • Up to 16-channel, 10-bit Analog-to-Digital PIC17 instruction sets Converter module (A/D) with: • Linear program memory addressing to 2 Mbytes - Fast sampling rate • Linear data memory addressing to 4096bytes - Programmable acquisition time • 1Kbyte of data EEPROM - Conversion available during Sleep • Up to 10 MIPs operation: • Programmable 16-level Low-Voltage Detection - DC – 40 MHz osc./clock input (LVD) module: - 4 MHz-10 MHz osc./clock input with PLL active - Supports interrupt on Low-Voltage Detection • 16-bit wide instructions, 8-bit wide data path • Programmable Brown-out Reset (BOR) • Priority levels for interrupts • Dual analog comparators: • 31-level, software accessible hardware stack - Programmable input/output configuration • 8 x 8 Single-Cycle Hardware Multiplier ECAN Module Features: External Memory Interface • Message bit rates up to 1 Mbps (PIC18F8X8X Devices Only): • Conforms to CAN 2.0B ACTIVE Specification • Address capability of up to 2Mbytes • Fully backward compatible with PIC18XXX8 CAN • 16-bit interface modules • Three modes of operation: Peripheral Features: - Legacy, Enhanced Legacy, FIFO • High current sink/source 25 mA/25 mA • Three dedicated transmit buffers with prioritization • Four external interrupt pins • Two dedicated receive buffers • Timer0 module: 8-bit/16-bit timer/counter • Six programmable receive/transmit buffers • Timer1 module: 16-bit timer/counter • Three full 29-bit acceptance masks • Timer2 module: 8-bit timer/counter • 16 full 29-bit acceptance filters with dynamic association • Timer3 module: 16-bit timer/counter • DeviceNet™ data byte filter support • Secondary oscillator clock option – Timer1/Timer3 • Automatic remote frame handling • One Capture/Compare/PWM (CCP) module: • Advanced Error Management features - Capture is 16-bit, max. resolution 6.25 ns Special Microcontroller Features: (TCY/16) - Compare is 16-bit, max. resolution 100 ns (TCY) • 100,000 erase/write cycle Enhanced Flash - PWM output: PWM resolution is 1 to 10-bit program memory typical • Enhanced Capture/Compare/PWM (ECCP) module: • 1,000,000 erase/write cycle Data EEPROM - Same Capture/Compare features as CCP memory typical - One, two or four PWM outputs • 1-second programming time - Selectable polarity • Flash/Data EEPROM Retention: > 40 years - Programmable dead time • Self-reprogrammable under software control - Auto-shutdown on external event • Power-on Reset (POR), Power-up Timer (PWRT) - Auto-restart and Oscillator Start-up Timer (OST) • Master Synchronous Serial Port (MSSP) module • Watchdog Timer (WDT) with its own On-Chip with two modes of operation: RC Oscillator - 3-wire SPI (supports all 4 SPI modes) • Programmable code protection - I2C™ Master and Slave mode • Power saving Sleep mode • Enhanced Addressable USART module: • Selectable oscillator options including: - Supports RS-232, RS-485 and LIN 1.2 - Software enabled 4x Phase Lock Loop (of - Programmable wake-up on Start bit primary oscillator) - Auto-baud detect - Secondary Oscillator (32 kHz) clock input • Parallel Slave Port (PSP) module • In-Circuit Serial Programming™ (ICSP™) via two pins • MPLAB® In-Circuit Debug (ICD) via two pins  2003-2013 Microchip Technology Inc. DS30491D-page 1

18F8680.book Page 2 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 CMOS Technology: • Low-power, high-speed Flash technology • Fully static design • Wide operating voltage range (2.0V to 5.5V) • Industrial and Extended temperature ranges Program Memory Data Memory CCP/ MSSP 10-bit ECAN/ Timers Device Bytes #I Snsintrgulec-tWioonrsd (SbRytAeMs) E(EbPyRteOs)M I/O A/D (ch) (EPCWCMP) SPI MaI2sCter AUSART 8-bit/16-bit EMA PIC18F6585 48K 24576 3328 1024 53 12 1/1 Y Y Y/Y 2/3 N PIC18F6680 64K 32768 3328 1024 53 12 1/1 Y Y Y/Y 2/3 N PIC18F8585 48K 24576 3328 1024 69 16 1/1 Y Y Y/Y 2/3 Y PIC18F8680 64K 32768 3328 1024 69 16 1/1 Y Y Y/Y 2/3 Y DS30491D-page 2  2003-2013 Microchip Technology Inc.

18F8680.book Page 3 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Pin Diagrams 64-Pin TQFP CS P1C P1B(1)CCP2 PSP0 PSP1 PSP2 PSP3 PSP4 PSP5 PSP6 PSP7 RE2/ RE3 RE4 RE5/ RE6/ RE7/ RD0/ VDD VSS RD1/ RD2/ RD3/ RD4/ RD5/ RD6/ RD7/ 64636261 605958575655545352515049 RE1/WR 1 48 RB0/INT0 RE0/RD 2 47 RB1/INT1 RG0/CANTX1 3 46 RB2/INT2 RG1/CANTX2 4 45 RB3/INT3 RG2/CANRX 5 44 RB4/KBI0 RG3 6 43 RB5/KBI1/PGM RG5/MCLR/VPP 7 PIC18F6X8X 42 RB6/KBI2/PGC RG4/P1D 8 41 VSS VSS 9 40 OSC2/CLKO/RA6 VDD 10 39 OSC1/CLKI RF7/SS 11 38 VDD RF6/AN11/C1IN- 12 37 RB7/KBI3/PGD RF5/AN10/C1IN+/CVREF 13 36 RC5/SDO RF4/AN9/C2IN- 14 35 RC4/SDI/SDA RF3/AN8/C2IN+ 15 34 RC3/SCK/SCL RF2/AN7/C1OUT 16 33 RC2/CCP1/P1A 17181920212223242526 272829303132 RF1/AN6/C2OUT RF0/AN5 AVDD AVSSRA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0VSS VDD RA5/AN4/LVDIN RA4/T0CKI(1)RC1/T1OSI/CCP2 RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT Note 1: CCP2 pin placement depends on CCP2MX setting.  2003-2013 Microchip Technology Inc. DS30491D-page 3

18F8680.book Page 4 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Pin Diagrams (Continued) 68-Pin PLCC (1)20 1234567 S 1C1BCPSP SPSPSPSPSPSPSP C PPCP PPPPPPP RE2/RE3RE4RE5/RE6/RE7/RD0/VDDN/CVSSRD1/RD2/RD3/RD4/RD5/RD6/RD7/ 9 8 7 6 5 4 3 2 1 6867666564636261 RE1/WR 10 60 RB0/INT0 RE0/RD 11 Top View 59 RB1/INT1 RG0/CANTX1 12 58 RB2/INT2 RG1/CANTX2 13 57 RB3/INT3 RG2/CANRX 14 56 RB4/KBI0 RG3 15 55 RB5/KBI1/PGM RG5/MCLR/VPP 16 54 RB6/KBI2/PGC RG4/P1D 17 53 VSS N/C 18 PIC18F6X8X 52 N/C VSS 19 51 OSC2/CLKO/RA6 VDD 20 50 OSC1/CLKI RF7/SS 21 49 VDD RF6/AN11/C1IN- 22 48 RB7/KBI3/PGD RF5/AN10/C1IN+/CVREF 23 47 RC5/SDO RF4/AN9/C2IN- 24 46 RC4/SDI/SDA RF3/AN8/C2IN+ 25 45 RC3/SCK/SCL RF2/AN7/C1OUT 26 44 RC2/CCP1/P1A 2728293031323334353637383940414243 RF1/AN6/C2OUTRF0/AN5AVDDAVSSRA3/AN3/V+REFRA2/AN2/V-REFRA1/AN1RA0/AN0N/CVSS VDDRA5/AN4/LVDINRA4/T0CKI(1)C1/T1OSI/CCP2C0/T1OSO/T13CKIRC6/TX/CKRC7/RX/DT RR Note 1: CCP2 pin placement depends on CCP2MX setting. DS30491D-page 4  2003-2013 Microchip Technology Inc.

18F8680.book Page 5 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Pin Diagrams (Continued) 80-Pin TQFP 5 RH1/A17 RH0/A16RE2/CS/AD10 RE3/AD11 RE4/AD12(3)RE5/AD13/P1C(3)RE6/AD14/P1B(2)RE7/CCP2/AD1(1)RD0/PSP0/AD0 VDD VSS(1)RD1/PSP1/AD1(1)RD2/PSP2/AD2(1)RD3/PSP3/AD3(1)RD4/PSP4/AD4(1)RD5/PSP5/AD5(1)RD6/PSP6/AD6(1)RD7/PSP7/AD7 RJ0/ALE RJ1/OE 807978777675 7473727170696867666564636261 RH2/A18 1 60 RJ2/WRL RH3/A19 2 59 RJ3/WRH RE1/WR/AD9 3 58 RB0/INT0 RE0/RD/AD8 4 57 RB1/INT1 RG0/CANTX1 5 56 RB2/INT2 RG1/CANTX2 6 55 RB3/INT3/CCP2(2) RG2/CANRX 7 54 RB4/KBI0 RG3 8 53 RB5/KBI1/PGM RG5/MCLR/VPP 9 52 RB6/KBI2/PGC RG4/P1D 10 PIC18F8X8X 51 VSS VSS 11 50 OSC2/CLKO/RA6 VDD 12 49 OSC1/CLKI RF7/SS 13 48 VDD RF6/AN11/C1IN- 14 47 RB7/KBI3/PGD RF5/AN10/C1IN+/CVREF 15 46 RC5/SDO RF4/AN9/C2IN- 16 45 RC4/SDI/SDA RF3/AN8/C2IN+ 17 44 RC3/SCK/SCL RF2/AN7/C1OUT 18 43 RC2/CCP1/P1A RH7/AN15/P1B(3) 19 42 RJ7/UB RH6/AN14/P1C(3) 20 41 RJ6/LB 212223242526272829303132 3334353637383940 RH5/AN13 RH4/AN12 RF1/AN6/C2OUT RF0/AN5 AVDD AVSSRA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0VSS VDD RA5/AN4/LVDIN RA4/T0CKI(2)RC1/T1OSI/CCP2 RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RJ4/BA0 RJ5/CE Note 1: PSP is available only in Microcontroller mode. 2: CCP2 pin placement depends on CCP2MX and Processor mode settings. 3: P1B and P1C pin placement depends on ECCPMX setting.  2003-2013 Microchip Technology Inc. DS30491D-page 5

18F8680.book Page 6 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Oscillator Configurations............................................................................................................................................................23 3.0 Reset..........................................................................................................................................................................................33 4.0 Memory Organization.................................................................................................................................................................51 5.0 Flash Program Memory..............................................................................................................................................................83 6.0 External Memory Interface.........................................................................................................................................................93 7.0 Data EEPROM Memory...........................................................................................................................................................101 8.0 8 x 8 Hardware Multiplier..........................................................................................................................................................107 9.0 Interrupts..................................................................................................................................................................................109 10.0 I/O Ports...................................................................................................................................................................................125 11.0 Timer0 Module.........................................................................................................................................................................155 12.0 Timer1 Module.........................................................................................................................................................................159 13.0 Timer2 Module.........................................................................................................................................................................162 14.0 Timer3 Module.........................................................................................................................................................................164 15.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................167 16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................175 17.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................189 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART)..................................................................229 19.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................249 20.0 Comparator Module..................................................................................................................................................................259 21.0 Comparator Voltage Reference Module...................................................................................................................................265 22.0 Low-Voltage Detect..................................................................................................................................................................269 23.0 ECAN Module...........................................................................................................................................................................275 24.0 Special Features of the CPU....................................................................................................................................................345 25.0 Instruction Set Summary..........................................................................................................................................................365 26.0 Development Support...............................................................................................................................................................407 27.0 Electrical Characteristics..........................................................................................................................................................413 28.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................449 29.0 Packaging Information..............................................................................................................................................................465 Appendix A: Revision History.............................................................................................................................................................469 Appendix B: Device Differences.........................................................................................................................................................469 Appendix C: Conversion Considerations...........................................................................................................................................470 Appendix D: Migration from Mid-Range to Enhanced Devices..........................................................................................................470 Appendix E: Migration from High-End to Enhanced Devices.............................................................................................................471 Index..................................................................................................................................................................................................473 On-Line Support.................................................................................................................................................................................487 Systems Information and Upgrade Hot Line......................................................................................................................................487 Reader Response..............................................................................................................................................................................488 PIC18F6585/8585/6680/8680 Product Identification System............................................................................................................489 DS30491D-page 6  2003-2013 Microchip Technology Inc.

18F8680.book Page 7 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products.  2003-2013 Microchip Technology Inc. DS30491D-page 7

18F8680.book Page 8 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 8  2003-2013 Microchip Technology Inc.

18F8680.book Page 9 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 1.0 DEVICE OVERVIEW All other features for devices in the PIC18F6585/8585/6680/8680 family are identical. This document contains device specific information for These are summarized in Table1-1. the following devices: Block diagrams of the PIC18F6X8X and PIC18F8X8X • PIC18F6585 • PIC18F8585 devices are provided in Figure1-1 and Figure1-2, • PIC18F6680 • PIC18F8680 respectively. The pinouts for these device families are listed in Table1-2. PIC18F6X8X devices are available in 64-pin TQFP and 68-pin PLCC packages. PIC18F8X8X devices are available in the 80-pin TQFP package. They are differentiated from each other in four ways: 1. Flash program memory (48Kbytes for PIC18FX585 devices, 64Kbytes for PIC18FX680) 2. A/D channels (12 for PIC18F6X8X devices, 16 for PIC18F8X8X) 3. I/O ports (7 on PIC18F6X8X devices, 9 on PIC18F8X8X) 4. External program memory interface (present only on PIC18F8X8X devices) TABLE 1-1: PIC18F6585/8585/6680/8680 DEVICE FEATURES Features PIC18F6585 PIC18F6680 PIC18F8585 PIC18F8680 Operating Frequency DC–40MHz DC–40MHz DC–40MHz DC–40MHz DC–25MHzw/EMA DC–25MHzw/EMA Program Memory (Bytes) 48K 64K 48K (2 MB EMA) 64K (2 MB EMA) Program Memory (Instructions) 24576 32768 24576 32768 Data Memory (Bytes) 3328 3328 3328 3328 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 External Memory Interface No No Yes Yes Interrupt Sources 29 29 29 29 I/O Ports Ports A-G Ports A-G Ports A-H, J Ports A-H, J Timers 4 4 4 4 Capture/Compare/PWM Module 1 1 1 1 Enhanced Capture/Compare/PWM 1 1 1 1 Module Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced AUSART, Enhanced AUSART, Enhanced AUSART, Enhanced AUSART, ECAN ECAN ECAN ECAN Parallel Communications PSP PSP PSP(1) PSP(1) 10-bit Analog-to-Digital Module 12 input channels 12 input channels 16 input channels 16 input channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Programmable Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions Package 64-pin TQFP, 64-pin TQFP, 80-pin TQFP 80-pin TQFP 68-pin PLCC 68-pin PLCC Note 1: PSP is only available in Microcontroller mode.  2003-2013 Microchip Technology Inc. DS30491D-page 9

18F8680.book Page 10 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 1-1: PIC18F6X8X BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 21 Table Pointer<21> Data Latch RA1/AN1 RA2/AN2/VREF- 8 8 Data RAM RA3/AN3/VREF+ 21 inc/dec logic (3328 bytes) RA4/T0CKI RA5/AN4/LVDIN Address Latch OSC2/CLKO/RA6 21 PCLATUPCLATH 12 PORTB Address<12> RB2/INT2:RB0/INT0 PCU PCH PCL RB3/INT3 Program Counter 4 12 4 RB4/KBI0 Address Latch BSR FSR0 Bank0, F RB5/KBI1/PGM Program Memory 31 Level Stack FSR1 RRBB67//KKBBII23//PPGGCD (48Kbytes) FSR2 12 Data Latch inc/dec PORTC Decode logic RC0/T1OSO/T13CKI Table Latch RC1/T1OSI/CCP2(1) RC2/CCP1/P1A 16 8 RC3/SCK/SCL ROM Latch RC4/SDI/SDA RC5/SDO RC6/TX/CK IR RC7/RX/DT PORTD 8 RD7/PSP7:RD0/PSP0 PRODH PRODL PORTE IDnCestcoroundtcretoio l&n 3 8 x 8 Multiply 8 RREE01//RWDR RE2/CS BITOP W RE3 OOSSCC21//CCLLKKOI/RA6 PoTwimere-rup 8 8 8 RREE54/P1C GeTnimeriantgion StaOrts-cuiplla Ttoimrer 8 RREE67//PC1CBP2(1) Power-on ALU<8> PORTF Reset RF0/AN5 Watchdog 8 RF1/AN6/C2OUT Precision Timer RF2/AN7/C1OUT Band Gap Brown-out RF3/AN8/C2IN+ Reference Reset RF4/AN9/C2IN- Test Mode RF5/AN10/C1IN+/CVREF Select RF6/AN11/C1IN- RF7/SS RG5/ VDD, VSS MCLR PORTG RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 RG4/P1D RG5/MCLR/VPP BOR LVD Timer0 Timer1 Timer2 Timer3 Comparator ECCP1 CCP2 AUSART ECAN Module SSynecriharlo Pnooruts 1A0D-bCit Data EEPROM Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings. DS30491D-page 10  2003-2013 Microchip Technology Inc.

18F8680.book Page 11 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 1-2: PIC18F8X8X BLOCK DIAGRAM Data Bus<8> AD7:AD0 PORTA RA0/AN0 21 Table Pointer<21> Data Latch RA1/AN1 RA2/AN2/VREF- 8 8 Data RAM RA3/AN3/VREF+ inc/dec logic (3328 bytes) RA4/T0CKI RA5/AN4/LVDIN 21 Address Latch OSC2/CLKO/RA6 21 PCLATUPCLATH 12 PORTB Address<12> RB2/INT2:RB0/INT0 m Bus Interface PAro(dg6dr4raemKsbs My Lteeamstc)ohry PPCr3o1Ug rLaemPvCe ClH So ut a n cPtkeCrL B4SR 1FFF2SSSRRR012 Ba4nk0,1 2F RRRRRBBBBB35467/////KIKKKNBBBBTIIII13203////PCPPGGCGPMCD2(1) e Syst Data Latch inc/dec PORTC Decode logic RC0/T1OSO/T13CKI Table Latch RC1/T1OSI/CCP2(1) RC2/CCP1/P1A 16 8 RC3/SCK/SCL ROM Latch RC4/SDI/SDA RC5/SDO RC6/TX/CK IR RC7/RX/DT PORTD A16, AD15:AD8 8 RD7/PSP7/AD7: RD0/PSP0/AD0 PRODH PRODL PORTE IDnCsetcoroundctrteoio l&n 3 8 x 8 Multiply 8 RREE01//RWDR//AADD89 RE2/CS/AD10 BITOP W RE3/AD11 OOSSCC21//CCLLKKOI/RGA6eTnimeriantgion StaOPrtosT-cwuimiplela reT-truoimprer 8 8 8 8 RRRREEEE4765////ACAADDDC111P2432//(PP1)11/ABCD((221))5 Power-on ALU<8> PORTF Reset RF0/AN5 Watchdog 8 RF1/AN6/C2OUT Precision Timer RF2/AN7/C1OUT Band Gap Brown-out RF3/AN8/C2IN+ Reference Reset RF4/AN9/C2IN- Test Mode RF5/AN10/C1IN+/CVREF Select PORTJ RF6/AN11/C1IN- RJ0/ALE RF7/SS RJ1/OE RJ2/WRL PORTG RG5/ VDD, VSS RJ3/WRH RG0/CANTX1 MCLR RJ4/BA0 RG1/CANTX2 RJ5/CE RG2/CANRX RJ6/LB RG3 RJ7/UB RG4/P1D RG5/MCLR/VPP PORTH RH7/AN15/P1B(2) BOR RH6/AN14/P1C(2) LVD Timer0 Timer1 Timer2 Timer3 RH5/AN13 RH4/AN12 RH3/A19:RH0/A16 Comparator ECCP1 CCP2 AUSART ECAN Module SSynecriharlo Pnooruts 1A0D-bCit Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings. 2: P1B and P1C pin placement depends on the ECCPMX setting.  2003-2013 Microchip Technology Inc. DS30491D-page 11

18F8680.book Page 12 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP RG5/MCLR/VPP 7 16 9 Master Clear (input) or programming voltage (input). RG5 I ST General purpose input pin. MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. OSC1/CLKI 39 50 49 Oscillator crystal or external clock input. OSC1 I CMOS/ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. CLKI I CMOS External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO/RA6 40 51 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. DS30491D-page 12  2003-2013 Microchip Technology Inc.

18F8680.book Page 13 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTA is a bidirectional I/O port. RA0/AN0 24 34 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 23 33 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 22 32 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (Low) input. RA3/AN3/VREF+ 21 31 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (High) input. RA4/T0CKI 28 39 34 RA4 I/O ST/OD Digital I/O – Open-drain when configured as output. T0CKI I ST Timer0 external clock input. RA5/AN4/LVDIN 27 38 33 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. LVDIN I Analog Low-voltage detect input. RA6 See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.  2003-2013 Microchip Technology Inc. DS30491D-page 13

18F8680.book Page 14 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 48 60 58 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. RB1/INT1 47 59 57 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/INT2 46 58 56 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. RB3/INT3/CCP2 45 57 55 RB3 I/O TTL Digital I/O. INT3 I/O ST External interrupt 3. CCP2(1) I/O ST Capture 2 input/Compare 2 output/ PWM 2 output. RB4/KBI0 44 56 54 RB4 I/O TTL Digital I/O. KBI0 I ST Interrupt-on-change pin. RB5/KBI1/PGM 43 55 53 RB5 I/O TTL Digital I/O. KBI1 I ST Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP Programming enable pin. RB6/KBI2/PGC 42 54 52 RB6 I/O TTL Digital I/O. KBI2 I ST Interrupt-on-change pin. PGC I/O ST In-circuit debugger and ICSP programming clock. RB7/KBI3/PGD 37 48 47 RB7 I/O TTL Digital I/O. KBI3 I/O ST Interrupt-on-change pin. PGD In-circuit debugger and ICSP programming data. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. DS30491D-page 14  2003-2013 Microchip Technology Inc.

18F8680.book Page 15 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 41 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 29 40 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(1, 4) I/O ST CCP2 Capture input/Compare output/ PWM 2 output. RC2/CCP1/P1A 33 44 43 RC2 I/O ST Digital I/O. CCP1 I/O ST CCP1 Capture input/Compare output. P1A I/O ST CCP1 PWM output A. RC3/SCK/SCL 34 45 44 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 35 46 45 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O ST I2C data I/O. RC5/SDO 36 47 46 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 31 42 37 RC6 I/O ST Digital I/O. TX O — USART asynchronous transmit. CK I/O ST USART synchronous clock (see RX/DT). RC7/RX/DT 32 43 38 RC7 I/O ST Digital I/O. RX I ST USART 1 asynchronous receive. DT I/O ST USART 1 synchronous data (see TX/CK). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.  2003-2013 Microchip Technology Inc. DS30491D-page 15

18F8680.book Page 16 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/PSP0/AD0 58 3 72 RD0 I/O ST Digital I/O. PSP0(6) I/O TTL Parallel Slave Port data. AD0(3) I/O TTL External memory address/data 0. RD1/PSP1/AD1 55 67 69 RD1 I/O ST Digital I/O. PSP1(6) I/O TTL Parallel Slave Port data. AD1(3) I/O TTL External memory address/data 1. RD2/PSP2/AD2 54 66 68 RD2 I/O ST Digital I/O. PSP2(6) I/O TTL Parallel Slave Port data. AD2(3) I/O TTL External memory address/data 2. RD3/PSP3/AD3 53 65 67 RD3 I/O ST Digital I/O. PSP3(6) I/O TTL Parallel Slave Port data. AD3(3) I/O TTL External memory address/data 3. RD4/PSP4/AD4 52 64 66 RD4 I/O ST Digital I/O. PSP4(6) I/O TTL Parallel Slave Port data. AD4(3) I/O TTL External memory address/data 4. RD5/PSP5/AD5 51 63 65 RD5 I/O ST Digital I/O. PSP5(6) I/O TTL Parallel Slave Port data. AD5(3) I/O TTL External memory address/data 5. RD6/PSP6/AD6 50 62 64 RD6 I/O ST Digital I/O. PSP6(6) I/O TTL Parallel Slave Port data. AD6(3) I/O TTL External memory address/data 6. RD7/PSP7/AD7 49 61 63 RD7 I/O ST Digital I/O. PSP7(6) I/O TTL Parallel Slave Port data. AD7(3) I/O TTL External memory address/data 7. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. DS30491D-page 16  2003-2013 Microchip Technology Inc.

18F8680.book Page 17 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTE is a bidirectional I/O port. RE0/RD/AD8 2 11 4 RE0 I/O ST Digital I/O. RD(6) I TTL Read control for Parallel Slave Port (see WR and CS pins). AD8(3) I/O TTL External memory address/data 8. RE1/WR/AD9 1 10 3 RE1 I/O ST Digital I/O. WR(6) I TTL Write control for Parallel Slave Port (see CS and RD pins). AD9(3) I/O TTL External memory address/data 9. RE2/CS/AD10 64 9 78 RE2 I/O ST Digital I/O. CS(6) I TTL Chip select control for Parallel Slave Port (see RD and WR). AD10(3) I/O TTL External memory address/data 10. RE3/AD11 63 8 77 RE3 I/O ST Digital I/O. AD11(3) I/O TTL External memory address/data 11. RE4/AD12 62 7 76 RE4 I/O ST Digital I/O. AD12(3) I/O TTL External memory address/data 12. RE5/AD13/P1C 61 6 75 RE5 I/O ST Digital I/O. AD13(3) I/O TTL External memory address/data 13. P1C(7) I/O ST ECCP1 PWM output C. RE6/AD14/P1B 60 5 74 RE6 I/O ST Digital I/O. AD14(3) I/O TTL External memory address/data 14. P1B(7) I/O ST ECCP1 PWM output B. RE7/CCP2/AD15 59 4 73 RE7 I/O ST Digital I/O. CCP2(1,4) I/O ST Capture 2 input/Compare 2 output/ PWM 2 output. AD15(3) I/O TTL External memory address/data 15. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.  2003-2013 Microchip Technology Inc. DS30491D-page 17

18F8680.book Page 18 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTF is a bidirectional I/O port. RF0/AN5 18 28 24 RF0 I/O ST Digital I/O. AN5 I Analog Analog input 5. RF1/AN6/C2OUT 17 27 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog input 6. C2OUT O ST Comparator 2 output. RF2/AN7/C1OUT 16 26 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog input 7. C1OUT O ST Comparator 1 output. RF3/AN8/C2IN+ 15 25 17 RF1 I/O ST Digital I/O. AN8 I Analog Analog input 8. C2IN+ I Analog Comparator 2 input (+). RF4/AN9/C2IN- 14 24 16 RF1 I/O ST Digital I/O. AN9 I Analog Analog input 9. C2IN- I Analog Comparator 2 input (-). RF5/AN10/C1IN+/CVREF 13 23 15 RF1 AN10 I/O ST Digital I/O. C1IN+ I Analog Analog input 10. CVREF I Analog Comparator 1 input (+). O Analog Comparator VREF output. RF6/AN11/C1IN- 12 22 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. C1IN- I Analog Comparator 1 input (-) RF7/SS 11 21 13 RF7 I/O ST Digital I/O. SS I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. DS30491D-page 18  2003-2013 Microchip Technology Inc.

18F8680.book Page 19 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTG is a bidirectional I/O port. RG0/CANTX1 3 12 5 RG0 I/O ST Digital I/O. CANTX1 O TTL CAN bus transmit 1. RG1/CANTX2 4 13 6 RG1 I/O ST Digital I/O. CANTX2 O TTL CAN bus transmit 2. RG2/CANRX 5 14 7 RG2 I/O ST Digital I/O. CANRX I TTL CAN bus receive. RG3 6 15 8 RG3 I/O ST Digital I/O. RG4/P1D 8 17 10 RG4 I/O ST Digital I/O. P1D O TTL ECCP1 PWM output D. RG5 7 16 9 I ST General purpose input pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.  2003-2013 Microchip Technology Inc. DS30491D-page 19

18F8680.book Page 20 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTH is a bidirectional I/O port(5). RH0/A16 — — 79 RH0 I/O ST Digital I/O. A16 O TTL External memory address 16. RH1/A17 — — 80 RH1 I/O ST Digital I/O. A17 O TTL External memory address 17. RH2/A18 — — 1 RH2 I/O ST Digital I/O. A18 O TTL External memory address 18. RH3/A19 — — 2 RH3 I/O ST Digital I/O. A19 O TTL External memory address 19. RH4/AN12 — — 22 RH4 I/O ST Digital I/O. AN12 I Analog Analog input 12. RH5/AN13 — — 21 RH5 I/O ST Digital I/O. AN13 I Analog Analog input 13. RH6/AN14/P1C — — 20 RH6 I/O ST Digital I/O. AN14 I Analog Analog input 14. P1C(7) I/O ST Alternate CCP1 PWM output C. RH7/AN15/P1B — — 19 RH7 I/O ST Digital I/O. AN15 I Analog Analog input 15. P1B(7) Alternate CCP1 PWM output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit. DS30491D-page 20  2003-2013 Microchip Technology Inc.

18F8680.book Page 21 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name PIC18F6X8X PIC18F8X8X Description Type Type TQFP PLCC TQFP PORTJ is a bidirectional I/O port(5). RJ0/ALE — — 62 RJ0 I/O ST Digital I/O. ALE O TTL External memory address latch enable. RJ1/OE — — 61 RJ1 I/O ST Digital I/O. OE O TTL External memory output enable. RJ2/WRL — — 60 RJ2 I/O ST Digital I/O. WRL O TTL External memory write low control. RJ3/WRH — — 59 RJ3 I/O ST Digital I/O. WRH O TTL External memory write high control. RJ4/BA0 — — 39 RJ4 I/O ST Digital I/O. BA0 O TTL System bus byte address 0 control. RJ5/CE — — 40 I/O ST Digital I/O CE O TTL External memory chip enable. RJ6/LB — — 42 RJ6 I/O ST Digital I/O. LB O TTL External memory low byte select. RJ7/UB — — 41 RJ7 I/O ST Digital I/O. UB O TTL External memory high byte select. VSS 9, 25, 19, 36, 11, 31, P — Ground reference for logic and I/O pins. 41, 56 53, 68 51, 70 VDD 10, 26, 2, 20, 12, 32, P — Positive supply for logic and I/O pins. 38, 57 37, 49 48, 71 AVSS 20 30 26 P — Ground reference for analog modules. AVDD 19 29 25 P — Positive supply for analog modules. NC — 1, 18, — — — No connect. 35, 52 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only. 2: Default assignment when CCP2MX is set. 3: External memory interface functions are only available on PIC18F8X8X devices. 4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is multiplexed with either RB3 or RC1. 5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices. 6: PSP is available in Microcontroller mode only. 7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX configuration bit.  2003-2013 Microchip Technology Inc. DS30491D-page 21

18F8680.book Page 22 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 22  2003-2013 Microchip Technology Inc.

18F8680.book Page 23 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (HS, XT OR LP CONFIGURATION) 2.1 Oscillator Types The PIC18F6585/8585/6680/8680 devices can be C1(1) OSC1 operated in eleven different oscillator modes. The user To can program four configuration bits (FOSC3, FOSC2, Internal FOSC1 and FOSC0) to select one of these eleven XTAL RF(3) Logic modes: Sleep 1. LP Low-Power Crystal RS(2) 2. XT Crystal/Resonator C2(1) OSC2 PIC18FXX80/XX85 3. HS High-Speed Crystal/Resonator 4. RC External Resistor/Capacitor Note 1: See Table2-1 and Table2-2 for recommended 5. EC External Clock values of C1 and C2. 6. ECIO External Clock with I/O 2: A series resistor (RS) may be required for AT pin enabled strip cut crystals. 7. HS+PLL High-Speed Crystal/Resonator 3: RF varies with the oscillator mode chosen. with PLL enabled 8. RCIO External Resistor/Capacitor with TABLE 2-1: CAPACITOR SELECTION FOR I/O pin enabled CERAMIC RESONATORS 9. ECIO+SPLL External Clock with software Ranges Tested: controlled PLL 10. ECIO+PLL External Clock with PLL and I/O Mode Freq C1 C2 pin enabled XT 455 kHz 68-100 pF 68-100 pF 11. HS+SPLL High-Speed Crystal/Resonator 2.0 MHz 15-68 pF 15-68 pF with software control 4.0 MHz 15-68 pF 15-68 pF HS 8.0 MHz 10-68 pF 10-68 pF 2.2 Crystal Oscillator/Ceramic 16.0 MHz 10-22 pF 10-22 pF Resonators These values are for design guidance only. In XT, LP, HS, HS+PLL or HS+SPLL Oscillator modes, See notes following this table. a crystal or ceramic resonator is connected to the OSC1 Resonators Used: and OSC2 pins to establish oscillation. Figure2-1 shows the pin connections. 2.0 MHz Murata Erie CSA2.00MG  0.5% The PIC18F6585/8585/6680/8680 oscillator design 4.0 MHz Murata Erie CSA4.00MG  0.5% requires the use of a parallel cut crystal. 8.0 MHz Murata Erie CSA8.00MT  0.5% Note: Use of a series cut crystal may give a fre- 16.0 MHz Murata Erie CSA16.00MX  0.5% quency out of the crystal manufacturers All resonators used did not have built-in capacitors. specifications. Note1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use high gain HS mode, try a lower frequency resonator, or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components, or verify oscillator performance.  2003-2013 Microchip Technology Inc. DS30491D-page 23

18F8680.book Page 24 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 2-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the CRYSTAL OSCILLATOR OSC1 pin in the HS, XT and LP modes, as shown in Figure2-2. Ranges Tested: Mode Freq C1 C2 FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP 32.0 kHz 33 pF 33 pF LP OSC CONFIGURATION) 200 kHz 15 pF 15 pF XT 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF Clock from OSC1 Ext. System PIC18FXX80/XX85 4.0 MHz 15 pF 15 pF Open OSC2 HS 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 2.3 RC Oscillator 25.0 MHz TBD TBD For timing insensitive applications, the “RC” and These values are for design guidance only. “RCIO” device options offer additional cost savings. See notes following this table. The RC oscillator frequency is a function of the supply Crystals Used voltage, the resistor (REXT) and capacitor (CEXT) val- 32.0 kHz Epson C-001R32.768K-A ± 20 PPM ues and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit, due 200 kHz STD XTL 200.000KHz ± 20 PPM to normal process parameter variation. Furthermore, 1.0 MHz ECS ECS-10-13-1 ± 50 PPM the difference in lead frame capacitance between pack- 4.0 MHz ECS ECS-40-20-1 ± 50 PPM age types will also affect the oscillation frequency, 8.0 MHz Epson CA-301 8.000M-C ± 30 PPM especially for low CEXT values. The user also needs to take into account variation due to tolerance of external 20.0 MHz Epson CA-301 20.000M-C ± 30 PPM R and C components used. Figure2-3 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency Note1: Higher capacitance increases the stability divided by 4 is available on the OSC2 pin. This signal of the oscillator, but also increases the may be used for test purposes or to synchronize other start-up time. logic. 2: Rs (see Figure2-1) may be required in HS mode, as well as XT mode, to avoid FIGURE 2-3: RC OSCILLATOR MODE overdriving crystals with low drive level specifications. VDD 3: Since each resonator/crystal has its own REXT characteristics, the user should consult the Internal OSC1 resonator/crystal manufacturer for appro- Clock priate values of external components, or verify oscillator performance. CEXT VSS PIC18FXX80/XX85 OSC2/CLKO FOSC/4 Recommended values: 3 k  REXT  100 k CEXT > 20pF The RCIO Oscillator mode functions like the RC mode except that the OSC2 pin becomes an additional gen- eral purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). DS30491D-page 24  2003-2013 Microchip Technology Inc.

18F8680.book Page 25 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.4 External Clock Input 2.5 Phase Locked Loop (PLL) The EC, ECIO, EC+PLL and EC+SPLL Oscillator A Phase Locked Loop circuit is provided as a modes require an external clock source to be con- programmable option for users that want to multiply the nected to the OSC1 pin. The feedback device between frequency of the incoming oscillator signal by 4. For an OSC1 and OSC2 is turned off in these modes to save input clock frequency of 10 MHz, the internal clock current. There is a maximum 1.5 s start-up required frequency will be multiplied to 40 MHz. This is useful for after a Power-on Reset, or wake-up from Sleep mode. customers who are concerned with EMI due to high-frequency crystals. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal The PLL can only be enabled when the oscillator config- may be used for test purposes or to synchronize other uration bits are programmed for High-Speed Oscillator logic. Figure2-4 shows the pin connections for the EC or External Clock mode. If they are programmed for any Oscillator mode. other mode, the PLL is not enabled and the system clock will come directly from OSC1. There are two types of FIGURE 2-4: EXTERNAL CLOCK INPUT PLL modes: Software Controlled PLL and Configuration OPERATION bits Controlled PLL. In Software Controlled PLL mode, (EC CONFIGURATION) PIC18F6585/8585/6680/8680 executes at regular clock frequency after all Reset conditions. During execution, application can enable PLL and switch to 4x clock Clock from OSC1 frequency operation by setting the PLLEN bit in the Ext. System PIC18FXX80/XX85 OSCCON register. In Configuration bits Controlled PLL mode, PIC18F6585/8585/6680/8680 always executes FOSC/4 OSC2 with 4x clock frequency. The type of PLL is selected by programming the The ECIO Oscillator mode functions like the EC mode, FOSC<3:0> configuration bits in the CONFIG1H except that the OSC2 pin becomes an additional gen- Configuration register. The oscillator mode is specified eral purpose I/O pin. The I/O pin becomes bit 6 of during device programming. PORTA (RA6). Figure2-5 shows the pin connections A PLL lock timer is used to ensure that the PLL has for the ECIO Oscillator mode. locked before device execution starts. The PLL lock FIGURE 2-5: EXTERNAL CLOCK INPUT timer has a time-out that is called TPLL. OPERATION (ECIO CONFIGURATION) Clock from OSC1 Ext. System PIC18FXX80/XX85 RA6 I/O (OSC2) FIGURE 2-6: PLL BLOCK DIAGRAM PLL Enable Phase Comparator FIN Loop VCO Filter FOUT X SYSCLK U M Divide by 4  2003-2013 Microchip Technology Inc. DS30491D-page 25

18F8680.book Page 26 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.6 Oscillator Switching Feature execution mode. Figure2-7 shows a block diagram of the system clock sources. The clock switching feature The PIC18F6585/8585/6680/8680 devices include a is enabled by programming the Oscillator Switching feature that allows the system clock source to be Enable (OSCSEN) bit in configuration register, switched from the main oscillator to an alternate CONFIG1H, to a ‘0’. Clock switching is disabled in an low-frequency clock source. For the erased device. See Section12.0 “Timer1 Module” for PIC18F6585/8585/6680/8680 devices, this alternate further details of the Timer1 oscillator. See Section24.0 clock source is the Timer1 oscillator. If a low-frequency “Special Features of the CPU” for configuration crystal (32 kHz, for example) has been attached to the register details. Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a low-power FIGURE 2-7: DEVICE CLOCK SOURCES PIC18FXX80/XX85 Main Oscillator OSC2 Tosc/4 Sleep 4 x PLL OSC1 TOSC M TSCLK U Timer1 Oscillator X TT1P T1OSO T1OSCEN Clock Enable Source T1OSI Oscillator Clock Source Option for other Modules DS30491D-page 26  2003-2013 Microchip Technology Inc.

18F8680.book Page 27 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.6.1 SYSTEM CLOCK SWITCH BIT enabled (PLLEN = 1) and locked (LOCK = 1), else it will be forced clear. When programmed with Configuration The system clock source switching is performed under Controlled PLL mode, the SCS1 bit will be forced clear. software control. The System Clock Switch bits, SCS1:SCS0 (OSCCON<1:0>), control the clock switch- Note: The Timer1 oscillator must be enabled ing. When the SCS0 bit is ‘0’, the system clock source and operating to switch the system clock comes from the main oscillator that is selected by the source. The Timer1 oscillator is enabled FOSC configuration bits in configuration register, by setting the T1OSCEN bit in the Timer1 CONFIG1H. When the SCS0 bit is set, the system clock Control register (T1CON). If the Timer1 source will come from the Timer1 oscillator. The SCS0 oscillator is not enabled, then any write to bit is cleared on all forms of Reset. the SCS0 bit will be ignored (SCS0 bit When FOSC bits are programmed for software PLL forced cleared) and the main oscillator will mode, the SCS1 bit can be used to select between pri- continue to be the system clock source. mary oscillator/clock and PLL output. The SCS1 bit will only have an effect on the system clock if the PLL is REGISTER 2-1: OSCCON REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — LOCK PLLEN SCS1 SCS0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 LOCK: Phase Lock Loop Lock Status bit 1 = Phase Lock Loop output is stable as system clock 0 = Phase Lock Loop output is not stable and output cannot be used as system clock bit 2 PLLEN(1): Phase Lock Loop Enable bit 1 = Enable Phase Lock Loop output as system clock 0 = Disable Phase Lock Loop bit 1 SCS1: System Clock Switch bit 1 When PLLEN and LOCK bits are set: 1 = Use PLL output 0 = Use primary oscillator/clock input pin When PLLEN or LOCK bit is cleared: Bit is forced clear. bit 0 SCS0(2): System Clock Switch bit 0 When OSCSEN configuration bit = 0 and T1OSCEN bit = 1: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When OSCSEN and T1OSCEN are in other states: Bit is forced clear. Note1: PLLEN bit is ignored when configured for ECIO+PLL and HS+PLL. This bit is used in ECIO+SPLL and HS+SPLL modes only. 2: The setting of SCS0 = 1 supersedes SCS1 = 1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 27

18F8680.book Page 28 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.6.2 OSCILLATOR TRANSITIONS The sequence of events that takes place when switch- ing from the Timer1 oscillator to the main oscillator will PIC18F6585/8585/6680/8680 devices contain circuitry depend on the mode of the main oscillator. In addition to prevent “glitches” when switching between oscillator to eight clock cycles of the main oscillator, additional sources. Essentially, the circuitry waits for eight rising delays may take place. edges of the clock source that the processor is switch- ing to. This ensures that the new clock source is stable If the main oscillator is configured for an external and that its pulse width will not be less than the shortest crystal (HS, XT, LP), then the transition will take place pulse width of the two clock sources. after an oscillator start-up time (TOST) has occurred. A timing diagram, indicating the transition from the A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and main oscillator to the Timer1 oscillator, is shown in LP modes, is shown in Figure2-9. Figure2-8. The Timer1 oscillator is assumed to be run- ning all the time. After the SCS0 bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 TT1P T1OSI 1 2 3 4 5 6 7 8 TSCS OSC1 Internal TOSC System Clock TDLY SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note: TDLY is the delay from SCS high to first count of transition circuit. FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP) Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 TT1P T1OSI OSC1 1 2 3 4 5 6 7 8 TOST TSCS Internal TOSC System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 6 Note: TOST = 1024 TOSC (drawing not to scale). DS30491D-page 28  2003-2013 Microchip Technology Inc.

18F8680.book Page 29 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If the main oscillator is configured for HS mode with If the main oscillator is configured for EC mode with PLL PLL active, an oscillator start-up time (TOST) plus an active, only the PLL time-out (TPLL) will occur. The PLL additional PLL time-out (TPLL) will occur. The PLL time- time-out is typically 2 ms and allows the PLL to lock to out is typically 2 ms and allows the PLL to lock to the the main oscillator frequency. A timing diagram, indicat- main oscillator frequency. A timing diagram, indicating ing the transition from the Timer1 oscillator to the main the transition from the Timer1 oscillator to the main oscillator for EC with PLL active, is shown in Figure2-11. oscillator for HS-PLL mode, is shown in Figure2-10. FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL ACTIVE, SCS1 = 1) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST TPLL PLL Clock TOSC TSCS Input 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 Note: TOST = 1024 TOSC (drawing not to scale). FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (EC WITH PLL ACTIVE, SCS1 = 1) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TPLL TOSC TSCS PLL Clock Input 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4  2003-2013 Microchip Technology Inc. DS30491D-page 29

18F8680.book Page 30 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indi- cating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure2-12. FIGURE 2-12: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4Q1 Q2 Q3Q4 T1OSI TOSC OSC1 1 2 3 4 5 6 7 8 Internal System Clock SCS (OSCCON<0>) TSCS Program Counter PC PC + 2 PC + 4 Note: RC Oscillator mode assumed. DS30491D-page 30  2003-2013 Microchip Technology Inc.

18F8680.book Page 31 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.7 Effects of Sleep Mode on the switching currents have been removed, Sleep mode On-Chip Oscillator achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature When the device executes a SLEEP instruction, the on- that will operate during Sleep will increase the current chip clocks and oscillator are turned off and the device consumed during Sleep. The user can wake from is held at the beginning of an instruction cycle (Q1 Sleep through external Reset, Watchdog Timer Reset, state). With the oscillator off, the OSC1 and OSC2 or through an interrupt. signals will stop oscillating. Since all the transistor TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC Floating, external resistor should pull high At logic low RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating Configured as PORTA, bit 6 EC Floating At logic low LP, XT, and HS Feedback inverter disabled at Feedback inverter disabled at quiescent voltage level quiescent voltage level Note: See Table3-1 in Section3.0 “Reset”, for time-outs due to Sleep and MCLR Reset. 2.8 Power-up Delays With the PLL enabled (HS+PLL and EC+PLL Oscillator mode), the time-out sequence following a Power-on Power-up delays are controlled by two timers so that no Reset is different from other oscillator modes. The external Reset circuitry is required for most applica- time-out sequence is as follows: First, the PWRT time- tions. The delays ensure that the device is kept in out is invoked after a POR time delay has expired. Reset until the device power supply and clock are sta- Then, the Oscillator Start-up Timer (OST) is invoked. ble. For additional information on Reset operation, see However, this is still not a sufficient amount of time to Section3.0 “Reset”. allow the PLL to lock at high frequencies. The PWRT The first timer is the Power-up Timer (PWRT) which timer is used to provide an additional fixed 2 ms optionally provides a fixed delay of 72 ms (nominal) on (nominal) time-out to allow the PLL ample time to lock power-up only (POR and BOR). The second timer is to the incoming clock frequency. the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable.  2003-2013 Microchip Technology Inc. DS30491D-page 31

18F8680.book Page 32 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 32  2003-2013 Microchip Technology Inc.

18F8680.book Page 33 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 3.0 RESET Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal oper- The PIC18F6585/8585/6680/8680 devices differentiate ation. Status bits from the RCON register, RI, TO, PD, between various kinds of Reset: POR and BOR, are set or cleared differently in different a) Power-on Reset (POR) Reset situations, as indicated in Table3-2. These bits are used in software to determine the nature of the b) MCLR Reset during normal operation Reset. See Table3-3 for a full description of the Reset c) MCLR Reset during Sleep states of all registers. d) Watchdog Timer (WDT) Reset (during normal A simplified block diagram of the On-Chip Reset Circuit operation) is shown in Figure3-1. e) Programmable Brown-out Reset (BOR) f) RESET Instruction The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and g) Stack Full Reset ignore small pulses. The MCLR pin is not driven low by h) Stack Underflow Reset any internal Resets, including the WDT. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” on Power-on Reset, MCLR, WDT Reset, Brown- out Reset, MCLR Reset during Sleep and by the RESET instruction. FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Pointer Stack Full/Underflow Reset External Reset MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset BOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 PWRT On-chip RC OSC(1) 10-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table3-1 for time-out situations.  2003-2013 Microchip Technology Inc. DS30491D-page 33

18F8680.book Page 34 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 3.1 Power-on Reset (POR) 3.3 Oscillator Start-up Timer (OST) A Power-on Reset pulse is generated on-chip when The Oscillator Start-up Timer (OST) provides 1024 VDD rise is detected. To take advantage of the POR cir- oscillator cycles (from OSC1 input) delay after the cuitry, tie the MCLR pin through a 1k to 10k resis- PWRT delay is over (parameter #32). This ensures that tor to VDD. This will eliminate external RC components the crystal oscillator or resonator has started and usually needed to create a Power-on Reset delay. A stabilized. minimum rise rate for VDD is specified (parameter The OST time-out is invoked only for XT, LP and HS D004). For a slow rise time, see Figure3-2. modes and only on Power-on Reset, or wake-up from When the device starts normal operation (i.e., exits the Sleep. Reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to 3.4 PLL Lock Time-out ensure operation. If these conditions are not met, the device must be held in Reset until the operating With the PLL enabled, the time-out sequence following conditions are met. a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to pro- FIGURE 3-2: EXTERNAL POWER-ON vide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out RESET CIRCUIT (FOR SLOW VDD POWER-UP) (TPLL) is typically 2 ms and follows the oscillator start-up time-out (OST). VDD 3.5 Brown-out Reset (BOR) A configuration bit, BOREN, can disable (if clear/ D R programmed), or enable (if set) the Brown-out Reset R1 MCLR circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation will reset C PIC18FXX8X the chip. A Reset may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. If the Power-up Timer is enabled, it will be Note 1: External Power-on Reset circuit is required invoked after VDD rises above BVDD; it then will keep only if the VDD power-up slope is too slow. the chip in Reset for an additional time delay (parame- The diode D helps discharge the capacitor ter #33). If VDD drops below BVDD while the Power-up quickly when VDD powers down. Timer is running, the chip will go back into a Brown-out 2: R < 40 k is recommended to make sure that Reset and the Power-up Timer will be initialized. Once the voltage drop across R does not violate VDD rises above BVDD, the Power-up Timer will the device’s electrical specification. execute the additional time delay. 3: R1 = 1k to 10k will limit any current flow- ing into MCLR from external capacitor C, in 3.6 Time-out Sequence the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical On power-up, the time-out sequence is as follows: Overstress (EOS). First, PWRT time-out is invoked after the POR time delay has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and 3.2 Power-up Timer (PWRT) the status of the PWRT. For example, in RC mode with The Power-up Timer provides a fixed nominal time-out the PWRT disabled, there will be no time-out at all. (parameter #33) only on power-up from the POR. The Figure3-3, Figure3-4, Figure3-5, Figure3-6 and Power-up Timer operates on an internal RC oscillator. Figure3-7 depict time-out sequences on power-up. The chip is kept in Reset as long as the PWRT is active. Since the time-outs occur from the POR pulse, the The PWRT’s time delay allows VDD to rise to an time-outs will expire if MCLR is kept low long enough. acceptable level. A configuration bit is provided to Bringing MCLR high will begin execution immediately enable/disable the PWRT. (Figure3-5). This is useful for testing purposes or to The power-up time delay will vary from chip-to-chip due synchronize more than one PIC18FXX8X device to VDD, temperature and process variation. See DC operating in parallel. parameter #33 for details. Table3-2 shows the Reset conditions for some Special Function Registers while Table3-3 shows the Reset conditions for all of the registers. DS30491D-page 34  2003-2013 Microchip Technology Inc.

18F8680.book Page 35 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Wake-up from Oscillator Brown-out Sleep or Configuration PWRTE = 0 PWRTE = 1 Oscillator Switch HS with PLL enabled(1) 72 ms + 1024 TOSC + 2ms 1024 TOSC + 2 ms 1024 TOSC + 2ms 1024 TOSC + 2 ms EC with PLL enabled(1) 72 ms + 2ms 1.5 s + 2 ms 2ms 1.5 s + 2 ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 1024 TOSC 1024 TOSC EC 72 ms 1.5 s 1.5 s 1.5 s(3) External RC 72 ms 1.5 s 1.5 s 1.5 s Note 1: 2 ms is the nominal time required for the 4x PLL to lock. 2: 72 ms is the nominal power-up timer delay if implemented. 3: 1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 Note: Refer to Section4.14 “RCON Register” for bit definitions. TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program RCON Condition RI TO PD POR BOR STKFUL STKUNF Counter Register Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u MCLR Reset during normal 0000h 0--u uuuu u u u u u u u operation Software Reset during normal 0000h 0--0 uuuu 0 u u u u u u operation Stack Full Reset during normal 0000h 0--u uu11 u u u u u u 1 operation Stack Underflow Reset during 0000h 0--u uu11 u u u u u 1 u normal operation MCLR Reset during Sleep 0000h 0--u 10uu u 1 0 u u u u WDT Reset 0000h 0--u 01uu 1 0 1 u u u u WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u Interrupt wake-up from Sleep PC + 2(1) u--u 00uu u 1 0 u u u u Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h).  2003-2013 Microchip Technology Inc. DS30491D-page 35

18F8680.book Page 36 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU PIC18F6X8X PIC18F8X8X ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F6X8X PIC18F8X8X 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F6X8X PIC18F8X8X ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6X8X PIC18F8X8X 0000 000x 0000 000x uuuu uuuu(1) INTCON2 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 PIC18F6X8X PIC18F8X8X 1100 0000 1100 0000 uuuu uuuu(1) INDF0 PIC18F6X8X PIC18F8X8X N/A N/A N/A POSTINC0 PIC18F6X8X PIC18F8X8X N/A N/A N/A POSTDEC0 PIC18F6X8X PIC18F8X8X N/A N/A N/A PREINC0 PIC18F6X8X PIC18F8X8X N/A N/A N/A PLUSW0 PIC18F6X8X PIC18F8X8X N/A N/A N/A FSR0H PIC18F6X8X PIC18F8X8X ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6X8X PIC18F8X8X N/A N/A N/A POSTINC1 PIC18F6X8X PIC18F8X8X N/A N/A N/A POSTDEC1 PIC18F6X8X PIC18F8X8X N/A N/A N/A PREINC1 PIC18F6X8X PIC18F8X8X N/A N/A N/A PLUSW1 PIC18F6X8X PIC18F8X8X N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 36  2003-2013 Microchip Technology Inc.

18F8680.book Page 37 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets FSR1H PIC18F6X8X PIC18F8X8X ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6X8X PIC18F8X8X ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6X8X PIC18F8X8X N/A N/A N/A POSTINC2 PIC18F6X8X PIC18F8X8X N/A N/A N/A POSTDEC2 PIC18F6X8X PIC18F8X8X N/A N/A N/A PREINC2 PIC18F6X8X PIC18F8X8X N/A N/A N/A PLUSW2 PIC18F6X8X PIC18F8X8X N/A N/A N/A FSR2H PIC18F6X8X PIC18F8X8X ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F6X8X PIC18F8X8X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6X8X PIC18F8X8X 0000 0000 uuuu uuuu uuuu uuuu TMR0L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6X8X PIC18F8X8X ---- 0000 ---- 0000 ---- uuuu LVDCON PIC18F6X8X PIC18F8X8X --00 0101 --00 0101 --uu uuuu WDTCON PIC18F6X8X PIC18F8X8X ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F6X8X PIC18F8X8X 0--q 11qq 0--q qquu u--u qquu TMR1H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6X8X PIC18F8X8X 0-00 0000 u-uu uuuu u-uu uuuu TMR2 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 1111 1111 T2CON PIC18F6X8X PIC18F8X8X -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 37

18F8680.book Page 38 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets ADRESH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu ADCON1 PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6X8X PIC18F8X8X 0-00 0000 0-00 0000 u-uu uuuu CCPR1H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6X8X PIC18F8X8X --00 0000 --00 0000 --uu uuuu CCPAS1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TMR3H PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu T3CON PIC18F6X8X PIC18F8X8X 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6X8X PIC18F8X8X 0000 ---- 0000 ---- uuuu ---- SPBRG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RCREG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TXREG PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TXSTA PIC18F6X8X PIC18F8X8X 0000 0010 0000 0010 uuuu uuuu RCSTA PIC18F6X8X PIC18F8X8X 0000 000x 0000 000x uuuu uuuu EEADRH PIC18F6X8X PIC18F8X8X ---- --00 ---- --00 ---- --uu EEADR PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu EECON2 PIC18F6X8X PIC18F8X8X xx-0 x000 uu-0 u000 uu-0 u000 EECON1 PIC18F6X8X PIC18F8X8X 00-0 x000 00-0 u000 uu-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 38  2003-2013 Microchip Technology Inc.

18F8680.book Page 39 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets IPR3 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu PIE3 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu IPR2 PIC18F6X8X PIC18F8X8X -1-1 1111 -1-1 1111 -u-u uuuu PIR2 PIC18F6X8X PIC18F8X8X -0-0 0000 -0-0 0000 -u-u uuuu(1) PIE2 PIC18F6X8X PIC18F8X8X -0-0 0000 -0-0 0000 -u-u uuuu IPR1 PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu(1) PIE1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu MEMCON PIC18F6X8X PIC18F8X8X 0-00 --00 0-00 --00 u-uu --uu TRISJ PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6X8X PIC18F8X8X ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu TRISE PIC18F6X8X PIC18F8X8X 0000 -111 0000 -111 uuuu -uuu TRISD PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6X8X PIC18F8X8X 1111 1111 1111 1111 uuuu uuuu TRISA(5,6) PIC18F6X8X PIC18F8X8X -111 1111(5) -111 1111(5) -uuu uuuu(5) LATJ PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATG PIC18F6X8X PIC18F8X8X ---x xxxx ---u uuuu ---u uuuu LATF PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATE PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATD PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu LATA(5,6) PIC18F6X8X PIC18F8X8X -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 39

18F8680.book Page 40 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets PORTJ PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6X8X PIC18F8X8X 0000 xxxx 0000 uuuu uuuu uuuu PORTG PIC18F6X8X PIC18F8X8X --xx xxxx --uu uuuu --uu uuuu PORTF PIC18F6X8X PIC18F8X8X x000 0000 u000 0000 u000 0000 PORTE PIC18F6X8X PIC18F8X8X ---- -000 ---- -000 ---- -uuu PORTD PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5,6) PIC18F6X8X PIC18F8X8X -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) SPBRGH PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu BAUDCON PIC18F6X8X PIC18F8X8X -1-0 0-00 -1-0 0-00 -u-u u-uu ECCP1DEL PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu ECANCON PIC18F6X8X PIC18F8X8X 0001 0000 0001 0000 uuuu uuuu TXERRCNT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXERRCNT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu COMSTAT PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CIOCON PIC18F6X8X PIC18F8X8X 0000 ---- 0000 ---- uuuu ---- BRGCON3 PIC18F6X8X PIC18F8X8X 00-- -000 00-- -000 uu-- -uuu BRGCON2 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu BRGCON1 PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu CANCON PIC18F6X8X PIC18F8X8X 1000 000- 1000 000- uuuu uuu- CANSTAT PIC18F6X8X PIC18F8X8X 100- 000- 100- 000- uuu- uuu- RXB0D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 40  2003-2013 Microchip Technology Inc.

18F8680.book Page 41 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXB0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON PIC18F6X8X PIC18F8X8X 000- 0000 000- 0000 uuu- uuuu RXB1D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu RXB1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu RXB1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON PIC18F6X8X PIC18F8X8X 000- 0000 000- 0000 uuu- uuuu TXB0D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC PIC18F6X8X PIC18F8X8X -x-- xxxx -u-- uuuu -u-- uuuu TXB0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu TXB0SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 41

18F8680.book Page 42 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TXB0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu TXB1D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC PIC18F6X8X PIC18F8X8X -x-- xxxx -u-- uuuu -u-- uuuu TXB1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- uu-u TXB1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu TXB1CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu TXB2D7 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D6 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D1 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D0 PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu 0uuu uuuu TXB2DLC PIC18F6X8X PIC18F8X8X -x-- xxxx -u-- uuuu -u-- uuuu TXB2EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu TXB2SIDH PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu TXB2CON PIC18F6X8X PIC18F8X8X 0000 0-00 0000 0-00 uuuu u-uu RXM1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 42  2003-2013 Microchip Technology Inc.

18F8680.book Page 43 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXM1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXM1SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXM1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXM0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF3SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 43

18F8680.book Page 44 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets B5D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B5EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B5SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B5SIDH(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B5CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B4D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B4EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B4SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B4CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B3D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 44  2003-2013 Microchip Technology Inc.

18F8680.book Page 45 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets B3D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B3EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B3SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B3CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B2D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B2SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B2CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B1D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 45

18F8680.book Page 46 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets B1D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B1EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B1SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B1CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu B0D7(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D6(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D5(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D4(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D3(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D2(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D1(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0D0(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0DLC(7) PIC18F6X8X PIC18F8X8X -xxx xxxx -uuu uuuu -uuu uuuu B0EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0SIDL(7) PIC18F6X8X PIC18F8X8X xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu B0CON(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu TXBIE(7) PIC18F6X8X PIC18F8X8X ---0 00-- ---u uu-- ---u uu-- BIE0(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu BSEL0(7) PIC18F6X8X PIC18F8X8X 0000 00-- 0000 00-- uuuu uu-- MSEL3(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu MSEL2(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu MSEL1(7) PIC18F6X8X PIC18F8X8X 0000 0101 0000 0101 uuuu uuuu MSEL0(7) PIC18F6X8X PIC18F8X8X 0101 0000 0101 0000 uuuu uuuu SDFLC(7) PIC18F6X8X PIC18F8X8X ---0 0000 ---0 0000 -u-- uuuu RXFCON1(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 46  2003-2013 Microchip Technology Inc.

18F8680.book Page 47 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXFCON0(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXFBCON7(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXFBCON6(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXFBCON5(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXFBCON4(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXFBCON3(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXFBCON2(7) PIC18F6X8X PIC18F8X8X 0001 0001 0001 0001 uuuu uuuu RXFBCON1(7) PIC18F6X8X PIC18F8X8X 0001 0001 0001 0001 uuuu uuuu RXFBCON0(7) PIC18F6X8X PIC18F8X8X 0000 0000 0000 0000 uuuu uuuu RXF15EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF15EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF15SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF15SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF14EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF14SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF14SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF13EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF13SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF13SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF12EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF12SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF12SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF11SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu uuu- u-uu RXF11SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu uuuu uuuu RXF10EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF10EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 47

18F8680.book Page 48 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Power-on Reset, WDT Reset Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets RXF10SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu -uuu uuuu RXF10SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF9EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF9EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF9SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu -uuu uuuu RXF9SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF8EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF8EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF8SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu -uuu uuuu RXF8SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF7EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF7EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF7SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu -uuu uuuu RXF7SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF6EIDL(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF6EIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu RXF6SIDL(7) PIC18F6X8X PIC18F8X8X xxx- x-xx uuu- u-uu -uuu uuuu RXF6SIDH(7) PIC18F6X8X PIC18F8X8X xxxx xxxx uuuu uuuu -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table3-2 for Reset value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. DS30491D-page 48  2003-2013 Microchip Technology Inc.

18F8680.book Page 49 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2003-2013 Microchip Technology Inc. DS30491D-page 49

18F8680.book Page 50 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD VIA 1 kRESISTOR) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS30491D-page 50  2003-2013 Microchip Technology Inc.

18F8680.book Page 51 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.0 MEMORY ORGANIZATION 4.1.1 PIC18F8X8X PROGRAM MEMORY MODES There are three memory blocks in PIC18F6585/8585/6680/8680 devices. They are: PIC18F8X8X devices differ significantly from their PIC18 predecessors in their utilization of program • Program Memory memory. In addition to available on-chip Flash program • Data RAM memory, these controllers can also address up to • Data EEPROM 2Mbytes of external program memory through the external memory interface. There are four distinct Data and program memory use separate busses which operating modes available to the controllers: allows for concurrent access of these blocks. Additional detailed information for Flash program memory and data • Microprocessor (MP) EEPROM is provided in Section5.0 “Flash Program • Microprocessor with Boot Block (MPBB) Memory” and Section7.0 “Data EEPROM Memory”, • Extended Microcontroller (EMC) respectively. • Microcontroller (MC) In addition to on-chip Flash, the PIC18F8X8X devices The Program Memory mode is determined by setting are also capable of accessing external program mem- the two Least Significant bits of the CONFIG3L config- ory through an external memory bus. Depending on the uration byte, as shown in Register4-1. (See also selected operating mode (discussed in Section4.1.1 Section24.1 “Configuration Bits” for additional “PIC18F8X8X Program Memory Modes”), the details on the device configuration bits.) controllers may access either internal or external pro- gram memory exclusively, or both internal and external The Program Memory modes operate as follows: memory in selected blocks. Additional information on • The Microprocessor Mode permits access only the external memory interface is provided in to external program memory; the contents of the Section6.0 “External Memory Interface”. on-chip Flash memory are ignored. The 21-bit program counter permits access to a 2-MByte 4.1 Program Memory Organization linear program memory space. • The Microprocessor with Boot Block Mode A 21-bit program counter is capable of addressing the accesses on-chip Flash memory from addresses 2-Mbyte program memory space. Accessing a location 000000h to 0007FFh. Above this, external between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP program memory is accessed all the way up to the 2-MByte limit. Program execution auto- instruction). matically switches between the two memories as The PIC18F6585 and PIC18F8585 each have required. 48Kbytes of on-chip Flash memory, while the • The Microcontroller Mode accesses only PIC18F6680 and PIC18F8680 have 64Kbytes of Flash. on-chip Flash memory. Attempts to read above This means that PIC18FX585 devices can store inter- the physical limit of the on-chip Flash (0BFFFh for nally up to 24,576 single-word instructions and the PIC18F8585, 0FFFFh for the PIC18F8680) PIC18FX680 devices can store up to 32,768 single-word causes a read of all ‘0’s (a NOP instruction). instructions. The Microcontroller mode is the only operating The Reset vector address is at 0000h and the interrupt mode available to PIC18F6X8X devices. vector addresses are at 0008h and 0018h. • The Extended Microcontroller Mode allows Figure4-1 shows the program memory map for access to both internal and external program PIC18F6585/8585 devices while Figure4-2 shows the memories as a single block. The device can program memory map for PIC18F6680/8680 devices. access its entire on-chip Flash memory; above this, the device accesses external program mem- ory up to the 2-MByte program space limit. As with Boot Block mode, execution automatically switches between the two memories as required. In all modes, the microcontroller has complete access to data RAM and EEPROM. Figure4-3 compares the memory maps of the different Program Memory modes. The differences between on- chip and external memory access limitations are more fully explained in Table4-1.  2003-2013 Microchip Technology Inc. DS30491D-page 51

18F8680.book Page 52 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 4-1: INTERNAL PROGRAM FIGURE 4-2: INTERNAL PROGRAM MEMORY MAP AND MEMORY MAP AND STACK FOR STACK FOR PIC18F6585/8585 PIC18F6680/8680 PC<20:0> PC<20:0> CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21 RETFIE,RETLW RETFIE,RETLW Stack Level 1 Stack Level 1   Stack Level 31 Stack Level 31 Reset Vector 000000h Reset Vector 000000h High Priority Interrupt Vector 000008h High Priority Interrupt Vector 000008h Low Priority Interrupt Vector 000018h Low Priority Interrupt Vector 000018h On-Chip Flash Program Memory 00BFFFh 00C000h e On-Chip Flash e c Program Memory c a a p p S S y y or or m m e e M M er 00FFFFh er s s Read ‘0’ U 010000h U Read ‘0’ 1FFFFFh 1FFFFFh 200000h 200000h TABLE 4-1: MEMORY ACCESS FOR PIC18F8X8X PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Execution Table Read Table Write To Table Write To From From From From Microprocessor No Access No Access No Access Yes Yes Yes Microprocessor w/ Yes Yes Yes Yes Yes Yes Boot Block Microcontroller Yes Yes Yes No Access No Access No Access Extended Yes Yes Yes Yes Yes Yes Microcontroller DS30491D-page 52  2003-2013 Microchip Technology Inc.

18F8680.book Page 53 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 4-1: CONFIG3L CONFIGURATION BYTE R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microcontroller with Boot Block mode 00 = Extended Microcontroller mode Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 4-3: MEMORY MAPS FOR PIC18F8X8X PROGRAM MEMORY MODES Microprocessor Microprocessor Microcontroller Extended Mode with Boot Block Mode Microcontroller Mode Mode 000000h On-Chip 000000h 000000h 000000h Program On-Chip On-Chip On-Chip Memory Program Program Program ac(cNeoss) Memory 00BFFFh(1) Memory 00BFFFh(1) Memory n 0007FFh 00FFFFh(2) 00FFFFh(2) utio 000800h 00100C000000hh((21)) 00100C000000hh((21)) ec External ace Ex PMreomgroarmy External R e‘0a’sds External p S Program Program am Memory Memory gr o Pr 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh External On-Chip External On-Chip On-Chip External On-Chip Memory Flash Memory Flash Flash Memory Flash Note 1: PIC18F6585 and PIC18F8585. 2: PIC18F6680 and PIC18F8680.  2003-2013 Microchip Technology Inc. DS30491D-page 53

18F8680.book Page 54 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.2 Return Address Stack 4.2.2 RETURN STACK POINTER (STKPTR) The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC The STKPTR register contains the stack pointer value, (Program Counter) is pushed onto the stack when a the STKFUL (Stack Full) status bit, and the STKUNF CALL or RCALL instruction is executed or an interrupt is (Stack Underflow) status bits. Register4-2 shows the Acknowledged. The PC value is pulled off the stack on STKPTR register. The value of the stack pointer can be a RETURN, RETLW, or a RETFIE instruction. PCLATU 0 through 31. The stack pointer increments when values and PCLATH are not affected by any of the RETURN or are pushed onto the stack and decrements when values CALL instructions. are popped off the stack. At Reset, the stack pointer value will be ‘0’. The user may read and write the stack The stack operates as a 31-word by 21-bit RAM and a pointer value. This feature can be used by a Real-Time 5-bit stack pointer, with the stack pointer initialized to Operating System for return stack maintenance. 00000b after all Resets. There is no RAM associated with stack pointer 00000b. This is only a Reset value. After the PC is pushed onto the stack 31 times (without During a CALL type instruction causing a push onto the popping any values off the stack), the STKFUL bit is stack, the stack pointer is first incremented and the set. The STKFUL bit can only be cleared in software or RAM location pointed to by the stack pointer is written by a POR. with the contents of the PC. During a RETURN type The action that takes place when the stack becomes instruction causing a pop from the stack, the contents full depends on the state of the STVREN (Stack of the RAM location pointed to by the STKPTR are Overflow Reset Enable) configuration bit. Refer to transferred to the PC and then the stack pointer is Section25.0 “Instruction Set Summary” for a decremented. description of the device configuration bits. If STVREN The stack space is not part of either program or data is set (default), the 31st push will push the (PC + 2) space. The stack pointer is readable and writable and value onto the stack, set the STKFUL bit and reset the the address on the top of the stack is readable and writ- device. The STKFUL bit will remain set and the stack able through SFR registers. Data can also be pushed pointer will be set to ‘0’. to or popped from the stack, using the top-of-stack If STVREN is cleared, the STKFUL bit will be set on the SFRs. Status bits indicate if the stack pointer is at or 31st push and the stack pointer will increment to 31. beyond the 31 levels provided. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. 4.2.1 TOP-OF-STACK ACCESS When the stack has been popped enough times to The top of the stack is readable and writable. Three unload the stack, the next pop will return a value of zero register locations, TOSU, TOSH and TOSL, hold the to the PC and sets the STKUNF bit while the stack contents of the stack location pointed to by the pointer remains at ‘0’. The STKUNF bit will remain set STKPTR register. This allows users to implement a until cleared in software or a POR occurs. software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by Note: Returning a value of zero to the PC on an reading the TOSU, TOSH and TOSL registers. These underflow has the effect of vectoring the values can be placed on a user defined software stack. program to the Reset vector, where the At return time, the software can replace the TOSU, stack conditions can be verified and TOSH and TOSL and do a return. appropriate actions can be taken. The user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations. DS30491D-page 54  2003-2013 Microchip Technology Inc.

18F8680.book Page 55 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 4-2: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note1: Bit 7 and bit 6 can only be cleared in user software or by a POR. Legend: C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’ W = Writable bit - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 4-4: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 4.2.3 PUSH AND POP INSTRUCTIONS 4.2.4 STACK FULL/UNDERFLOW RESETS Since the Top-of-Stack (TOS) is readable and writable, These Resets are enabled by programming the the ability to push values onto the stack and pull values STVREN configuration bit. When the STVREN bit is off the stack, without disturbing normal program execu- disabled, a full or underflow condition will set the tion, is a desirable option. To push the current PC value appropriate STKFUL or STKUNF bit, but not cause a onto the stack, a PUSH instruction can be executed. device Reset. When the STVREN bit is enabled, a full This will increment the stack pointer and load the cur- or underflow condition will set the appropriate STKFUL rent PC value onto the stack. TOSU, TOSH and TOSL or STKUNF bit and then cause a device Reset. The can then be modified to place a return address on the STKFUL or STKUNF bits are only cleared by the user stack. software or a POR Reset. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value.  2003-2013 Microchip Technology Inc. DS30491D-page 55

18F8680.book Page 56 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.3 Fast Register Stack 4.4 PCL, PCLATH and PCLATU A “fast interrupt return” option is available for interrupts. The program counter (PC) specifies the address of the A fast register stack is provided for the Status, WREG instruction to fetch for execution. The PC is 21 bits and BSR registers and is only one in depth. The stack wide. The low byte is called the PCL register; this reg- is not readable or writable and is loaded with the ister is readable and writable. The high byte is called current value of the corresponding register when the the PCH register. This register contains the PC<15:8> processor vectors for an interrupt. The values in the bits and is not directly readable or writable; updates to registers are then loaded back into the working regis- the PCH register may be performed through the ters if the FAST RETURN instruction is used to return PCLATH register. The upper byte is called PCU. This from the interrupt. register contains the PC<20:16> bits and is not directly readable or writable; updates to the PCU register may A low or high priority interrupt source will push values be performed through the PCLATU register. into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be The PC addresses bytes in the program memory. To used reliably for low priority interrupts. If a high priority prevent the PC from becoming misaligned with word interrupt occurs while servicing a low priority interrupt, instructions, the LSB of the PCL is fixed to a value of the stack register values stored by the low priority ‘0’. The PC increments by 2 to address sequential interrupt will be overwritten. instructions in the program memory. If high priority interrupts are not disabled during low The CALL, RCALL, GOTO and program branch priority interrupts, users must save the key registers in instructions write to the program counter directly. For software during a low priority interrupt. these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at The contents of PCLATH and PCLATU will be trans- the end of a subroutine call. To use the fast register ferred to the program counter by an operation that stack for a subroutine call, a FAST CALL instruction writes PCL. Similarly, the upper two bytes of the pro- must be executed. gram counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful Example4-1 shows a source code example that uses for computed offsets to the PC (see Section4.8.1 the fast register stack. “Computed GOTO”). EXAMPLE 4-1: FAST REGISTER STACK 4.5 Clocking Scheme/Instruction CODE EXAMPLE Cycle CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER The clock input (from OSC1) is internally divided by ;STACK four to generate four non-overlapping quadrature  clocks, namely Q1, Q2, Q3 and Q4. Internally, the  program counter (PC) is incremented every Q1, the SUB1  instruction is fetched from the program memory and  latched into the instruction register in Q4. The instruc-  tion is decoded and executed during the following Q1 RETURN FAST ;RESTORE VALUES SAVED through Q4. The clocks and instruction execution flow ;IN FAST REGISTER STACK are shown in Figure4-5. FIGURE 4-5: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 PChloacske Q4 PC PC PC+2 PC+4 OSC2/CLKO (RC Mode) Execute INST (PC-2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+2) Fetch INST (PC+4) DS30491D-page 56  2003-2013 Microchip Technology Inc.

18F8680.book Page 57 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, In the execution cycle, the fetched instruction is latched Q2, Q3 and Q4). The instruction fetch and execute are into the “Instruction Register” (IR) in cycle Q1. This pipelined such that fetch takes one instruction cycle, instruction is then decoded and executed during the while decode and execute takes another instruction Q2, Q3, and Q4 cycles. Data memory is read during Q2 cycle. However, due to the pipelining each instruction (operand read) and written during Q4 (destination effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), write). then two cycles are required to complete the instruction (Example4-2). EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, 3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 4.7 Instructions in Program Memory The CALL and GOTO instructions have an absolute pro- gram memory address embedded into the instruction. The program memory is addressed in bytes. Instruc- Since instructions are always stored on word bound- tions are stored as two bytes or four bytes in program aries, the data contained in the instruction is a word memory. The Least Significant Byte (LSB) of an address. The word address is written to PC<20:1> instruction word is always stored in a program memory which accesses the desired byte address in program location with an even address (LSB = 0). Figure4-6 memory. Instruction #2 in Figure4-6 shows how the shows an example of how instruction words are stored instruction “GOTO 000006h” is encoded in the program in the program memory. To maintain alignment with memory. Program branch instructions which encode a instruction boundaries, the PC increments in steps of 2 relative address offset operate in the same manner. and the LSB will always read ‘0’ (see Section4.4 The offset value stored in a branch instruction repre- “PCL, PCLATH and PCLATU”). sents the number of single-word instructions that the PC will be offset by. Section25.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 4-6: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 000006h 0EFh 03h 00000Ah 0F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h 0C1h 23h 00000Eh 0F4h 56h 000010h 000012h 000014h  2003-2013 Microchip Technology Inc. DS30491D-page 57

18F8680.book Page 58 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.7.1 TWO-WORD INSTRUCTIONS accessed. If the second word of the instruction is exe- cuted by itself (first word was skipped), it will execute as The PIC18F6585/8585/6680/8680 devices have four a NOP. This action is necessary when the two-word two-word instructions: MOVFF, CALL, GOTO and instruction is preceded by a conditional instruction that LFSR. The second word of these instructions has the 4 changes the PC. A program example that demon- MSBs set to ‘1’s and is a special kind of NOP instruction. strates this concept is shown in Example4-3. Refer to The lower 12 bits of the second word contain data to be Section25.0 “Instruction Set Summary” for further used by the instruction. If the first word of the instruc- details of the instruction set. tion is executed, the data in the second word is EXAMPLE 4-3: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of REG2 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes 1111 0100 0101 0110 ; 2nd operand becomes NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code 4.8 Look-up Tables 4.8.2 TABLE READS/TABLE WRITES Look-up tables are implemented two ways. These are: A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction • Computed GOTO location. • Table Reads Look-up table data may be stored 2 bytes per program 4.8.1 COMPUTED GOTO word by using table reads and writes. The Table Pointer (TBLPTR) specifies the byte address and the Table A computed GOTO is accomplished by adding an offset Latch (TABLAT) contains the data that is read from, or to the program counter (ADDWF PCL). written to program memory. Data is transferred to/from A look-up table can be formed with an ADDWF PCL program memory, one byte at a time. instruction and a group of RETLW 0xnn instructions. A description of the table read/table write operation is WREG is loaded with an offset into the table before shown in Section5.0 “Flash Program Memory”. executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. DS30491D-page 58  2003-2013 Microchip Technology Inc.

18F8680.book Page 59 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.9 Data Memory Organization 4.9.1 GENERAL PURPOSE REGISTER FILE The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, The register file can be accessed either directly or indi- allowing up to 4096 bytes of data memory. Figure4-7 rectly. Indirect addressing operates using a File Select shows the data memory organization for the Register and corresponding Indirect File Operand. The PIC18F6585/8585/6680/8680 devices. operation of indirect addressing is shown in Section4.12 “Indirect Addressing, INDF and FSR The data memory map is divided into 16 banks that Registers”. contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be Enhanced MCU devices may have banked memory in accessed. The upper 4 bits for the BSR are not the GPR area. GPRs are not initialized by a Power-on implemented. Reset and are unchanged on all other Resets. The data memory contains Special Function Registers Data RAM is available for use as general purpose regis- (SFR) and General Purpose Registers (GPR). The ters by all instructions. The top section of Bank 15 SFRs are used for control and status of the controller (0F60h to 0FFFh) contains SFRs. All other banks of data and peripheral functions, while GPRs are used for data memory contain GPR registers, starting with Bank 0. storage and scratch pad operations in the user’s appli- 4.9.2 SPECIAL FUNCTION REGISTERS cation. The SFRs start at the last location of Bank 15 (0FFFh) and extend downwards. Any remaining space The Special Function Registers (SFRs) are registers beyond the SFRs in the Bank may be implemented as used by the CPU and peripheral modules for controlling GPRs. GPRs start at the first location of Bank 0 and the desired operation of the device. These registers are grow upwards. Any read of an unimplemented location implemented as static RAM. A list of these registers is will read as ‘0’s. given in Table4-2 and Table4-3. The entire data memory may be accessed directly or The SFRs can be classified into two sets: those asso- indirectly. Direct addressing may require the use of the ciated with the “core” function and those related to the BSR register. Indirect addressing requires the use of a peripheral functions. Those registers related to the File Select Register (FSRn) and a corresponding Indi- “core” are described in this section, while those related rect File Operand (INDFn). Each FSR holds a 12-bit to the operation of the peripheral features are address value that can be used to access any location described in the section of that peripheral feature. The in the data memory map without banking. SFRs are typically distributed among the peripherals The instruction set and architecture allow operations whose functions they control. across all banks. This may be accomplished by indirect The unused SFR locations are unimplemented and addressing or by the use of the MOVFF instruction. The read as ‘0’s. The addresses for the SFRs are listed in MOVFF instruction is a two-word/two-cycle instruction Table4-2. that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle regard- less of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section4.10 “Access Bank” provides a detailed description of the Access RAM.  2003-2013 Microchip Technology Inc. DS30491D-page 59

18F8680.book Page 60 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 4-7: DATA MEMORY MAP FOR PIC18FXX80/XX85 DEVICES BSR<3:0> Data Memory Map = 0000 00h Access RAM 00500Fhh Bank 0 060h GPRs FFh 0FFh 00h 100h = 0001 Bank 1 GPRs FFh 1FFh = 0010 00h 200h Bank 2 GPRs FFh 2FFh 00h 300h = 0011 Bank 3 GPRs FFh 3FFh 400h = 0100 Bank 4 GPRs Access Bank 4FFh 00h 500h Access RAM low 5Fh 60h Access RAM high (SFRs) FFh Bank 5 to Bank 12 GPRs When a = 0, CFFh the BSR is ignored and the = 1101 D00h Access Bank is used. Bank 13 CAN SFRs The first 96 bytes are General DFFh Purpose RAM (from Bank 0). = 1110 00h E00h The second 160 bytes are Bank 14 CAN SFRs Special Function Registers FFh EFFh (from Bank 15). = 1111 00h CAN SFRs FF50F0hh Bank 15 F60h FFh SFRs FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. DS30491D-page 60  2003-2013 Microchip Technology Inc.

18F8680.book Page 61 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2) FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —(1) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(2) FF9h PCL FD9h FSR2L FB9h —(1) F99h TRISH(2) FF8h TBLPTRU FD8h STATUS FB8h —(1) F98h TRISG FF7h TBLPTRH FD7h TMR0H FB7h —(1) F97h TRISF FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD FF4h PRODH FD4h —(1) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(2) FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(2) FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh LATG FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh LATF FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA FE8h WREG FC8h SSPADD FA8h EEDATA F88h PORTJ(2) FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2 F87h PORTH(2) FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h PORTG FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h PORTF FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register.  2003-2013 Microchip Technology Inc. DS30491D-page 61

18F8680.book Page 62 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name F7Fh SPBRGH F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F7Eh BAUDCON F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh —(1) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch —(1) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh —(1) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah —(1) F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h ECCP1DEL F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h —(1) F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh CANCON_RO1 F2Fh CANCON_RO3 F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTAT_RO1 F2Eh CANSTAT_RO3 F0Eh RXF3EIDH F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. DS30491D-page 62  2003-2013 Microchip Technology Inc.

18F8680.book Page 63 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name EFFh —(1) EDFh —(1) EBFh —(1) E9Fh —(1) EFEh —(1) EDEh —(1) EBEh —(1) E9Eh —(1) EFDh —(1) EDDh —(1) EBDh —(1) E9Dh —(1) EFCh —(1) EDCh —(1) EBCh —(1) E9Ch —(1) EFBh —(1) EDBh —(1) EBBh —(1) E9Bh —(1) EFAh —(1) EDAh —(1) EBAh —(1) E9Ah —(1) EF9h —(1) ED9h —(1) EB9h —(1) E99h —(1) EF8h —(1) ED8h —(1) EB8h —(1) E98h —(1) EF7h —(1) ED7h —(1) EB7h —(1) E97h —(1) EF6h —(1) ED6h —(1) EB6h —(1) E96h —(1) EF5h —(1) ED5h —(1) EB5h —(1) E95h —(1) EF4h —(1) ED4h —(1) EB4h —(1) E94h —(1) EF3h —(1) ED3h —(1) EB3h —(1) E93h —(1) EF2h —(1) ED2h —(1) EB2h —(1) E92h —(1) EF1h —(1) ED1h —(1) EB1h —(1) E91h —(1) EF0h —(1) ED0h —(1) EB0h —(1) E90h —(1) EEFh —(1) ECFh —(1) EAFh —(1) E8Fh —(1) EEEh —(1) ECEh —(1) EAEh —(1) E8Eh —(1) EEDh —(1) ECDh —(1) EADh —(1) E8Dh —(1) EECh —(1) ECCh —(1) EACh —(1) E8Ch —(1) EEBh —(1) ECBh —(1) EABh —(1) E8Bh —(1) EEAh —(1) ECAh —(1) EAAh —(1) E8Ah —(1) EE9h —(1) EC9h —(1) EA9h —(1) E89h —(1) EE8h —(1) EC8h —(1) EA8h —(1) E88h —(1) EE7h —(1) EC7h —(1) EA7h —(1) E87h —(1) EE6h —(1) EC6h —(1) EA6h —(1) E86h —(1) EE5h —(1) EC5h —(1) EA5h —(1) E85h —(1) EE4h —(1) EC4h —(1) EA4h —(1) E84h —(1) EE3h —(1) EC3h —(1) EA3h —(1) E83h —(1) EE2h —(1) EC2h —(1) EA2h —(1) E82h —(1) EE1h —(1) EC1h —(1) EA1h —(1) E81h —(1) EE0h —(1) EC0h —(1) EA0h —(1) E80h —(1) Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register.  2003-2013 Microchip Technology Inc. DS30491D-page 63

18F8680.book Page 64 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name E7Fh CANCON_RO4 E5Fh CANCON_RO6 E3Fh CANCON_RO8 E1Fh —(1) E7Eh CANSTAT_RO4 E5Eh CANSTAT_RO6 E3Eh CANSTAT_RO8 E1Eh —(1) E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh —(1) E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch —(1) E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh —(1) E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah —(1) E79h B5D3 E59h B3D3 E39h B1D3 E19h —(1) E78h B5D2 E58h B3D2 E38h B1D2 E18h —(1) E77h B5D1 E57h B3D1 E37h B1D1 E17h —(1) E76h B5D0 E56h B3D0 E36h B1D0 E16h —(1) E75h B5DLC E55h B3DLC E35h B1DLC E15h —(1) E74h B5EIDL E54h B3EIDL E34h B1EIDL E14h —(1) E73h B5EIDH E53h B3EIDH E33h B1EIDH E13h —(1) E72h B5SIDL E52h B3SIDL E32h B1SIDL E12h —(1) E71h B5SIDH E51h B3SIDH E31h B1SIDH E11h —(1) E70h B5CON E50h B3CON E30h B1CON E10h —(1) E6Fh CANCON_RO5 E4Fh CANCON_RO7 E2Fh CANCON_RO9 E0Fh —(1) E6Eh CANSTAT_RO5 E4Eh CANSTAT_RO7 E2Eh CANSTAT_RO9 E0Eh —(1) E6Dh B4D7 E4Dh B2D7 E2Dh B0D7 E0Dh —(1) E6Ch B4D6 E4Ch B2D6 E2Ch B0D6 E0Ch —(1) E6Bh B4D5 E4Bh B2D5 E2Bh B0D5 E0Bh —(1) E6Ah B4D4 E4Ah B2D4 E2Ah B0D4 E0Ah —(1) E69h B4D3 E49h B2D3 E29h B0D3 E09h —(1) E68h B4D2 E48h B2D2 E28h B0D2 E08h —(1) E67h B4D1 E47h B2D1 E27h B0D1 E07h —(1) E66h B4D0 E46h B2D0 E26h B0D0 E06h —(1) E65h B4DLC E45h B2DLC E25h B0DLC E05h —(1) E64h B4EIDL E44h B2EIDL E24h B0EIDL E04h —(1) E63h B4EIDH E43h B2EIDH E23h B0EIDH E03h —(1) E62h B4SIDL E42h B2SIDL E22h B0SIDL E02h —(1) E61h B4SIDH E41h B2SIDH E21h B0SIDH E01h —(1) E60h B4CON E40h B2CON E20h B0CON E00h —(1) Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. DS30491D-page 64  2003-2013 Microchip Technology Inc.

18F8680.book Page 65 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name DFFh —(1) DDFh —(1) DBFh —(1) D9Fh —(1) DFEh —(1) DDEh —(1) DBEh —(1) D9Eh —(1) DFDh —(1) DDDh —(1) DBDh —(1) D9Dh —(1) DFCh TXBIE DDCh —(1) DBCh —(1) D9Ch —(1) DFBh —(1) DDBh —(1) DBBh —(1) D9Bh —(1) DFAh BIE0 DDAh —(1) DBAh —(1) D9Ah —(1) DF9h —(1) DD9h —(1) DB9h —(1) D99h —(1) DF8h BSEL0 DD8h SDFLC DB8h —(1) D98h —(1) DF7h —(1) DD7h —(1) DB7h —(1) D97h —(1) DF6h —(1) DD6h —(1) DB6h —(1) D96h —(1) DF5h —(1) DD5h RXFCON1 DB5h —(1) D95h —(1) DF4h —(1) DD4h RXFCON0 DB4h —(1) D94h —(1) DF3h MSEL3 DD3h —(1) DB3h —(1) D93h RXF15EIDL DF2h MSEL2 DD2h —(1) DB2h —(1) D92h RXF15EIDH DF1h MSEL1 DD1h —(1) DB1h —(1) D91h RXF15SIDL DF0h MSEL0 DD0h —(1) DB0h —(1) D90h RXF15SIDH DEFh —(1) DCFh —(1) DAFh —(1) D8Fh —(1) DEEh —(1) DCEh —(1) DAEh —(1) D8Eh —(1) DEDh —(1) DCDh —(1) DADh —(1) D8Dh —(1) DECh —(1) DCCh —(1) DACh —(1) D8Ch —(1) DEBh —(1) DCBh —(1) DABh —(1) D8Bh RXF14EIDL DEAh —(1) DCAh —(1) DAAh —(1) D8Ah RXF14EIDH DE9h —(1) DC9h —(1) DA9h —(1) D89h RXF14SIDL DE8h —(1) DC8h —(1) DA8h —(1) D88h RXF14SIDH DE7h RXFBCON7 DC7h —(1) DA7h —(1) D87h RXF13EIDL DE6h RXFBCON6 DC6h —(1) DA6h —(1) D86h RXF13EIDH DE5h RXFBCON5 DC5h —(1) DA5h —(1) D85h RXF13SIDL DE4h RXFBCON4 DC4h —(1) DA4h —(1) D84h RXF13SIDH DE3h RXFBCON3 DC3h —(1) DA3h —(1) D83h RXF12EIDL DE2h RXFBCON2 DC2h —(1) DA2h —(1) D82h RXF12EIDH DE1h RXFBCON1 DC1h —(1) DA1h —(1) D81h RXF12SIDL DE0h RXFBCON0 DC0h —(1) DA0h —(1) D80h RXF12SIDH Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register.  2003-2013 Microchip Technology Inc. DS30491D-page 65

18F8680.book Page 66 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address Name Address Name Address Name D7Fh —(1) D7Eh —(1) D7Dh —(1) D7Ch —(1) D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh —(1) D6Eh —(1) D6Dh —(1) D6Ch —(1) D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. DS30491D-page 66  2003-2013 Microchip Technology Inc.

18F8680.book Page 67 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 36, 54 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 54 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 54 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 36, 55 PCLATU — — bit 21 Holding Register for PC<20:16> --00 0000 36, 56 PCLATH Holding Register for PC<15:8> 0000 0000 36, 56 PCL PC Low Byte (PC<7:0>) 0000 0000 36, 56 TBLPTRU — — bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 36, 86 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 36, 86 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 36, 86 TABLAT Program Memory Table Latch 0000 0000 36, 86 PRODH Product Register High Byte xxxx xxxx 36, 107 PRODL Product Register Low Byte xxxx xxxx 36, 107 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 36, 111 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 36, 112 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 36, 113 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 79 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) n/a 79 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) n/a 79 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 79 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented n/a 79 (not a physical register) – value of FSR0 offset by value in WREG FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 36, 79 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 36, 79 WREG Working Register xxxx xxxx 36 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) n/a 79 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) n/a 79 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) n/a 79 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) n/a 79 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented n/a 79 (not a physical register) – value of FSR1 offset by value in WREG FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 37, 79 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 37, 79 BSR — — — — Bank Select Register ---- 0000 37, 78 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) n/a 79 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) n/a 79 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) n/a 79 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) n/a 79 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented n/a 79 (not a physical register) – value of FSR2 offset by value in WREG FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 37, 79 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 37, 79 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 67

18F8680.book Page 68 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: STATUS — — — N OV Z DC C ---x xxxx 37, 81 TMR0H Timer0 Register High Byte 0000 0000 37, 157 TMR0L Timer0 Register Low Byte xxxx xxxx 37, 157 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 37, 155 OSCCON — — — — LOCK PLLEN SCS1 SCS ---- 0000 27, 37 LVDCON — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 271 WDTCON — — — — — — — SWDTE ---- ---0 37, 355 RCON IPEN — — RI TO PD POR BOR 0--1 11qq 37, 82, 123 TMR1H Timer1 Register High Byte xxxx xxxx 37, 159 TMR1L Timer1 Register Low Byte xxxx xxxx 37, 159 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 37, 159 TMR2 Timer2 Register 0000 0000 37, 162 PR2 Timer2 Period Register 1111 1111 37, 163 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 162 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 37, 189 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 37, 198 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 37, 199 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 37, 191 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 37, 201 ADRESH A/D Result Register High Byte xxxx xxxx 38, 257 ADRESL A/D Result Register Low Byte xxxx xxxx 38, 257 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 38, 249 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 38, 257 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 38, 251 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 38, 173 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 38, 172 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 38, 172 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 38, 172 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 38, 172 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 38, 172 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 38, 172 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 38, 265 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 38, 259 TMR3H Timer3 Register High Byte xxxx xxxx 38, 164 TMR3L Timer3 Register Low Byte xxxx xxxx 38, 164 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 38, 164 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 38, 153 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. DS30491D-page 68  2003-2013 Microchip Technology Inc.

18F8680.book Page 69 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRG USART Baud Rate Generator 0000 0000 38, 239 RCREG USART Receive Register 0000 0000 38, 241 TXREG USART Transmit Register 0000 0000 38, 239 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 38, 230 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 38, 231 EEADRH — — — — — — EE Adr Register High ---- --00 38, 105 EEADR Data EEPROM Address Register 0000 0000 38, 105 EEDATA Data EEPROM Data Register 0000 0000 38, 105 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 38, 105 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 00-0 x000 38, 102 IPR3 IRXIP WAKIP ERRIP TXB2IP/ TXB1IP TXB0IP RXB1IP/ RXB0IP/ 1111 1111 39, 122 TXBnIP RXBnIP FIFOWMIP PIR3 IRXIF WAKIF ERRIF TXB2IF/ TXB1IF TXB0IF RXB1IF/ RXB0IF/ 0000 0000 39, 116 TXBnIF RXBnIF FIFOWMIF PIE3 IRXIE WAKIE ERRIE TXB2IE/ TXB1IE TXB0IE RXB1IE/ RXB0IE/ 0000 0000 39, 119 TXBnIE RXBnIE FIFOWMIE IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 39, 121 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 39, 115 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 39, 118 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 39, 120 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 39, 114 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 39, 117 MEMCON(3) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 39, 94 TRISJ(3) Data Direction Control Register for PORTJ 1111 1111 39, 151 TRISH(3) Data Direction Control Register for PORTH 1111 1111 39, 148 TRISG — — — Data Direction Control Register for PORTG ---1 1111 39, 145 TRISF Data Direction Control Register for PORTF 1111 1111 39, 141 TRISE Data Direction Control Register for PORTE 1111 1111 39, 138 TRISD Data Direction Control Register for PORTD 1111 1111 39, 135 TRISC Data Direction Control Register for PORTC 1111 1111 39, 131 TRISB Data Direction Control Register for PORTB 1111 1111 39, 128 TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 39, 125 LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 39, 151 LATH(3) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 39, 148 LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 39, 145 LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 39, 141 LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 39, 138 LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 39, 133 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 39, 131 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 39, 128 LATA — LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 39, 125 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 69

18F8680.book Page 70 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 40, 151 PORTH(3) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 40, 148 PORTG — — RG5(6) Read PORTG pins, Write PORTG Data Latch --0x xxxx 40, 145 PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 40, 141 PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 40, 136 PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 40, 133 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 40, 131 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 40, 128 PORTA — RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 40, 125 SPBRGH Enhanced USART Baud Rate Generator High Byte 0000 0000 40, 233 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 40, 233 ECCP1DEL PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 40, 187 TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 40, 288 RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 40, 296 COMSTAT RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 40, 284 Mode 0 COMSTAT — RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN -000 0000 40, 284 Mode 1 COMSTAT FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 40, 284 Mode 2 CIOCON TX2SRC TX2EN ENDRHI CANCAP — — — — 0000 ---- 40, 318 BRGCON3 WAKDIS WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 40, 317 BRGCON2 SEG2PHT SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 40, 317 BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 40, 317 CANCON REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — 1000 000- 40, 239 Mode 0 CANCON REQOP2 REQOP1 REQOP0 ABAT — — — — 1000 ---- 40, 239 Mode 1 CANCON REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 1000 0000 40, 239 Mode 2 CANSTAT OPMODE2 OPMODE1 OPMODE0 — ICODE2 ICODE1 ICODE0 — 000- 0000 40, 239 Mode 0 CANSTAT OPMODE2 OPMODE1 OPMODE0 EICODE4 EICODE3 EICODE2 EICODE1 EICODE0 0000 0000 40, 239 Modes 0, 1 ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 0001 0000 40, 323 RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 40, 230 RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx 40, 230 RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx 40, 230 RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx 40, 230 RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx 40, 230 RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx 40, 230 RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx 40, 230 RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx 40, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. DS30491D-page 70  2003-2013 Microchip Technology Inc.

18F8680.book Page 71 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 40, 230 RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 41, 230 RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 41, 230 RXB0SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 41, 230 RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 41, 230 RXB0CON RXFUL RXM1 RXM0(4) —(4) RXRTRR0(4) RXB0DBEN(4) JTOFF(4) FILHIT0(4) 000- 0000 41, 230 Mode 0 RXB0CON RXFUL RXM1 RTRR0(4) FILHIT4(4) FILHIT3(4) FILHIT2(4) FILHIT1(4) FILHIT0(4) 0000 0000 41, 230 Mode 1, 2 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx 41, 230 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx 41, 230 RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 41, 230 RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 41, 230 RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 41, 230 RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx 41, 230 RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx 41, 230 RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx 41, 230 RXB1DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 41, 230 RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 41, 230 RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 41, 230 RXB1SIDL SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 41, 230 RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 41, 230 RXB1CON RXFUL RXM1 RXM0(4) —(4) RXRTRR0(4) FILHIT2(4) FILHIT1(4) FILHIT0(4) 000- 0000 41, 230 Mode 0 RXB1CON RXFUL RXM1 RTRRO(4) FILHIT4(4) FILHIT3(4) FILHIT2(4) FILHIT1(4) FILHIT0(4) 0000 0000 41, 230 Mode 1, 2 TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 41, 230 TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx 41, 230 TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx 41, 230 TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx 41, 230 TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx 41, 230 TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx 41, 230 TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx 41, 230 TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx 41, 230 TXB0DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 41, 230 TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 41, 230 TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 41, 230 TXB0SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xx-x x-xx 41, 230 TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 42, 230 TXB0CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 -000 0-00 42, 230 Mode 0 TXB0CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 42, 230 Mode 1, 2 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 71

18F8680.book Page 72 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 42, 230 TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx 42, 230 TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 42, 230 TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 42, 230 TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 42, 230 TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 42, 230 TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 42, 230 TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 42, 230 TXB1DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 42, 230 TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 42, 230 TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 42, 230 TXB1SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xx-x x-xx 42, 230 TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 42, 230 TXB1CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 -000 0-00 42, 230 Mode 0 TXB1CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 42, 230 Mode 1, 2 TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 42, 230 TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 42, 230 TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 42, 230 TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 42, 230 TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 42, 230 TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 42, 230 TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 42, 230 TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 42, 230 TXB2DLC — TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 42, 230 TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 42, 230 TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 42, 230 TXB2SIDL SID2 SID1 SID0 — EXIDE — EID17 EID16 xxx- x-xx 42, 230 TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 42, 230 TXB2CON — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 -000 0-00 42, 230 Mode 0 TXB2CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 42, 230 Mode 1, 2 RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 42, 230 RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXM1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x 0-xx 43, 230 RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXM0SIDL SID2 SID1 SID0 — EXIDM — EID17 EID16 xx-x 0-xx 43, 230 RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXF15EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. DS30491D-page 72  2003-2013 Microchip Technology Inc.

18F8680.book Page 73 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: RXF15EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230 RXF15SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 47, 230 RXF15SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 47, 230 RXF14EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 RXF14EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230 RXF14SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 47, 230 RXF14SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 47, 230 RXF13EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 RXF13EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230 RXF13SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 47, 230 RXF13SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 47, 230 RXF12EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 RXF12EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230 RXF12SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 47, 230 RXF12SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 47, 230 RXF11EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 RXF11EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230 RXF11SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 47, 230 RXF11SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 47, 230 RXF10EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 RXF10EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 47, 230 RXF10SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 48, 230 RXF10SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 48, 230 RXF9EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 47, 230 RXF9EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 48, 230 RXF9SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 48, 230 RXF9SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 48, 230 RXF8EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 48, 230 RXF8EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 48, 230 RXF8SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 48, 230 RXF8SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 48, 230 RXF7EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 48, 230 RXF7EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 48, 230 RXF7SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 48, 230 RXF7SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 48, 230 RXF6EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 48, 230 RXF6EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 48, 230 RXF6SIDL(7) SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 48, 230 RXF6SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 48, 230 RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 73

18F8680.book Page 74 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: RXF5SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230 RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXF4SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230 RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXF3SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230 RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXF2SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230 RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXF1SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230 RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 43, 230 RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 43, 230 RXF0SIDL SID2 SID1 SID0 — EXIDEN — EID17 EID16 xx-x x-xx 43, 230 RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 43, 230 B5D7(7) B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 xxxx xxxx 44, 230 B5D6(7) B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 xxxx xxxx 44, 230 B5D5(7) B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 xxxx xxxx 44, 230 B5D4(7) B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 xxxx xxxx 44, 230 B5D3(7) B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 xxxx xxxx 44, 230 B5D2(7) B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 xxxx xxxx 44, 230 B5D1(7) B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 xxxx xxxx 44, 230 B5D0(7) B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 xxxx xxxx 44, 230 B5DLC(7) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 44, 230 B5EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 44, 230 B5EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 44, 230 B5SIDL(7) SID2 SID1 SID0 SRR EXID/ — EID17 EID16 xxxx x-xx 44, 230 EXIDE(5) B5SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 44, 230 B5CON(5, 7) RXFUL/ RXM1/ RTRRO/ FILHIT4/ FILHIT3/ FILHIT2/ FILHIT1/ FILHIT0/ 0000 0000 44, 230 TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 B4D7(7) B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 xxxx xxxx 44, 230 B4D6(7) B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 xxxx xxxx 44, 230 B4D5(7) B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 xxxx xxxx 44, 230 B4D4(7) B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 xxxx xxxx 44, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. DS30491D-page 74  2003-2013 Microchip Technology Inc.

18F8680.book Page 75 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: B4D3(7) B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 xxxx xxxx 44, 230 B4D2(7) B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 xxxx xxxx 44, 230 B4D1(7) B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 xxxx xxxx 44, 230 B4D0(7) B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 xxxx xxxx 44, 230 B4DLC(7) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 44, 230 B4EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 44, 230 B4EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 44, 230 B4SIDL(7) SID2 SID1 SID0 SRR EXID/ — EID17 EID16 xxxx x-xx 44, 230 EXIDE(5) B4SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 44, 230 B4CON(5, 7) RXFUL/ RXM1/ RTRRO/ FILHIT4/ FILHIT3/ FILHIT2/ FILHIT1/ FILHIT0/ 0000 0000 44, 230 TXB3IF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 B3D7(7) B3D77 B3D76 B3D75 B3D74 B3D73 B3D72 B3D71 B3D70 xxxx xxxx 44, 230 B3D6(7) B3D67 B3D66 B3D65 B3D64 B3D63 B3D62 B3D61 B3D60 xxxx xxxx 44, 230 B3D5(7) B3D57 B3D56 B3D55 B3D54 B3D53 B3D52 B3D51 B3D50 xxxx xxxx 44, 230 B3D4(7) B3D47 B3D46 B3D45 B3D44 B3D43 B3D42 B3D41 B3D40 xxxx xxxx 45, 230 B3D3(7) B3D37 B3D36 B3D35 B3D34 B3D33 B3D32 B3D31 B3D30 xxxx xxxx 45, 230 B3D2(7) B3D27 B3D26 B3D25 B3D24 B3D23 B3D22 B3D21 B3D20 xxxx xxxx 45, 230 B3D1(7) B3D17 B3D16 B3D15 B3D14 B3D13 B3D12 B3D11 B3D10 xxxx xxxx 45, 230 B3D0(7) B3D07 B3D06 B3D05 B3D04 B3D03 B3D02 B3D01 B3D00 xxxx xxxx 45, 230 B3DLC(7) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 45, 230 B3EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 45, 230 B3EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 45, 230 B3SIDL(7) SID2 SID1 SID0 SRR EXID/ — EID17 EID16 xxxx x-xx 45, 230 EXIDE(5) B3SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 45, 230 B3CON(5, 7) RXFUL/ RXM1/ RTRRO/ FILHIT4/ FILHIT3/ FILHIT2/ FILHIT1/ FILHIT0/ 0000 0000 45, 230 TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 B2D7(7) B2D77 B2D76 B2D75 B2D74 B2D73 B2D72 B2D71 B2D70 xxxx xxxx 45, 230 B2D6(7) B2D67 B2D66 B2D65 B2D64 B2D63 B2D62 B2D61 B2D60 xxxx xxxx 45, 230 B2D5(7) B2D57 B2D56 B2D55 B2D54 B2D53 B2D52 B2D51 B2D50 xxxx xxxx 45, 230 B2D4(7) B2D47 B2D46 B2D45 B2D44 B2D43 B2D42 B2D41 B2D40 xxxx xxxx 45, 230 B2D3(7) B2D37 B2D36 B2D35 B2D34 B2D33 B2D32 B2D31 B2D30 xxxx xxxx 45, 230 B2D2(7) B2D27 B2D26 B2D25 B2D24 B2D23 B2D22 B2D21 B2D20 xxxx xxxx 45, 230 B2D1(7) B2D17 B2D16 B2D15 B2D14 B2D13 B2D12 B2D11 B2D10 xxxx xxxx 45, 230 B2D0(7) B2D07 B2D06 B2D05 B2D04 B2D03 B2D02 B2D01 B2D00 xxxx xxxx 45, 230 B2DLC(7) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 45, 230 B2EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 45, 230 B2EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 45, 230 B2SIDL(7) SID2 SID1 SID0 SRR EXID/ — EID17 EID16 xxxx x-xx 45, 230 EXIDE(5) B2SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 45, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 75

18F8680.book Page 76 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: B2CON(5, 7) RXFUL/ RXM1/ RTRRO/ FILHIT4/ FILHIT3/ FILHIT2/ FILHIT1/ FILHIT0/ 0000 0000 45, 230 TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 B1D7(7) B1D77 B1D76 B1D75 B1D74 B1D73 B1D72 B1D71 B1D70 xxxx xxxx 45, 230 B1D6(7) B1D67 B1D66 B1D65 B1D64 B1D63 B1D62 B1D61 B1D60 xxxx xxxx 45, 230 B1D5(7) B1D57 B1D56 B1D55 B1D54 B1D53 B1D52 B1D51 B1D50 xxxx xxxx 45, 230 B1D4(7) B1D47 B1D46 B1D45 B1D44 B1D43 B1D42 B1D41 B1D40 xxxx xxxx 45, 230 B1D3(7) B1D37 B1D36 B1D35 B1D34 B1D33 B1D32 B1D31 B1D30 xxxx xxxx 45, 230 B1D2(7) B1D27 B1D26 B1D25 B1D24 B1D23 B1D22 B1D21 B1D20 xxxx xxxx 45, 230 B1D1(7) B1D17 B1D16 B1D15 B1D14 B1D13 B1D12 B1D11 B1D10 xxxx xxxx 46, 230 B1D0(7) B1D07 B1D06 B1D05 B1D04 B1D03 B1D02 B1D01 B1D00 xxxx xxxx 46, 230 B1DLC(7) — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 46, 230 B1EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 46, 230 B1EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 46, 230 B1SIDL(7) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 46, 230 B1SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 46, 230 B1CON(5, 7) RXFUL/ RXM1/ RTRRO/ FILHIT4/ FILHIT3/ FILHIT2/ FILHIT1/ FILHIT0/ 0000 0000 46, 230 TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 B0D7(7) B0D77 B0D76 B0D75 B0D74 B0D73 B0D72 B0D71 B0D70 xxxx xxxx 46, 230 B0D6(7) B0D67 B0D66 B0D65 B0D64 B0D63 B0D62 B0D61 B0D60 xxxx xxxx 46, 230 B0D5(7) B0D57 B0D56 B0D55 B0D54 B0D53 B0D52 B0D51 B0D50 xxxx xxxx 46, 230 B0D4(7) B0D47 B0D46 B0D45 B0D44 B0D43 B0D42 B0D41 B0D40 xxxx xxxx 46, 230 B0D3(7) B0D37 B0D36 B0D35 B0D34 B0D33 B0D32 B0D31 B0D30 xxxx xxxx 46, 230 B0D2(7) B0D27 B0D26 B0D25 B0D24 B0D23 B0D22 B0D21 B0D20 xxxx xxxx 46, 230 B0D1(7) B0D17 B0D16 B0D15 B0D14 B0D13 B0D12 B0D11 B0D10 xxxx xxxx 46, 230 B0D0(7) B0D07 B0D06 B0D05 B0D04 B0D03 B0D02 B0D01 B0D00 xxxx xxxx 46, 230 B0DLC(7) — RTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 46, 230 B0EIDL(7) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 46, 230 B0EIDH(7) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 46, 230 B0SIDL(7) SID2 SID1 SID0 SRR EXID — EID17 EID16 xxxx x-xx 46, 230 B0SIDH(7) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 46, 230 B0CON(5, 7) RXFUL/ RXM1/ RTRRO/ FILHIT4/ FILHIT3/ FILHIT2/ FILHIT1/ FILHIT0/ 0000 0000 46, 230 TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 TXBIE(7) — — — TXB2IE TXB1IE TXB0IE — — ---0 00-- 46, 230 BIE0(7) B5IE B4IE B3IE B2IE B1IE B0IE RXB1IE RXB0IE 0000 0000 46, 230 BSEL0(7) B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — — 0000 00-- 46, 230 MSEL3(7) FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 0000 0000 46, 230 MSEL2(7) FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 0000 0000 46, 230 MSEL1(7) FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 0000 0101 46, 230 MSEL0(7) FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 0101 0000 46, 230 SDFLC(7) — — — DFLC4 DFLC3 DFLC2 DFLC1 DFLC0 ---0 0000 46, 230 RXFCON1(7) RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN 0000 0000 46, 230 RXFCON0(7) RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN 0011 1111 47, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. DS30491D-page 76  2003-2013 Microchip Technology Inc.

18F8680.book Page 77 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: RXFBCON7(7) F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_01 0000 0000 47, 230 RXFBCON6(7) F13BP_3 F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_01 0000 0000 47, 230 RXFBCON5(7) F11BP_3 F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_01 0000 0000 47, 230 RXFBCON4(7) F9BP_3 F9BP_2 F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_01 0000 0000 47, 230 RXFBCON3(7) F7BP_3 F7BP_2 F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_01 0000 0000 47, 230 RXFBCON2(7) F5BP_3 F5BP_2 F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_01 0000 0000 47, 230 RXFBCON1(7) F3BP_3 F3BP_2 F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_01 0000 0000 47, 230 RXFBCON0(7) F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_01 0000 0000 47, 230 Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X80 devices; always maintain these clear. 4: These bits have multiple functions depending on the CAN module mode selection. 5: Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.  2003-2013 Microchip Technology Inc. DS30491D-page 77

18F8680.book Page 78 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement The need for a large general purpose memory space which is very useful for C compiler code optimization. dictates a RAM banking scheme. The data memory is The techniques used by the C compiler may also be partitioned into sixteen banks. When using direct useful for programs written in assembly. addressing, the BSR should be configured for the desired bank. This data memory region can be used for: BSR<3:0> holds the upper 4 bits of the 12-bit RAM • Intermediate computational values address. The BSR<7:4> bits will always read ‘0’s and • Local variables of subroutines writes will have no effect. • Faster context saving/switching of variables A MOVLB instruction has been provided in the • Common variables instruction set to assist in selecting banks. • Faster evaluation/control of SFRs (no banking) If the currently selected bank is not implemented, any The Access Bank is comprised of the upper 160 bytes read will return all ‘0’s and all writes are ignored. The in Bank 15 (SFRs) and the lower 96 bytes in Bank 0. Status register bits will be set/cleared as appropriate for These two sections will be referred to as Access RAM the instruction performed. High and Access RAM Low, respectively. Figure4-7 Each Bank extends up to 0FFh (256 bytes). All data indicates the Access RAM areas. memory is implemented as static RAM. A bit in the instruction word specifies if the operation is A MOVFF instruction ignores the BSR since the 12-bit to occur in the bank specified by the BSR register or in addresses are embedded into the instruction word. the Access Bank. This bit is denoted by the ‘a’ bit (for access bit). Section4.12 “Indirect Addressing, INDF and FSR When forced in the Access Bank (a = 0), the last Registers” provides a description of indirect address- ing which allows linear addressing of the entire RAM address in Access RAM Low is followed by the first space. address in Access RAM High. Access RAM High maps the Special Function Registers so that these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. FIGURE 4-8: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 From Opcode(3) 0 Bank Select(2) Location Select(3) 00h 01h 0Eh 0Fh 000h 100h E00h F00h Data Memory(1) 0FFh 1FFh EFFh FFFh Bank 0 Bank 1 Bank 14 Bank 15 Note 1: For register file map detail, see Table4-2. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS30491D-page 78  2003-2013 Microchip Technology Inc.

18F8680.book Page 79 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.12 Indirect Addressing, INDF and the data from the address pointed to by FSR Registers FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. Indirect addressing is a mode of addressing data mem- If INDF0, INDF1, or INDF2 are read indirectly via an ory where the data memory address in the instruction FSR, all ‘0’s are read (zero bit is set). Similarly, if is not fixed. An FSR register is used as a pointer to the INDF0, INDF1, or INDF2 are written to indirectly, the data memory location that is to be read or written. Since operation will be equivalent to a NOP instruction and the this pointer is in RAM, the contents can be modified by Status bits are not affected. the program. This can be useful for data tables in the data memory and for software stacks. Figure4-9 4.12.1 INDIRECT ADDRESSING shows the operation of indirect addressing. This shows OPERATION the moving of the value to the data memory address specified by the value of the FSR register. Each FSR register has an INDF register associated with it plus four additional register addresses. Indirect addressing is possible by using one of the Performing an operation on one of these five registers INDF registers. Any instruction using the INDF register determines how the FSR will be modified during actually accesses the register pointed to by the File indirect addressing. Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF When data access is done to one of the five INDFn register indirectly, results in a no operation. The FSR locations, the address selected will configure the FSRn register contains a 12-bit address which is shown in register to: Figure4-10. • Do nothing to FSRn after an indirect access (no The INDFn register is not a physical register. Address- change) – INDFn. ing INDFn actually addresses the register whose • Auto-decrement FSRn after an indirect access address is contained in the FSRn register (FSRn is a (post-decrement) – POSTDECn. pointer). This is indirect addressing. • Auto-increment FSRn after an indirect access Example4-4 shows a simple use of indirect addressing (post-increment) – POSTINCn. to clear the RAM in Bank 1 (locations 100h-1FFh) in a • Auto-increment FSRn before an indirect access minimum number of instructions. (pre-increment) – PREINCn. • Use the value in the WREG register as an offset EXAMPLE 4-4: HOW TO CLEAR RAM to FSRn. Do not modify the value of the WREG or (BANK 1) USING the FSRn register after an indirect access (no INDIRECT ADDRESSING change) – PLUSWn. LFSR FSR0, 100h ; When using the auto-increment or auto-decrement fea- NEXT CLRF POSTINC0 ; Clear INDF tures, the effect on the FSR is not reflected in the Status ; register and register. For example, if the indirect address causes the ; inc pointer FSR to equal ‘0’, the Z bit will not be set. BTFSS FSR0H, 1 ; All done with ; Bank1? Incrementing or decrementing an FSR affects all BRA NEXT ; NO, clear next 12bits. That is, when FSRnL overflows from an CONTINUE ; YES, continue increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a There are three Indirect Addressing registers. To stack pointer in addition to its uses for table operations address the entire data memory space (4096 bytes), in data memory. these registers are 12-bits wide. To store the 12 bits of addressing information, two 8-bit registers are Each FSR has an address associated with it that required. These Indirect Addressing registers are: performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the 1. FSR0: composed of FSR0H:FSR0L FSRn is configured to add the signed value in the 2. FSR1: composed of FSR1H:FSR1L WREG register and the value in FSR to form the 3. FSR2: composed of FSR2H:FSR2L address before an indirect access. The FSR value is In addition, there are registers INDF0, INDF1 and not changed. INDF2 which are not physically implemented. Reading If an FSR register contains a value that points to one of or writing to these registers activates indirect address- the INDFn, an indirect read will read 00h (zero bit is ing with the value in the corresponding FSR register set), while an indirect write will be equivalent to a NOP being the address of the data. If an instruction writes a (Status bits are not affected). value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads  2003-2013 Microchip Technology Inc. DS30491D-page 79

18F8680.book Page 80 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions. FIGURE 4-9: INDIRECT ADDRESSING OPERATION 0h RAM Instruction Executed Opcode Address 0FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> 12 12 Instruction Fetched 4 8 Opcode File FSR FIGURE 4-10: INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table4-2. DS30491D-page 80  2003-2013 Microchip Technology Inc.

18F8680.book Page 81 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.13 Status Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register The Status register, shown in Register4-3, contains the as 000u u1uu (where u = unchanged). arithmetic status of the ALU. The Status register can be It is recommended, therefore, that only BCF, BSF, the destination for any instruction as with any other reg- SWAPF, MOVFF and MOVWF instructions are used to ister. If the Status register is the destination for an alter the Status register because these instructions do instruction that affects the Z, DC, C, OV or N bits, then not affect the Z, C, DC, OV or N bits from the Status the write to these five bits is disabled. These bits are set register. For other instructions not affecting any status or cleared according to the device logic. Therefore, the bits, see Table25-2. result of an instruction with the Status register as destination may be different than intended. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-3: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions: 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 81

18F8680.book Page 82 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.14 RCON Register Note1: It is recommended that the POR bit be set The Reset Control (RCON) register contains flag bits after a Power-on Reset has been that allow differentiation between the sources of a detected so that subsequent Power-on device Reset. These flags include the TO, PD, POR, Resets may be detected. BOR and RI bits. This register is readable and writable. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assum- ing that POR was set to ‘1’ by software immediately after POR). REGISTER 4-4: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 82  2003-2013 Microchip Technology Inc.

18F8680.book Page 83 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.0 FLASH PROGRAM MEMORY 5.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 8 bytes at a time. Program memory is erased The program memory space is 16 bits wide, while the in blocks of 64 bytes at a time. A bulk erase operation data RAM space is 8-bits wide. Table reads and table cannot be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and places it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure5-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding location that forms an invalid instruction results in a registersinto program memory is detailed in NOP. Section5.5 “Writing to Flash Program Memory”. Figure5-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 5-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory.  2003-2013 Microchip Technology Inc. DS30491D-page 83

18F8680.book Page 84 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section5.5 “Writing to Flash Program Memory”. 5.2 Control Registers The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase Several control registers are used in conjunction with operation is initiated on the next WR command. When the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled. • EECON1 register The WREN bit, when set, will allow a write operation. • EECON2 register On power-up, the WREN bit is clear. The WRERR bit is • TABLAT register set when a write operation is interrupted by a MCLR • TBLPTR registers Reset or a WDT Time-out Reset during normal opera- tion. In these situations, the user can check the 5.2.1 EECON1 AND EECON2 REGISTERS WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EECON1 is the control register for memory accesses. EEADR) due to Reset values of zero. EECON2 is not a physical register. Reading EECON2 The WR control bit initiates write operations. The bit will read all ‘0’s. The EECON2 register is used cannot be cleared, only set in software; it is cleared in exclusively in the memory write and erase sequences. hardware at the completion of the write operation. The Control bit EEPGD determines if the access will be a inability to clear the WR bit in software prevents the program or data EEPROM memory access. When accidental or premature termination of a write clear, any subsequent operations will operate on the operation. data EEPROM memory. When set, any subsequent Note: Interrupt flag bit, EEIF in the PIR2 register, operations will operate on the program memory. is set when the write is complete. It must Control bit CFGS determines if the access will be to the be cleared in software. configuration/calibration registers or to program memory/data EEPROM memory. When set, subse- quent operations will operate on configuration registers regardless of EEPGD (see Section24.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. DS30491D-page 84  2003-2013 Microchip Technology Inc.

18F8680.book Page 85 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ W = Writable bit S = Settable bit - n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 85

18F8680.book Page 86 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.2.2 TABLAT – TABLE LATCH REGISTER 5.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch is used to hold 8- Flash program memory. bit data during data transfers between program When a TBLRD is executed, all 22 bits of the table memory and data RAM. pointer determine which byte is read from program memory into TABLAT. 5.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight The Table Pointer (TBLPTR) addresses a byte within program memory holding registers is written to. When the program memory. The TBLPTR is comprised of the timed write to program memory (long write) begins, three SFR registers: Table Pointer Upper Byte, Table the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will Pointer High Byte and Table Pointer Low Byte determine which program memory block of 8 bytes is (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- written to. For more detail, see Section5.5 “Writing to ters join to form a 22-bit wide pointer. The low-order Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the device ID, the user ID and the configuration bits. 16MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer, TBLPTR, is used by the TBLRD and Significant bits (TBLPTR<5:0>) are ignored. TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table opera- Figure5-3 describes the relevant boundaries of tion. These operations are shown in Table5-1. These TBLPTR based on Flash program memory operations. operations on the TBLPTR only affect the low-order 21bits. TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 5-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE – TBLPTR<20:6> WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> DS30491D-page 86  2003-2013 Microchip Technology Inc.

18F8680.book Page 87 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure5-4 shows the interface between the internal program memory and the TABLAT. FIGURE 5-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register FETCH TBLRD TABLAT (IR) Read Register EXAMPLE 5-1: READING A FLASH PROGRAM MEMORY WORD MOVLW upper(CODE_ADDR) ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW high(CODE_ADDR) MOVWF TBLPTRH MOVLW low(CODE_ADDR_LOW) MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF LSB TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF MSB  2003-2013 Microchip Technology Inc. DS30491D-page 87

18F8680.book Page 88 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.4 Erasing Flash Program Memory 5.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer or through The sequence of events for erasing a block of internal ICSP control can larger blocks of program memory be program memory location is: bulk erased. Word erase in the Flash array is not 1. Load table pointer with address of row being supported. erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase controller itself, a block of 64 bytes of program memory operation: is erased. The Most Significant 16 bits of the • set EEPGD bit to point to program memory; TBLPTR<21:6> point to the block being erased. • clear the CFGS bit to access program memory; TBLPTR<5:0> are ignored. • set WREN bit to enable writes; The EECON1 register commands the erase operation. • set FREE bit to enable the erase. The EEPGD bit must be set to point to the Flash 3. Disable interrupts. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 4. Write 55h to EECON2. operation. 5. Write 0AAh to EECON2. For protection, the write initiate sequence for EECON2 6. Set the WR bit. This will begin the row erase must be used. cycle. 7. The CPU will stall for duration of the erase A long write is necessary for erasing the internal Flash. (about 2ms using internal timer). Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal 8. Execute a NOP. programming timer. 9. Re-enable interrupts. EXAMPLE 5-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW upper(CODE_ADDR) ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW high(CODE_ADDR) MOVWF TBLPTRH MOVLW low(CODE_ADDR) MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h Required MOVLW 0AAh Sequence MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DS30491D-page 88  2003-2013 Microchip Technology Inc.

18F8680.book Page 89 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.5 Writing to Flash Program Memory the holding registers are written. At the end of updating eight registers, the EECON1 register must be written The minimum programming block is 4 words or 8 bytes. to, to start the programming operation with a long write. Word or byte programming is not supported. The long write is necessary for programming the inter- Table writes are used internally to load the holding nal Flash. Instruction execution is halted while in a long registers needed to program the Flash memory. There write cycle. The long write will be terminated by the are eight holding registers used by the table writes for internal programming timer. programming. The EEPROM on-chip timer controls the write time. Since the Table Latch (TABLAT) is only a single byte, The write/erase voltages are generated by an on-chip the TBLWT instruction has to be executed 8 times for charge pump, rated to operate over the voltage range each programming operation. All of the table write of the device for byte or word operations. operations will essentially be short writes because only FIGURE 5-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxxx7 Holding Register Holding Register Holding Register Holding Register Program Memory  2003-2013 Microchip Technology Inc. DS30491D-page 89

18F8680.book Page 90 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write (about 5ms using internal timer). 2. Update data values in RAM as necessary. 13. Execute a NOP. 3. Load table pointer with address being erased. 14. Re-enable interrupts. 4. Do the row erase procedure. 15. Repeat steps 6-14 seven times to write 64bytes. 5. Load table pointer with address of first byte being written. 16. Verify the memory (table read). 6. Write the first 8 bytes into the holding registers This procedure will require about 40ms to update one with auto-increment. row of 64 bytes of memory. An example of the required 7. Set the EECON1 register for the write operation: code is given in Example5-3. • set EEPGD bit to point to program memory; Note: Before setting the WR bit, the Table • clear the CFGS bit to access program memory; Pointer address needs to be within the • set WREN to enable byte writes. intended address range of the eight bytes in the holding register. EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D’64 ; number of bytes in erase block MOVWF COUNTER MOVLW high(BUFFER_ADDR) ; point to buffer MOVWF FSR0H MOVLW low(BUFFER_ADDR) MOVWF FSR0L MOVLW upper(CODE_ADDR) ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW high(CODE_ADDR) MOVWF TBLPTRH MOVLW low(CODE_ADDR) MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLW high(DATA_ADDR) ; point to buffer MOVWF FSR0H MOVLW low(DATA_ADDR) MOVWF FSR0L MOVLW low(NEW_DATA) ; update buffer word MOVWF POSTINC0 MOVLW high(NEW_DATA) MOVWF INDF0 DS30491D-page 90  2003-2013 Microchip Technology Inc.

18F8680.book Page 91 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) ERASE_BLOCK MOVLW upper(CODE_ADDR) ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW high(CODE_ADDR) MOVWF TBLPTRH MOVLW low(CODE_ADDR) MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55H Required MOVLW 0AAh Sequence MOVWF EECON2 ; write AAH BSF EECON1, WR ; start erase (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement WRITE_BUFFER_BACK MOVLW 8 ; number of write buffer groups of 8 bytes MOVWF COUNTER_HI MOVLW high(BUFFER_ADDR) ; point to buffer MOVWF FSR0H MOVLW low(BUFFER_ADDR) MOVWF FSR0L PROGRAM_LOOP MOVLW 8 ; number of bytes in holding register MOVWF COUNTER WRITE_WORD_TO_HREGS MOVFW POSTINC0, W ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h Required MOVLW 0AAh Sequence MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) NOP BSF INTCON, GIE ; re-enable interrupts DECFSZ COUNTER_HI ; loop until done BRA PROGRAM_LOOP BCF EECON1, WREN ; disable write to memory  2003-2013 Microchip Technology Inc. DS30491D-page 91

18F8680.book Page 92 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.5.2 WRITE VERIFY 5.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the mem- To protect against spurious writes to Flash program ory should be verified against the original value. This memory, the write initiate sequence must also be should be used in applications where excessive writes followed. See Section24.0 “Special Features of the can stress bits near the specification limit. CPU” for more detail. 5.5.3 UNEXPECTED TERMINATION OF 5.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section24.0 “Special Features of the CPU” for location just programmed should be verified and repro- details on code protection of Flash program memory. grammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte --00 0000 --00 0000 (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 0000 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. DS30491D-page 92  2003-2013 Microchip Technology Inc.

18F8680.book Page 93 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.0 EXTERNAL MEMORY 6.1 Program Memory Modes and the INTERFACE External Memory Interface As previously noted, PIC18F8X8X controllers are Note: The external memory interface is not capable of operating in any one of four program mem- implemented on PIC18F6X8X (64/68-pin) ory modes using combinations of on-chip and external devices. program memory. The functions of the multiplexed port The external memory interface is a feature of the pins depend on the program memory mode selected as PIC18F8X8X devices that allows the controller to well as the setting of the EBDIS bit. access external memory devices (such as Flash, In Microprocessor Mode, the external bus is always EPROM, SRAM, etc.) as program memory. active and the port pins have only the external bus The physical implementation of the interface uses function. 27pins. These pins are reserved for external address/ In Microcontroller Mode, the bus is not active and the data bus functions; they are multiplexed with I/O port pins have their port functions only. Writes to the pins on four ports. Three I/O ports are multiplexed with MEMCOM register are not permitted. the address/data bus, while the fourth port is multi- plexed with the bus control signals. The I/O port func- In Microprocessor with Boot Block or Extended tions are enabled when the EBDIS bit in the MEMCON Microcontroller Mode, the external program memory register is set (see Register6-1). A list of the bus shares I/O port functions on the pins. When the multiplexed pins and their functions is provided in device is fetching or doing table read/table write Table6-1. operations on the external program memory space, the pins will have the external bus function. If the device is As implemented in the PIC18F8X8X devices, the fetching and accessing internal program memory interface operates in a similar manner to the external locations only, the EBDIS control bit will change the memory interface introduced on PIC18C601/801 pins from external memory to I/O port functions. When microcontrollers. The most notable difference is that EBDIS = 0, the pins function as the external bus. When the interface on PIC18F8X8X devices only operates in EBDIS = 1, the pins function as I/O ports. 16-bit modes. The 8-bit mode is not supported. For a more complete discussion of the operating modes that use the external memory interface, refer to Section4.1.1 “PIC18F8X8X Program Memory Modes”.  2003-2013 Microchip Technology Inc. DS30491D-page 93

18F8680.book Page 94 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 6-1: MEMCON REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS(1) — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 bit 7 EBDIS: External Bus Disable bit(1) 1 = External system bus disabled, all external bus drivers are mapped as I/O ports 0 = External system bus enabled and I/O ports are disabled Note1: This bit is ignored when device is accessing external memory either to fetch an instruction or perform TBLRD/TBLWT. bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM<1:0>: TBLWT Operation with 16-bit Bus bits 1x =Word Write mode: LSB and MSB word output, WRH active when MSB written 01 =Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB) will activate 00 =Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: The MEMCON register is held in Reset in Microcontroller mode. DS30491D-page 94  2003-2013 Microchip Technology Inc.

18F8680.book Page 95 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If the device fetches or accesses external memory When the device is executing out of internal memory while EBDIS = 1, the pins will switch to external bus. If (with EBDIS = 0) in Microprocessor with Boot Block the EBDIS bit is set by a program executing from exter- mode or Extended Microcontroller mode, the control sig- nal memory, the action of setting the bit will be delayed nals will be in inactive. They will go to a state where the until the program branches into the internal memory. At AD<15:0>, A<19:16> are tri-state; the OE, WRH, WRL, that time, the pins will change from external bus to I/O UB and LB signals are ‘1’; and ALE and BA0 are ‘0’. ports. TABLE 6-1: PIC18F8X8X EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit Function RD0/AD0 PORTD bit 0 Input/Output or System Bus Address bit 0 or Data bit 0 RD1/AD1 PORTD bit 1 Input/Output or System Bus Address bit 1 or Data bit 1 RD2/AD2 PORTD bit 2 Input/Output or System Bus Address bit 2 or Data bit 2 RD3/AD3 PORTD bit 3 Input/Output or System Bus Address bit 3 or Data bit 3 RD4/AD4 PORTD bit 4 Input/Output or System Bus Address bit 4 or Data bit 4 RD5/AD5 PORTD bit 5 Input/Output or System Bus Address bit 5 or Data bit 5 RD6/AD6 PORTD bit 6 Input/Output or System Bus Address bit 6 or Data bit 6 RD7/AD7 PORTD bit 7 Input/Output or System Bus Address bit 7 or Data bit 7 RE0/AD8 PORTE bit 0 Input/Output or System Bus Address bit 8 or Data bit 8 RE1/AD9 PORTE bit 1 Input/Output or System Bus Address bit 9 or Data bit 9 RE2/AD10 PORTE bit 2 Input/Output or System Bus Address bit 10 or Data bit 10 RE3/AD11 PORTE bit 3 Input/Output or System Bus Address bit 11 or Data bit 11 RE4/AD12 PORTE bit 4 Input/Output or System Bus Address bit 12 or Data bit 12 RE5/AD13 PORTE bit 5 Input/Output or System Bus Address bit 13 or Data bit 13 RE6/AD14 PORTE bit 6 Input/Output or System Bus Address bit 14 or Data bit 14 RE7/AD15 PORTE bit 7 Input/Output or System Bus Address bit 15 or Data bit 15 RH0/A16 PORTH bit 0 Input/Output or System Bus Address bit 16 RH1/A17 PORTH bit 1 Input/Output or System Bus Address bit 17 RH2/A18 PORTH bit 2 Input/Output or System Bus Address bit 18 RH3/A19 PORTH bit 3 Input/Output or System Bus Address bit 19 RJ0/ALE PORTJ bit 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin RJ1/OE PORTJ bit 1 Input/Output or System Bus Output Enable (OE) Control pin RJ2/WRL PORTJ bit 2 Input/Output or System Bus Write Low (WRL) Control pin RJ3/WRH PORTJ bit 3 Input/Output or System Bus Write High (WRH) Control pin RJ4/BA0 PORTJ bit 4 Input/Output or System Bus Byte Address bit 0 RJ5/CE PORTJ bit 5 Input/Output or Chip Enable RJ6/LB PORTJ bit 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin  2003-2013 Microchip Technology Inc. DS30491D-page 95

18F8680.book Page 96 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2 16-bit Mode For all 16-bit modes, the Address Latch Enable (ALE) pin indicates that the Address bits (A<15:0>) are avail- The external memory interface implemented in able on the external memory interface bus. Following PIC18F8X8X devices operates only in 16-bit mode. the address latch, the Output Enable signal (OE ) will The mode selection is not software configurable but is enable both bytes of program memory at once to form programmed via the configuration bits. a 16-bit instruction word. The WM<1:0> bits in the MEMCON register determine In Byte Select mode, JEDEC standard Flash memories three types of connections in 16-bit mode. They are will require BA0 for the byte address line, and one I/O referred to as: line to select between Byte and Word mode. The other • 16-bit Byte Write 16-bit modes do not need BA0. JEDEC standard static • 16-bit Word Write RAM memories will use the UB or LB signals for byte selection. • 16-bit Byte Select These three different configurations allow the designer 6.2.1 16-BIT BYTE WRITE MODE maximum flexibility in using 8-bit and 16-bit memory Figure6-1 shows an example of 16-bit Byte Write devices. mode for PIC18F8X8X devices. FIGURE 6-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8X8X (MSB) (LSB) AD<7:0> 373 A<19:0> A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(1) OE WR(1) ALE A<19:16> CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section5.1 “Table Reads and Table Writes”. DS30491D-page 96  2003-2013 Microchip Technology Inc.

18F8680.book Page 97 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2.2 16-BIT WORD WRITE MODE Figure6-2 shows an example of 16-bit Word Write mode for PIC18F8X8X devices. FIGURE 6-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F8X8X AD<7:0> 373 A<20:1> A<x:0> JEDEC Word EPROM Memory D<15:0> D<15:0> CE OE WR(1) AD<15:8> 373 ALE A<19:16> CE OE WRH Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section5.1 “Table Reads and Table Writes”.  2003-2013 Microchip Technology Inc. DS30491D-page 97

18F8680.book Page 98 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2.3 16-BIT BYTE SELECT MODE Figure6-3 shows an example of 16-bit Byte Select mode for PIC18F8X8X devices. FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X8X A<20:1> AD<7:0> 373 AD<15:8> 373 ALE A<20:1> A<19:16> A<x:1> OE OE WRH WR(1) WRL JEDEC Word BA0 A0 SRAM Memory CE CE LB LB D<15:0> D<15:0> UB UB Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section5.1 “Table Reads and Table Writes”. DS30491D-page 98  2003-2013 Microchip Technology Inc.

18F8680.book Page 99 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2.4 16-BIT MODE TIMING Figure6-4 shows the 16-bit mode external bus timing for PIC18F8X8X devices. FIGURE 6-4: EXTERNAL PROGRAM MEMORY BUS TIMING (16-BIT MODE) Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4 Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0h Ch AD<15:0> 3AABh 0E55h CF33h 9256h BA0 ALE OE WRH ‘1’ ‘1’ WRL ‘1’ ‘1’ 1 TCY Wait Opcode Fetch Table Read MOVLW 55h of 92h from 007556h from 199E67h  2003-2013 Microchip Technology Inc. DS30491D-page 99

18F8680.book Page 100 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 100  2003-2013 Microchip Technology Inc.

18F8680.book Page 101 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 7.0 DATA EEPROM MEMORY 7.1 EEADRH:EEADR The data EEPROM is readable and writable during nor- The address register pair, EEADRH:EEADR, can mal operation over the entire VDD range. The data address up to a maximum of 1024 bytes of data memory is not directly mapped in the register file EEPROM. space. Instead, it is indirectly addressed through the Special Function Registers (SFR). 7.2 EECON1 and EECON2 Registers There are five SFRs used to read and write the EECON1 is the control register for EEPROM memory program and data EEPROM memory. These registers accesses. are: EECON2 is not a physical register. Reading EECON2 • EECON1 will read all ‘0’s. The EECON2 register is used • EECON2 exclusively in the EEPROM write sequence. • EEDATA Control bits RD and WR initiate read and write opera- • EEADR tions, respectively. These bits cannot be cleared, only • EEADRH set in software. They are cleared in hardware at the completion of the read or write operation. The inability The EEPROM data memory allows byte read and write. to clear the WR bit in software prevents the accidental When interfacing to the data memory block, EEDATA or premature termination of a write operation. holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. The WREN bit, when set, will allow a write operation. These devices have 1024 bytes of data EEPROM with On power-up, the WREN bit is clear. The WRERR bit is an address range from 0h to 3FFh. set when a write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal opera- The EEPROM data memory is rated for high erase/ tion. In these situations, the user can check the write cycles. A byte write automatically erases the loca- WRERR bit and rewrite the location. It is necessary to tion and writes the new data (erase-before-write). The reload the data and address registers (EEDATA and write time is controlled by an on-chip timer. The write EEADR) due to the Reset condition forcing the time will vary with voltage and temperature as well as contents of the registers to zero. from chip to chip. Please refer to parameter D122 (Electrical Characteristics, Section27.0 “Electrical Note: Interrupt flag bit, EEIF in the PIR2 register, Characteristics”) for exact limits. is set when write is complete. It must be cleared in software.  2003-2013 Microchip Technology Inc. DS30491D-page 101

18F8680.book Page 102 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EE Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EE Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ W = Writable bit S = Settable bit - n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 102  2003-2013 Microchip Technology Inc.

18F8680.book Page 103 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 7.3 Reading the Data EEPROM (EECON1<6>) and then set control bit, RD Memory (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can To read a data memory location, the user must write the be read by the next instruction. EEDATA will hold this address to the EEADR register, clear the EEPGD con- value until another read operation or until it is written to trol bit (EECON1<7>), clear the CFGS control bit by the user (during a write operation). EXAMPLE 7-1: DATA EEPROM READ MOVLW DATA_EE_ADR_HI ; MOVWF EEADRH ; MOVLW DATA_EE_ADDR_LOW ; MOVWF EEADR ; Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access program Flash or Data EEPROM memory BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA 7.4 Writing to the Data EEPROM cution (i.e., runaway programs). The WREN bit should Memory be kept clear at all times except when updating the EEPROM. The WREN bit is not cleared byhardware. To write an EEPROM data location, the address must After a write sequence has been initiated, EECON1, first be written to the EEADRH:EEADR register pair EEADRH:EEADR and EDATA cannot be modified. The and the data written to the EEDATA register. Then the WR bit will be inhibited from being set unless the sequence in Example7-2 must be followed to initiate WREN bit is set. The WREN bit must be set on a pre- the write cycle. vious instruction. Both WR and WREN cannot be set The write will not initiate if the above sequence is not with the same instruction. exactly followed (write 55h to EECON2, write 0AAh to At the completion of the write cycle, the WR bit is EECON2, then set WR bit) for each byte. It is strongly cleared in hardware and the EEPROM Write Complete recommended that interrupts be disabled during this Interrupt Flag bit (EEIF) is set. The user may either codesegment. enable this interrupt or poll this bit. EEIF must be Additionally, the WREN bit in EECON1 must be set to cleared by software. enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- EXAMPLE 7-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDR_HI ; MOVWF EEADRH ; MOVLW DATA_EE_ADDR_LOW ; MOVWF EEADR ; Data Memory Address to read MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access program Flash or Data EEPROM memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable interrupts Required MOVLW 55h ; Sequence MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable interrupts . ; user code execution . . BCF EECON1, WREN ; Disable writes on write complete (EEIF set)  2003-2013 Microchip Technology Inc. DS30491D-page 103

18F8680.book Page 104 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 7.5 Write Verify 7.7 Operation During Code-Protect Depending on the application, good programming Data EEPROM memory has its own code-protect practice may dictate that the value written to the mem- mechanism. External read and write operations are ory should be verified against the original value. This disabled if either of these mechanisms are enabled. should be used in applications where excessive writes The microcontroller itself can both read and write to the can stress bits near the specification limit. internal data EEPROM regardless of the state of the code-protect configuration bit. Refer to Section24.0 7.6 Protection Against Spurious Write “Special Features of the CPU” for additional information. There are conditions when the device may not want to write to the data EEPROM memory. To protect against 7.8 Using the Data EEPROM spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. The data EEPROM is a high endurance, byte address- Also, the Power-up Timer (72 ms duration) prevents able array that has been optimized for the storage of EEPROMwrite. frequently changing information (e.g., program vari- The write initiate sequence and the WREN bit together ables or other data that are updated often). Frequently help prevent an accidental write during brown-out, changing values will typically be updated more often power glitch, or software malfunction. than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example7-3. Note: If data EEPROM is only used to store con- stants and/or data that changes rarely, an array refresh is likely not required. See specification D124. EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF EEADRH ; CLRF EEADR ; Start at address 0 BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA Loop ; Not zero, do it again INCFS2 EEADRH, F ; BRA Loop ; BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS30491D-page 104  2003-2013 Microchip Technology Inc.

18F8680.book Page 105 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u GIEH GIEL EEADRH — — — — — — EE Addr High ---- --00 ---- --00 EEADR EEPROM Address Register 0000 0000 0000 0000 EEDATA EEPROM Data Register 0000 0000 0000 0000 EECON2 EEPROM Control Register 2 (not a physical register) — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000 Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2003-2013 Microchip Technology Inc. DS30491D-page 105

18F8680.book Page 106 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 106  2003-2013 Microchip Technology Inc.

18F8680.book Page 107 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 8.0 8 x 8 HARDWARE MULTIPLIER 8.2 Operation Example8-1 shows the sequence to do an 8 x 8 8.1 Introduction unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in An 8 x 8 hardware multiplier is included in the ALU of the WREG register. the PIC18F6585/8585/6680/8680 devices. By making the multiply a hardware operation, it completes in a sin- Example8-2 shows the sequence to do an 8 x 8 signed gle instruction cycle. This is an unsigned multiply that multiply. To account for the sign bits of the arguments, gives a 16-bit result. The result is stored in the 16-bit each argument’s Most Significant bit (MSb) is tested product register pair (PRODH:PRODL). The multiplier and the appropriate subtractions are done. does not affect any flags in the ALUSTA register. Making the 8 x 8 multiplier execute in a single cycle EXAMPLE 8-1: 8 x 8 UNSIGNED gives the following advantages: MULTIPLY ROUTINE • Higher computational throughput MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> • Reduces code size requirements for multiply ; PRODH:PRODL algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY Processors. ROUTINE Table8-1 shows a performance comparison between MOVF ARG1, W ; enhanced devices using the single-cycle hardware MULWF ARG2 ; ARG1 * ARG2 -> multiply and performing the same function without the ; PRODH:PRODL hardware multiply. BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH ; - ARG1 MOVF ARG2, W ; BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH ; - ARG2 TABLE 8-1: PERFORMANCE COMPARISON Program Time Cycles Routine Multiply Method Memory (Words) (Max) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 s 27.6 s 69 s 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s 16 x 16 unsigned Hardware multiply 24 24 2.4 s 9.6 s 24 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s 16 x 16 signed Hardware multiply 36 36 3.6 s 14.4 s 36 s  2003-2013 Microchip Technology Inc. DS30491D-page 107

18F8680.book Page 108 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiply. Equation8-1 shows the algorithm MULTIPLICATION that is used. The 32-bit result is stored in four registers, ALGORITHM RES3:RES0. RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L EQUATION 8-1: 16 x 16 UNSIGNED = (ARG1H  ARG2H  216) + MULTIPLICATION (ARG1H  ARG2L  28) + ALGORITHM (ARG1L  ARG2H  28) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (ARG1L  ARG2L) + = (ARG1H  ARG2H  216) + (-1  ARG2H<7>  ARG1H:ARG1L  216) + (ARG1H  ARG2L  28) + (-1  ARG1H<7>  ARG2H:ARG2L  216) (ARG1L  ARG2H  28) + (ARG1L  ARG2L) EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY ROUTINE EXAMPLE 8-3: 16 x 16 UNSIGNED MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES1 ; MULWF ARG2L ; ARG1L * ARG2L -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES1 ; MOVF ARG1H, W MOVFF PRODL, RES0 ; MULWF ARG2H ; ARG1H * ARG2H -> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1L, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1L * ARG2H -> ; ; PRODH:PRODL MOVF ARG1L, W MOVF PRODL, W ; MULWF ARG2H ; ARG1L * ARG2H -> ADDWF RES1 ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2 ; ADDWF RES1 ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3 ; ADDWFC RES2 ; ; CLRF WREG ; MOVF ARG1H, W ; ADDWFC RES3 ; MULWF ARG2L ; ARG1H * ARG2L -> ; ; PRODH:PRODL MOVF ARG1H, W ; MOVF PRODL, W ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWF RES1 ; Add cross ; PRODH:PRODL MOVF PRODH, W ; products MOVF PRODL, W ; ADDWFC RES2 ; ADDWF RES1 ; Add cross CLRF WREG ; MOVF PRODH, W ; products ADDWFC RES3 ; ADDWFC RES2 ; ; CLRF WREG ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? ADDWFC RES3 ; BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers, ; RES3:RES0. To account for the sign bits of the argu- SIGN_ARG1 ments, each argument pairs’ Most Significant bit (MSb) BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? is tested and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS30491D-page 108  2003-2013 Microchip Technology Inc.

18F8680.book Page 109 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18F6585/8585/6680/8680 devices have multi- compatible with PIC® mid-range devices. In Compati- ple interrupt sources and an interrupt priority feature bility mode, the interrupt priority bits for each source that allows each interrupt source to be assigned a high have no effect. INTCON<6> is the PEIE bit which or a low priority level. The high priority interrupt vector enables/disables all peripheral interrupt sources. is at 000008h while the low priority interrupt vector is at INTCON<7> is the GIE bit which enables/disables all 000018h. High priority interrupt events will override any interrupt sources. All interrupts branch to address low priority interrupts that may be in progress. 000008h in Compatibility mode. There are thirteen registers which are used to control When an interrupt is responded to, the global interrupt interrupt operation. They are: enable bit is cleared to disable further interrupts. If the • RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. • INTCON High priority interrupt sources can interrupt a low • INTCON2 priority interrupt. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address • PIE1, PIE2, PIE3 (000008h or 000018h). Once in the Interrupt Service • IPR1, IPR2, IPR3 Routine, the source(s) of the interrupt can be deter- It is recommended that the Microchip header files mined by polling the interrupt flag bits. The interrupt supplied with MPLAB® IDE be used for the symbolic bit flag bits must be cleared in software before re-enabling names in these registers. This allows the assembler/ interrupts to avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL Each interrupt source (except INT0) has three bits to if priority levels are used) which re-enables interrupts. control its operation. The functions of these bits are: For external interrupt events, such as the INT pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one- or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits.  2003-2013 Microchip Technology Inc. DS30491D-page 109

18F8680.book Page 110 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 9-1: INTERRUPT LOGIC Wake-up if in Sleep Mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location Peripheral Interrupt Flag bit IINNTT11IIEP 0008h Peripheral Interrupt Enable bit INT2IF Peripheral Interrupt Priority bit INT2IE INT2IP TMR1IF GIEH/GIE TMR1IE TMR1IP IPE XXXXIF IPEN XXXXIE GIEL/PEIE XXXXIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h TMR1IF TMR0IP TMR1IE TMR1IP RBIF RBIE XXXXIF RBIP GIEL/PEIE XXXXXXXXIIEP GIE/GEIH INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS30491D-page 110  2003-2013 Microchip Technology Inc.

18F8680.book Page 111 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag enable bit. User software should ensure bits. the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN (RCON<7>) = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN (RCON<7>) = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN (RCON<7>) = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 111

18F8680.book Page 112 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30491D-page 112  2003-2013 Microchip Technology Inc.

18F8680.book Page 113 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2003-2013 Microchip Technology Inc. DS30491D-page 113

18F8680.book Page 114 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the global peripheral interrupts. Due to the number of peripheral enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Flag registers (PIR1, PIR2 and PIR3). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: Enhanced CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note1: Available in Microcontroller mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 114  2003-2013 Microchip Technology Inc.

18F8680.book Page 115 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred while the SSP module (configured in I2C Master mode) was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 or TMR3 register capture occurred (must be cleared in software) 0 = No TMR1 or TMR3 register capture occurred Compare mode: 1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 115

18F8680.book Page 116 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF/ TXB1IF(1) TXB0IF(1) RXB1IF/ RXB0IF/ TXBnIF RXBnIF FIFOWMIF bit 7 bit 0 bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors bit 4 When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers has completed transmission of a message and may be reloaded (TXBIE or BIE0<7:2> must be non-zero) 0 = No message was transmitted bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: CAN Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message bit 0 When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit(1) 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 116  2003-2013 Microchip Technology Inc.

18F8680.book Page 117 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note1: Available in Microcontroller mode only. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: Enhanced CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 117

18F8680.book Page 118 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enables the write operation interrupt 0 = Disables the write operation interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enables the bus collision interrupt 0 = Disables the bus collision interrupt bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enables the Low-Voltage Detect interrupt 0 = Disables the Low-Voltage Detect interrupt bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 118  2003-2013 Microchip Technology Inc.

18F8680.book Page 119 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE/ TXB1IE(1) TXB0IE(1) RXB1IE/ RXB0IE/ TXBnIE RXBnIE FIFOWMIE bit 7 bit 0 bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 119

18F8680.book Page 120 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note1: Available in Microcontroller mode only. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 120  2003-2013 Microchip Technology Inc.

18F8680.book Page 121 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 121

18F8680.book Page 122 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP/ TXB1IP(1) TXB0IP(1) RXB1IP/ RXB0IP/ TXBnIP RXBnIP FIFOWMIP bit 7 bit 0 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 122  2003-2013 Microchip Technology Inc.

18F8680.book Page 123 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.5 RCON Register The RCON register contains the IPEN bit which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section4.14 “RCON Register”. REGISTER 9-13: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16 Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-4. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-4. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register4-4. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-4. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 123

18F8680.book Page 124 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.6 INT0 Interrupt 9.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ In 8-bit mode (which is the default), an overflow in the INT2 and RB3/INT3 pins are edge-triggered: either ris- TMR0 register (0FFh 00h) will set flag bit TMR0IF. In ing if the corresponding INTEDGx bit is set in the 16-bit mode, an overflow in the TMR0H:TMR0L regis- INTCON2 register, or falling if the INTEDGx bit is clear. ters (0FFFFh 0000h) will set flag bit, TMR0IF. The When a valid edge appears on the RBx/INTx pin, the interrupt can be enabled/disabled by setting/clearing corresponding flag bit, INTxF, is set. This interrupt can enable bit, TMR0IE (INTCON<5>). Interrupt priority for be disabled by clearing the corresponding enable bit, Timer0 is determined by the value contained in the INTxE. Flag bit, INTxF, must be cleared in software in interrupt priority bit, TMR0IP (INTCON2<2>). See the Interrupt Service Routine before re-enabling the Section11.0 “Timer0 Module” for further details on interrupt. All external interrupts (INT0, INT1, INT2 and the Timer0 module. INT3) can wake-up the processor from Sleep if bit INTxIE was set prior to going into Sleep. If the global 9.8 PORTB Interrupt-on-Change interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled The interrupt priority for INT, INT2 and INT3 is deter- by setting/clearing enable bit, RBIE (INTCON<3>). mined by the value contained in the interrupt priority Interrupt priority for PORTB interrupt-on-change is bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) determined by the value contained in the interrupt and INT3IP (INTCON2<1>). There is no priority bit priority bit, RBIP (INTCON2<0>). associated with INT0; it is always a high priority interrupt source. 9.9 Context Saving During Interrupts During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (See Section4.3 “Fast Register Stack”), the user may need to save the WREG, Status and BSR registers in software. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS30491D-page 124  2003-2013 Microchip Technology Inc.

18F8680.book Page 125 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.0 I/O PORTS 10.1 PORTA, TRISA and LATA Registers Depending on the device selected, there are either seven or nine I/O ports available on PIC18F6X8X/8X8X PORTA is a 7-bit wide, bidirectional port. The corre- devices. Some of their pins are multiplexed with one or sponding data direction register is TRISA. Setting a more alternate functions from the other peripheral fea- TRISA bit (= 1) will make the corresponding PORTA pin tures on the device. In general, when a peripheral is an input (i.e., put the corresponding output driver in a enabled, that pin may not be used as a general purpose high-impedance mode). Clearing a TRISA bit (= 0) will I/O pin. make the corresponding PORTA pin an output (i.e., put Each port has three registers for its operation. These the contents of the output latch on the selected pin). registers are: Reading the PORTA register reads the status of the • TRIS register (data direction register) pins, whereas writing to it will write to the port latch. • PORT register (reads the levels on the pins of the The Data Latch register (LATA) is also memory device) mapped. Read-modify-write operations on the LATA • LAT register (output latch) register read and write the latched output value for PORTA. The Data Latch register (LAT) is useful for read-modify- write operations on the value that the I/O pins are The RA4 pin is multiplexed with the Timer0 module driving. clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open- A simplified version of a generic I/O port and its drain output. All other RA port pins have TTL input operation is shown in Figure10-1. levels and full CMOS output drivers. The RA6 pin is only enabled as a general I/O pin in FIGURE 10-1: SIMPLIFIED BLOCK ECIO and RCIO Oscillator modes. DIAGRAM OF PORT/LAT/TRIS The other PORTA pins are multiplexed with analog OPERATION inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). RD LAT TRIS Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read D Q as ‘0’. RA6 and RA4 are configured as digital inputs. WR LAT + WR Port CK The TRISA register controls the direction of the RA pins even when they are being used as analog inputs. The Data Latch user must ensure the bits in the TRISA register are Data Bus maintained set when using them as analog inputs. RD Port I/O pin EXAMPLE 10-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs  2003-2013 Microchip Technology Inc. DS30491D-page 125

18F8680.book Page 126 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-2: BLOCK DIAGRAM OF FIGURE 10-3: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS RA4/T0CKI PIN RD LATA RD LATA Data Bus Data D Q Bus D Q WorR LATA VDD WorR LATA PORTA CK Q P PORTA CK Q N I/O pin(1) Data Latch Data Latch D Q N I/O pin(1) D Q VSS WR TRISA CK Q VSS WR TRISA CK Q STrcighgmeitrt Analog TRIS Latch Input TRIS Latch Input Mode Buffer RD TRISA RD TRISA TTL Input Buffer Q D Q D ENEN EN RD PORTA RD PORTA TMR0 Clock Input To A/D Converter and LVD Modules Note1: I/O pins have protection diodes to VDD and VSS. Note1: I/O pins have protection diodes to VDD and VSS. FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O) ECRA6 orRCRA6 Enable DataBus RD LATA D Q VDD WR LATAorPORTA CK Q P Data Latch N I/O pin(1) D Q WR TRISA CK Q VSS TRIS Latch TTL RD TRISA Input Buffer ECRA6 or RCRA6 Enable Q D EN RD PORTA Note1: I/O pins have protection diodes to VDD and VSS. DS30491D-page 126  2003-2013 Microchip Technology Inc.

18F8680.book Page 127 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit 4 ST/OD Input/output or external clock input for Timer0. Output is open-drain type. RA5/AN4/LVDIN bit 5 TTL Input/output or slave select input for synchronous serial port or analog input, or Low-Voltage Detect input. OSC2/CLKO/RA6 bit 6 TTL OSC2 or clock output, or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 -u0u 0000 LATA — LATA Data Output Register -xxx xxxx -uuu uuuu TRISA — PORTA Data Direction Register -111 1111 -111 1111 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.  2003-2013 Microchip Technology Inc. DS30491D-page 127

18F8680.book Page 128 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.2 PORTB, TRISB and LATB A mismatch condition will continue to set flag bit, RBIF. Registers Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. PORTB is an 8-bit wide, bidirectional port. The corre- The interrupt-on-change feature is recommended for sponding data direction register is TRISB. Setting a wake-up on key depression operation and operations TRISB bit (= 1) will make the corresponding PORTB where PORTB is only used for the interrupt-on-change pin an input (i.e., put the corresponding output driver in feature. Polling of PORTB is not recommended while a high-impedance mode). Clearing a TRISB bit (= 0) using the interrupt-on-change feature. will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). For PIC18FXX85 devices, RB3 can be configured by the configuration bit, CCP2MX, as the alternate peripheral The Data Latch register (LATB) is also memory mapped. pin for the CCP2 module. This is only available when the Read-modify-write operations on the LATB register read device is configured in Microprocessor, Microprocessor and write the latched output value for PORTB. with Boot Block, or Extended Microcontroller Operating modes. EXAMPLE 10-2: INITIALIZING PORTB The RB5 pin is used as the LVP programming pin. CLRF PORTB ; Initialize PORTB by When the LVP configuration bit is programmed, this pin ; clearing output loses the I/O function and becomes a programming test ; data latches CLRF LATB ; Alternate method function. ; to clear output Note: When LVP is enabled, the weak pull-up on ; data latches RB5 is disabled. MOVLW 0CFh ; Value used to ; initialize data ; direction FIGURE 10-5: BLOCK DIAGRAM OF MOVWF TRISB ; Set RB<3:0> as inputs RB7:RB4 PINS ; RB<5:4> as outputs ; RB<7:6> as inputs VDD RBPU(2) Weak PPull-up Each of the PORTB pins has a weak internal pull-up. A Data Latch single control bit can turn on all the pull-ups. This is Data Bus D Q performed by clearing bit RBPU (INTCON2<7>). The WR LATB I/O pin(1) weak pull-up is automatically turned off when the port orPORTB CK pin is configured as an output. The pull-ups are TRIS Latch disabled on a Power-on Reset. D Q Note: Oconn fiag uPreodw aesr- doing itRale isneptu, tsth.ese pins are WR TRISB CK TInTpLut Buffer ST Buffer Four of the PORTB pins (RB3:RB0) are the external RD TRISB interrupt pins, INT3 through INT0. In order to use these pins as external interrupts, the corresponding TRISB bit must be set to ‘1’. RD LATB The other four PORTB pins (RB7:RB4) have an Latch interrupt-on-change feature. Only pins configured as Q D inputs can cause this interrupt to occur (i.e., any RD PORTB EN Q1 RB7:RB4 pin configured as an output is excluded from Set RBIF the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of Q D RD PORTB RB7:RB4 are OR’ed together to generate the RB port From other EN change interrupt with flag bit, RBIF (INTCON<0>). RB7:RB4 pins Q3 RB7:RB5 in Serial Programming Mode This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the Note1: I/O pins have diode protection to VDD and VSS. interrupt in the following manner: 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. b) Clear flag bit RBIF. DS30491D-page 128  2003-2013 Microchip Technology Inc.

18F8680.book Page 129 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q I/O pin(1) WR Port CK TRIS Latch D Q TTL WR TRIS CK IBnupfufetr RD TRIS Q D RD Port EN INTx Schmitt Trigger RD Port Buffer Note1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). FIGURE 10-7: BLOCK DIAGRAM OF RB3 PIN VDD RCBCPPU2M(2)X PWPuella-ukp CCP Output(3) 1 VDD P Enable(3) 0 CCP Output Data Latch Data Bus I/O pin(1) D Q WR LATB or WR PORTB N CK TRIS Latch VSS D TTL WR TRISB CK Q IBnupfufetr RD TRISB RD LATB Q D RD PORTB EN RD PORTB CCP2 or INT3 Schmitt Trigger Buffer CCP2MX = 0 Note1: I/O pin has diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.  2003-2013 Microchip Technology Inc. DS30491D-page 129

18F8680.book Page 130 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2. Internal software programmable weak pull-up. RB3/INT3/CCP2(3) bit 3 TTL/ST(4) Input/output pin or external interrupt input 3. Capture 2 input/ Compare 2 output/PWM output (when CCP2MX configuration bit is enabled, all PIC18FXX85 operating modes except Microcontroller mode). Internal software programmable weak pull-up. RB4/KBI0 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5/KBI1/PGM bit 5 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low-voltage ICSP enable pin. RB6/KBI2/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/KBI3/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except Microcontroller mode). 4: This buffer is a Schmitt Trigger input when configured as the CCP2 input. TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 1111 1111 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 1100 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30491D-page 130  2003-2013 Microchip Technology Inc.

18F8680.book Page 131 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.3 PORTC, TRISC and LATC The pin override value is not loaded into the TRIS reg- Registers ister. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTC is an 8-bit wide, bidirectional port. The corre- RC1 is normally configured by configuration bit, sponding data direction register is TRISC. Setting a CCP2MX, as the default peripheral pin of the CCP2 TRISC bit (= 1) will make the corresponding PORTC module (default/erased state, CCP2MX = 1). pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) EXAMPLE 10-3: INITIALIZING PORTC will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by ; clearing output The Data Latch register (LATC) is also memory mapped. ; data latches Read-modify-write operations on the LATC register read CLRF LATC ; Alternate method and write the latched output value for PORTC. ; to clear output PORTC is multiplexed with several peripheral functions ; data latches MOVLW 0CFh ; Value used to (Table10-5). PORTC pins have Schmitt Trigger input ; initialize data buffers. ; direction When enabling peripheral functions, care should be MOVWF TRISC ; Set RC<3:0> as inputs taken in defining TRIS bits for each PORTC pin. Some ; RC<5:4> as outputs peripherals override the TRIS bit to make a pin an ; RC<7:6> as inputs output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corre- sponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs. FIGURE 10-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORTC/Peripheral Out Select Peripheral Data Out 0 VDD P RD LATC 1 Data Bus D Q WR LATC or I/O pin(1) CK Q WR PORTC Data Latch N TRIS OVERRIDE D Q Pin Override Peripheral WR TRISC TRIS VSS CK Q Override RC0 Yes Timer1 Osc for Logic Timer1/Timer3 TRIS Latch RC1 Yes Timer1 Osc for RD TRISC Timer1/Timer3, Schmitt CCP2 I/O Peripheral Output Trigger RC2 Yes CCP1 I/O Enable(2) Q D RC3 Yes SPI/I2C Master Clock EN RC4 Yes I2C Data Out RD PORTC RC5 Yes SPI Data Out Peripheral Data In RC6 Yes USART Async Xmit, Sync Clock Note 1: I/O pins have diode protection to VDD and VSS. RC7 Yes USART Sync 2: Peripheral output enable is only active if peripheral select is active. Data Out  2003-2013 Microchip Technology Inc. DS30491D-page 131

18F8680.book Page 132 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI/CCP2(1) bit 1 ST Input/output port pin, Timer1 oscillator input or Capture 2 input/ Compare 2 output/PWM output (when CCP2MX configuration bit is disabled). RC2/CCP1/P1A bit 2 ST Input/output port pin or Capture 1 input/Compare 1 output/ PWM1 output. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode). RC5/SDO bit 5 ST Input/output port pin or synchronous serial port data output. RC6/TX/CK bit 6 ST Input/output port pin, addressable USART asynchronous transmit or addressable USART synchronous clock. RC7/RX/DT bit 7 ST Input/output port pin, addressable USART asynchronous receive or addressable USART synchronous data. Legend: ST = Schmitt Trigger input Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set. TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu LATC LATC Data Output Register xxxx xxxx uuuu uuuu TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS30491D-page 132  2003-2013 Microchip Technology Inc.

18F8680.book Page 133 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.4 PORTD, TRISD and LATD FIGURE 10-9: PORTD BLOCK DIAGRAM Registers IN I/O PORT MODE PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a RD LATD TRISD bit (= 1) will make the corresponding PORTD Data pin an input (i.e., put the corresponding output driver in Bus a high-impedance mode). Clearing a TRISD bit (= 0) WR LATD D Q will make the corresponding PORTD pin an output (i.e., or I/O pin(1) PORTD put the contents of the output latch on the selected pin). CK The Data Latch register (LATD) is also memory mapped. Data Latch Read-modify-write operations on the LATD register read D Q and write the latched output value for PORTD. Schmitt WR TRISD Trigger PORTD is an 8-bit port with Schmitt Trigger input CK Input buffers. Each pin is individually configurable as an input TRIS Latch Buffer or output. Note: On a Power-on Reset, these pins are RD TRISD configured as digital inputs. On PIC18F8X8X devices, PORTD is multiplexed with Q D the system bus as the external memory interface; I/O port functions are only available when the system bus ENEN is disabled by setting the EBDIS bit in the MEMCOM register (MEMCON<7>). When operating as the exter- RD PORTD nal memory interface, PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0). Note1: I/O pins have diode protection to VDD and VSS. PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section10.10 “Parallel Slave Port (PSP)” for additional information. EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs  2003-2013 Microchip Technology Inc. DS30491D-page 133

18F8680.book Page 134 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY) Q D ENEN RD PORTD RD LATD Data Bus Port D Q 0 WR LATD Data orPORTD CK 1 I/O pin(1) Data Latch D Q WR TRISD TTL CK Input TRIS Latch Buffer RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. DS30491D-page 134  2003-2013 Microchip Technology Inc.

18F8680.book Page 135 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0/AD0(2) bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. RD1/PSP1/AD1(2) bit 1 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. RD2/PSP2/AD2(2) bit 2 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2. RD3/PSP3/AD3(2) bit 3 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3. RD4/PSP4/AD4(2) bit 4 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4. RD5/PSP5/AD5(2) bit 5 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5. RD6/PSP6/AD6(2) bit 6 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6. RD7/PSP7/AD7(2) bit 7 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: Available in PIC18F8X8X devices only. TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD Data Output Register xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.  2003-2013 Microchip Technology Inc. DS30491D-page 135

18F8680.book Page 136 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.5 PORTE, TRISE and LATE Pin RE7 can be configured as the alternate peripheral Registers pin for the CCP2 module when the device is operating in Microcontroller mode. This is done by clearing the PORTE is an 8-bit wide, bidirectional port. The corre- configuration bit, CCP2MX, in configuration register, sponding data direction register is TRISE. Setting a CONFIG3H (CONFIG3H<0>). TRISE bit (= 1) will make the corresponding PORTE Note: For PIC18F8X8X (80-pin) devices operat- pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) ing in other than Microcontroller mode, PORTE defaults to the system bus on will make the corresponding PORTE pin an output (i.e., Power-on Reset. put the contents of the output latch on the selected pin). Read-modify-write operations on the LATE register read and write the latched output value for PORTE. EXAMPLE 10-5: INITIALIZING PORTE PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input CLRF PORTE ; Initialize PORTE by or output. PORTE is multiplexed with the Enhanced ; clearing output ; data latches CCP module (Table10-9). CLRF LATE ; Alternate method On PIC18F8X8X devices, PORTE is also multiplexed ; to clear output with the system bus as the external memory interface; ; data latches the I/O bus is available only when the system bus is MOVLW 03h ; Value used to disabled by setting the EBDIS bit in the MEMCON ; initialize data register (MEMCON<7>). If the device is configured in ; direction MOVWF TRISE ; Set RE1:RE0 as inputs Microprocessor or Extended Microcontroller mode, then ; RE7:RE2 as outputs the PORTE<7:0> becomes the high byte of the address/ data bus for the external program memory interface. In Microcontroller mode, the PORTE<2:0> pins become the control inputs for the Parallel Slave Port when bit PSPMODE (PSPCON<4>) is set. (Refer to Section4.1.1 “PIC18F8X8X Program Memory Modes” for more information on program memory modes.) When the Parallel Slave Port is active, three PORTE pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10) function as its control inputs. This automatically occurs when the PSPMODE bit (PSPCON<4>) is set. Users must also make certain that bits TRISE<2:0> are set to configure the pins as digital inputs and the ADCON1 register is configured for digital I/O. The PORTE PSP control functions are summarized in Table10-9. DS30491D-page 136  2003-2013 Microchip Technology Inc.

18F8680.book Page 137 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out 0 VDD P RD LATE 1 Data Bus D Q WR LATE I/O pin(1) orWR PORTE CK Q Data Latch N D Q TRIS OVERRIDE WR TRISE CK Q TRIS VSS Pin Override Peripheral Override TRIS Latch RE0 Yes External Bus RE1 Yes External Bus RD TRISE Schmitt RE2 Yes External Bus Peripheral Enable Trigger RE3 Yes External Bus Q D RE4 Yes External Bus RE5 Yes External Bus EN RE6 Yes External Bus RD PORTE RE7 Yes External Bus Peripheral Data In Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 10-12: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY) Q D ENEN RD PORTE RD LATE Data Bus Port D Q 0 WR LATE Data 1 orPORTE CK I/O pin(1) Data Latch D Q WR TRISE TTL CK Input TRIS Latch Buffer RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS.  2003-2013 Microchip Technology Inc. DS30491D-page 137

18F8680.book Page 138 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AD8(2) bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or address/data bit 8. For RD (PSP Control mode): 1 =Not a read operation 0 =Read operation, reads PORTD register (if chip selected) RE1/WR/AD9(2) bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or address/data bit 9. For WR (PSP Control mode): 1 =Not a write operation 0 =Write operation, writes PORTD register (if chip selected) RE2/CS/AD10(2) bit 2 ST/TTL(1) Input/output port pin, chip select control for Parallel Slave Port or address/data bit 10. For CS (PSP Control mode): 1 =Device is not selected 0 =Device is selected RE3/AD11(2) bit 3 ST/TTL(1) Input/output port pin or address/data bit 11. RE4/AD12(2) bit 4 ST/TTL(1) Input/output port pin or address/data bit 12. RE5/AD13/(2)P1C(3) bit 5 ST/TTL(1) Input/output port pin, address/data bit 13 or ECCP1 PWM output C. RE6/AD14/(2)P1B(3) bit 6 ST/TTL(1) Input/output port pin, address/data bit 13 or ECCP1 PWM output B. RE7/CCP2/AD15(2) bit 7 ST/TTL(1) Input/output port pin, Capture 2 input/Compare 2 output/PWM output (PIC18F8X20 devices in Microcontroller mode only) or address/data bit 15. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode, and TTL buffers when in System Bus or PSP Control mode. 2: Available in PIC18F8X8X devices only. 3: On PIC18F8X8X devices, these pins may be moved to RHY or RH6 by changing the ECCPMX configuration bit. TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISE PORTE Data Direction Control Register 1111 1111 1111 1111 PORTE Read PORTE pin/Write PORTE Data Latch xxxx xxxx uuuu uuuu LATE Read PORTE Data Latch/Write PORTE Data Latch xxxx xxxx uuuu uuuu MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0000 --00 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE. DS30491D-page 138  2003-2013 Microchip Technology Inc.

18F8680.book Page 139 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.6 PORTF, LATF and TRISF Registers EXAMPLE 10-6: INITIALIZING PORTF CLRF PORTF ; Initialize PORTF by PORTF is an 8-bit wide, bidirectional port. The corre- ; clearing output sponding data direction register is TRISF. Setting a ; data latches TRISF bit (= 1) will make the corresponding PORTF pin CLRF LATF ; Alternate method an input (i.e., put the corresponding output driver in a ; to clear output high-impedance mode). Clearing a TRISF bit (= 0) will ; data latches make the corresponding PORTF pin an output (i.e., put MOVLW 07h ; the contents of the output latch on the selected pin). MOVWF CMCON ; Turn off comparators MOVLW 0Fh ; Read-modify-write operations on the LATF register MOVWF ADCON1 ; Set PORTF as digital I/O read and write the latched output value for PORTF. MOVLW 0CFh ; Value used to PORTF is multiplexed with several analog peripheral ; initialize data functions, including the A/D converter inputs and ; direction comparator inputs, outputs, and voltage reference. MOVWF TRISF ; Set RF3:RF0 as inputs ; RF5:RF4 as outputs Note1: On a Power-on Reset, the RF6:RF0 pins ; RF7:RF6 as inputs are configured as inputs and read as ‘0’. 2: To configure PORTF as digital I/O, turn off comparators and set ADCON1 value. FIGURE 10-13: PORTF RF1/AN6/C2OUT AND RF2/AN7/C1OUT PINS BLOCK DIAGRAM Port/Comparator Select Comparator Data Out 0 VDD P 1 RD LATF Data Bus D Q WR LATF or WR PORTF I/O pin CK Q Data Latch N D Q WR TRISF VSS CK Q TRIS Latch Analog Input Mode RD TRISF Schmitt Trigger Q D EN RD PORTF To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS.  2003-2013 Microchip Technology Inc. DS30491D-page 139

18F8680.book Page 140 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-14: RF6:RF3 AND RF0 PINS FIGURE 10-15: RF7 PIN BLOCK BLOCK DIAGRAM DIAGRAM RD LATF RD LATF Data Data Bus Bus D Q D Q WorR LATF VDD WWRR PLAOTRFToFr CK I/O pin WR PORTF CK Q P Data Latch Data Latch D Q D Q N I/O pin Schmitt WR TRISF Trigger CK Input WR TRISF CK Q VSS TRIS Latch Buffer TTL TRIS Latch AIMnnpoadulteog IBnupfufetr RD TRISF RD TRISF ST Input Q D Buffer Q D ENEN EN RD PORTF RD PORTF SS Input To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to VDD and VSS. Note: I/O pins have diode protection to VDD and VSS. DS30491D-page 140  2003-2013 Microchip Technology Inc.

18F8680.book Page 141 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/AN5 bit 0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output. RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output. RF3/AN8/C2IN+ bit 3 ST Input/output port pin, analog input or comparator 2 input (+). RF4/AN9/C2IN- bit 4 ST Input/output port pin, analog input or comparator 2 input (-). RF5/AN10/ bit 5 ST Input/output port pin, analog input, comparator 1 input (+) or C1IN+/CVREF comparator reference output. RF6/AN11/C1IN- bit 6 ST Input/output port pin, analog input or comparator 1 input (-). RF7/SS bit 7 ST/TTL Input/output port pin or slave select pin for synchronous serial port. Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 PORTF Read PORTF pin/Write PORTF Data Latch xxxx xxxx uuuu uuuu LATF Read PORTF Data Latch/Write PORTF Data Latch 0000 0000 uuuu uuuu ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF.  2003-2013 Microchip Technology Inc. DS30491D-page 141

18F8680.book Page 142 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.7 PORTG, TRISG and LATG The pin override value is not loaded into the TRIS reg- Registers ister. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTG is a 6-bit wide port with 5 bidirectional pins and 1 unidirectional pin. The corresponding data direction EXAMPLE 10-7: INITIALIZING PORT register is TRISG. Setting a TRISG bit (= 1) will make CLRF PORTG ; Initialize PORTG by the corresponding PORTG pin an input (i.e., put the ; clearing output corresponding output driver in a high-impedance ; data latches mode). Clearing a TRISG bit (= 0) will make the corre- CLRF LATG ; Alternate method sponding PORTG pin an output (i.e., put the contents ; to clear output of the output latch on the selected pin). ; data latches MOVLW 04h ; Value used to The Data Latch register (LATG) is also memory mapped. ; initialize data Read-modify-write operations on the LATG register read ; direction and write the latched output value for PORTG. MOVWF TRISG ; Set RG1:RG0 as outputs Pins RG0-RG2 on PORTG are multiplexed with the CAN ; RG2 as input peripheral. Refer to Section23.0 “ECAN Module” for ; RG4:RG3 as inputs proper settings of TRISG when CAN is enabled. RG5 is multiplexed with MCLR/VPP. Refer to Register24-5 for Note1: On a Power-on Reset, RG5 is enabled as more information. a digital input only if Master Clear When enabling peripheral functions, care should be functionality is disabled (MCLRE = 0). taken in defining TRIS bits for each PORTG pin. Some 2: If the device Master Clear is disabled, peripherals override the TRIS bit to make a pin an output, verify that either of the following is done to while other peripherals override the TRIS bit to make a ensure proper entry into ICSP mode: pin an input. The user should refer to the corresponding a) disable Low-Voltage Programming peripheral section for the correct TRIS bit settings. (CONFIG4L<2> = 0); or b) make certain that RB5/KBI1/PGM is Note: On a Power-on Reset, these pins are held low during entry into ICSP. configured as digital inputs. FIGURE 10-16: RG0/CANTX1 PIN BLOCK DIAGRAM OPMODE2:OPMODE0 = 000 TXD ENDRHI 0 RD LATG VDD Data Bus 1 D Q P WR PORTG or WR LATG CK Q Data Latch D Q I/O pin WR TRISG N CK Q TRIS Latch VSS RD TRISG OPMODE2:OPMODE0 = 000 Schmitt Trigger Q D ENEN RD PORTG Note: I/O pins have diode protection to VDD and VSS. DS30491D-page 142  2003-2013 Microchip Technology Inc.

18F8680.book Page 143 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-17: RG1/CANTX2 PIN BLOCK DIAGRAM TX1SRC OPMODE2:OPMODE0 = 000 TXD 0 TX2EN CANCLK 1 ENDRHI 0 RD LATG VDD 1 Data Bus D Q P WR PORTG or WR LATG CK Q Data Latch I/O pin D Q WR TRISG N CK Q TRIS Latch VSS OPMODE2:OPMODE0 = 000 RD TRISG Schmitt Trigger Q D EN RD PORTG Note: I/O pins have diode protection to VDD and VSS. FIGURE 10-18: RG2/CANRX PIN BLOCK FIGURE 10-19: RG3 PIN BLOCK DIAGRAM DIAGRAM RD LATG RD LATG Data Bus Data Bus D Q D Q I/O pin I/O pin WR LATG CK WR LATG CK or or WR PORTG Data Latch WR PORTG Data Latch D Q D Q Schmitt Schmitt WR TRISG Trigger WR TRISG Trigger CK Input CK Input TRIS Latch Buffer TRIS Latch Buffer RD TRISG RD TRISG Q D Q D ENEN ENEN RD PORTG RD PORTG CANRX Note: I/O pins have diode protection to VDD and VSS. Note: I/O pins have diode protection to VDD and VSS.  2003-2013 Microchip Technology Inc. DS30491D-page 143

18F8680.book Page 144 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-20: RG4/P1D PIN BLOCK DIAGRAM CCP1 P1D Enable P1D Out RD LATG 1 Data Bus D Q 0 I/O pin WR LATG CK or Auto-Shutdown WR PORTG Data Latch D Q Schmitt WR TRISG CK Trigger Input TRIS Latch Buffer RD TRISG Q D ENEN RD PORTG Note: I/O pins have diode protection to VDD and VSS. FIGURE 10-21: RG5/MCLR/VPP PIN BLOCK DIAGRAM MCLRE Data Bus RG5/MCLR/VPP RD TRISA Schmitt Trigger RD LATA Latch Q D EN RD PORTA High-Voltage Detect HV Internal MCLR Filter Low-Level MCLR Detect DS30491D-page 144  2003-2013 Microchip Technology Inc.

18F8680.book Page 145 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-13: PORTG FUNCTIONS Name Bit# Buffer Type Function RG0/CANTX1 bit 0 ST Input/output port pin or CAN bus transmit output. RG1/CANTX2 bit 1 ST Input/output port pin, CAN bus complimentary transmit output or CAN bus bit time clock. RG2/CANRX bit 2 ST Input/output port pin or CAN bus receive. RG3 bit 3 ST Input/output port pin. RG4/P1D bit 4 ST Input/output port pin or ECCP1 PWM output D. RG5/MCLR/VPP bit 5 ST Master Clear input or programming voltage input (if MCLR is enabled). Input only port pin or programming voltage input (if MCLR is disabled). Legend: ST = Schmitt Trigger input TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTG — — RG5(1) Read PORTF pin/Write PORTF Data Latch --0x xxxx --0u uuuu LATG — — — LATG Data Output Register ---x xxxx ---u uuuu TRISG — — — Data Direction Control Register for PORTG ---1 1111 ---1 1111 Legend: x = unknown, u = unchanged Note 1: RG5 is available as an input only when MCLR is disabled.  2003-2013 Microchip Technology Inc. DS30491D-page 145

18F8680.book Page 146 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.8 PORTH, LATH and TRISH FIGURE 10-22: RH3:RH0 PINS BLOCK Registers DIAGRAM IN I/O MODE Note: PORTH is available only on PIC18F8X8X devices. RD LATH PORTH is an 8-bit wide, bidirectional I/O port. The cor- Data Bus responding data direction register is TRISH. Setting a D Q TRISH bit (= 1) will make the corresponding PORTH I/O pin(1) pin an input (i.e., put the corresponding output driver in WorR LATH CK a high-impedance mode). Clearing a TRISH bit (= 0) PORTH Data Latch will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). D Q Read-modify-write operations on the LATH register WR TRISH Schmitt read and write the latched output value for PORTH. CK Trigger TRIS Latch Input Pins RH7:RH4 are multiplexed with analog inputs Buffer AN15:AN12. Pins RH3:RH0 are multiplexed with the RD TRISH system bus as the external memory interface; they are the high-order address bits, A19:A16. By default, pins RH7:RH4 are enabled as A/D inputs and pins RH3:RH0 are enabled as the system address bus. Q D Register ADCON1 configures RH7:RH4 as I/O or A/D inputs. Register MEMCON configures RH3:RH0 as I/O ENEN or system bus pins. RD PORTH Pins RH7 and RH6 can be configured as the alternate peripheral pins for CCP1 PWM output P1B and P1C, Note 1: I/O pins have diode protection to VDD and VSS. respectively. This is done by clearing the configuration bit ECCPMX, in configuration register CONFIG3H FIGURE 10-23: RH7:RH4 PINS BLOCK (CONFIG3H<1>). DIAGRAM IN I/O MODE Note1: On Power-on Reset, PORTH pins RH7:RH4 default to A/D inputs and read as ‘0’. RD LATH 2: On Power-on Reset, PORTH pins Data Bus RH3:RH0 default to system bus signals. D Q I/O pin(1) WR LATH EXAMPLE 10-8: INITIALIZING PORTH or CK PORTH Data Latch CLRF PORTH ; Initialize PORTH by ; clearing output D Q Schmitt ; data latches Trigger CLRF LATH ; Alternate method WR TRISH CK Input ; to clear output Buffer ; data latches TRIS Latch MOVLW 0Fh ; MOVWF ADCON1 ; RD TRISH MOVLW 0CFh ; Value used to ; initialize data ; direction Q D MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs ENEN RD PORTH To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS. DS30491D-page 146  2003-2013 Microchip Technology Inc.

18F8680.book Page 147 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-24: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTH RD LATD Data Bus Port D Q 0 Data 1 WorR LATH CK I/O pin(1) PORTH Data Latch D Q WR TRISH TTL CK Input TRIS Latch Buffer RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS.  2003-2013 Microchip Technology Inc. DS30491D-page 147

18F8680.book Page 148 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type Function RH0/A16 bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface. RH1/A17 bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface. RH2/A18 bit 2 ST/TTL(1) Input/output port pin or address bit 18 for external memory interface. RH3/A19 bit 3 ST/TTL(1) Input/output port pin or address bit 19 for external memory interface. RH4/AN12 bit 4 ST Input/output port pin or analog input channel 12. RH5/AN13 bit 5 ST Input/output port pin or analog input channel 13. RH6/AN14/P1C(2) bit 6 ST Input/output port pin or analog input channel 14. RH7/AN15/P1B(2) bit 7 ST Input/output port pin or analog input channel 15. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: Alternate pin assignment when ECCPMX configuration bit is cleared. TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Value on Value on: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TRISH PORTH Data Direction Control Register 1111 1111 1111 1111 PORTH Read PORTH pin/Write PORTH Data Latch xxxx xxxx uuuu uuuu LATH Read PORTH Data Latch/Write PORTH Data Latch xxxx xxxx uuuu uuuu ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 MEMCON(1) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 0-00 --00 Legend: x = unknown, u = unchanged, – = unimplemented. Shaded cells are not used by PORTH. Note 1: This register is held in Reset in Microcontroller mode. DS30491D-page 148  2003-2013 Microchip Technology Inc.

18F8680.book Page 149 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.9 PORTJ, TRISJ and LATJ FIGURE 10-25: PORTJ BLOCK DIAGRAM Registers IN I/O MODE Note: PORTJ is available only on PIC18F8X8X devices. RD LATJ PORTJ is an 8-bit wide, bidirectional port. The corre- Data Bus sponding data direction register is TRISJ. Setting a D Q TRISJ bit (= 1) will make the corresponding PORTJ pin I/O pin(1) an input (i.e., put the corresponding output driver in a WorR LATJ CK high-impedance mode). Clearing a TRISJ bit (= 0) will PORTJ Data Latch make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). D Q Schmitt The Data Latch register (LATJ) is also memory WR TRISJ Trigger mapped. Read-modify-write operations on the LATJ CK Input register read and write the latched output value for TRIS Latch Buffer PORTJ. RD TRISJ PORTJ is multiplexed with the system bus as the external memory interface; I/O port functions are only available when the system bus is disabled. When operating as the external memory interface, PORTJ Q D provides the control signal to external memory devices. The RJ5 pin is not multiplexed with any system bus ENEN functions. RD PORTJ When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTJ pin. Some Note 1: I/O pins have diode protection to VDD and VSS. peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs. The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. EXAMPLE 10-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTG by ; clearing output ; data latches CLRF LATJ ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs  2003-2013 Microchip Technology Inc. DS30491D-page 149

18F8680.book Page 150 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-26: RJ5:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ Data Bus Port D Q 0 Data WR LATJ CK 1 I/O pin(1) or PORTJ Data Latch D Q WR TRISJ CK TRIS Latch RD TRISJ Control Out System Bus External Enable Control Drive System Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 10-27: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ Data Bus Port D Q 0 Data 1 WR LATJ CK I/O pin(1) or PORTJ Data Latch D Q WR TRISJ CK TRIS Latch RD TRISJ UB/LB Out System Bus WM = 01 Control Drive System Note 1: I/O pins have diode protection to VDD and VSS. DS30491D-page 150  2003-2013 Microchip Technology Inc.

18F8680.book Page 151 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-17: PORTJ FUNCTIONS Name Bit# Buffer Type Function RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory interface. RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface. RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface. RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface. RJ4/BA0 bit 4 ST Input/output port pin or byte address 0 control for external memory interface. RJ5/CE bit 5 ST Input/output port pin or external memory chip enable. RJ6/LB bit 6 ST Input/output port pin or lower byte select control for external memory interface. RJ7/UB bit 7 ST Input/output port pin or upper byte select control for external memory interface. Legend: ST = Schmitt Trigger input TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTJ Read PORTJ pin/Write PORTJ Data Latch xxxx xxxx uuuu uuuu LATJ LATJ Data Output Register xxxx xxxx uuuu uuuu TRISJ Data Direction Control Register for PORTJ 1111 1111 1111 1111 Legend: x = unknown, u = unchanged  2003-2013 Microchip Technology Inc. DS30491D-page 151

18F8680.book Page 152 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.10 Parallel Slave Port (PSP) FIGURE 10-28: PORTD AND PORTE BLOCK DIAGRAM PORTD also operates as an 8-bit wide Parallel Slave (PARALLEL SLAVE PORT) Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. It is asynchronously readable and writable by the external world through RD Data Bus D Q control input pin, RE0/RD/AD8 and WR control input pin, RE1/WR/AD9. RDx WR LATD CK pin or Note: For PIC18F8X8X devices, the Parallel PORTD Slave Port is available only in Data Latch TTL Microcontroller mode. Q D The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can RD PORTD ENEN read or write the PORTD latch as an 8-bit latch. Setting TRIS Latch bit PSPMODE enables port pin RE0/RD/AD8 to be the RD input, RE1/WR/AD9 to be the WR input and RE2/CS/AD10 to be the CS (chip select) input. For this RD LATD functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits One bit of PORTD PCFG2:PCFG0 (ADCON1<2:0>) must be set, which will configure pins RE2:RE0 as digital I/O. Set Interrupt Flag A write to the PSP occurs when both the CS and WR PSPIF (PIR1<7>) lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (PSPCON<4>) is set. In this mode, the user must make Read sure that the TRISE<2:0> bits are set (pins are config- TTL RD ured as digital inputs) and the ADCON1 is configured Chip Select for digital I/O. In this mode, the input buffers are TTL. TTL CS Write TTL WR Note: I/O pin has protection diodes to VDD and VSS. DS30491D-page 152  2003-2013 Microchip Technology Inc.

18F8680.book Page 153 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 10-1: PSPCON REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A data byte has been received and is waiting to be read by the CPU 0 = No data byte has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written data byte 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input data byte has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FIGURE 10-29: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF  2003-2013 Microchip Technology Inc. DS30491D-page 153

18F8680.book Page 154 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-30: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets PORTD Port Data Latch when Written; Port pins when Read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PORTE RE7/CCP2/ RE6/AD14/ RE5/AD13/ RE4/ RE3/ RE2/CS(1)/ RE1/WR(1)/ RE0/RD(1)/ xxxx xxxx uuuu uuuu AD15 P1B P1C AD12 AD11 AD10 AD9 AD8 LATE LATE Data Output bits xxxx xxxx uuuu uuuu TRISE PORTE Data Direction bits 1111 1111 1111 1111 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 0000 ---- INTCON GIE/ PEIE/ TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Enabled only in Microcontroller mode. DS30491D-page 154  2003-2013 Microchip Technology Inc.

18F8680.book Page 155 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 11.0 TIMER0 MODULE Figure11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure11-2 shows a The Timer0 module has the following features: simplified block diagram of the Timer0 module in 16-bit • Software selectable as an 8-bit or 16-bit timer/ mode. counter The T0CON register (Register11-1) is a readable and • Readable and writable writable register that controls all the aspects of Timer0, • Dedicated 8-bit software programmable prescaler including the prescale selection. • Clock source selectable to be external or internal Note: Timer0 is enabled on POR. • Interrupt-on-overflow from 0FFh to 00h in 8-bit mode and 0FFFFh to 0000h in 16-bit mode • Edge select for external clock REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 155

18F8680.book Page 156 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 Sync with 1 Internal TMR0 RA4/T0CKI pin Programmable 1 Clocks Prescaler T0SE (2 TCY delay) 3 PSA Set Interrupt T0PS2, T0PS1, T0PS0 Flag bit TMR0IF T0CS on Overflow Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 0 T0CKI pinT0SE 1 ProPgrreasmcamlearble 1 (2S ITCynCntloeYccr dnwkeasitllhay) TMR0L HTigMh RB0yte 8 FlSaogne tbO Iintv tTeerMrfrluoRpw0tIF 3 Read TMR0L T0PS2, T0PS1, T0PS0 T0CS PSA Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS30491D-page 156  2003-2013 Microchip Technology Inc.

18F8680.book Page 157 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 11.1 Timer0 Operation 11.2.1 SWITCHING PRESCALER ASSIGNMENT Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software Timer mode is selected by clearing the T0CS bit. In control (i.e., it can be changed “on-the-fly” during Timer mode, the Timer0 module will increment every program execution). instruction cycle (without prescaler). If the TMR0 regis- ter is written, the increment is inhibited for the following 11.3 Timer0 Interrupt two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The TMR0 interrupt is generated when the TMR0 reg- Counter mode is selected by setting the T0CS bit. In ister overflows from 0FFh to 00h in 8-bit mode, or Counter mode, Timer0 will increment either on every 0FFFFh to 0000h in 16-bit mode. This overflow sets the rising or falling edge of pin RA4/T0CKI. The increment- TMR0IF bit. The interrupt can be masked by clearing ing edge is determined by the Timer0 Source Edge the TMR0IE bit. The TMR0IE bit must be cleared in Select bit (T0SE). Clearing the T0SE bit selects the software by the Timer0 module Interrupt Service rising edge. Restrictions on the external clock input are Routine before re-enabling this interrupt. The TMR0 discussed below. interrupt cannot awaken the processor from Sleep since the timer is shut-off during Sleep. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure 11.4 16-Bit Mode Timer Reads the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual and Writes incrementing of Timer0 after synchronization. TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the 11.2 Prescaler high byte of Timer0 (refer to Figure11-2). The high byte An 8-bit counter is available as a prescaler for the of the Timer0 counter/timer is not directly readable nor Timer0 module. The prescaler is not readable or writable. TMR0H is updated with the contents of the writable. high byte of Timer0 during a read of TMR0L. This pro- vides the ability to read all 16 bits of Timer0 without The PSA and T0PS2:T0PS0 bits determine the having to verify that the read of the high and low byte prescaler assignment and prescale ratio. were valid due to a rollover between successive reads Clearing bit PSA will assign the prescaler to the Timer0 of the high and low byte. module. When the prescaler is assigned to the Timer0 A write to the high byte of Timer0 must also take place module, prescale values of 1:2, 1:4, ..., 1:256 are through the TMR0H buffer register. Timer0 high byte is selectable. updated with the contents of TMR0H when a write When assigned to the Timer0 module, all instructions occurs to TMR0L. This allows all 16 bits of Timer0 to be writing to the TMR0 register (e.g., CLRF TMR0, MOVWF updated at once. TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 TRISA — PORTA Data Direction Register -111 1111 -111 1111 Legend: x = unknown, u = unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.  2003-2013 Microchip Technology Inc. DS30491D-page 157

18F8680.book Page 158 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 158  2003-2013 Microchip Technology Inc.

18F8680.book Page 159 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 12.0 TIMER1 MODULE Figure12-1 is a simplified block diagram of the Timer1 module. The Timer1 module timer/counter has the following Register12-1 details the Timer1 Control register. This features: register controls the operating mode of the Timer1 • 16-bit timer/counter module and contains the Timer1 Oscillator Enable bit (two 8-bit registers; TMR1H and TMR1L) (T1OSCEN). Timer1 can be enabled or disabled by • Readable and writable (both registers) setting or clearing control bit, TMR1ON (T1CON<0>). • Internal or external clock select • Interrupt on overflow from 0FFFFh to 0000h • Reset from CCP module special event trigger REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 159

18F8680.book Page 160 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruc- tion cycle. When TMR1CS = 1, Timer1 increments on Timer1 can operate in one of these modes: every rising edge of the external clock input or the • As a timer Timer1 oscillator if enabled. • As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is • As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored and the pins are read as ‘0’. bit, TMR1CS (T1CON<1>). Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section15.0 “Capture/Compare/PWM (CCP) Modules”). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF CCP Special Event Trigger Overflow Interrupt TMR1 0 Synchronized Flag Bit CLR Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T13CKI/T1OSO T1OSCEN 1 Prescaler Synchronize T1OSI EOnsacbilllaetor(1) IFnOteSrCn/a4l 0 1, 2, 4, 8 det Clock 2 Sleep Input T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L CCP Special Event Trigger Read TMR1L TOInMvteeRrrr1fuloIpFwt 8 Timer 1 TMR1 CLR 0 SyCnlocchkro Innipzuetd Flag bit High Byte TMR1L 1 TMR1ON On/Off T1SYNC T1OSC T13CKI/T1OSO 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR1CS Sleep Input T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30491D-page 160  2003-2013 Microchip Technology Inc.

18F8680.book Page 161 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 12.2 Timer1 Oscillator 12.4 Resetting Timer1 Using a CCP Trigger Output A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by If the CCP module is configured in Compare mode setting control bit, T1OSCEN (T1CON<3>). The oscil- to generate a “special event trigger” lator is a low-power oscillator rated up to 200 kHz. It will (CCP1M3:CCP1M0 = 1011), this signal will reset continue to run during Sleep. It is primarily intended for Timer1 and start an A/D conversion (if the A/D module a 32 kHz crystal. Table12-1 shows the capacitor is enabled). selection for the Timer1 oscillator. Note: The special event triggers from the CCP1 The user must provide a software time delay to ensure module will not set interrupt flag bit proper start-up of the Timer1 oscillator. TMR1IF (PIR1<0>). TABLE 12-1: CAPACITOR SELECTION Timer1 must be configured for either Timer or Synchro- FOR THE ALTERNATE nized Counter mode to take advantage of this feature. OSCILLATOR If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. Osc Type Freq C1 C2 In the event that a write to Timer1 coincides with a LP 32 kHz TBD(1) TBD(1) special event trigger from CCP1, the write will take precedence. Crystal to be Tested: In this mode of operation, the CCPR1H:CCPR1L register 32.768 kHz Epson C-001R32.768K-A  20 PPM pair effectively becomes the period register for Timer1. Note1: Microchip suggests 33 pF as a starting point in validating the oscillator circuit. 12.5 Timer1 16-Bit Read/Write Mode 2: Higher capacitance increases the stability Timer1 can be configured for 16-bit reads and writes of the oscillator but also increases the (see Figure12-2). When the RD16 control bit start-up time. (T1CON<7>) is set, the address for TMR1H is mapped 3: Since each resonator/crystal has its own to a buffer register for the high byte of Timer1. A read characteristics, the user should consult from TMR1L will load the contents of the high byte of the resonator/crystal manufacturer for Timer1 into the Timer1 high byte buffer. This provides appropriate values of external the user with the ability to accurately read all 16 bits of components. Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid 4: Capacitor values are for design guidance due to a rollover between reads. only. A write to the high byte of Timer1 must also take place 12.3 Timer1 Interrupt through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write The TMR1 register pair (TMR1H:TMR1L) increments occurs to TMR1L. This allows a user to write all 16 bits from 0000h to 0FFFFh and rolls over to 0000h. The to both the high and low bytes of Timer1 at once. TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF The high byte of Timer1 is not directly readable or writ- (PIR1<0>). This interrupt can be enabled/disabled by able in this mode. All reads and writes must take place setting/clearing TMR1 interrupt enable bit, TMR1IE through the Timer1 High Byte Buffer register. Writes to (PIE1<0>). TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2003-2013 Microchip Technology Inc. DS30491D-page 161

18F8680.book Page 162 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 13.0 TIMER2 MODULE 13.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is • 8-bit timer (TMR2 register) readable and writable and is cleared on any device • 8-bit period register (PR2) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits, • Software programmable prescaler (1:1, 1:4, 1:16) T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out- • Software programmable postscaler (1:1 to 1:16) put of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a • Interrupt on TMR2 match of PR2 TMR2 interrupt latched in flag bit, TMR2IF (PIR1<1>). • SSP module optional use of TMR2 output to generate clock shift The prescaler and postscaler counters are cleared when any of the following occurs: Timer2 has a control register shown in Register13-1. Timer2 can be shut-off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register Figure13-1 is a simplified block diagram of the Timer2 • any device Reset (Power-on Reset, MCLR Reset, module. Register13-1 shows the Timer2 Control regis- Watchdog Timer Reset, or Brown-out Reset) ter. The prescaler and postscaler selection of Timer2 TMR2 is not cleared when T2CON is written. are controlled by this register. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale • • • 1111 = 1:16 postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 162  2003-2013 Microchip Technology Inc.

18F8680.book Page 163 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 13.2 Timer2 Interrupt 13.3 Output of TMR2 The Timer2 module has an 8-bit period register, PR2. The output of TMR2 (before the postscaler) is fed to the Timer2 increments from 00h until it matches PR2 and synchronous serial port module which optionally uses it then resets to 00h on the next increment cycle. PR2 is to generate the shift clock. a readable and writable register. The PR2 register is initialized to 0FFh upon Reset. FIGURE 13-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 Output(1) bit TMR2IF Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS1:T2CKPS0 PR2 4 T2OUTPS3:T2OUTPS0 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.  2003-2013 Microchip Technology Inc. DS30491D-page 163

18F8680.book Page 164 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 14.0 TIMER3 MODULE Figure14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following Register14-1 shows the Timer3 Control register. This features: register controls the operating mode of the Timer3 • 16-bit timer/counter module and sets the Enhanced CCP1 and CCP2 clock (two 8-bit registers; TMR3H and TMR3L) source. • Readable and writable (both registers) Register12-1 shows the Timer1 Control register. This • Internal or external clock select register controls the operating mode of the Timer1 • Interrupt on overflow from FFFFh to 0000h module, as well as containing the Timer1 oscillator • Reset from CCP module trigger enable bit (T1OSCEN) which can be a clock source for Timer3. REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x =Timer3 is the clock source for compare/capture of CCP1 and CCP2 modules 01 =Timer3 is the clock source for compare/capture of CCP2 module, Timer1 is the clock source for compare/capture of CCP1 module 00 =Timer1 is the clock source for compare/capture of CCP1 and CCP2 modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 164  2003-2013 Microchip Technology Inc.

18F8680.book Page 165 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on Timer3 can operate in one of these modes: every rising edge of the Timer1 external clock input or • As a timer the Timer1 oscillator if enabled. • As a synchronous counter When the Timer1 oscillator is enabled (T1OSCEN is • As an asynchronous counter set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is The operating mode is determined by the clock select ignored and the pins are read as ‘0’. bit, TMR3CS (T3CON<1>). Timer3 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section14.0 “Timer3 Module”). FIGURE 14-1: TIMER3 BLOCK DIAGRAM CCP Special Trigger TMR3IF T3CCPx Overflow Interrupt Synchronized 0 Flag bit CLR Clock Input TMR3H TMR3L 1 TMR3ON On/Off T3SYNC T1OSO/ T1OSC (3) T13CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 TMR3CS Sleep Input T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 14-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 8 Write TMR3L Read TMR3L CCP Special Trigger Set TMR3IF Flag bit 8 TMR3 T3CCPx 0 Synchronized on Overflow Timer3 CLR Clock Input High Byte TMR3L 1 To Timer1 Clock Input TMR3ON On/Off T3SYNC T1OSC T1OSO/ T13CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 T1OSI Oscillator(1) Clock 2 Sleep Input T3CKPS1:T3CKPS0 TMR3CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.  2003-2013 Microchip Technology Inc. DS30491D-page 165

18F8680.book Page 166 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 14.2 Timer1 Oscillator 14.4 Resetting Timer3 Using a CCP Trigger Output The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting If the CCP module is configured in Compare mode the T1OSCEN (T1CON<3>) bit. The oscillator is a low- to generate a “special event trigger” power oscillator rated up to 200 kHz. See Section12.0 (CCP1M3:CCP1M0=1011), this signal will reset “Timer1 Module” for further details. Timer3. Note: The special event triggers from the CCP 14.3 Timer3 Interrupt module will not set interrupt flag bit, The TMR3 register pair (TMR3H:TMR3L) increments TMR3IF (PIR1<0>). from 0000h to 0FFFFh and rolls over to 0000h. The Timer3 must be configured for either Timer or Synchro- TMR3 interrupt, if enabled, is generated on overflow nized Counter mode to take advantage of this feature. which is latched in interrupt flag bit, TMR3IF If Timer3 is running in Asynchronous Counter mode, (PIR2<1>). This interrupt can be enabled/disabled by this Reset operation may not work. In the event that a setting/clearing TMR3 interrupt enable bit, TMR3IE write to Timer3 coincides with a special event trigger (PIE2<1>). from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer3. TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 GIEH GIEL PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. DS30491D-page 166  2003-2013 Microchip Technology Inc.

18F8680.book Page 167 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.0 CAPTURE/COMPARE/PWM Additionally, the CCP2 special event trigger may be (CCP) MODULES used to start an A/D conversion if the A/D module is enabled. PIC18FXX80/XX85 devices contain a total of two CCP To avoid duplicate information, this section describes modules: CCP1 and CCP2. CCP1 is an enhanced basic CCP module operation that applies to both CCP1 version of the CCP2 module. CCP1 is fully backward and CCP2. Enhanced CCP functionality of the compatible with the CCP2 module. CCP1module is described in Section16.0 “Enhanced The CCP1 module differs from CCP2 in the following Capture/Compare/PWM (ECCP) Module”. respect: The control registers for the CCP1 and CCP2 modules • CCP1 contains a special trigger event that may are shown in Register15-1 and Register15-2, reset Timer1 or the Timer3 register pair respectively. Table15-2 details the interactions of the • CCP1 contains “CAN Message Time-Stamp Trigger” CCP and ECCP modules. • CCP1 contains enhanced PWM output with programmable dead band and auto-shutdown functionality REGISTER 15-1: CCP1CON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx =P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 =Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 =Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 =Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 =Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP pin low, on compare match force CCP pin high 1001 = Compare mode, initialize CCP pin high, on compare match force CCP pin low 1010 = Compare mode, generate software interrupt only, CCP pin is unaffected 1011 = Compare mode, trigger special event, resets TMR1 or TMR3 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 167

18F8680.book Page 168 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 15-2: CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR2L. bit 3-0 CCP2M3:CCP2M0: CCP2 Mode Select bits 0000 =Capture/Compare/PWM off (resets CCP2 module) 0001 =Reserved 0010 =Compare mode, toggle output on match 0011 =Reserved 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, initialize CCP pin low, on compare match force CCP pin high 1001 =Compare mode, initialize CCP pin high, on compare match force CCP pin low 1010 =Compare mode, generate software interrupt only, CCP pin is unaffected 1011 =Compare mode, trigger special event, resets TMR1 or TMR3 and starts A/D conversion if A/D module is enabled 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 168  2003-2013 Microchip Technology Inc.

18F8680.book Page 169 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.1 CCP Module An event is selected by control bits CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the inter- Both CCP1 and CCP2 are comprised of two 8-bit rupt request flag bit, CCPxIF (PIR registers), is set. It registers: CCPRxL (low byte) and CCPRxH (high byte), must be cleared in software. If another capture occurs 1x2. The CCPxCON register controls the before the value in register CCPRx is read, the old operation of CCPx. All are readable and writable. captured value will be lost. Table15-1 shows the timer resources of the CCP module modes. 15.2.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured TABLE 15-1: CCP MODE – TIMER as an input by setting the appropriate TRIS bit. RESOURCE Note: If the CCPx is configured as an output, a CCP Mode Timer Resource write to the port can cause a capture condition. Capture Timer1 or Timer3 Compare Timer1 or Timer3 15.2.2 TIMER1/TIMER3 MODE SELECTION PWM Timer2 The timer used with each CCP module is selected in the T3CCP2:T3CCP1 bits of the T3CON register. The 15.2 Capture Mode timers used with the capture feature (either Timer1 or Timer3) must be running in Timer mode or Synchro- In Capture mode, CCPRxH:CCPRxL captures the nized Counter mode. In Asynchronous Counter mode, 16-bit value of the TMR1 or TMR3 register when an the capture operation may not work. event occurs on pin CCPn. An event is defined as: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge TABLE 15-2: INTERACTION OF CCP MODULES CCP1 CCP2 Interaction Mode Mode Capture Capture TMR1 or TMR3 time base. Time base can be different for each CCP. Capture Compare The compare could be configured for the special event trigger which clears either TMR1 or TMR3 depending upon which time base is used. Compare Compare The compare(s) could be configured for the special event trigger which clears TMR1 or TMR3 depending upon which time base is used. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None.  2003-2013 Microchip Technology Inc. DS30491D-page 169

18F8680.book Page 170 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.2.3 SOFTWARE INTERRUPT 15.2.5 CAN MESSAGE TIME-STAMP When the Capture mode is changed, a false capture The CAN capture event occurs when a message is interrupt may be generated. The user should keep bit received in any of the receive buffers. When config- CCPxIE (PIE registers) clear to avoid false interrupts ured, the CAN module provides the trigger to the CCP1 and should clear the flag bit, CCPxIF, following any module to cause a capture event. This feature is such change in operating mode. provided to time-stamp the received CAN messages. This feature is enabled by setting the CANCAP bit of 15.2.4 CCP PRESCALER the CAN I/O Control register (CIOCON<4>). The There are four prescaler settings specified by bits message receive signal from the CAN module then CCPxM3:CCPxM0. Whenever the CCPx module is takes the place of the events on RC2/CCP1. turned off, or the CCPx module is not in Capture mode, the prescaler counter is cleared. This means that any EXAMPLE 15-1: CHANGING BETWEEN Reset will clear the prescaler counter. CAPTURE PRESCALERS Switching from one capture prescaler to another may CLRF CCP1CON ; Turn CCP module off generate an interrupt. The prescaler counter will not be MOVLW NEW_CAPT_PS ; Load WREG with the cleared; therefore, the first capture may be from a ; new prescaler mode non-zero prescaler. Example15-1 shows the ; value and CCP ON recommended method for switching between capture MOVWF CCP1CON ; Load CCP1CON with prescalers. This example also clears the prescaler ; this value counter and will not generate the “false” interrupt. FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set Flag bit CCP1IF T3CCP2 TMR3 Prescaler Enable  1, 4, 16 CCP1 pin CCPR1H CCPR1L TMR1 and T3CCP2 Enable Edge Detect TMR1H TMR1L CCP1CON<3:0> Q’s Set Flag bit CCP2IF T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Prescaler Enable  1, 4, 16 CCP2 pin CCPR2H CCPR2L and TMR1 Edge Detect Enable T3CCP2 T3CCP1 TMR1H TMR1L CCP2CON<3:0> Q’s DS30491D-page 170  2003-2013 Microchip Technology Inc.

18F8680.book Page 171 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.3 Compare Mode 15.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is The timer used with each CCP module is selected in constantly compared against either the TMR1 register the T3CCP2:T3CCP1 bits of the T3CON register. pair value or the TMR3 register pair value. When a Timer1 and/or Timer3 must be running in Timer mode, match occurs, the CCPx pin can have one of the or Synchronized Counter mode, if the CCP module is following actions: using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • Driven high • Driven low 15.3.3 SOFTWARE INTERRUPT MODE • Toggle output (high-to-low or low-to-high) When generate software interrupt is chosen, the CCPx • Remains unchanged pin is not affected. Only a CCP interrupt is generated (if The action on the pin is based on the value of control enabled). bits, CCPxM3:CCPxM0. At the same time, interrupt 15.3.4 SPECIAL EVENT TRIGGER flag bit, CCPxIF, is set. In this mode, an internal hardware trigger is generated When configured to drive the CCP pin, the CCP1 pin which may be used to initiate an action. cannot be changed; CCP1 module controls the pin. The special event trigger output of CCP1 resets either 15.3.1 CCP PIN CONFIGURATION the TMR1 or TMR3 register pair. This allows the CCPR1 The user must configure the CCPx pin as an output by register to effectively be a 16-bit programmable period clearing the appropriate TRIS bit. register for TMR1 or TMR3. By default, the CCP2 pin is multiplexed with RC1. Additionally, the CCP2 special event trigger will start an Alternately, it can also be multiplexed with either RB3 A/D conversion if the A/D module is enabled. or RE7. This is done by changing the CCP2MX Note: The special event trigger from the CCPx configuration bit. module will not set the Timer1 or Timer3 Note: Clearing the CCPxCON register will force interrupt flag bits. the CCPx compare output latch to the default low level. This is not the data latch. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only) Set Flag bit CCP1IF CCPR1H CCPR1L Q S Output RC2/CCP1 pin R Logic Match Comparator TRISC<2> Output Enable CCP1CON<3:0> T3CCP2 0 1 Mode Select TMR1H TMR1L TMR3H TMR3L Special Event Trigger Set Flag bit CCP2IF T3CCP1 T3CCP2 0 1 Q S Output Comparator RC1/CCP2 pin R Logic Match TRISC<1> CCPR2H CCPR2L Output Enable CCP2CON<3:0> Mode Select  2003-2013 Microchip Technology Inc. DS30491D-page 171

18F8680.book Page 172 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u GIEH GIEL PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISD PORTD Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by capture and Timer1. DS30491D-page 172  2003-2013 Microchip Technology Inc.

18F8680.book Page 173 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.4 PWM Mode 15.4.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. For register. The PWM period can be calculated using the PWM mode to function properly, the TRIS bit for the following formula. CCPx pin must be cleared to make it an output. EQUATION 15-1: Note: Clearing the CCPxCON register will force the CCPx PWM output latch to the default PWM Period = [(PR2) + 1] • 4 • TOSC • low level. This is not the port data latch. (TMR2 Prescale Value) Figure15-3 shows a simplified block diagram of the CCP module in PWM mode. PWM frequency is defined as 1/[PWM period]. For a step-by-step procedure on how to set up the CCP When TMR2 is equal to PR2, the following three events module for PWM operation, see Section15.4.3 occur on the next increment cycle: “Setup for PWM Operation”. • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty FIGURE 15-3: SIMPLIFIED PWM BLOCK cycle=0%, the CCP1 pin will not be set) DIAGRAM • The PWM duty cycle is latched from CCPR1L into CCPR1H Duty Cycle Registers CCPxCON<5:4> Note: The Timer2 postscaler (see Section13.0 CCPRxL (Master) “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than CCPRxH (Slave) the PWM output. Comparator R Q 15.4.2 PWM DUTY CYCLE CCPx The PWM duty cycle is specified by writing to the TMR2 (Note 1) CCPRxL register and to the CCPxCON<5:4> bits. Up S to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contain the Comparator TRIS bit two LSbs. This 10-bit value is represented by Cselet aCrC TPimx epri,n and CCPRxL:CCPxCON<5:4>. The following equation is PR2 latch D.C. used to calculate the PWM duty cycle in time. EQUATION 15-2: Note1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base. PWM Duty Cycle = (CCPRxL:CCPxCON<5:4>) • TOSC • (TMR2 Prescale Value) A PWM output (Figure15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period CCPRxL and CCPxCON<5:4> can be written to at any (1/period). time but the duty cycle value is not latched into CCPRxH until after a match between PR2 and TMR2 FIGURE 15-4: PWM OUTPUT occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Period The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. Duty Cycle When the CCPRxH and 2-bit latch match TMR2, TMR2 = PR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. TMR2 = Duty Cycle TMR2 = PR2  2003-2013 Microchip Technology Inc. DS30491D-page 173

18F8680.book Page 174 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 The maximum PWM resolution (bits) for a given PWM 15.4.3 SETUP FOR PWM OPERATION frequency is given by the following equation. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 15-3: 1. Set the PWM period by writing to the PR2 log-F----O----S---C--- register. PWM Resolution (max) = ------------F---P---W-----M------bits 2. Set the PWM duty cycle by writing to the log2 CCPRxL register and CCPxCON<5:4> bits. 3. Make the CCPx pin an output by clearing corresponding TRIS bit. Note: If the PWM duty cycle value is longer than 4. Set the TMR2 prescale value and enable Timer2 the PWM period, the CCP1 pin will not be by writing to T2CON. cleared. 5. Configure the CCPx module for PWM operation. TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 312.5 kHz 416.6 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0FFh 0FFh 0FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. DS30491D-page 174  2003-2013 Microchip Technology Inc.

18F8680.book Page 175 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.0 ENHANCED CAPTURE/ The control register for CCP1 is shown in Register16-1. COMPARE/PWM (ECCP) In addition to the expanded functions of the MODULE CCP1CON register, the CCP1 module has two additional registers associated with enhanced PWM The CCP1 module is implemented as a standard CCP operation and auto-shutdown features: module with enhanced PWM capabilities. These capa- • ECCP1DEL bilities allow for 2 or 4 output channels, user selectable • ECCP1AS polarity, dead-band control, and automatic shutdown and restart and are discussed in detail in Section16.2 “Enhanced PWM Mode”. REGISTER 16-1: CCP1CON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 =Single output; P1A modulated, P1B, P1C, P1D assigned as port pins 01 =Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 =Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 =Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits 0000 =Capture/Compare/PWM off (resets CCP1 module) 0001 =Reserved 0010 =Compare mode, toggle output on match 0011 =Capture mode, CAN message time-stamp 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, initialize CCP pin low, on compare match, force CCP pin high 1001 =Compare mode, initialize CCP pin high, on compare match, force CCP pin low 1010 =Compare mode, generate software interrupt only, CCP pin is unaffected 1011 =Compare mode, trigger special event, resets TMR1 or TMR3 1100 =PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 =PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 =PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 =PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 175

18F8680.book Page 176 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.1 ECCP Outputs To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mx and The enhanced CCP module may have up to four CCP1Mx bits (CCP1CON<7:6> and <3:0>, respec- outputs depending on the selected operating mode. tively). The appropriate TRIS direction bits for the port These outputs, designated P1A through P1D, are pins must also be set as outputs. multiplexed with I/O pins RC2, RE6, RE5 and RG4. The pin assignments are summarized in Table16-1. TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES CCP1CON ECCP Mode RC2 RE6 RE5 RG4 Configuration Compatible CCP 00xx11xx CCP1 RE6 RE5 RG4 Dual PWM 10xx11xx P1A P1B(2) RE5 RG4 Quad PWM x1xx11xx P1A P1B(2) P1C(2) P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode. Note 1: TRIS register values must be configured appropriately. 2: On PIC18F8X8X devices, these pins can be alternately multiplexed with RH7 or RH6 by changing the ECCPMX configuration bit. FIGURE 16-1: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3, but will not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion. Set Flag bit CCP1IF CCPR1H CCPR1L Q S Output Comparator RB3/CCP1/P1A pin R Logic Match TRISB<3> Output Enable T3CCP2 0 1 CCP1CON<3:0> Mode Select TMR1H TMR1L TMR3H TMR3L DS30491D-page 176  2003-2013 Microchip Technology Inc.

18F8680.book Page 177 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2 Enhanced PWM Mode 16.2.2 PWM DUTY CYCLE The Enhanced PWM mode provides additional PWM The PWM duty cycle is specified by writing to the output options for a broader range of control applica- CCPR1L register and to the CCP1CON<5:4> bits. Up tions. The module is a backward compatible version of to 10-bit resolution is available. The CCPR1L contains the standard CCP module and offers up to four outputs, the eight MSbs and the CCP1CON<5:4> contains the designated P1A through P1D. Users are also able to two LSbs. This 10-bit value is represented by select the polarity of the signal (either active-high or CCPR1L:CCP1CON<5:4>. The PWM duty cycle is active-low). The module’s output mode and polarity are calculated by the following equation. configured by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits of the CCP1CON register EQUATION 16-2: (CCP1CON<7:6> and CCP1CON<3:0>, respectively). PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) • Figure16-2 shows a simplified block diagram of PWM TOSC • (TMR2 Prescale Value) operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the CCPR1L and CCP1CON<5:4> can be written to at any period boundary when Timer2 resets) in order to pre- time, but the duty cycle value is not copied into vent glitches on any of the outputs. The exception is the CCPR1H until a match between PR2 and TMR2 occurs PWM Delay register, ECCP1DEL, which is loaded at (i.e., the period is complete). In PWM mode, CCPR1H either the duty cycle boundary or the boundary period is a read-only register. (whichever comes first). Because of the buffering, the The CCPR1H register and a 2-bit internal latch are module waits until the assigned timer resets instead of used to double-buffer the PWM duty cycle. This starting immediately. This means that enhanced PWM double-buffering is essential for glitchless PWM opera- waveforms do not exactly match the standard PWM tion. When the CCPR1H and 2-bit latch match TMR2, waveforms, but are instead offset by one full instruction concatenated with an internal 2-bit Q clock or two bits cycle (4 TOSC). of the TMR2 prescaler, the CCP1 pin is cleared. The As before, the user must manually configure the maximum PWM resolution (bits) for a given PWM appropriate TRIS bits for output. frequency is given by the following equation: 16.2.1 PWM PERIOD EQUATION 16-3: The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the log FOSC FPWM following equation. PWM Resolution (max) = bits log(2) EQUATION 16-1: PWM Period = [(PR2) + 1] • 4 • TOSC • Note: If the PWM duty cycle value is longer than (TMR2 Prescale Value) the PWM period, the CCP1 pin will not be PWM frequency is defined as 1/[PWM period]. When cleared. TMR2 is equal to PR2, the following three events occur 16.2.3 PWM OUTPUT CONFIGURATIONS on the next increment cycle: • TMR2 is cleared The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: • The CCP1 pin is set (if PWM duty cycle=0%, the CCP1 pin will not be set) • Single Output • The PWM duty cycle is copied from CCPR1L into • Half-Bridge Output CCPR1H • Full-Bridge Output, Forward mode • Full-Bridge Output, Reverse mode Note: The Timer2 postscaler (see Section13.0 “Timer2 Module”) is not used in the The Single Output mode is the standard PWM mode determination of the PWM frequency. The discussed in Section16.2 “Enhanced PWM Mode”. postscaler could be used to have a servo The Half-Bridge and Full-Bridge Output modes are update rate at a different frequency than covered in detail in the sections that follow. the PWM output. The general relationship of the outputs in all configurations is summarized in Figure16-3.  2003-2013 Microchip Technology Inc. DS30491D-page 177

18F8680.book Page 178 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 FIGURE 16-2: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A RC2/CCP1/P1A TRISC<2> CCPR1H (Slave) P1B RE6/AD14/P1B or RH7(2) Comparator R Q Output TRISE<6> Controller P1C RE5/AD13/P1C or RH6(2) TMR2 (Note 1) S TRISE<5> P1D RG4/P1D Comparator Clear Timer, TRISG<4> set CCP1 pin and latch D.C. PR2 CCP1DEL Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base. 2: Alternate setting controlled by the ECCPMX bit (PIC18F8X8X devices only). FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) CCP1CON SIGNAL 0 Duty PR2 + 1 Cycle <7:6> Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section16.2.6 “Programmable Dead-Band Delay”). DS30491D-page 178  2003-2013 Microchip Technology Inc.

18F8680.book Page 179 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 16-4: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON SIGNAL 0 Duty PR2 + 1 Cycle <7:6> Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section16.2.6 “Programmable Dead-Band Delay”). Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value) • Delay = 4 * TOSC * (PWM1CON<6:0>)  2003-2013 Microchip Technology Inc. DS30491D-page 179

18F8680.book Page 180 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.4 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the In the Half-Bridge Output mode, two pins are used as TRISC<2> and TRISE<6> bits must be cleared to outputs to drive push-pull loads. The PWM output signal configure P1A and P1B as outputs. is output on the P1A pin while the complementary PWM output signal is output on the P1B pin (Figure16-5). FIGURE 16-5: HALF-BRIDGE PWM This mode can be used for half-bridge applications, as shown in Figure16-6, or for full-bridge applications OUTPUT where four power switches are being modulated with Period Period two PWM signals. Duty Cycle In Half-Bridge Output mode, the programmable dead- band delay can be used to prevent shoot-through P1A(2) current in half-bridge power devices. The value of bits td PDC6:PDC0 sets the number of instruction cycles td before the output is driven active. If the value is greater P1B(2) than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section16.2.6 (1) (1) (1) “Programmable Dead-Band Delay” for more details of the dead-band delay operations. td = Dead-band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 16-6: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18FXX80/XX85 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18FXX80/XX85 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS30491D-page 180  2003-2013 Microchip Technology Inc.

18F8680.book Page 181 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data In Full-Bridge Output mode, four pins are used as latches. The TRISC<2>, TRISC<6:5> and TRISG<4> outputs; however, only two outputs are active at a time. bits must be cleared to make the P1A, P1B, P1C and In the Forward mode, pin P1A is continuously active P1D pins outputs. and pin P1D is modulated. In the Reverse mode, pin PGC is continuously active and pin P1B is modulated. These are illustrated in Figure16-7. FIGURE 16-7: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high.  2003-2013 Microchip Technology Inc. DS30491D-page 181

18F8680.book Page 182 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 16-8: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18FXX80/XX85 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 16.2.5.1 Direction Change in Full-Bridge Mode Figure16-10 shows an example where the PWM direc- tion changes from forward to reverse at a near 100% In the Full-Bridge Output mode, the P1M1 bit in the duty cycle. At time t1, the output P1A and P1D become CCP1CON register allows the user to control the inactive while output P1C becomes active. In this forward/reverse direction. When the application example, since the turn off time of the power devices is firmware changes this direction control bit, the module longer than the turn on time, a shoot-through current will assume the new direction on the next PWM cycle. may flow through power devices QC and QD (see Just before the end of the current PWM period, the mod- Figure16-8) for the duration of ‘t’. The same phenom- ulated outputs (P1B and P1D) are placed in their inactive enon will occur to power devices QA and QB for PWM state while the unmodulated outputs (P1A and P1C) are direction change from reverse to forward. switched to drive in the opposite direction. This occurs in If changing PWM direction at high duty cycle is required a time interval of (4 TOSC * (Timer2 Prescale value)) for an application, one of the following requirements before the next PWM period begins. The Timer2 must be met: prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS bit (T2CON<1:0>). During the 1. Reduce PWM for a PWM period before interval from the switch of the unmodulated outputs to changing directions. the beginning of the next period, the modulated outputs 2. Use switch drivers that can drive the switches off (P1B and P1D) remain inactive. This relationship is faster than they can drive them on. shown in Figure16-9. Other options to prevent shoot-through current may Note that in the Full-Bridge Output mode, the CCP1 exist. module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. DS30491D-page 182  2003-2013 Microchip Technology Inc.

18F8680.book Page 183 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 16-9: PWM DIRECTION CHANGE SIGNAL Period(1) Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at inter- vals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 16-10: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B DC P1C P1D DC tON External Switch C tOFF External Switch D Potential t = tOFF – tON Shoot-Through Current Note 1: All signals are shown as active-high. 2: tON is the turn on delay of power switch QC and its driver. 3: tOFF is the turn off delay of power switch QD and its driver.  2003-2013 Microchip Technology Inc. DS30491D-page 183

18F8680.book Page 184 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.6 PROGRAMMABLE A shutdown event can be caused by either of the two DEAD-BAND DELAY comparator modules or a low level on the RB0 pin (or any combination of these three sources). The compar- In half-bridge applications where all power switches are ators may be used to monitor a voltage input propor- modulated at the PWM frequency at all times, the tional to a current being monitored in the bridge circuit. power switches normally require more time to turn off If the voltage exceeds a threshold, the comparator than to turn on. If both the upper and lower power switches state and triggers a shutdown. Alternatively, a switches are switched at the same time (one turned on low digital signal on the RB0 pin can also trigger a and the other turned off), both switches may be on for shutdown. The auto-shutdown feature can be disabled a short period of time until one switch completely turns by not selecting any auto-shutdown sources. The off. During this brief interval, a very high current (shoot- auto-shutdown sources to be used are selected using through current) may flow through both power the ECCPAS2:ECCPAS0 bits (bits <6:4> of the switches, shorting the bridge supply. To avoid this ECCP1AS register). potentially destructive shoot-through current from flow- ing during switching, turning on either of the power When a shutdown occurs, the output pins are asyn- switches is normally delayed to allow the other switch chronously placed in their shutdown states, specified to completely turn off. by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/ In the Half-Bridge Output mode, a digitally pro- P1D) may be set to drive high, drive low, or be tri-stated grammable dead-band delay is available to avoid (not driving). The ECCPASE bit (ECCP1AS<7>) is also shoot-through current from destroying the bridge set to hold the enhanced PWM outputs in their power switches. The delay occurs at the signal shutdown states. transition from the non-active state to the active state. See Figure16-5 for an illustration. The lower seven bits The ECCPASE bit is set by hardware when a shutdown of the ECCP1DEL register (Register16-2) set the event occurs. If automatic restarts are not enabled, the delay period in terms of microcontroller instruction ECCPASE bit is cleared by firmware when the cause of cycles (TCY or 4 TOSC). the shutdown clears. If automatic restarts are enabled, the ECCPASE bit is automatically cleared when the 16.2.7 ENHANCED PWM cause of the auto-shutdown has cleared. AUTO-SHUTDOWN If the ECCPASE bit is set when a PWM period begins, When the CCP1 is programmed for any of the the PWM outputs remain in their shutdown state for that enhanced PWM modes, the active output pins may be entire PWM period. When the ECCPASE bit is cleared, configured for auto-shutdown. Auto-shutdown immedi- the PWM outputs will return to normal operation at the ately places the enhanced PWM output pins into a beginning of the next PWM period. defined shutdown state when a shutdown event Note: Writing to the ECCPASE bit is disabled occurs. while a shutdown condition is active. REGISTER 16-2: ECCP1DEL: ECCP1 DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 184  2003-2013 Microchip Technology Inc.

18F8680.book Page 185 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits 000 =Auto-shutdown is disabled 001 =Comparator 1 output 010 =Comparator 2 output 011 =Either Comparator 1 or 2 100 =RB0 101 =RB0 or Comparator 1 110 =RB0 or Comparator 2 111 =RB0 or Comparator 1 or Comparator 2 bit 3-2 PSSACn: Pins A and C Shutdown State Control bits 00 =Drive pins A and C to ‘0’ 01 =Drive pins A and C to ‘1’ 1x =Pins A and C tri-state bit 1-0 PSSBDn: Pins B and D Shutdown State Control bits 00 =Drive pins B and D to ‘0’ 01 =Drive pins B and D to ‘1’ 1x =Pins B and D tri-state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 185

18F8680.book Page 186 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.7.1 Auto-Shutdown and Automatic 16.2.8 START-UP CONSIDERATIONS Restart When the ECCP module is used in the PWM mode, the The auto-shutdown feature can be configured to allow application hardware must use the proper external pull- automatic restarts of the module following a shutdown up and/or pull-down resistors on the PWM output pins. event. This is enabled by setting the PRSEN bit of the When the microcontroller is released from Reset, all of ECCP1DEL register (ECCP1DEL<7>). the I/O pins are in the high-impedance state. The exter- nal circuits must keep the power switch devices in the In Shutdown mode with PRSEN = 1 (Figure16-11), the off state until the microcontroller drives the I/O pins with ECCPASE bit will remain set for as long as the cause the proper signal levels or activates the PWM output(s). of the shutdown continues. When the shutdown condi- tion clears, the ECCPASE bit is cleared. If PRSEN = 0 The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow (Figure16-12), once a shutdown condition occurs, the the user to choose whether the PWM output signals are ECCPASE bit will remain set until it is cleared by firm- active-high or active-low for each pair of PWM output ware. Once ECCPASE is cleared, the enhanced PWM pins (P1A/P1C and P1B/P1D). The PWM output will resume at the beginning of the next PWM period. polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configura- Note: Writing to the ECCPASE bit is disabled tion while the PWM pins are configured as outputs is while a shutdown condition is active. not recommended since it may result in damage to the Independent of the PRSEN bit setting, if the auto- application circuits. shutdown source is one of the comparators, the shut- The P1A, P1B, P1C and P1D output latches may not be down condition is a level. The ECCPASE bit cannot be in the proper states when the PWM module is initialized. cleared as long as the cause of the shutdown persists. Enabling the PWM pins for output at the same time as The Auto-Shutdown mode can be forced by writing a ‘1’ the ECCP module may cause damage to the applica- to the ECCPASE bit. tion circuit. The ECCP module must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCPASE bit PWMActivity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 16-12: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCPASE bit PWMActivity Normal PWM ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS30491D-page 186  2003-2013 Microchip Technology Inc.

18F8680.book Page 187 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.9 SETUP FOR PWM OPERATION 7. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). The following steps should be taken when configuring the ECCP1 module for PWM operation: 8. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing 1. Configure the PWM pins, P1A and P1B (and the TMR2IF bit (PIR1<1>). P1C and P1D, if used), as inputs by setting the corresponding TRISB bits. • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). 2. Set the PWM period by loading the PR2 register. • Enable Timer2 by setting the TMR2ON bit 3. Configure the ECCP1 module for the desired (T2CON<2>). PWM mode and configuration by loading the CCP1CON register with the appropriate values: 9. Enable PWM outputs after a new PWM cycle has started: • Select one of the available output configurations and direction with the • Wait until TMR2 overflows (TMR2IF bit is set). P1M1:P1M0 bits. • Enable the CCP1/P1A, P1B, P1C and/or P1D • Select the polarities of the PWM output pin outputs by clearing the respective TRISB signals with the CCP1M3:CCP1M0 bits. bits. 4. Set the PWM duty cycle by loading the CCPR1L • Clear the ECCPASE bit (ECCP1AS<7>). register and CCP1CON<5:4> bits. 16.2.10 EFFECTS OF A RESET 5. For Half-Bridge Output mode, set the dead- band delay by loading ECCP1DEL<6:0> with Both Power-on and subsequent Resets will force all the appropriate value. ports to Input mode and the CCP registers to their Reset states. 6. If auto-shutdown operation is required, load the ECCPAS register: This forces the Enhanced CCP module to reset to a • Select the auto-shutdown sources using the state compatible with the standard CCP module. ECCPAS<2:0> bits. • Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. • Set the ECCPASE bit (ECCPAS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. TABLE 16-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TRISE PORTE Data Direction Register 1111 1111 1111 1111 TRISG — — — PORTG Data Direction Register ---1 1111 ---1 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000 ECCP1DEL PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.  2003-2013 Microchip Technology Inc. DS30491D-page 187

18F8680.book Page 188 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 188  2003-2013 Microchip Technology Inc.

18F8680.book Page 189 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.0 MASTER SYNCHRONOUS 17.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 17.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA The Master Synchronous Serial Port (MSSP) module is • Serial Clock (SCK) – RC3/SCK/SCL a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, dis- mode of operation: play drivers, A/D converters, etc. The MSSP module • Slave Select (SS) – RF7/SS can operate in one of two modes: Figure17-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C) - Full Master mode FIGURE 17-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPIMODE) The I2C interface supports the following modes in Internal hardware: Data Bus • Master mode Read Write • Multi-Master mode SSPBUF Reg • Slave mode 17.2 Control Registers RC4/SDI/SDA The MSSP module has three associated registers. SSPSR Reg These include a status register (SSPSTAT) and two RC5/SDO bit0 Shift Clock control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual RF7/SS SSControl sections. Enable Edge Select 2 Clock Select SSPM3:SSPM0 RC3/SCK/ SMP:CKE 4 (T M R 2 O u t p u t) SCL 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit  2003-2013 Microchip Technology Inc. DS30491D-page 189

18F8680.book Page 190 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not double- • MSSP Shift Register (SSPSR) – Not directly buffered. A write to SSPBUF will write to both SSPBUF accessible and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 regis- ter is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Edge Select bit When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write bit Information Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 190  2003-2013 Microchip Technology Inc.

18F8680.book Page 191 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 191

18F8680.book Page 192 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.2 OPERATION reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data When initializing the SPI, several options need to be will be ignored and the Write Collision detect bit, WCOL specified. This is done by programming the appropriate (SSPCON1<7>), will be set. User software must clear control bits (SSPCON1<5:0> and SSPSTAT<7:6>). the WCOL bit so that it can be determined if the follow- These control bits allow the following to be specified: ing write(s) to the SSPBUF register completed • Master mode (SCK is the clock output) successfully. • Slave mode (SCK is the clock input) When the application software is expecting to receive • Clock Polarity (Idle state of SCK) valid data, the SSPBUF should be read before the next • Data Input Sample Phase (middle or end of data byte of data to transfer is written to the SSPBUF. Buffer output time) Full bit, BF (SSPSTAT<0>), indicates when SSPBUF • Clock Edge (output data on rising/falling edge of has been loaded with the received data (transmission SCK) is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a • Clock Rate (Master mode only) transmitter. Generally, the MSSP interrupt is used to • Slave Select mode (Slave mode only) determine when the transmission/reception has com- The MSSP consists of a Transmit/Receive Shift regis- pleted. The SSPBUF must be read and/or written. If the ter (SSPSR) and a Buffer register (SSPBUF). The interrupt method is not going to be used, then software SSPSR shifts the data in and out of the device, MSb polling can be done to ensure that a write collision does first. The SSPBUF holds the data that was written to the not occur. Example17-1 shows the loading of the SSPSR, until the received data is ready. Once the 8 bits SSPBUF (SSPSR) for data transmission. of data have been received, that byte is moved to the The SSPSR is not directly readable or writable and can SSPBUF register. Then the Buffer Full detect bit, BF only be accessed by addressing the SSPBUF register. (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are Additionally, the MSSP Status register (SSPSTAT) set. This double-buffering of the received data indicates the various status conditions. (SSPBUF) allows the next byte to start reception before EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS30491D-page 192  2003-2013 Microchip Technology Inc.

18F8680.book Page 193 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN Figure17-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI is automatically controlled by the SPI module depends on the application software. This leads to • SDO must have TRISC<5> bit cleared three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit • Master sends data-Slave sends dummy data cleared • Master sends data-Slave sends data • SCK (Slave mode) must have TRISC<3> bit set • Master sends dummy data-Slave sends data • SS must have TRISF<7> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) Shift Register SDI SDO Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2  2003-2013 Microchip Technology Inc. DS30491D-page 193

18F8680.book Page 194 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.5 MASTER MODE Figure17-3, Figure17-5 and Figure17-6, where the MSB is transmitted first. In Master mode, the SPI clock The master can initiate the data transfer at any time rate (bit rate) is user programmable to be one of the because it controls the SCK. The master determines following: when the slave (Processor 2, Figure17-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPBUF register is written to. If the SPI is • FOSC/64 (or 16 • TCY) only going to receive, the SDO output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPSR register This allows a maximum data rate (at 40 MHz) of will continue to shift in the signal present on the SDI pin 10.00Mbps. at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as Figure17-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDO data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCK. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received The clock polarity is selected by appropriately program- data is shown. ming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication, as shown in FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock SCK Modes (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF DS30491D-page 194  2003-2013 Microchip Technology Inc.

18F8680.book Page 195 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.6 SLAVE MODE the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes In Slave mode, the data is transmitted and received as a floating output. External pull-up/pull-down resistors the external clock pulses appear on SCK. When the may be desirable depending on the application. last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by Note1: When the SPI is in Slave mode with SS pin the external clock source on the SCK pin. This external control enabled (SSPCON<3:0> = 0100), clock must meet the minimum high and low times as the SPI module will reset if the SS pin is set specified in the electrical specifications. to VDD. While in Sleep mode, the slave can transmit/receive 2: If the SPI is used in Slave mode with CKE data. When a byte is received, the device will wake-up set, then the SS pin control must be from Sleep. enabled. When the SPI module resets, the bit counter is forced 17.3.7 SLAVE SELECT to ‘0’. This can be done by either forcing the SS pin to SYNCHRONIZATION a high level or clearing the SSPEN bit. The SS pin allows a Synchronous Slave mode. The SPI To emulate two-wire communication, the SDO pin can must be in Slave mode with SS pin control enabled be connected to the SDI pin. When the SPI needs to (SSPCON1<3:0> = 04h). The pin must not be driven operate as a receiver, the SDO pin can be configured low for the SS pin to function as an input. The data latch as an input. This disables transmissions from the SDO. must be high. When the SS pin is low, transmission and The SDI can always be left as an input (SDI function) reception are enabled and the SDO pin is driven. When since it cannot create a bus conflict. FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF  2003-2013 Microchip Technology Inc. DS30491D-page 195

18F8680.book Page 196 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF DS30491D-page 196  2003-2013 Microchip Technology Inc.

18F8680.book Page 197 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.8 SLEEP OPERATION 17.3.10 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted and the Table17-1 shows the compatibility between the transmission/reception will remain in that state until the standard SPI modes and the states of the CKP and device wakes from Sleep. After the device returns to CKE control bits. normal mode, the module will continue to transmit/receive data. TABLE 17-1: SPI BUS MODES In Slave mode, the SPI Transmit/Receive Shift register Standard SPI Mode Control Bits State operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be Terminology CKP CKE shifted into the SPI Transmit/Receive Shift register. 0, 0 0 1 When all 8 bits have been received, the MSSP interrupt 0, 1 0 0 flag bit will be set and if enabled, will wake the device from Sleep. 1, 0 1 1 1, 1 1 0 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the There is also a SMP bit which controls when the data is current transfer. sampled. TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 uuuu uuuu SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.  2003-2013 Microchip Technology Inc. DS30491D-page 197

18F8680.book Page 198 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4 I2C Mode 17.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call sup- These are: port) and provides interrupts on Start and Stop bits in • MSSP Control Register 1 (SSPCON1) hardware to determine a free bus (multi-master func- • MSSP Control Register 2 (SSPCON2) tion). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer (SSPBUF) addressing. • MSSP Shift Register (SSPSR) – Not directly Two pins are used for data transfer: accessible • Serial clock (SCL) – RC3/SCK/SCL • MSSP Address Register (SSPADD) • Serial data (SDA) – RC4/SDI/SDA SSPCON, SSPCON2 and SSPSTAT are the control The user must configure these pins as inputs or outputs and status registers in I2C mode operation. The through the TRISC<4:3> bits. SSPCON and SSPCON2 registers are readable and writable. The lower six bits of the SSPSTAT are read- FIGURE 17-7: MSSP BLOCK DIAGRAM only. The upper two bits of the SSPSTAT are (I2C MODE) read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the RCS3C/SLCK/ SSPBUF Reg SSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload Shift value. Clock In receive operations, SSPSR and SSPBUF together SSPSR Reg create a double-buffered receiver. When SSPSR RC4/ MSb LSb SDI/ receives a complete byte, it is transferred to SSPBUF SDA and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT Reg) DS30491D-page 198  2003-2013 Microchip Technology Inc.

18F8680.book Page 199 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 199

18F8680.book Page 200 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 200  2003-2013 Microchip Technology Inc.

18F8680.book Page 201 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).  2003-2013 Microchip Technology Inc. DS30491D-page 201

18F8680.book Page 202 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.2 OPERATION 17.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C oper- the 8 bits are shifted into the SSPSR register. All incom- ing bits are sampled with the rising edge of the clock ation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: (SCL) line. The value of register SSPSR<7:1> is com- pared to the value of the SSPADD register. The • I2C Master mode, clock = OSC/4 (SSPADD + 1) address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The buffer full bit BF is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. MSSP interrupt flag bit, SSPIF (PIR1<3>), is set Idle (interrupt is generated, if enabled) on the falling Selection of any I2C mode with the SSPEN bit set, edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, pro- In 10-bit Address mode, two address bytes need to be vided these pins are programmed to inputs by setting received by the slave. The five Most Significant bits the appropriate TRISC bits. To ensure proper operation (MSbs) of the first address byte specify if this is a 10-bit of the module, pull-up resistors must be provided address. Bit R/W (SSPSTAT<2>) must specify a write externally to the SCL and SDA pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 17.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two In Slave mode, the SCL and SDA pins must be config- MSbs of the address. The sequence of events for ured as inputs (TRISC<4:3> set). The MSSP module 10-bit address is as follows, with steps 7 through 9 for will override the input state with the output data when the slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF, The I2C Slave mode hardware will always generate an BF and bit UA (SSPSTAT<1>) are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit UA and releases the Start and Stop bits SCL line). When an address is matched or the data transfer after 3. Read the SSPBUF register (clears bit BF) and an address match is received, the hardware automati- clear flag bit SSPIF. cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of address (bits load the SSPBUF register with the received value SSPIF, BF, and UA are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. If match releases SCL line, this the MSSP module not to give this ACK pulse: will clear bit UA. • The buffer full bit BF (SSPSTAT<0>) was set 6. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPIF. • The overflow bit SSPOV (SSPCON<6>) was set 7. Receive Repeated Start condition. before the transfer was received. 8. Receive first (high) byte of address (bits SSPIF and BF are set). In this case, the SSPSR register value is not loaded into the SSPBUF but bit SSPIF (PIR1<3>) is set. The 9. Read the SSPBUF register (clears bit BF) and BF bit is cleared by reading the SSPBUF register while clear flag bit SSPIF. bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101. DS30491D-page 202  2003-2013 Microchip Technology Inc.

18F8680.book Page 203 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.3.2 Reception 17.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held low, regardless of SEN (see Section17.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more detail). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit BF (SSPSTAT<0>) is until the slave is done preparing the transmit data. The set or bit SSPOV (SSPCON1<6>) is set. transmit data must be loaded into the SSPBUF register An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then pin RC3/ byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- SCK/SCL should be enabled by setting bit CKP ware. The SSPSTAT register is used to determine the (SSPCON1<4>). The eight data bits are shifted out on status of the byte. the falling edge of the SCL input. This ensures that the If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL SDA signal is valid during the SCL high time will be held low (clock stretch) following each data (Figure17-9). transfer. The clock must be released by setting bit The ACK pulse from the master-receiver is latched on CKP(SSPCON<4>). See Section17.4.4 “Clock the rising edge of the ninth SCL input pulse. If the SDA Stretching” for more detail. line is high (not ACK), then the data transfer is com- plete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT regis- ter) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.  2003-2013 Microchip Technology Inc. DS30491D-page 203

18F8680.book Page 204 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-8: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 D1 7 D2 6 Data D3 5 Receiving D5D4 34 D6 2 D7 1 K C A 9 D0 8 D1 7 D2 6 Receiving Data D6D5D4D3 2345 Cleared in softwareSSPBUF is read D7 1 K 9 0W = AC 8 R/ A1 7 Receiving Address SDAA7A6A5A4A3A2 SCL123456S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) CKP00(CKP does not reset to ‘’ when SEN = ) DS30491D-page 204  2003-2013 Microchip Technology Inc.

18F8680.book Page 205 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-9: I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R ACK 9 PIF IS S D0 8 m S Data D1 7 Fro Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software CKP is set in software D7 1 R ACK 9 PIF IS S D0 8 m S D1 7 Fro Transmitting Data D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software CKP is set in software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 1W = 8 R/ A1 7 Address A3A2 56 Receiving A4A5 34 SDAA6A7 SCL12SData in sampled SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP  2003-2013 Microchip Technology Inc. DS30491D-page 205

18F8680.book Page 206 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-10: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 D1 7 Receive Data Byte D5D4D3D2 3456 Cleared in software D6 2 D7 1 K AC 9 D0 8 Clock is held low untilClock is held low untilupdate of SSPADD has update of SSPADD has taken placetaken place Receive First Byte of AddressReceive Second Byte of AddressReceive Data Byte0R/W = ACKACKSDA11110A9A8A7A6A5A4A3A2A1A0D7D6D5D4D3D1D2 SCL1234567891234567891234576S SSPIF (PIR1<3>) Cleared in softwareCleared in softwareCleared in software BF (SSPSTAT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag SSPOV (SSPCON<6>) UA (SSPSTAT<1>) UA is set indicating thatCleared by hardware whenCleared by hardwarethe SSPADD needs to beSSPADD is updated with highwhen SSPADD is updatedupdatedbyte of addresswith low byte of address UA is set indicating thatSSPADD needs to beupdated CKP00(CKP does not reset to ‘’ when SEN = ) DS30491D-page 206  2003-2013 Microchip Technology Inc.

18F8680.book Page 207 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-11: I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatesClock is held low untiltransferupdate of SSPADD has Clock is held low untiltaken place1CKP is set to ‘’ ACKReceive First Byte of AddressTransmitting Data Byte1R/W = ACK11110A8A9D7D6D5D4D3D1D2D0ACK 9123457896123457896PSr Cleared in softwareCleared in software Dummy read of SSPBUFCompletion ofWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitdata transmissionat the end of theclears BF flagthird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hardware, holding SCL low Clock is held low untilupdate of SSPADD has taken place 0W = Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/Receive First Byte of Address SDA11110A9A8 SCL12345678S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPBUF is written withcontents of SSPSR UA (SSPSTAT<1>) UA is set indicating thatthe SSPADD needs to beupdated CKP (SSPCON<4>)  2003-2013 Microchip Technology Inc. DS30491D-page 207

18F8680.book Page 208 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.4 CLOCK STRETCHING 17.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the ninth be enabled during receives. Setting SEN will cause the clock, if the BF bit is clear. This occurs regardless of the SCL pin to be held low at the end of each data receive state of the SEN bit. sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line low, 17.4.4.1 Clock Stretching for 7-bit Slave the user has time to service the ISR and load the con- Receive Mode (SEN = 1) tents of the SSPBUF before the master device can In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure17-9). ninth clock at the end of the ACK sequence if the BF bit Note1: If the user loads the contents of SSPBUF, is set, the CKP bit in the SSPCON1 register is automat- setting the BF bit before the falling edge of ically cleared, forcing the SCL output to be held low. the ninth clock, the CKP bit will not be The CKP being cleared to ‘0’ will assert the SCL line cleared and clock stretching will not occur. low. The CKP bit must be set in the user’s ISR before 2: The CKP bit can be set in software reception is allowed to continue. By holding the SCL regardless of the state of the BF bit. line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device 17.4.4.4 Clock Stretching for 10-bit Slave can initiate another receive sequence. This will prevent Transmit Mode buffer overruns from occurring (see Figure17-13). In 10-bit Slave Transmit mode, clock stretching is Note1: If the user reads the contents of the controlled during the first two address sequences by SSPBUF before the falling edge of the the state of the UA bit, just as it is in 10-bit Slave ninth clock, thus clearing the BF bit, the Receive mode. The first two addresses are followed by CKP bit will not be cleared and clock a third address sequence which contains the high order stretching will not occur. bits of the 10-bit address and the R/W bit set to ‘1’. After 2: The CKP bit can be set in software the third address sequence is performed, the UA bit is regardless of the state of the BF bit. The not set, the module is now configured in Transmit user should be careful to clear the BF bit mode, and clock stretching is controlled by the BF flag in the ISR before the next receive as in 7-bit Slave Transmit mode (see Figure17-11). sequence in order to prevent an overflow condition. 17.4.4.2 Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS30491D-page 208  2003-2013 Microchip Technology Inc.

18F8680.book Page 209 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.4.5 Clock Synchronization and until an external I2C master device has already the CKP bit asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C When the CKP bit is cleared, the SCL output is forced bus have deasserted SCL. This ensures that a write to to ‘0’. However, setting the CKP bit will not assert the the CKP bit will not violate the minimum high time SCL output low until the SCL output is already sampled requirement for SCL (see Figure17-12). low. Therefore, the CKP bit will not assert the SCL line FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3Q4 SDA DX DX-1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON  2003-2013 Microchip Technology Inc. DS30491D-page 209

18F8680.book Page 210 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-13: I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lo1because ACK = ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 D1 7 D2 6 Data D3 5 Receiving D5D4 34 Clock is held low until1CKP is set to ‘’ ACK D0D7D6 8912 CKPwritten1to ‘’ insoftwareBF is set after falling edge of the 9th clock,CKP is reset to ‘0’ andclock stretching occurs D1 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in softwareSPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be reset0to ‘’ and no clockstretching will occur S K 9 0R/W = AC 8 A1 7 A2 6 Address A3 5 Receiving A5A4 34 A6 2 SDAA7 SCL1S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) CKP DS30491D-page 210  2003-2013 Microchip Technology Inc.

18F8680.book Page 211 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) Clock is not held low1because ACK = ACK D0 89P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D1 7 Clock is held low untilupdate of SSPADD has Clock is held low untiltaken place1CKP is set to ‘’ Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock. 1CKP written to ‘’in software Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of Address0W = A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ SDA11110A9A8 SCL12345678S SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) SSPBUF is written withcontents of SSPSR SSPOV (SSPCON<6>) UA (SSPSTAT<1>) UA is set indicating thatthe SSPADD needs to beupdated CKP  2003-2013 Microchip Technology Inc. DS30491D-page 211

18F8680.book Page 212 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the inter- the master. The exception is the general call address rupt can be checked by reading the contents of the which can address all devices. When this address is SSPBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set while the slave is configured in 10-bit Address mode, then the second The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not eral Call Enable bit (GCEN) is enabled (SSPCON2<7> be set and the slave will begin receiving data after the is set). Following a Start bit detect, 8 bits are shifted into Acknowledge (Figure17-15). the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS30491D-page 212  2003-2013 Microchip Technology Inc.

18F8680.book Page 213 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start condi- Master mode of operation is supported by interrupt tion is complete. In this case, the SSPBUF generation on the detection of the Start and Stop will not be written to and the WCOL bit will conditions. The Stop (P) and Start (S) bits are cleared be set, indicating that a write to the from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is SSPBUF did not occur. set or the bus is Idle, with both the S and P bits clear. The following events will cause SSP interrupt flag bit, In Firmware Controlled Master mode, user code SSPIF, to be set (SSP interrupt if enabled): conducts all I2C bus operations based on Start and • Start Condition Stop bit conditions. • Stop Condition Once Master mode is enabled, the user has six • Data Transfer Byte Transmitted/Received options. • Acknowledge Transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e e MSb SSPSR LSb OL Detource) SCL Receive Enabl StAarcGtk beninot,ew Srlaetotdepg ebit, Clock Cntl ck Arbitrate/WC(hold off clock s o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV  2003-2013 Microchip Technology Inc. DS30491D-page 213

18F8680.book Page 214 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted con- 7. The user loads the SSPBUF with eight bits of tains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate a receive bit. Serial 9. The MSSP module shifts in the ACK bit from the data is received via SDA while SCL outputs the serial slave device and writes its value into the clock. Serial data is received 8 bits at a time. After each SSPCON2 register (SSPCON2<6>). byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and 10. The MSSP module generates an interrupt at the end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See the Stop enable bit PEN (SSPCON2<2>). Section17.4.7 “Baud Rate Generator” for more 12. Interrupt is generated once the Stop condition is detail. complete. DS30491D-page 214  2003-2013 Microchip Technology Inc.

18F8680.book Page 215 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table17-3 demonstrates clock rates based on begin counting. The BRG counts down to ‘0’ and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 17-3: I2C CLOCK RATE w/BRG FSCL FCY FCY*2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz(1) 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 64h 100 kHz 4 MHz 8 MHz 0Ah 400 kHz(1) 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz(1) 1 MHz 2 MHz 0Ah 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details but may be used with care where higher rates are required by the application.  2003-2013 Microchip Technology Inc. DS30491D-page 215

18F8680.book Page 216 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure17-18). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS30491D-page 216  2003-2013 Microchip Technology Inc.

18F8680.book Page 217 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.8 I2C MASTER MODE START 17.4.8.1 WCOL Status Flag CONDITION TIMING If the user writes the SSPBUF when a Start sequence To initiate a Start condition, the user sets the Start Con- is in progress, the WCOL is set and the contents of the dition Enable bit, SEN (SSPCON2<0>). If the SDA and buffer are unchanged (the write doesn’t occur). SCL pins are sampled high, the Baud Rate Generator Note: Because queueing of events is not is reloaded with the contents of SSPADD<6:0> and allowed, writing to the lower 5 bits of starts its count. If SCL and SDA are both sampled high SSPCON2 is disabled until the Start when the Baud Rate Generator times out (TBRG), the condition is complete. SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note: If at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. FIGURE 17-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S  2003-2013 Microchip Technology Inc. DS30491D-page 217

18F8680.book Page 218 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.9 I2C MASTER MODE REPEATED Immediately following the SSPIF bit getting set, the START CONDITION TIMING user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. A Repeated Start condition occurs when the RSEN bit After the first eight bits are transmitted and an ACK is (SSPCON2<1>) is programmed high and the I2C logic received, the user may then transmit an additional eight module is in the Idle state. When the RSEN bit is set, bits of address (10-bit mode) or eight bits of data (7-bit the SCL pin is asserted low. When the SCL pin is mode). sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. 17.4.9.1 WCOL Status Flag The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate If the user writes the SSPBUF when a Repeated Start Generator times out, if SDA is sampled high, the SCL sequence is in progress, the WCOL is set and the con- pin will be deasserted (brought high). When SCL is tents of the buffer are unchanged (the write doesn’t sampled high, the Baud Rate Generator is reloaded occur). with the contents of SSPADD<6:0> and begins count- Note: Because queueing of events is not ing. SDA and SCL must be sampled high for one TBRG. allowed, writing of the lower 5 bits of This action is then followed by assertion of the SDA pin SSPCON2 is disabled until the Repeated (SDA = 0) for one TBRG while SCL is high. Following Start condition is complete. this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 17-20: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG 1st bit SDA Falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start DS30491D-page 218  2003-2013 Microchip Technology Inc.

18F8680.book Page 219 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.10 I2C MASTER MODE 17.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address, or the cleared when the slave has sent an Acknowledge other half of a 10-bit address is accomplished by simply (ACK = 0) and is set when the slave does not Acknowl- writing a value to the SSPBUF register. This action will edge (ACK = 1). A slave sends an Acknowledge when set the Buffer Full flag bit, BF and allow the Baud Rate it has recognized its address (including a general call) Generator to begin counting and start the next trans- or when the slave has properly received its data. mission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is 17.4.11 I2C MASTER MODE RECEPTION asserted (see data hold time specification parameter Master mode reception is enabled by programming the #106). SCL is held low for one Baud Rate Generator receive enable bit, RCEN (SSPCON2<3>). rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification Note: The MSSP module must be in an Idle state parameter #107). When the SCL pin is released high, it before the RCEN bit is set or the RCEN bit is held that way for TBRG. The data on the SDA pin will be disregarded. must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each time after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high-to-low/ bit is shifted out (the falling edge of the eighth clock), low-to-high) and data is shifted into the SSPSR. After the the BF flag is cleared and the master releases SDA. falling edge of the eighth clock, the receive enable flag is This allows the slave device being addressed to automatically cleared, the contents of the SSPSR are respond with an ACK bit during the ninth bit time if an loaded into the SSPBUF, the BF flag bit is set, the SSPIF address match occurred, or if data was received flag bit is set and the Baud Rate Generator is suspended properly. The status of ACK is written into the ACKDT from counting, holding SCL low. The MSSP is now in Idle bit on the falling edge of the ninth clock. If the master state awaiting the next command. When the buffer is receives an Acknowledge, the Acknowledge Status bit, read by the CPU, the BF flag bit is automatically cleared. ACKSTAT, is cleared. If not, the bit is set. After the ninth The user can then send an Acknowledge bit at the end clock, the SSPIF bit is set and the master clock (Baud of reception by setting the Acknowledge sequence Rate Generator) is suspended until the next data byte enable bit, ACKEN (SSPCON2<4>). is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure17-21). 17.4.11.1 BF Status Flag After the write to the SSPBUF, each bit of the address In receive operation, the BF bit is set when an address will be shifted out on the falling edge of SCL until all or data byte is loaded into SSPBUF from SSPSR. It is seven address bits and the R/W bit are completed. On cleared when the SSPBUF register is read. the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond 17.4.11.2 SSPOV Status Flag with an Acknowledge. On the falling edge of the ninth In receive operation, the SSPOV bit is set when 8 bits clock, the master will sample the SDA pin to see if the are received into the SSPSR and the BF flag bit is address was recognized by a slave. The status of the already set from a previous reception. ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth 17.4.11.3 WCOL Status Flag clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is If the user writes the SSPBUF when a receive is turned off until another write to the SSPBUF takes already in progress (i.e., SSPSR is still shifting in a data place, holding SCL low and allowing SDA to float. byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). 17.4.10.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software.  2003-2013 Microchip Technology Inc. DS30491D-page 219

18F8680.book Page 220 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in 1SSPCON2 = P ared in software CK 9 Cle A From slave clear ACKSTAT bit SSPCON2<6> Transmitting Data or Second Halfof 10-bit Address D7D6D5D4D3D2D1D0 12345678w SPIF Cleared in software service routinefrom SSP interrupt SSPBUF is written in software 0W = 0 = ACK W 9SCL held lowhile CPUresponds to S ware 1SPCON2<0> SEN = , ndition begins 0SEN = R/Transmit Address to Slave A7A6A5A4A3A2A1 SSPBUF written with 7-bit address and R/start transmit 12345678 Cleared in software SSPBUF written After Start condition, SEN cleared by hard Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS30491D-page 220  2003-2013 Microchip Technology Inc.

18F8680.book Page 221 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequence,0SDA = ACKDT (SSPCON2<5>) = Set ACKEN, start Acknowledge sequence,ACK from MasterMaster configured as a receiver01SDA = ACKDT = SDA = ACKDT = 1by programming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = ,RCEN clearedRCEN clearedwritten hereACK from Slavestart next receiveautomaticallyautomatically Receiving Data from Slave1Receiving Data from SlaveR/W = ACKD0D2D5A1D2D5D3D4D6D7D3D4D6D7D1D1ACKD0ACK Bus masterACK is not sentterminatestransfer799678985876123453124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full 1Write to SSPCON2<0>(SEN = ),begin Start Condition 0SEN = Write to SSPBUF occurs here,start XMIT Transmit Address to SlaveA7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared in software01SDA = , SCL = while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN  2003-2013 Microchip Technology Inc. DS30491D-page 221

18F8680.book Page 222 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.12 ACKNOWLEDGE SEQUENCE 17.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting receive/transmit by setting the Stop Sequence Enable theAcknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is erate an Acknowledge, then the ACKDT bit should be sampled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to ‘0’. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam- SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF pulled low. Following this, the ACKEN bit is automatically bit is set (Figure17-24). cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure17-23). 17.4.13.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence 17.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the con- If the user writes the SSPBUF when an Acknowledge tents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Set SSPIF at the end Cleared in of receive Cleared in software software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS30491D-page 222  2003-2013 Microchip Technology Inc.

18F8680.book Page 223 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.14 SLEEP OPERATION 17.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND addresses or data and when an address match or com- BUS ARBITRATION plete byte transfer occurs, wake the processor from Multi-Master mode support is achieved by bus arbitra- Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 17.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 17.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure17-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be moni- If a Start, Repeated Start, Stop, or Acknowledge condi- tored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, expected output level. This check is performed in the condition is aborted, the SDA and SCL lines are hardware with the result placed in the BCLIF bit. deasserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Dwhaitlae cShCaLn g=e 0s SbyD Aan lionteh epru slloeudr cloew Sdbyaa tmtah pedl oeme SasDnst’Ate r.m. Wathcihle w ShCaLt iiss dhriigvhe,n Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2003-2013 Microchip Technology Inc. DS30491D-page 223

18F8680.book Page 224 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure17-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure17-26). counts down to ‘0’ and during this time, if the SCL pins b) SCL is sampled low before SDA is asserted low are sampled as ‘0’, a bus collision does not occur. At (Figure17-27). the end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus If the SDA pin is already low or the SCL pin is already masters can assert a Start condition at the low, then all of the following occur: exact same time. Therefore, one master will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus • the BCLIF flag is set, and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address follow- (Figure17-26). ing the Start condition. If the address is the same, arbitration must be allowed to The Start condition begins with the SDA and SCL pins continue into the data portion, Repeated deasserted. When the SDA pin is sampled high, the Start or Stop conditions. Baud Rate Generator is loaded from SSPADD<6:0> and counts down to ‘0’. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF; S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF; S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS30491D-page 224  2003-2013 Microchip Technology Inc.

18F8680.book Page 225 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG Time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software  2003-2013 Microchip Technology Inc. DS30491D-page 225

18F8680.book Page 226 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.17.2 Bus Collision During a Repeated reloaded and begins counting. If SDA goes from high to Start Condition low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the During a Repeated Start condition, a bus collision same time. occurs if: If SCL goes from high to low before the BRG times out a) A low level is sampled on SDA when SCL goes and SDA has not already been asserted, a bus collision from low level to high level. occurs. In this case, another master is attempting to b) SCL goes low before SDA is asserted low, transmit a data ‘1’ during the Repeated Start condition indicating that another master is attempting to (see Figure17-30). transmit a data ‘1’. If, at the end of the BRG time-out, both SCL and SDA When the user deasserts SDA and the pin is allowed to are still high, the SDA pin is driven low and the BRG is float high, the BRG is loaded with SSPADD<6:0> and reloaded and begins counting. At the end of the count, counts down to ‘0’. The SCL pin is then deasserted and regardless of the status of the SCL pin, the SCL pin is when sampled high, the SDA pin is sampled. driven low and the Repeated Start condition is If SDA is low, a bus collision has occurred (i.e., another complete. master is attempting to transmit a data ‘0’, see Figure17-29). If SDA is sampled high, the BRG is FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS30491D-page 226  2003-2013 Microchip Technology Inc.

18F8680.book Page 227 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to ‘0’. After the BRG times out, SDA allowed to float high, SDA is sampled low after is sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure17-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure17-32). FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’  2003-2013 Microchip Technology Inc. DS30491D-page 227

18F8680.book Page 228 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 228  2003-2013 Microchip Technology Inc.

18F8680.book Page 229 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.0 ENHANCED UNIVERSAL In order to configure pins RC6/TX/CK and RC7/RX/DT SYNCHRONOUS as the Universal Synchronous Asynchronous Receiver Transmitter: ASYNCHRONOUS RECEIVER • SPEN (RCSTA<7>) bit must be set (= 1), TRANSMITTER (USART) • TRISC<6> bit must be set (= 1), and The Universal Synchronous Asynchronous Receiver • TRISC<7> bit must be set (= 1). Transmitter (USART) module is one of the two serial Note: The USART control will automatically I/O modules. (USART is also known as a Serial reconfigure the pin from input to output as Communications Interface or SCI.) The USART can be needed. configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as The operation of the Enhanced USART module is CRT terminals and personal computers. It can also be controlled through three registers: configured as a half-duplex synchronous system that • Transmit Status and Control (TXSTA) can communicate with peripheral devices, such as A/D • Receive Status and Control (RCSTA) or D/A integrated circuits, serial EEPROMs, etc. • Baud Rate Control (BAUDCON) The Enhanced USART module implements additional These are detailed on the following pages in features, including automatic baud rate detection and Register18-1, Register18-2 and Register18-3, calibration, automatic wake-up on sync break reception respectively. and 12-bit break character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The USART can be configured in the following modes: • Asynchronous (full-duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity  2003-2013 Microchip Technology Inc. DS30491D-page 229

18F8680.book Page 230 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send sync break on next transmission (cleared by hardware upon completion) 0 = Sync break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 230  2003-2013 Microchip Technology Inc.

18F8680.book Page 231 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be an address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 231

18F8680.book Page 232 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = USART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character – requires reception of a sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 232  2003-2013 Microchip Technology Inc.

18F8680.book Page 233 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.1 USART Baud Rate Generator (BRG) the error in baud rate can be determined. An example calculation is shown in Example18-1. Typical baud The BRG is a dedicated 8-bit or 16-bit generator that rates and error values for the various Asynchronous supports both the Asynchronous and Synchronous modes are shown in Table18-2. It may be advantageous modes of the USART. By default, the BRG operates in to use the high baud rate (BRGH = 1) or the 16-bit BRG 8-bit mode; setting the BRG16 bit (BAUDCON<3>) to reduce the baud rate error, or achieve a slow baud selects 16-bit mode. rate for a fast oscillator frequency. The SPBRGH:SPBRG register pair controls the period Writing a new value to the SPBRGH:SPBRG registers of a free-running timer. In Asynchronous mode, bits causes the BRG timer to be reset (or cleared). This BRGH (TXSTA<2>) and BRG16 also control the baud ensures the BRG does not wait for a timer overflow rate. In Synchronous mode, bit BRGH is ignored. before outputting the new baud rate. Table18-1 shows the formula for computation of the baud rate for different USART modes which only apply 18.1.1 SAMPLING in Master mode (internally generated clock). The data on the RC7/RX/DT pin is sampled three times Given the desired baud rate and FOSC, the nearest by a majority detect circuit to determine if a high or a integer value for the SPBRGH:SPBRG registers can be low level is present at the RX pin. calculated using the formulas in Table18-1. From this, TABLE 18-1: BAUD RATE FORMULAS Configuration Bits BRG/USART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = Value of SPBRGH:SPBRG register pair EXAMPLE 18-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate= 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on all Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2003-2013 Microchip Technology Inc. DS30491D-page 233

18F8680.book Page 234 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — DS30491D-page 234  2003-2013 Microchip Technology Inc.

18F8680.book Page 235 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — —  2003-2013 Microchip Technology Inc. DS30491D-page 235

18F8680.book Page 236 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.1.2 AUTO-BAUD RATE DETECT carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table18-4 for counter The enhanced USART module supports the automatic clock rates to the BRG. detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE While the ABD sequence takes place, the USART state bit is clear. machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the The automatic baud rate measurement sequence RCREG needs to be read to clear the RCIF interrupt. (Figure18-1) begins whenever a Start bit is received RCREG content should be discarded. and the ABDEN bit is set. The calculation is self-averaging. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Rate Detect (ABD) mode, the clock to auto-baud rate detection will occur on the the BRG is reversed. Rather than the BRG clocking the byte following the break character. incoming RX signal, the RX signal is timing the BRG. In 2: It is up to the user to determine that the ABD mode, the internal Baud Rate Generator is used incoming character baud rate is within the as a counter to time the bit period of the incoming serial range of the selected BRG clock source. byte stream. Some combinations of oscillator fre- Once the ABDEN bit is set, the state machine will clear quency and USART baud rates are not the BRG and look for a Start bit. The auto-baud detect possible due to bit error rates. Overall must receive a byte with the value 55h (ASCII “U”, system timing and communication baud which is also the LIN bus sync character) in order to rates must be taken into consideration calculate the proper bit rate. The measurement is taken when using the auto-baud rate detection over both a low and a high bit time in order to minimize feature. any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up TABLE 18-4: BRG COUNTER CLOCK using the preselected clock source on the first rising RATES edge of RX. After eight bits on the RX pin or the fifth BRG16 BRGH BRG Counter Clock rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG registers. 0 0 FOSC/512 Once the 5th edge is seen (should correspond to the 0 1 FOSC/128 Stop bit), the ABDEN bit is automatically cleared. 1 0 FOSC/128 While calibrating the baud rate period, the BRG regis- 1 1 FOSC/32 ters are clocked at 1/8th the preconfigured clock rate. Note: During the ABD sequence, SPBRG and Note that the BRG clock will be configured by the SPBRGH are both used as a 16-bit BRG16 and BRGH bits. Independent of the BRG16 bit counter independent of BRG16 setting. setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note1: The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE=0. DS30491D-page 236  2003-2013 Microchip Technology Inc.

18F8680.book Page 237 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2 USART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is The Asynchronous mode of operation is selected by empty and flag bit TXIF (PIR1<4>) is set. This interrupt clearing the SYNC bit (TXSTA<4>). In this mode, the can be enabled/disabled by setting/clearing enable bit USART uses standard Non-Return-to-Zero (NRZ) for- TXIE (PIE1<4>). Flag bit TXIF will be set regardless of mat (one Start bit, eight or nine data bits and one Stop the state of enable bit TXIE and cannot be cleared in bit). The most common data format is 8 bits. An on-chip software. Flag bit TXIF is not cleared immediately upon dedicated 8-bit/16-bit Baud Rate Generator can be loading the Transmit Buffer register, TXREG. TXIF used to derive standard baud rate frequencies from the becomes valid in the second instruction cycle following oscillator. the load instruction. Polling TXIF immediately following The USART transmits and receives the LSb first. The a load of TXREG will return invalid results. USART’s transmitter and receiver are functionally inde- While flag bit TXIF indicates the status of the TXREG pendent but use the same data format and baud rate. register, another bit, TRMT (TXSTA<1>), shows the The Baud Rate Generator produces a clock, either x16 status of the TSR register. Status bit TRMT is a read- or x64 of the bit shift rate depending on the BRGH and only bit which is set when the TSR register is empty. No BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is interrupt logic is tied to this bit, so the user has to poll not supported by the hardware but can be implemented this bit in order to determine if the TSR register is in software and stored as the 9th data bit. empty. Asynchronous mode is available in all low-power Note1: The TSR register is not mapped in data modes; it is available in Sleep mode only when auto- memory so it is not available to the user. wake-up on sync break is enabled. When in PRI_IDLE mode, no changes to the Baud Rate Generator values 2: Flag bit TXIF is set when enable bit TXEN are required; however, other low-power mode clocks is set. may operate at another frequency than the primary To set up an Asynchronous Transmission: clock. Therefore, the Baud Rate Generator values may need to be adjusted. 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH When operating in Asynchronous mode, the USART and BRG16 bits, as required, to achieve the module consists of the following important elements: desired baud rate. • Baud Rate Generator Note: When BRGH and BRG16 bits are set, • Sampling Circuit SPBRGH:SPBRG must be more than ‘1’. • Asynchronous Transmitter 2. Enable the asynchronous serial port by clearing • Asynchronous Receiver bit SYNC and setting bit SPEN. • Auto-Wake-up on Sync Break Character 3. If interrupts are desired, set enable bit TXIE. • 12-bit Break Character Transmit 4. If 9-bit transmission is desired, set transmit bit • Auto-Baud Rate Detection TX9. Can be used as address/data bit. 5. Enable the transmission by setting bit TXEN 18.2.1 USART ASYNCHRONOUS which will also set bit TXIF. TRANSMITTER 6. If 9-bit transmission is selected, the ninth bit The USART transmitter block diagram is shown in should be loaded in bit TX9D. Figure18-2. The heart of the transmitter is the Transmit 7. Load data to the TXREG register (starts (Serial) Shift register (TSR). The Shift register obtains transmission). its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The If using interrupts, ensure that the GIE and PEIE bits in TSR register is not loaded until the Stop bit has been the INTCON register (INTCON<7:6>) are set. transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available).  2003-2013 Microchip Technology Inc. DS30491D-page 237

18F8680.book Page 238 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 18-2: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb RC6/TX/CK pin (8)  0 aPnidn CBounffterrol TSR Register Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH SPBRG TX9 Baud Rate Generator TX9D FIGURE 18-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX/CK (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) TRMT bit WTraonrds m1it Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Reg(T. rEamnsTpmRtyiMt FSTlah bgifi)tt TWraonrds m1it Shift Reg. WTraonrds m2it Shift Reg. Note: This timing diagram shows two consecutive transmissions. DS30491D-page 238  2003-2013 Microchip Technology Inc.

18F8680.book Page 239 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.  2003-2013 Microchip Technology Inc. DS30491D-page 239

18F8680.book Page 240 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2.2 USART ASYNCHRONOUS 18.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure18-5. This mode would typically be used in RS-485 systems. The data is received on the RC7/RX/DT pin and drives To set up an asynchronous reception with address the data recovery block. The data recovery block is detect enable: actually a high-speed shifter operating at x16 times the 1. Initialize the SPBRGH:SPBRG registers for the baud rate, whereas the main receive serial shifter oper- appropriate baud rate. Set or clear the BRGH ates at the bit rate or at FOSC. This mode would and BRG16 bits, as required, to achieve the typically be used in RS-232 systems. desired baud rate.. To set up an asynchronous reception: Note: When BRGH and BRG16 bits are set, 1. Initialize the SPBRGH:SPBRG registers for the SPBRGH:SPBRG must be more than ‘1’. appropriate baud rate. Set or clear the BRGH 2. Enable the asynchronous serial port by clearing and BRG16 bits, as required, to achieve the the SYNC bit and setting the SPEN bit. desired baud rate. 3. If interrupts are required, set the RCEN bit and 2. Enable the asynchronous serial port by clearing select the desired priority level with the RCIP bit. bit SYNC and setting bit SPEN. 4. Set the RX9 bit to enable 9-bit reception. 3. If interrupts are desired, set enable bit RCIE. 5. Set the ADDEN bit to enable address detect. 4. If 9-bit reception is desired, set bit RX9. 6. Enable reception by setting the CREN bit. 5. Enable the reception by setting bit CREN. 7. The RCIF bit will be set when reception is com- 6. Flag bit RCIF will be set when reception is com- plete. The interrupt will be Acknowledged if the plete and an interrupt will be generated if enable RCIE and GIE bits are set. bit RCIE was set. 8. Read the RCSTA register to determine if any 7. Read the RCSTA register to get the 9th bit (if error occurred during reception, as well as read enabled) and determine if any error occurred bit 9 of data (if applicable). during reception. 9. Read RCREG to determine if the device is being 8. Read the 8-bit received data by reading the addressed. RCREG register. 10. If any error occurred, clear the CREN bit. 9. If any error occurred, clear the error by clearing 11. If the device has been addressed, clear the enable bit CREN. ADDEN bit to allow all received data into the 10. If using interrupts, ensure that the GIE and PEIE receive buffer and interrupt the CPU. bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-5: USART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG  o6r4 MSb RSR Register LSb  o1r6 Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 RC7/RX/DT Pin Buffer Data and Control Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE DS30491D-page 240  2003-2013 Microchip Technology Inc.

18F8680.book Page 241 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 To set up an asynchronous transmission: 5. Enable the transmission by setting bit TXEN which will also set bit TXIF. 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, 6. If 9-bit transmission is selected, the ninth bit set bit BRGH (see Section18.1 “USART Baud should be loaded in bit TX9D. Rate Generator (BRG)”). 7. Load data to the TXREG register (starts 2. Enable the asynchronous serial port by clearing transmission). bit SYNC and setting bit SPEN. If using interrupts, ensure that the GIE and PEIE bits in 3. If interrupts are desired, set enable bit TXIE. the INTCON register (INTCON<7:6>) are set. 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. FIGURE 18-6: ASYNCHRONOUS RECEPTION Start Start Start RX (pin) bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.  2003-2013 Microchip Technology Inc. DS30491D-page 241

18F8680.book Page 242 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2.4 AUTO-WAKE-UP ON SYNC BREAK and cause data or framing errors. To work properly, CHARACTER therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 During Sleep mode, all clocks to the USART are devices or 000h (12 bits) for LIN bus. suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be per- Oscillator start-up time must also be considered, formed. The auto-wake-up feature allows the controller especially in applications using oscillators with longer to wake-up due to activity on the RX/DT line while the start-up intervals (i.e., XT or HS mode). The sync break USART is operating in Asynchronous mode. (or wake-up signal) character must be of sufficient length and be followed by a sufficient interval to allow The auto-wake-up feature is enabled by setting the enough time for the selected oscillator to start and WUE bit (BAUDCON<1>). Once set, the typical receive provide proper initialization of the USART. sequence on RX/DT is disabled and the USART remains in an Idle state monitoring for a wake-up event 18.2.4.2 Special Considerations Using independent of the CPU mode. A wake-up event con- the WUE Bit sists of a high-to-low transition on the RX/DT line. (This coincides with the start of a sync break or a wake-up The timing of WUE and RCIF events may cause some signal character for the LIN protocol.) confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the Following a wake-up event, the module generates an USART in an Idle mode. The wake-up event causes a RCIF interrupt. The interrupt is generated synchro- receive interrupt by setting the RCIF bit. The WUE bit nously to the Q clocks in normal operating modes is cleared after this when a rising edge is seen on (Figure18-7) and asynchronously, if the device is in RX/DT. The interrupt condition is then cleared by read- Sleep mode (Figure18-8). The interrupt condition is ing the RCREG register. Ordinarily, the data in RCREG cleared by reading the RCREG register. will be dummy data and should be discarded. The WUE bit is automatically cleared once a low-to- The fact that the WUE bit has been cleared (or is still high transition is observed on the RX line following the set) and the RCIF flag is set should not be used as an wake-up event. At this point, the USART module is in indicator of the integrity of the data in RCREG. Users Idle mode and returns to normal operation. This signals should consider implementing a parallel method in to the user that the sync break event is over. firmware to verify received data integrity. 18.2.4.1 Special Considerations Using To assure that no actual data is lost, check the RCIDL Auto-Wake-up bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may Since auto-wake-up functions by sensing rising edge then be set just prior to entering the Sleep mode. transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-of-character FIGURE 18-7: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto-Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note: The USART remains in Idle while the WUE bit is set. FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto-Cleared WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Sleep Ends Cleared due to User Read of RCREG Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The USART remains in Idle while the WUE bit is set. DS30491D-page 242  2003-2013 Microchip Technology Inc.

18F8680.book Page 243 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2.5 BREAK CHARACTER SEQUENCE 18.2.5.1 Break and Sync Transmit Sequence The enhanced USART module has the capability of The following sequence will send a message frame sending the special break character sequences that header made up of a break, followed by an auto-baud are required by the LIN bus standard. The break char- sync byte. This sequence is typical of a LIN bus master. acter transmit consists of a Start bit, followed by twelve 1. Configure the USART for the desired mode. ‘0’ bits and a Stop bit. The frame break character is sent 2. Set the TXEN and SENDB bits to set up the whenever the SENDB and TXEN bits (TXSTA<3> and break character. TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to 3. Load the TXREG with a dummy character to TXREG will be ignored and all ‘0’s will be transmitted. initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the sync character The SENDB bit is automatically reset by hardware after into the transmit FIFO buffer. the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte 5. After the break has been sent, the SENDB bit is following the break character (typically, the sync reset by hardware. The sync character now character in the LIN specification). transmits in the preconfigured mode. Note that the data value written to the TXREG for the When the TXREG becomes empty, as indicated by the break character is ignored. The write simply serves the TXIF, the next data byte can be written to TXREG. purpose of initiating the proper sequence. 18.2.6 RECEIVING A BREAK CHARACTER The TRMT bit indicates when the transmit operation is The enhanced USART module can receive a break active or Idle, just as it does during normal transmis- character in two ways. sion. See Figure18-9 for the timing of the break character sequence. The first method forces the configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section18.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the USART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a break character, the user will typ- ically want to enable the auto-baud rate detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 18-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag)  2003-2013 Microchip Technology Inc. DS30491D-page 243

18F8680.book Page 244 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.3 USART Synchronous Once the TXREG register transfers the data to the TSR Master Mode register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt The Synchronous Master mode is entered by setting can be enabled/disabled by setting/clearing enable bit, the CSRC bit (TXSTA<7>). In this mode, the data is TXIE (PIE1<4>). Flag bit TXIF will be set regardless of transmitted in a half-duplex manner (i.e., transmission the state of enable bit TXIE and cannot be cleared in and reception do not occur at the same time). When software. It will reset only when new data is loaded into transmitting data, the reception is inhibited and vice the TXREG register. versa. Synchronous mode is entered by setting bit While flag bit TXIF indicates the status of the TXREG SYNC (TXSTA<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTA<1>), shows the sta- (RCSTA<7>), is set in order to configure the tus of the TSR register. TRMT is a read-only bit which is RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and set when the TSR is empty. No interrupt logic is tied to DT (data) lines, respectively. this bit so the user must poll this bit in order to determine The Master mode indicates that the processor trans- if the TSR register is empty. The TSR is not mapped in mits the master clock on the CK line. Clock polarity is data memory so it is not available to the user. selected with the SCKP bit (BAUDCON<5>); setting To set up a synchronous master transmission: SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. This option is provided 1. Initialize the SPBRGH:SPBRG registers for the to support Microwire devices with this module. appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the 18.3.1 USART SYNCHRONOUS MASTER desired baud rate. TRANSMISSION 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. The USART transmitter block diagram is shown in Figure18-2. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit TXIE. (Serial) Shift Register (TSR). The Shift register obtains 4. If 9-bit transmission is desired, set bit TX9. its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit TXEN. TXREG. The TXREG register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the last should be loaded in bit TX9D. bit has been transmitted from the previous load. As 7. Start transmission by loading data to the TXREG soon as the last bit is transmitted, the TSR is loaded register. with new data from the TXREG (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-10: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DS30491D-page 244  2003-2013 Microchip Technology Inc.

18F8680.book Page 245 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 18-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.  2003-2013 Microchip Technology Inc. DS30491D-page 245

18F8680.book Page 246 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.3.2 USART SYNCHRONOUS MASTER 3. Ensure bits CREN and SREN are clear. RECEPTION 4. If interrupts are desired, set enable bit RCIE. Once Synchronous mode is selected, reception is 5. If 9-bit reception is desired, set bit RX9. enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit SREN. SREN (RCSTA<5>), or the Continuous Receive For continuous reception, set bit CREN. Enable bit, CREN (RCSTA<4>). Data is sampled on the 7. Interrupt flag bit RCIF will be set when reception RC7/RX/DT pin on the falling edge of the clock. is complete and an interrupt will be generated if If enable bit SREN is set, only a single word is received. the enable bit RCIE was set. If enable bit CREN is set, the reception is continuous 8. Read the RCSTA register to get the 9th bit (if until CREN is cleared. If both bits are set, then CREN enabled) and determine if any error occurred takes precedence. during reception. To set up a synchronous master reception: 9. Read the 8-bit received data by reading the RCREG register. 1. Initialize the SPBRGH:SPBRG registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRGH bit CREN. and BRG16 bits, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are 2. Enable the synchronous master serial port by set. setting bits SYNC, SPEN and CSRC. FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC7/TX/CK pin (SCKP = 0) RC7/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. DS30491D-page 246  2003-2013 Microchip Technology Inc.

18F8680.book Page 247 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.4 USART Synchronous Slave Mode To set up a synchronous slave transmission: 1. Enable the synchronous slave serial port by Synchronous Slave mode is entered by clearing bit setting bits SYNC and SPEN and clearing bit CSRC (TXSTA<7>). This mode differs from the CSRC. Synchronous Master mode in that the shift clock is sup- plied externally at the RC6/TX/CK pin (instead of being 2. Clear bits CREN and SREN. supplied internally in Master mode). This allows the 3. If interrupts are desired, set enable bit TXIE. device to transfer or receive data while in any low-power 4. If 9-bit transmission is desired, set bit TX9. mode. 5. Enable the transmission by setting enable bit TXEN. 18.4.1 USART SYNCHRONOUS SLAVE 6. If 9-bit transmission is selected, the ninth bit TRANSMIT should be loaded in bit TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the TXREG modes are identical except in the case of the Sleep register. mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREG and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.  2003-2013 Microchip Technology Inc. DS30491D-page 247

18F8680.book Page 248 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.4.2 USART SYNCHRONOUS SLAVE To set up a synchronous slave reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits SYNC and SPEN and clearing bit modes is identical, except in the case of Sleep or any CSRC. Idle mode and bit SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit RCIE. Slave mode. 3. If 9-bit reception is desired, set bit RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit RCIF will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit RCIE was set. RCREG register; if the RCIE enable bit is set, the inter- 6. Read the RCSTA register to get the 9th bit (if rupt generated will wake the chip from low-power enabled) and determine if any error occurred mode. If the global interrupt is enabled, the program will during reception. branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x RCREG USART Receive Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-0 0-00 -1-0 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. DS30491D-page 248  2003-2013 Microchip Technology Inc.

18F8680.book Page 249 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.0 10-BIT ANALOG-TO-DIGITAL The module has five registers: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) converter module has 12 • A/D Control Register 0 (ADCON0) inputs for the PIC18F6X8X devices and 16 inputs for the PIC18F8X8X devices. This module allows conver- • A/D Control Register 1 (ADCON1) sion of an analog input signal to a corresponding 10-bit • A/D Control Register 2 (ADCON2) digital number. The ADCON0 register, shown in Register19-1, A new feature for the A/D converter is the addition of pro- controls the operation of the A/D module. The grammable acquisition time. This feature allows the user ADCON1 register, shown in Register19-2, configures to select a new channel for conversion and to set the the functions of the port pins. The ADCON2 register, GO/DONE bit immediately. When the GO/DONE bit is shown in Register19-3, configures the A/D clock set, the selected channel is sampled for the source, programmed acquisition time and justification. programmed acquisition time before a conversion is actually started. This removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see Register19-3 and Section19.4 “Selecting the A/D Conversion Clock”). REGISTER 19-1: ADCON0 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(1) 1101 = Channel 13 (AN13)(1) 1110 = Channel 14 (AN14)(1) 1111 = Channel 15 (AN15)(1) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress. This bit is automatically cleared when the A/D conversion is complete. 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled and consumes no current Note1: These channels are only available on PIC18F8X8X devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 249

18F8680.book Page 250 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 19-2: ADCON1 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0000 A A A A A A A A A A A A A A A A 0001 D D A A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A A 0101 D D D D D D A A A A A A A A A A 0110 D D D D D D D A A A A A A A A A 0111 D D D D D D D D A A A A A A A A 1000 D D D D D D D D D A A A A A A A 1001 D D D D D D D D D D A A A A A A 1010 D D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Shaded cells = Additional channels available on the PIC18F8X8X devices Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Channels AN15 through AN12 are not available on the 68-pin devices. DS30491D-page 250  2003-2013 Microchip Technology Inc.

18F8680.book Page 251 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 19-3: ADCON2 REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from A/D RC oscillator)(1) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from A/D RC oscillator)(1) Note1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 251

18F8680.book Page 252 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (AVDD and AVSS) or the voltage level on the RA3/AN3/ conversion in progress is aborted. VREF+ and RA2/AN2/VREF- pins. Each port pin associated with the A/D converter can be The A/D converter has a unique feature of being able configured as an analog input or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and A/D interrupt flag bit ADIF is set. The block converter which generates the result via successive diagram of the A/D module is shown in Figure19-1. approximation. FIGURE 19-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0101 AN5 0100 AN4 VAIN 10-bit (Input Voltage) 0011 AN3 Converter A/D 0010 AN2 0001 VCFG1:VCFG0 AN1 0000 VDD AN0 VREF+ Reference Voltage VREF- VSS Note 1: Channels AN15 through AN12 are not available on the PIC18F6X8X. 2: I/O pins have diode protection to VDD and VSS. DS30491D-page 252  2003-2013 Microchip Technology Inc.

18F8680.book Page 253 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 The value in the ADRESH/ADRESL registers is not The following steps should be followed to do an A/D modified for a Power-on Reset. The ADRESH/ conversion: ADRESL registers will contain unknown data after a 1. Configure the A/D module: Power-on Reset. • Configure analog pins, voltage reference and After the A/D module has been configured as desired, digital I/O (ADCON1) the selected channel must be acquired before the con- • Select A/D input channel (ADCON0) version is started. The analog input channels must • Select A/D acquisition time (ADCON2) have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section19.1 • Select A/D conversion clock (ADCON2) “A/D Acquisition Requirements”. After this acquisi- • Turn on A/D module (ADCON0) tion time has elapsed, the A/D conversion can be 2. Configure A/D interrupt (if desired): started. An acquisition time can be programmed to • Clear ADIF bit occur between setting the GO/DONE bit and the actual • Set ADIE bit start of the conversion. • Set GIE bit 3. Wait the required acquisition time (if required). 4. Start conversion: • Set GO/DONE bit (ADCON0 register) 5. Wait for A/D conversion to complete by either: • Polling for the GO/DONE bit to be cleared or • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF if required. 7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts. FIGURE 19-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L E5A0K0A nGAE CHOLD = 120 pF VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V ILEAKAGE = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) RSS = sampling switch resistance 5 6 7 8 910 11 Sampling Switch(k)  2003-2013 Microchip Technology Inc. DS30491D-page 253

18F8680.book Page 254 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.1 A/D Acquisition Requirements 19.2 A/D VREF+ and VREF- References For the A/D converter to meet its specified accuracy, If external voltage references are used instead of the the charge holding capacitor (CHOLD) must be allowed internal AVDD and AVSS sources, the source impedance to fully charge to the input channel voltage level. The of the VREF+ and VREF- voltage sources must be consid- analog input model is shown in Figure19-2. The ered. During acquisition, currents supplied by these source impedance (RS) and the internal sampling sources are insignificant. However, during conversion, switch (RSS) impedance directly affect the time the A/D module sinks and sources current through the required to charge the capacitor CHOLD. The sampling reference sources. The effect of this current, as specified switch (RSS) impedance varies over the device voltage in parameter A50, along with source impedance must be (VDD). The source impedance affects the offset voltage considered to meet specified A/D resolution. at the analog input (due to pin leakage current). The Note: When using external voltage references maximum recommended impedance for analog with the A/D converter, the source imped- sources is 2.5 k. After the analog input channel is ance of the external voltage references selected (changed), this acquisition must be done must be less than 20to obtain the spec- before the conversion can be started. ified A/D resolution. Higher reference Note: When the conversion is started, the source impedances will increase both holding capacitor is disconnected from the offset and gain errors. Resistive voltage input pin. dividers will not provide a sufficiently low source impedance. To calculate the minimum acquisition time, Equation19-1 may be used. This equation assumes To maintain the best possible performance that 1/2 LSb error is used (1024 steps for the A/D). The in A/D conversions, external VREF inputs 1/2 LSb error is the maximum error allowed for the A/D should be buffered with an operational to meet its specified resolution. amplifier or other low output impedance circuit. Example19-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD = 120 pF Rs = 2.5 k Conversion Error  1/2 LSb VDD = 5V  Rss = 7 k Temperature = 50C (system max.) VHOLD = 0V @ time = 0 EQUATION 19-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 19-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))) or TC = -(120 pF)(1 k + RSS + RS) ln(1/2047) EXAMPLE 19-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF Temperature coefficient is only required for temperatures > 25C. TACQ = 2 s + TC + [(Temp – 25C)(0.05 s/C)] TC = -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004885) -120 pF (10.5 k) ln(0.0004885) -1.26 s (-7.6241) 9.61 s TACQ = 2 s + 9.61 s + [(50C – 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s DS30491D-page 254  2003-2013 Microchip Technology Inc.

18F8680.book Page 255 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.3 Selecting and Configuring 19.4 Selecting the A/D Conversion Clock Automatic Acquisition Time The A/D conversion time per bit is defined as TAD. The The ADCON2 register allows the user to select an A/D conversion requires 11 TAD per 10-bit conversion. acquisition time that occurs each time the GO/DONE The source of the A/D conversion clock is software bit is set. selectable. There are seven possible options for TAD: When the GO/DONE bit is set, sampling is stopped and • 2 TOSC • 4 TOSC a conversion begins. The user is responsible for ensur- • 8 TOSC • 16 TOSC ing the required acquisition time has passed between • 32 TOSC • 64 TOSC selecting the desired input channel and setting the • Internal RC Oscillator GO/DONE bit. This occurs when the ACQT2:ACQT0 bits (ADCON2<5:3>) remain in their Reset state (‘000’) For correct A/D conversions, the A/D conversion clock and is compatible with devices that do not offer (TAD) must be as short as possible but greater than the programmable acquisition times. minimum TAD (approximately 2s, see parameter 130 for more information). If desired, the ACQT bits can be set to select a pro- grammable acquisition time for the A/D module. When Table19-1 shows the resultant TAD times derived from the GO/DONE bit is set, the A/D module continues to the device operating frequencies and the A/D clock sample the input for the selected acquisition time, then source selected. automatically begins a conversion. Since the acquisi- tion time is programmed, there may be no need to wait 19.5 Configuring Analog Port Pins for an acquisition time between selecting a channel and The ADCON1, TRISA, TRISF and TRISH registers con- setting the GO/DONE bit. trol the operation of the A/D port pins. The port pins In either case, when the conversion is completed, the needed as analog inputs must have their corresponding GO/DONE bit is cleared, the ADIF flag is set, and the TRIS bits set (input). If the TRIS bit is cleared (output), A/D begins sampling the currently selected channel the digital output level (VOH or VOL) will be converted. again. If an acquisition time is programmed, there is The A/D operation is independent of the state of the nothing to indicate if the acquisition time has ended or CHS3:CHS0 bits and the TRIS bits. if the conversion has begun. Note1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins config- ured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin defined as a dig- ital input may cause the input buffer to consume current out of the device’s specification limits. TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18FXX80/XX85 PIC18LFXX80/XX85 2 TOSC 000 1.25 MHz 666 kHz 4 TOSC 100 2.50 MHz 1.33 MHz 8 TOSC 001 5.00 MHz 2.66 MHz 16 TOSC 101 10.0 MHz 5.33 MHz 32 TOSC 010 20.0 MHz 10.65 MHz 64 TOSC 110 40.0 MHz 21.33 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 4 s. 2: The RC source has a typical TAD time of 6 s. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification.  2003-2013 Microchip Technology Inc. DS30491D-page 255

18F8680.book Page 256 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.6 A/D Conversions 19.7 Use of the CCP2 Trigger Figure19-3 shows the operation of the A/D converter An A/D conversion can be started by the “special event after the GO bit has been set and the ACQT2:ACQT0 trigger” of the CCP2 module. This requires that the bits are cleared. A conversion is started after the follow- CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- ing instruction to allow entry into Sleep mode before the grammed as ‘1011’ and that the A/D module is enabled conversion begins. (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion Figure19-4 shows the operation of the A/D converter and the Timer1 (or Timer3) counter will be reset to zero. after the GO bit has been set, the ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4 TAD acquisition time Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead before the conversion starts. (moving ADRESH/ADRESL to the desired location). Clearing the GO/DONE bit during a conversion will The appropriate analog input channel must be selected abort the current conversion. The A/D Result register and the minimum acquisition done before the “special pair will not be updated with the partially completed A/D event trigger” sets the GO/DONE bit (starts a conversion sample. This means the ADRESH:ADRESL conversion). registers will continue to contain the value of the last If the A/D module is not enabled (ADON is cleared), the completed conversion (or the last value written to the “special event trigger” will be ignored by the A/D ADRESH:ADRESL registers). module but will still reset the Timer1 (or Timer3) After the A/D conversion is completed or aborted, a counter. 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 19-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 19-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS30491D-page 256  2003-2013 Microchip Technology Inc.

18F8680.book Page 257 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 19-2: SUMMARY OF A/D REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu ADCON0 — — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000 ADCON2 ADFM — — — — ADCS2 ADCS1 ADCS0 0--- -000 0--- -000 PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu TRISA — PORTA Data Direction Register --11 1111 --11 1111 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx uuuu uuuu LATH(1) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx uuuu uuuu TRISH(1) PORTH Data Direction Control Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Only available on PIC18F8X8X devices.  2003-2013 Microchip Technology Inc. DS30491D-page 257

18F8680.book Page 258 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 258  2003-2013 Microchip Technology Inc.

18F8680.book Page 259 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.0 COMPARATOR MODULE The CMCON register, shown in Register20-1, controls the comparator input and output multiplexers. A block The comparator module contains two analog diagram of the various comparator configurations is comparators. The inputs to the comparators are shown in Figure20-1. multiplexed with the RF1 through RF6 pins. The on- chip voltage reference (Section21.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 20-1: CMCON REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RF5/AN10 C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM2:CM0: Comparator Mode bits Figure20-1 shows the Comparator modes and CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 259

18F8680.book Page 260 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section27.0 “Electrical Characteristics”. tors. The CMCON register is used to select these modes. Figure20-1 shows the eight possible modes. Note: Comparator interrupts should be disabled The TRISF register controls the data direction of the during a Comparator mode change. comparator pins for each mode. If the Comparator Otherwise, a false interrupt may occur. FIGURE 20-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM2:CM0 = 000 CM2:CM0 = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- RF5/AN10 A VIN+ C1 Off (Read as ‘0’) RF5/AN10 D VIN+ C1 Off (Read as ‘0’) RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ‘0’) RF3/AN8 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators with Outputs Two Independent Comparators CM2:CM0 = 011 CM2:CM0 = 010 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT RF2/AN7/C1OUT RF4/AN9 A VIN- RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT RF2/AN7/C1OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RF5/AN10 A VIN+ C1 C1OUT RF5/AN10 A CIS = 1 VIN+ C1 C1OUT RF2/AN7/C1OUT A RF4/AN9 CIS = 0 VIN- RF4/AN9 D VIN- RF3/AN8 A CIS = 1 VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ‘0’) CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) = Comparator Input Switch DS30491D-page 260  2003-2013 Microchip Technology Inc.

18F8680.book Page 261 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.2 Comparator Operation 20.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure20-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference for the compara- the digital output. When the analog input at VIN+ is less tors. Section21.0 “Comparator Voltage Reference than the analog input VIN-, the output of the comparator Module” contains a detailed description of the compar- is a digital low level. When the analog input at VIN+ is ator voltage reference module that provides this signal. greater than the analog input VIN-, the output of the The internal reference signal is used when comparators comparator is a digital high level. The shaded areas of are in mode CM<2:0>=110 (Figure20-1). In this mode, the output of the comparator in Figure20-2 represent the internal voltage reference is applied to the VIN+ pin the uncertainty due to input offsets and response time. of both comparators. 20.3 Comparator Reference 20.4 Comparator Response Time An external or internal reference signal may be used Response time is the minimum time, after selecting a depending on the Comparator Operating mode. The new reference voltage or input source, before the analog signal present at VIN- is compared to the signal comparator output has a valid level. If the internal at VIN+ and the digital output of the comparator is reference is changed, the maximum delay of the inter- adjusted accordingly (Figure20-2). nal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Section27.0 FIGURE 20-2: SINGLE COMPARATOR “Electrical Characteristics”). VIN+ + 20.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the com- VIVNI-N– parator. The uncertainty of each of the comparators is related to the input offset voltage and the response time VVININ++ given in the specifications. Figure20-3 shows the comparator output block diagram. The TRISA bits will still function as an output OOuuttppuutt enable/disable for the RF1 and RF2 pins while in this mode. The polarity of the comparator outputs can be changed 20.3.1 EXTERNAL REFERENCE SIGNAL using the C2INV and C1INV bits (CMCON<4:5>). When external voltage references are used, the Note1: When reading the Port register, all pins comparator module can be configured to have the com- configured as analog inputs will read as a parators operate from the same or different reference ‘0’. Pins configured as digital inputs will sources. However, threshold detector applications may convert an analog input according to the require the same reference. The reference signal must Schmitt Trigger input specification. be between VSS and VDD and can be applied to either 2: Analog levels on any pin defined as a dig- pin of the comparator(s). ital input may cause the input buffer to consume more current than is specified.  2003-2013 Microchip Technology Inc. DS30491D-page 261

18F8680.book Page 262 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port pins MULTIPLEX + - CxINV To RF1 or RF2 pin Bus Q D Data Read CMCON EN Set CMIF Q D bit From other EN Comparator CL Read CMCON RESET 20.6 Comparator Interrupts Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a The comparator interrupt flag is set whenever there is read operation is being executed (start of a change in the output value of either comparator. the Q2 cycle), then the CMIF (PIR Software will need to maintain information about the registers) interrupt flag may not get set. status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF The user, in the Interrupt Service Routine, can clear the bit (PIR registers) is the Comparator Interrupt Flag. The interrupt in the following manner: CMIF bit must be reset by clearing it to ‘0’. Since it is a) Any read or write of CMCON will end the also possible to write a ‘1’ to this register, a simulated mismatch condition. interrupt may be initiated. b) Clear flag bit CMIF. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, A mismatch condition will continue to set flag bit CMIF. the GIE bit must also be set. If any of these bits are Reading CMCON will end the mismatch condition and clear, the interrupt is not enabled, though the CMIF bit allow flag bit CMIF to be cleared. will still be set if an interrupt condition occurs. DS30491D-page 262  2003-2013 Microchip Technology Inc.

18F8680.book Page 263 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.7 Comparator Operation During 20.9 Analog Input Connection Sleep Considerations When a comparator is active and the device is placed A simplified circuit for an analog input is shown in in Sleep mode, the comparator remains active and the Figure20-4. Since the analog pins are connected to a interrupt is functional if enabled. This interrupt will digital output, they have reverse biased diodes to VDD wake-up the device from Sleep mode when enabled. and VSS. The analog input, therefore, must be between While the comparator is powered up, higher Sleep VSS and VDD. If the input voltage deviates from this currents than shown in the power-down current range by more than 0.6V in either direction, one of the specification will occur. Each operational comparator diodes is forward biased and a latch-up condition may will consume additional current as shown in the com- occur. A maximum source impedance of 10k is parator specifications. To minimize power consumption recommended for the analog sources. Any external while in Sleep mode, turn off the comparators component connected to an analog input pin, such as (CM<2:0>=111) before entering Sleep. If the device a capacitor or a Zener diode, should have very little wakes up from Sleep, the contents of the CMCON leakage current. register are not affected. 20.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator module to be in the Comparator Reset mode (CM<2:0>=000). This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at Reset time. The comparators will be powered down during the Reset interval. FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage  2003-2013 Microchip Technology Inc. DS30491D-page 263

18F8680.book Page 264 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000 IPR2 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. DS30491D-page 264  2003-2013 Microchip Technology Inc.

18F8680.book Page 265 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 21.0 COMPARATOR VOLTAGE 21.1 Configuring the Comparator REFERENCE MODULE Voltage Reference The comparator voltage reference is a 16-tap resistor The comparator voltage reference can output 16 distinct ladder network that provides a selectable voltage voltage levels for each range. The equations used to reference. The resistor ladder is segmented to provide calculate the output of the comparator voltage reference two ranges of CVREF values and has a power-down are as follows: function to conserve power when the reference is not If CVRR = 1: being used. The CVRCON register controls the CVREF = (CVR<3:0>/24) x CVRSRC operation of the reference as shown in Register21-1. If CVRR = 0: The block diagram is given in Figure21-1. CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC The comparator reference supply voltage can come The settling time of the comparator voltage reference from either VDD or VSS, or the external VREF+ and VREF- that are multiplexed with RA3 and RA2. The must be considered when changing the CVREF output (Section27.0 “Electrical Characteristics”). comparator reference supply voltage is controlled by the CVRSS bit. REGISTER 21-1: CVRCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/C1IN+/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/C1IN+/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.625 CVRSRC with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.71875 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF- 0 = Comparator reference source, CVRSRC = VDD – VSS Note: To select (VREF+ – VREF-) as the comparator voltage reference source, the voltage reference configuration bits in the ADCON1 register (ADCON1<5:4>) must also be set to ‘11’. bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0  VR3:VR0  15) When CVRR = 1: CVREF = (CVR<3:0>/24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR3:CVR0/32)  (CVRSRC) Note1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5> to ‘1’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 265

18F8680.book Page 266 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS = 0 CVRSS = 1 16 Stages CVREN 8R R R R R CVRR 8R CVRSS = 0 CVRSS = 1 VREF- CVR3 CVREF 16-1 Analog Mux (From CVRCON<3:0>) CVR0 Note: R is defined in Section27.0 “Electrical Characteristics”. 21.2 Voltage Reference Accuracy/Error 21.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure21-1) keep CVREF from approaching the refer- bit CVROE (CVRCON<6>) and selects the high- ence source rails. The voltage reference is derived voltage range by clearing bit CVRR (CVRCON<5>). from the reference source; therefore, the CVREF output The VRSS value select bits, CVRCON<3:0>, are also changes with fluctuations in that source. The tested cleared. absolute accuracy of the voltage reference can be found in Section27.0 “Electrical Characteristics”. 21.5 Connection Considerations 21.3 Operation During Sleep The voltage reference module operates independently of the comparator module. The output of the reference When the device wakes up from Sleep through an generator may be connected to the RF5 pin if the interrupt or a Watchdog Timer time-out, the contents of TRISF<5> bit is set and the CVROE bit is set. Enabling the CVRCON register are not affected. To minimize the voltage reference output onto the RF5 pin with an current consumption in Sleep mode, the voltage input signal present will increase current consumption. reference should be disabled. Connecting RF5 as a digital output with VRSS enabled will also increase current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage refer- ence output for external connections to VREF. Figure21-2 shows an example buffering technique. DS30491D-page 266  2003-2013 Microchip Technology Inc.

18F8680.book Page 267 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE CVREF R(1) RF5 Module +– CVREF Output Voltage Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits CVRCON<3:0> and CVRCON<5>. TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR Resets CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.  2003-2013 Microchip Technology Inc. DS30491D-page 267

18F8680.book Page 268 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 268  2003-2013 Microchip Technology Inc.

18F8680.book Page 269 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.0 LOW-VOLTAGE DETECT The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be “turned In many applications, the ability to determine if the off” by the software which minimizes the current device voltage (VDD) is below a specified voltage level consumption for the device. is a desirable feature. A window of operation for the Figure22-1 shows a possible application voltage curve application can be created where the application soft- (typically for batteries). Over time, the device voltage ware can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at done using the Low-Voltage Detect module. time TA. The application software then has the time, This module is a software programmable circuitry until the device voltage is no longer in valid operating where a device voltage trip point can be specified. range, to shut down the system. Voltage point VB is the When the voltage of the device becomes lower then the minimum valid operating voltage specification. This specified point, an interrupt flag is set. If the interrupt is occurs at time TB. The difference, TB – TA, is the total enabled, the program execution will branch to the inter- time for shutdown. rupt vector address and the software can then respond to that interrupt source. FIGURE 22-1: TYPICAL LOW-VOLTAGE DETECT APPLICATION VA VB e g a Volt Legend: VA = LVD trip point VB = Minimum valid device operating voltage Time TA TB The block diagram for the LVD module is shown in supply voltage is equal to the trip point, the voltage Figure22-2. A comparator uses an internally gener- tapped off of the resistor array is equal to the 1.2V ated reference voltage as the set point. When the internal reference voltage generated by the voltage selected tap output of the device voltage crosses the reference module. The comparator then generates an set point (is lower than), the LVDIF bit is set. interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Each node in the resistor divider represents a “trip Figure22-2). The trip point is selected by point” voltage. The “trip point” voltage is the minimum programming the LVDL3:LVDL0 bits (LVDCON<3:0>). supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the  2003-2013 Microchip Technology Inc. DS30491D-page 269

18F8680.book Page 270 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM VDD LVDIN LVD3:LVD0 LVDCON Register X U M 1 o LVDIF 6 t 1 LVDEN Internally Generated Reference Voltage (Parameter #D423) The LVD module has an additional feature that allows LVDIN (Figure22-3). This gives users flexibility the user to supply the trip voltage to the module from an because it allows them to configure the Low-Voltage external source. This mode is enabled when bits Detect interrupt to occur at any voltage in the valid LVDL3:LVDL0 are set to ‘1111’. In this state, the com- operating range. parator input is multiplexed from the external input pin, FIGURE 22-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD LVD3:LVD0 LVDCON Register LVDIN UX LVDEN Externally Generated M Trip Point 6 to 1 LVD 1 VxEN BODEN EN BGAP DS30491D-page 270  2003-2013 Microchip Technology Inc.

18F8680.book Page 271 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry. REGISTER 22-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V-4.77V 1101 = 4.2V-4.45V 1100 = 4.0V-4.24V 1011 = 3.8V-4.03V 1010 = 3.6V-3.82V 1001 = 3.5V-3.71V 1000 = 3.3V-3.50V 0111 = 3.0V-3.18V 0110 = 2.8V-2.97V 0101 = 2.7V-2.86V 0100 = 2.5V-2.65V 0011 = 2.4V-2.54V 0010 = 2.2V-2.33V 0001 = 2.0V-2.12V 0000 = Reserved Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 271

18F8680.book Page 272 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, 1. Write the value to the LVDL3:LVDL0 bits the voltage normally decreases relatively slowly. This (LVDCON register) which selects the desired means that the LVD module does not need to be LVD trip point. constantly operating. To decrease the current require- ments, the LVD circuitry only needs to be enabled for 2. Ensure that LVD interrupts are disabled (the short periods where the voltage is checked. After doing LVDIE bit is cleared or the GIE bit is cleared). the check, the LVD module may be disabled. 3. Enable the LVD module (set the LVDEN bit in the LVDCON register). Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has 4. Wait for the LVD module to stabilize (the IRVST stabilized, all status flags may be cleared. The module bit to become set). will then indicate the proper state of the system. 5. Clear the LVD interrupt flag which may have falsely become set until the LVD module has stabilized (clear the LVDIF bit). 6. Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure22-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 22-4: LOW-VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated TIVRST Reference Stable LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated TIVRST Reference Stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS30491D-page 272  2003-2013 Microchip Technology Inc.

18F8680.book Page 273 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.2.1 REFERENCE VOLTAGE SET POINT 22.3 Operation During Sleep The internal reference voltage of the LVD module, When enabled, the LVD circuitry continues to operate specified in electrical specification parameter #D423, during Sleep. If the device voltage crosses the trip may be used by other internal circuitry (the Program- point, the LVDIF bit will be set and the device will mable Brown-out Reset). If these circuits are disabled wake-up from Sleep. Device execution will continue (lower current consumption), the reference voltage from the interrupt vector address if interrupts have circuit requires a time to become stable before a low- been globally enabled. voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is 22.4 Effects of a Reset specified in electrical specification parameter #36. The low-voltage interrupt flag will not be enabled until a A device Reset forces all registers to their Reset state. stable reference voltage is reached. Refer to the This forces the LVD module to be turned off. waveform in Figure22-4. 22.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static cur- rent. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B.  2003-2013 Microchip Technology Inc. DS30491D-page 273

18F8680.book Page 274 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 274  2003-2013 Microchip Technology Inc.

18F8680.book Page 275 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.0 ECAN MODULE 23.1 Module Overview PIC18F6585/8585/6680/8680 devices contain an The CAN bus module consists of a protocol engine and Enhanced Controller Area Network (ECAN) module. message buffering and control. The CAN protocol The ECAN module is fully backward compatible with engine automatically handles all functions for receiving the CAN module available in PIC18CXX8 and and transmitting messages on the CAN bus. Messages PIC18FXX8 devices. are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading The Controller Area Network (CAN) module is a serial the appropriate registers. Any message detected on interface which is useful for communicating with other the CAN bus is checked for errors and then matched peripherals or microcontroller devices. This interface, against filters to see if it should be received and stored or protocol, was designed to allow communications in one of the two receive registers. within noisy environments. The CAN module supports the following frame types: The ECAN module is a communication controller, implementing the CAN 2.0A or B protocol as defined in • Standard Data Frame the BOSCH specification. The module will support • Extended Data Frame CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B • Remote Frame Active versions of the protocol. The module implemen- • Error Frame tation is a full CAN system; however, the CAN specifi- • Overload Frame Reception cation is not covered within this data sheet. Refer to the BOSCH CAN specification for further details. • Interframe Space Generation/Detection The module features are as follows: The CAN module uses the RG0/CANTX1, RG1/CANTX2 and RG2/CANRX pins to interface with • Implementation of the CAN protocol CAN 1.2, the CAN bus. In Normal mode, the CAN module CAN 2.0A and CAN 2.0B automatically overrides the TRISG0 and TRISG1 bits • DeviceNetTM data bytes filter support of the CAN module pins. • Standard and extended data frames • 0-8 bytes data length 23.1.1 MODULE FUNCTIONALITY • Programmable bit rate up to 1 Mbit/sec The CAN bus module consists of a protocol engine, • Fully backward compatible with PIC18XX8 CAN message buffering and control (see Figure 23-1). The module protocol engine can best be understood by defining the • Three modes of operation: types of data frames to be transmitted and received by - Mode 0 – Legacy mode the module. - Mode 1 – Enhanced Legacy mode with The following sequence illustrates the necessary initial- DeviceNet support ization steps before the ECAN module can be used to - Mode 2 – FIFO mode with DeviceNet support transmit or receive a message. Steps can be added or • Support for remote frames with automated handling removed depending on the requirements of the • Double-buffered receiver with two prioritized application. received message storage buffers 1. Ensure that the ECAN module is in Configuration • Six buffers programmable as RX and TX mode. message buffers 2. Select ECAN Operational mode. • 16 full (standard/extended identifier) acceptance 3. Set up the baud rate registers. filters that can be linked to one of four masks • Two full acceptance filter masks that can be 4. Set up the filter and mask registers. assigned to any filter 5. Set the ECAN module to Normal mode or any • One full acceptance filter that can be used as either other mode required by the application logic. an acceptance filter or acceptance filter mask • Three dedicated transmit buffers with application specified prioritization and abort capability • Programmable wake-up functionality with integrated low-pass filter • Programmable Loopback mode supports self-test operation • Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low-Power Sleep mode  2003-2013 Microchip Technology Inc. DS30491D-page 275

18F8680.book Page 276 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 23-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS 16-4 to 1 muxs sk a M ce M0 TXB0 TXB1 TXB2 A A(cRcXeMpFt0Oa n–Dc REe X 0FFil0te5r)s VCC cceptanRX A MSGREQABTFMLOATXERRMTXBUFF MESSAGE MSGREQABTFMLOATXERRMTXBUFF MESSAGE MSGREQABTFMLOATXERRMTXBUFF MESSAGE ccept A(RcXcMeFpO0t6aD n–Ec Re1 ,XF 2Filt1e5r)s RXF15 ptance MaskRXM1 e c c Message MODE 0 A Queue 2 RX Identifier Control Buffers MA Transmit Byte Sequencer Data Field B MODE 1, 2 Rcv Byte 6 TX/RX Buffers Transmit Option MESSAGE BUFFERS PROTOCOL Receive REC ENGINE Error Counter TEC Transmit Err-Pas Error Bus-Off Counter Transmit<7:0> Receive<8:0> Shift<14:0> {Transmit<5:0>, Receive<8:0>} Comparator Protocol Finite State CRC<14:0> Machine Bit Transmit Timing Clock Logic Logic Generator Configuration TX RX Registers DS30491D-page 276  2003-2013 Microchip Technology Inc.

18F8680.book Page 277 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2 CAN Module Registers 23.2.1 CAN CONTROL AND STATUS REGISTERS Note: Not all CAN registers are available in the The registers described in this section control the Access Bank. overall operation of the CAN module and show its There are many control and data registers associated operational status. with the CAN module. For convenience, their descriptions have been grouped into the following sections: • Control and Status Registers • Dedicated Transmit Buffer Registers • Dedicated Receive Buffer Registers • Programmable TX/RX and Auto RTR Buffers • Baud Rate Control Registers • I/O Control Register • Interrupt Status and Control Registers Detailed descriptions of each register and their usage are described in the following sections.  2003-2013 Microchip Technology Inc. DS30491D-page 277

18F8680.book Page 278 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-1: CANCON: CAN CONTROL REGISTER R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0 Mode 0 REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0 — R/W-1 R/W-0 R/W-0 R/S-0 U-0 U-0 U-0 U-0 Mode 1 REQOP2 REQOP1 REQOP0 ABAT — — — — R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0 Mode 2 REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0 bit 7 bit 0 bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode bit 4 ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal bit 3-1 Mode 0: WIN2:WIN0: Window Address bits This selects which of the CAN buffers to switch into the access bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See Example23-2 for a code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Unimplemented: Read as ‘0’ bit 3-0 Mode 1: Unimplemented: Read as ‘0’ Mode 2: FP3:FP0: FIFO Read Pointer bits These bits point to the message buffer to be read. 0111:0000 = Message buffer to be read 1111:1000 = Reserved Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 278  2003-2013 Microchip Technology Inc.

18F8680.book Page 279 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-2: CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 R-0 R-0 R-0 R-0 U-0 Mode 0 OPMODE2(1) OPMODE1(1) OPMODE0(1) — ICODE2 ICODE1 ICODE0 — R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1, 2 OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 EICODE2 EICODE1 EICODE0 bit 7 bit 0 bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mode 000 = Normal mode bit 4 Mode 0: Unimplemented: Read as ‘0’ bit 3-1 ICODE2:ICODE0: Interrupt Code bits in Mode 0 When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. By copying ICODE2:ICODE0 to WIN2:WIN0, it is pos- sible to select the correct buffer to map into the Access Bank area. See Example23-2 for a code example. ICODE2:ICODE0 Value No interrupt 000 Error interrupt 001 TXB2 interrupt 010 TXB1 interrupt 011 TXB0 interrupt 100 RXB1 interrupt 101 RXB0 interrupt 110 Wake-up interrupt 111 bit 0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 279

18F8680.book Page 280 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-2: CANSTAT: CAN STATUS REGISTER (CONTINUED) bit 4-0 Mode 1,2: EICODE4:EICODE0: Interrupt Code bits in Mode 1 and Mode 2 When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. Unlike ICODE bits in Mode 0, these bits may not be copied directly to EWIN bits to map interrupted buffer to Access Bank area. If required, user software may maintain a table in program memory to map EICODE bits to EWIN bits and access interrupt buffer in Access Bank area. EICODE4:EICODE0 Value No interrupt 00000 Error interrupt 00010 TXB2 interrupt 00100 TXB1 interrupt 00110 TXB0 interrupt 01000 RXB1 interrupt 10001/10000(2) RXB0 interrupt 10000 Wake-up interrupt 01110 RX/TX B0 interrupt 10010(2) RX/TX B1 interrupt 10011(2) RX/TX B2 interrupt 10100(2) RX/TX B3 interrupt 10101(2) RX/TX B4 interrupt 10110(2) RX/TX B4 interrupt 10111(2) Note1: To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch CAN module to Disable mode before putting the device to Sleep. 2: In Mode 2, if the buffer is configured as a receiver, EICODE bits will always contain ‘10000’ upon interrupt. Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared DS30491D-page 280  2003-2013 Microchip Technology Inc.

18F8680.book Page 281 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing. ConfigWait: MOVF CANSTAT, W ; Read current mode state. ANDLW B’10000000’ ; Interested in OPMODE bits only. TSTFSZ WREG ; Is it Configuration mode yet? BRA ConfigWait ; No. Continue to wait... ; Module is in Configuration mode now. ; Modify configuration registers as required. ; Switch back to Normal mode to be able to communicate. EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low MOVFF CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred MOVFF CANSTAT, TempCANSTAT ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ; than one changed by another CAN ; interrupt. MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B’00001110’ ADDWF PCL, F ; Perform computed GOTO ; to corresponding interrupt cause BRA NoInterrupt ; 000 = No interrupt BRA ErrorInterrupt ; 001 = Error interrupt BRA TXB2Interrupt ; 010 = TXB2 interrupt BRA TXB1Interrupt ; 011 = TXB1 interrupt BRA TXB0Interrupt ; 100 = TXB0 interrupt BRA RXB1Interrupt ; 101 = RXB1 interrupt BRA RXB0Interrupt ; 110 = RXB0 interrupt ; 111 = Wake-up on interrupt WakeupInterrupt BCF PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here … NoInterrupt … ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error.  2003-2013 Microchip Technology Inc. DS30491D-page 281

18F8680.book Page 282 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error. RETFIE TXB2Interrupt BCF PIR3, TXB2IF ; Clear the interrupt flag GOTO AccessBuffer TXB1Interrupt BCF PIR3, TXB1IF ; Clear the interrupt flag GOTO AccessBuffer TXB0Interrupt BCF PIR3, TXB0IF ; Clear the interrupt flag GOTO AccessBuffer RXB1Interrupt BCF PIR3, RXB1IF ; Clear the interrupt flag GOTO Accessbuffer RXB0Interrupt BCF PIR3, RXB0IF ; Clear the interrupt flag GOTO AccessBuffer AccessBuffer ; This is either TX or RX interrupt ; Copy CANSTAT.ICODE bits to CANCON.WIN bits MOVF TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. ANDLW B’11110001’ ; Use previously saved CANCON value to ; make sure same value. MOVWF TempCANCON ; Copy masked value back to TempCANCON MOVF TempCANSTAT, W ; Retrieve ICODE bits ANDLW B’00001110’ ; Use previously saved CANSTAT value ; to make sure same value. IORWF TempCANCON ; Copy ICODE bits to WIN bits. MOVFF TempCANCON, CANCON ; Copy the result to actual CANCON ; Access current buffer… ; User code ; Restore CANCON.WIN bits MOVF CANCON, W ; Preserve current non WIN bits ANDLW B’11110001’ IORWF TempCANCON ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source DS30491D-page 282  2003-2013 Microchip Technology Inc.

18F8680.book Page 283 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1, 2) MDSEL0(1, 2) FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 bit 7-6 MDSEL1:MDSEL0: Mode Select bits 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mode (Mode 2) 11 = Reserved bit 5 FIFOWM: FIFO High Water Mark bit(3) 1 = Will cause FIFO interrupt when one receive buffer remains(4) 0 = Will cause FIFO interrupt when four receive buffers remain bit 4-0 EWIN4:EWIN0: Enhanced Window Address bits These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh. Exact group of registers to map is determined by binary value of these bits. Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: 00000 = Acceptance Filters 0, 1, 2 and BRGCON3, 2 00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON 00010 = Acceptance Filter Masks, Error and Interrupt Control 00011 = Transmit Buffer 0 00100 = Transmit Buffer 1 00101 = Transmit Buffer 2 00110 = Acceptance Filters 6, 7, 8 00111 = Acceptance Filters 9, 10, 11 01000 = Acceptance Filters 12, 13, 14 01001 = Acceptance Filters 15 01010-01111 = Reserved 10000 = Receive Buffer 0 10001 = Receive Buffer 1 10010 = TX/RX Buffer 0 10011 = TX/RX Buffer 1 10100 = TX/RX Buffer 2 10101 = TX/RX Buffer 3 10110 = TX/RX Buffer 4 10111 = TX/RX Buffer 5 11000-11111 = Reserved Note1: These bits can only be changed in Configuration mode. See Register19-2 to change to Configuration mode. 2: A new mode takes into effect only after Configuration mode is exited. 3: This bit is used in Mode 2 only. 4: FIFO length of 4 or less will cause this bit to be set. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 283

18F8680.book Page 284 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-4: COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN U-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1 — RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 2 FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 bit 7 Mode 0: RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed Mode 1: Unimplemented: Read as ‘0’ Mode 2: FIFOEMPTY: FIFO Not Empty bit 1 = Receive FIFO is not empty 0 = Receive FIFO is empty bit 6 Mode 0: RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed Mode 1, 2: RXBnOVFL: Receive Buffer Overflow bit 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 5 TXBO: Transmitter Bus-Off bit 1 = Transmit error counter > 255 0 = Transmit error counter 255 bit 4 TXBP: Transmitter Bus Passive bit 1 = Transmit error counter > 127 0 = Transmit error counter 127 bit 3 RXBP: Receiver Bus Passive bit 1 = Receive error counter > 127 0 = Receive error counter 127 bit 2 TXWARN: Transmitter Warning bit 1 = 127  Transmit error counter > 95 0 = Transmit error counter 95 bit 1 RXWARN: Receiver Warning bit 1 = 127  Receive error counter > 95 0 = Receive error counter  95 bit 0 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits. 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 284  2003-2013 Microchip Technology Inc.

18F8680.book Page 285 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers. REGISTER 23-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0  n  2] U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 Mode 0 — TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 R/C-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 Mode 1, 2 TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 bit 7 bit 0 bit 7 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: TXBIF: Transmit Buffer Interrupt Flag bit 1 = Transmit buffer has completed transmission of message and may be reloaded 0 = Transmit buffer has not completed transmission of a message bit 6 TXABT: Transmission Aborted Status bit(1) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(2) 1 = Requests sending a message. Clears the TXABT, TXLARB, and TXERR bits. 0 = Automatically cleared when the message is successfully sent Note: Clearing this bit in software while the bit is set, will request a message abort. bit 2 Unimplemented: Read as ‘0’ bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits(3) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note1: This bit is automatically cleared when TXREQ is set. 2: While TXREQ is set, Transmit Buffer registers remain read-only. 3: These bits define the order in which transmit buffers will be transferred. They do not alter the CAN message identifier. Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared  2003-2013 Microchip Technology Inc. DS30491D-page 285

18F8680.book Page 286 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0; Extended Identifier bits EID28:EID21, if EXIDE = 1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-7: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0  n  2] R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0; Extended Identifier bits EID20:EID18, if EXIDE = 1. bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended ID, SID10:SID0 becomes EID28:EID18 0 = Message will transmit standard ID, EID17:EID0 are ignored bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-8: TXBnEIDH: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits (not used when transmitting standard identifier message) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 286  2003-2013 Microchip Technology Inc.

18F8680.book Page 287 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-9: TXBnEIDL: TRANSMIT BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits (not used when transmitting standard identifier message) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-10: TXBnDm: TRANSMIT BUFFER n DATA FIELD BYTE m REGISTERS [0  n  2, 0  m  7] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 0 bit 7-0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 287

18F8680.book Page 288 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0  n  2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 bit 7-0 TEC7:TEC0: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 288  2003-2013 Microchip Technology Inc.

18F8680.book Page 289 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSELTXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access. ; Now load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF TXB0D0 ; Compiler will automatically set “BANKED” bit ; Load rest of data bytes - up to 8 bytes into TXB0 buffer. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF TXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF TXB0SIDH ; No need to load TXB0EIDL:TXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B’00001000’ ; Normal priority; Request transmission MOVWF TXB0CON ; If required, wait for message to get transmitted BTFSC TXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted.  2003-2013 Microchip Technology Inc. DS30491D-page 289

18F8680.book Page 290 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits. ANDLW B’11110000’ ; Clear WIN bits. IORLW B’00001000’ ; Select Transmit Buffer 0 MOVWF CANCON ; Apply the changes. ; Now TXB0 is mapped in place of RXB0. All future access to RXB0 registers will actually ; yield TXB0 register values. ; Load transmit data into TXB0 buffer. MOVLW MY_DATA_BYTE1 ; Load first data byte into buffer MOVWF RXB0D0 ; Access TXB0D0 via RXB0D0 address. ; Load rest of the data bytes - up to 8 bytes into “TXB0” buffer using RXB0 registers. ... ; Load message identifier MOVLW 60H ; Load SID2:SID0, EXIDE = 0 MOVWF RXB0SIDL MOVLW 24H ; Load SID10:SID3 MOVWF RXB0SIDH ; No need to load RXB0EIDL:RXB0EIDH, as we are transmitting Standard Identifier Message only. ; Now that all data bytes are loaded, mark it for transmission. MOVLW B’00001000’ ; Normal priority; Request transmission MOVWF RXB0CON ; If required, wait for message to get transmitted BTFSC RXB0CON, TXREQ ; Is it transmitted? BRA $-2 ; No. Continue to wait... ; Message is transmitted. ; If required, reset the WIN bits to default state. DS30491D-page 290  2003-2013 Microchip Technology Inc.

18F8680.book Page 291 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers. REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 Mode 0 RXFUL RXM1 RXM0 — RXRTRRO RXB0DBEN JTOFF FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1, 2 RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. bit 6 Mode 0: RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits <4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits <4:0>. Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared  2003-2013 Microchip Technology Inc. DS30491D-page 291

18F8680.book Page 292 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT2: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits <4:0>. bit 1 Mode 0: JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN) 1 = Allows jump table offset between 6 and 7 0 = Allows jump table offset between 1 and 0 Note: This bit allows same filter jump table for both RXB0CON and RXB1CON. Mode 1, 2: FILHIT1: Filter Hit bit 1 This bit combines with other bits to form filter acceptance bits <4:0>. bit 0 Mode 0: FILHIT0: Filter Hit bit 0 This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0. 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Mode 1, 2: FILHIT0: Filter Hit bit 0 This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared DS30491D-page 292  2003-2013 Microchip Technology Inc.

18F8680.book Page 293 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 Mode 0 RXFUL RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 Mode 1, 2 RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. bit 6 Mode 0: RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5) 11 = Receive all messages (including those with errors); filter criteria is ignored 10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’ 01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’ 00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register Mode 1, 2: RXM1: Receive Buffer Mode bit 1 = Receive all messages (including those with errors); acceptance filters are ignored 0 = Receive all valid messages as per acceptance filters bit 5 Mode 0: RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6) Mode 1, 2: RTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received bit 4 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: FILHIT4: Filter Hit bit 4 This bit combines with other bits to form filter acceptance bits <4:0>. bit 3 Mode 0: RXRTRRO: Remote Transmission Request bit for Received Message (read-only) 1 = A remote transmission request is received 0 = A remote transmission request is not received Mode 1, 2: FILHIT3: Filter Hit bit 3 This bit combines with other bits to form filter acceptance bits <4:0>. bit 2-0 Mode 0: FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set Mode 1, 2: FILHIT2:FILHIT0 Filter Hit bits <2:0> These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception into this receive buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00000 = Acceptance Filter 0 (RXF0) Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared  2003-2013 Microchip Technology Inc. DS30491D-page 293

18F8680.book Page 294 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0  n  1] R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL<3>); Extended Identifier bits EID28:EID21, if EXID = 1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-16: RXBnSIDL: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE [0  n  1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXID = 0; Extended Identifier bits EID20:EID18, if EXID = 1. bit 4 SRR: Substitute Remote Request bit This bit is always ‘0’ when EXID = 1 or equal to the value of RXRTRRO (RBXnCON<3>) when EXID = 0. bit 3 EXID: Extended Identifier bit 1 = Received message is an extended data frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard data frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-17: RXBnEIDH: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  1] R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 294  2003-2013 Microchip Technology Inc.

18F8680.book Page 295 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-18: RXBnEIDL: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  1] R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-19: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTERS [0  n  1] U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ‘0’. bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 295

18F8680.book Page 296 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS [0  n  1, 0  m  7] R-x R-x R-x R-x R-x R-x R-x R-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 0 bit 7-0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 bit 7-0 REC7:REC0: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error-passive state. RXERRCNT does not have the ability to put the module in “bus-off” state. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown EXAMPLE 23-5: READING A CAN MESSAGE ; Need to read a pending message from RXB0 buffer. ; To receive any message, filter, mask and RXM1:RXM0 bits in RXB0CON registers must be ; programmed correctly. ; ; Make sure that there is a message pending in RXB0. BTFSS RXB0CON, RXFUL ; Does RXB0 contain a message? BRA NoMessage ; No. Handle this situation... ; We have verified that a message is pending in RXB0 buffer. ; If this buffer can receive both Standard or Extended Identifier messages, ; identify type of message received. BTFSS RXB0SIDL, EXID ; Is this Extended Identifier? BRA StandardMessage ; No. This is Standard Identifier message. ; Yes. This is Extended Identifier message. ; Read all 29-bits of Extended Identifier message. ... ; Now read all data bytes MOVFF RXB0DO, MY_DATA_BYTE1 ... ; Once entire message is read, mark the RXB0 that it is read and no longer FULL. BCF RXB0CON, RXFUL ; This will allow CAN Module to load new messages ; into this buffer. ... DS30491D-page 296  2003-2013 Microchip Technology Inc.

18F8680.book Page 297 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.3.1 Programmable TX/RX and Auto RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0. REGISTER 23-22: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 bit 7 RXFUL: Receive Full Status bit(1) 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module upon receiving a message and must be cleared by software after the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be considered full. bit 6 RXM1: Receive Buffer Mode bit 1 = Receive all messages including partial and invalid (acceptance filters are ignored) 0 = Receive all valid messages as per acceptance filters bit 5 RTRRO: Read-Only Remote Transmission Request bit for Received Message 1 = Received message is a remote transmission request 0 = Received message is not a remote transmission request bit 4-0 FILHIT4:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into this buffer. 01111 = Acceptance Filter 15 (RXF15) 01110 = Acceptance Filter 14 (RXF14) ... 00001 = Acceptance Filter 1 (RXF1) 00000 = Acceptance Filter 0 (RXF0) Note1: These registers are available in Mode 1 and 2 only. Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared  2003-2013 Microchip Technology Inc. DS30491D-page 297

18F8680.book Page 298 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 bit 7 bit 0 bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(1) 1 = A message is successfully transmitted 0 = No message was transmitted bit 6 TXABT: Transmission Aborted Status bit(1) 1 = Message was aborted 0 = Message was not aborted bit 5 TXLARB: Transmission Lost Arbitration Status bit(2) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Transmission Error Detected Status bit(2) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQ: Transmit Request Status bit(3) 1 = Requests sending a message; clears the TXABT, TXLARB, and TXERR bits 0 = Automatically cleared when the message is successfully sent Note: Clearing this bit in software while the bit is set will request a message abort. bit 2 RTREN: Automatic Remote Transmission Request Enable bit 1 = When a remote transmission request is received, TXREQ will be automatically set 0 = When a remote transmission request is received, TXREQ will be unaffected bit 1-0 TXPRI1:TXPRI0: Transmit Priority bits(4) 11 = Priority Level 3 (highest priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (lowest priority) Note1: These registers are available in Mode 1 and 2 only. 2: This bit is automatically cleared when TXREQ is set. 3: While TXREQ is set or transmission is in progress, transmit buffer registers remain read-only. 4: These bits set the order in which the transmit buffer will be transferred. They do not alter the CAN message identifier. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 298  2003-2013 Microchip Technology Inc.

18F8680.book Page 299 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0; Extended Identifier bits EID28:EID21, if EXIDE = 1. Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-25: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0; Extended Identifier bits EID28:EID21, if EXIDE = 1. Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 299

18F8680.book Page 300 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXID = 0; Extended Identifier bits EID20:EID18, if EXID = 1. bit 4 SRR: Substitute Remote Transmission Request bit (only when EXID = 1) 1 = Remote transmission request occurred 0 = No remote transmission request occurred bit 3 EXID: Extended Identifier Enable bit 1 = Received message is an extended identifier frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-27: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXIDE = 0; Extended Identifier bits EID20:EID18, if EXIDE = 1. bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Received message is an extended identifier frame, SID10:SID0 are EID28:EID18 0 = Received message is a standard identifier frame bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier bits Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 300  2003-2013 Microchip Technology Inc.

18F8680.book Page 301 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-29: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 301

18F8680.book Page 302 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-31: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN TRANSMIT MODE [0  n  5, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 302  2003-2013 Microchip Technology Inc.

18F8680.book Page 303 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE [0  n  5, 0  m  7, TXnEN (BSEL<n>) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 bit 7-0 BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers: B0D0 to B0D7. Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE [0  n  5, 0  m  7, TXnEN (BSEL<n>) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 0 bit 7-0 BnDm7:BnDm0: Transmit Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers: TXB0D0 to TXB0D7. Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 303

18F8680.book Page 304 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-34: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0  n  5, TXnEN (BSEL<n>) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request 0 = This is not a remote transmission request bit 5 RB1: Reserved bit 1 Reserved by CAN Spec and read as ‘0’. bit 4 RB0: Reserved bit 0 Reserved by CAN Spec and read as ‘0’. bit 3-0 DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 304  2003-2013 Microchip Technology Inc.

18F8680.book Page 305 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-35: BnDLC: TX/RX BUFFER n DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0  n  5, TXnEN (BSEL<n>) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will have RTR bit set 0 = Transmitted message will have RTR bit cleared bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 DLC3:DLC0: Data Length Code bits 1111-1001 = Reserved 1000 = Data length = 8 bytes 0111 = Data length = 7 bytes 0110 = Data length = 6 bytes 0101 = Data length = 5 bytes 0100 = Data length = 4 bytes 0011 = Data length = 3 bytes 0010 = Data length = 2 bytes 0001 = Data length = 1 bytes 0000 = Data length = 0 bytes Note1: These registers are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-36: BSEL0: BUFFER SELECT REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 B5TXEN B4TXEN B3TXEN B2TXEN B1TXEN B0TXEN — — bit 7 bit 0 bit 7-2 B5TXEN:B0TXEN: Buffer 5 to Buffer 0 Transmit Enable bit 1 = Buffer is configured in Transmit mode 0 = Buffer is configured in Receive mode bit 1-0 Unimplemented: Read as ‘0’ Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 305

18F8680.book Page 306 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.3.2 Message Acceptance Filters and Masks This subsection describes the message acceptance filters and masks for the CAN receive buffers. Note: These registers are writable in Configuration mode only. REGISTER 23-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, HIGH BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0; Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1. Note1: Registers RXF6SIDH:RXF15SIDH are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER REGISTERS, LOW BYTE [0  n  15](1) R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0; Extended Identifier Filter bits EID20:EID18, if EXIDEN = 1. bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDEN: Extended Identifier Filter Enable bit 1 = Filter will only accept extended ID messages 0 = Filter will only accept standard ID messages Note: In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier Filter bits Note1: Registers RXF6SIDL:RXF15SIDL are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 306  2003-2013 Microchip Technology Inc.

18F8680.book Page 307 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier Filter bits Note1: Registers RXF6EIDH:RXF15EIDH are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier Filter bits Note1: Registers RXF6EIDL:RXF15EIDL are available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, HIGH BYTE [0  n  1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 bit 7-0 SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 307

18F8680.book Page 308 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0  n  1] R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN(1) — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18 bit 4 Unimplemented: Read as ‘0’ bit 3 Mode 0: Unimplemented: Read as ‘0’ Mode 1, 2: EXIDEN: Extended Identifier Filter Enable Mask bit(1) 1 = Messages selected by EXIDEN bit in RXFnSIDL will be accepted 0 = Both standard and extended identifier messages will be accepted Note1: This bit is available in Mode 1 and 2 only. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID17:EID16: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, HIGH BYTE [0  n  1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 bit 7-0 EID15:EID8: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK REGISTERS, LOW BYTE [0  n  1] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-0 EID7:EID0: Extended Identifier Mask bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 308  2003-2013 Microchip Technology Inc.

18F8680.book Page 309 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-45: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLC4 FLC3 FLC2 FLC1 FLC0 bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 FLC4:FLC0: Filter Length Count bits Mode 0: Not used; forced to ‘00000’. Mode 1, 2: 00000-10010 = 0 18 bits are available for standard data byte filter. Actual number of bits used depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if configured as RX buffer) of message being received. If DLC3:DLC0 = 0000No bits will be compared with incoming data bits If DLC3:DLC0 = 0001Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will be compared with the corresponding number of data bits of the incoming message If DLC3:DLC0 = 0010Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0, will be compared with the corresponding number of data bits of the incoming message If DLC3:DLC0 = 0011Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0, will be compared with the corresponding number of data bits of the incoming message Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-46: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0  n  1](1) R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RXFCON0 RXF7EN RXF6EN RXF5EN RXF4EN RXF3EN RXF2EN RXF1EN RXF0EN R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 RXFCON1 RXF15EN RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN RXF8EN bit 7 bit 0 bit 7-0 RXFnEN: Receive Filter n Enable bit 0 = Filter is disabled 1 = Filter is enabled Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 309

18F8680.book Page 310 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER n(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON0 F1BP_3 F1BP_2 F1BP_1 F1BP_0 F0BP_3 F0BP_2 F0BP_1 F0BP_0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 RXFBCON1 F3BP_3 F3BP_2 F3BP_1 F3BP_0 F2BP_3 F2BP_2 F2BP_1 F2BP_0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 RXFBCON2 F5BP_3 F5BP_2 F5BP_1 F5BP_0 F4BP_3 F4BP_2 F4BP_1 F4BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON3 F7BP_3 F7BP_2 F7BP_1 F7BP_0 F6BP_3 F6BP_2 F6BP_1 F6BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON4 F9BP_3 F9BP_2 F9BP_1 F9BP_0 F8BP_3 F8BP_2 F8BP_1 F8BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON5 F11BP_3 F11BP_2 F11BP_1 F11BP_0 F10BP_3 F10BP_2 F10BP_1 F10BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON6 F13BP_3 F13BP_2 F13BP_1 F13BP_0 F12BP_3 F12BP_2 F12BP_1 F12BP_0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFBCON7 F15BP_3 F15BP_2 F15BP_1 F15BP_0 F14BP_3 F14BP_2 F14BP_1 F14BP_0 bit 7 bit 0 bit 7-0 FnBP_3:FnBP_0: Filter n Buffer Pointer Nibble bits 0000 = Filter n is associated with RXB0 0001 = Filter n is associated with RXB1 0010 = Filter n is associated with B0 0011 = Filter n is associated with B1 . . . 0111 = Filter n is associated with B5 1111:1000 = Reserved Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 310  2003-2013 Microchip Technology Inc.

18F8680.book Page 311 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 bit 7-6 FIL3_1:FIL3_0: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_1:FIL2_0: Filter 2 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL1_1:FIL1_0: Filter 1 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL0_1:FIL0_0: Filter 0 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 311

18F8680.book Page 312 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 bit 7-6 FIL7_1:FIL7_0: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_1:FIL6_0: Filter 6 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL5_1:FIL5_0: Filter 5 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL4_1:FIL4_0: Filter 4 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 312  2003-2013 Microchip Technology Inc.

18F8680.book Page 313 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 bit 7-6 FIL11_1:FIL11_0: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_1:FIL10_0: Filter 10 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL9_1:FIL9_0: Filter 9 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL8_1:FIL8_0: Filter 8 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 313

18F8680.book Page 314 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 bit 7-6 FIL15_1:FIL15_0: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_1:FIL14_0: Filter 14 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 3-2 FIL13_1:FIL13_0: Filter 13 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 1-0 FIL12_1:FIL12_0: Filter 12 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 Note1: This register is available in Mode 1 and 2 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 314  2003-2013 Microchip Technology Inc.

18F8680.book Page 315 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.4 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers. Note: These registers are writable in Configuration mode only. REGISTER 23-52: BRGCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Synchronization jump width time = 4 x TQ 10 = Synchronization jump width time = 3 x TQ 01 = Synchronization jump width time = 2 x TQ 00 = Synchronization jump width time = 1 x TQ bit 5-0 BRP5:BRP0: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC . . . 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 315

18F8680.book Page 316 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH2:SEG1PH0: Phase Segment 1 bits 111 = Phase Segment 1 time = 8 x TQ 110 = Phase Segment 1 time = 7 x TQ 101 = Phase Segment 1 time = 6 x TQ 100 = Phase Segment 1 time = 5 x TQ 011 = Phase Segment 1 time = 4 x TQ 010 = Phase Segment 1 time = 3 x TQ 001 = Phase Segment 1 time = 2 x TQ 000 = Phase Segment 1 time = 1 x TQ bit 2-0 PRSEG2:PRSEG0: Propagation Time Select bits 111 = Propagation time = 8 x TQ 110 = Propagation time = 7 x TQ 101 = Propagation time = 6 x TQ 100 = Propagation time = 5 x TQ 011 = Propagation time = 4 x TQ 010 = Propagation time = 3 x TQ 001 = Propagation time = 2 x TQ 000 = Propagation time = 1 x TQ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 316  2003-2013 Microchip Technology Inc.

18F8680.book Page 317 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 WAKDIS WAKFIL — — — SEG2PH2(1) SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits(1) 111 = Phase Segment 2 time = 8 x TQ 110 = Phase Segment 2 time = 7 x TQ 101 = Phase Segment 2 time = 6 x TQ 100 = Phase Segment 2 time = 5 x TQ 011 = Phase Segment 2 time = 4 x TQ 010 = Phase Segment 2 time = 3 x TQ 001 = Phase Segment 2 time = 2 x TQ 000 = Phase Segment 2 time = 1 x TQ Note1: Ignored if SEG2PHTS bit (BRGCON2<7>) is ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 317

18F8680.book Page 318 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller. REGISTER 23-55: CIOCON: CAN I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TX2SRC TX2EN ENDRHI CANCAP — — — — bit 7 bit 0 bit 7 TX2SRC: CANTX2 Pin Data Source bit 1 = CANTX2 pin will output the CAN clock 0 = CANTX2 pin will output CANTX1 bit 6 TX2EN: CANTX2 Pin Enable bit 1 = CANTX2 pin will output CANTX1 or CAN clock as selected by TX2SRC bit 0 = CANTX2 pin will have digital I/O function bit 5 ENDRHI: Enable Drive High bit(1) 1 = CANTX pin will drive VDD when recessive 0 = CANTX pin will be tri-state when recessive bit 4 CANCAP: CAN Message Receive Capture Enable bit 1 = Enable CAN capture, CAN message receive signal replaces input on RC2/CCP1 0 = Disable CAN capture, RC2/CCP1 input to CCP1 module bit 3-0 Unimplemented: Read as ‘0’ Note1: Always set this bit when using differential bus to avoid signal crosstalk in CANTX from other nearby pins. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 318  2003-2013 Microchip Technology Inc.

18F8680.book Page 319 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section9.0 “Interrupts”. They are duplicated here for convenience. REGISTER 23-56: PIR3: PERIPHERAL INTERRUPT FLAG REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF/ TXB1IF(1) TXB0IF(1) RXB1IF/ RXB0IF/ TXBnIF RXBnIF FIFOWMIF bit 7 bit 0 bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus bit 5 ERRIF: CAN bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors bit 4 When CAN is in Mode 0: TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message When CAN is in Mode 1 or 2: TXBnIF: Any Transmit Buffer Interrupt Flag bit 1 = One or more transmit buffers has completed transmission of a message and may be reloaded 0 = No transmit buffer is ready for reload bit 3 TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit(1) 1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message bit 2 TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit(1) 1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message bit 1 When CAN is in Mode 0: RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message When CAN is in Mode 1 or 2: RXBnIF: Any Receive Buffer Interrupt Flag bit 1 = One or more receive buffers has received a new message 0 = No receive buffer has received a new message bit 0 When CAN is in Mode 0: RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIF: FIFO Watermark Interrupt Flag bit 1 = FIFO high watermark is reached 0 = FIFO high watermark is not reached Note1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 319

18F8680.book Page 320 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-57: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE/ TXB1IE(1) TXB0IE(1) RXB1IE/ RXB0IE/ TXBnIE RXBnIE FIFOWMIE bit 7 bit 0 bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt bit 6 WAKIE: CAN bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt bit 5 ERRIE: CAN bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt bit 4 When CAN is in Mode 0: TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt When CAN is in Mode 1 or 2: TXBnIE: CAN Transmit Buffer Interrupts Enable bit 1 = Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0 0 = Disable all transmit buffer interrupts bit 3 TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt bit 2 TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1) 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt bit 1 When CAN is in Mode 0: RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt When CAN is in Mode 1 or 2: RXBnIE: CAN Receive Buffer Interrupts Enable bit 1 = Enable receive buffer interrupt; individual interrupt is enabled by BIE0 0 = Disable all receive buffer interrupts bit 0 When CAN is in Mode 0: RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 320  2003-2013 Microchip Technology Inc.

18F8680.book Page 321 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-58: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP/ TXB1IP(1) TXB0IP(1) RXB1IP/ RXB0IP/ TXBnIP RXBnIP FIFOWMIP bit 7 bit 0 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 When CAN is in Mode 0: TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: TXBnIP: CAN Transmit Buffer Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 2 TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 1 When CAN is in Mode 0: RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1 or 2: RXBnIP: CAN Receive Buffer Interrupts Priority bit 1 = High priority 0 = Low priority bit 0 When CAN is in Mode 0: RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority When CAN is in Mode 1: Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIP: FIFO Watermark Interrupt Priority bit 1 = High priority 0 = Low priority Note1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 321

18F8680.book Page 322 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — TXB2IE TXB1IE TXB0IE — — bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TX2BIE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt is disabled bit 1-0 Unimplemented: Read as ‘0’ Note1: This register is available in Mode 1 and 2 only. 2: TXBIE in PIE3 register must be set to get an interrupt. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGISTER 23-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 B5IE B4IE B3IE B2IE B1IE B0IE RXB1IE RXB0IE bit 7 bit 0 bit 7-2 B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bit(2) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1-0 RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bit(2) 1 = Interrupt is enabled 0 = Interrupt is disabled Note1: This register is available in Mode 1 and 2 only. 2: Either TXBIE or RXBIE in PIE3 register must be set to get an interrupt. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS30491D-page 322  2003-2013 Microchip Technology Inc.

18F8680.book Page 323 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 23-1: CAN CONTROLLER REGISTER MAP Address(1) Name Address Name Address Name Address Name F7Fh SPBRGH(3) F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL F7Eh BAUDCON(3) F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH F7Dh —(4) F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL F7Ch —(4) F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH F7Bh —(4) F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL F7Ah —(4) F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH F79h ECCP1DEL(3) F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL F78h —(4) F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH F6Fh CANCON F4Fh CANCON_RO1(2) F2Fh CANCON_RO3(2) F0Fh RXF3EIDL F6Eh CANSTAT F4Eh CANSTAT_RO1(2) F2Eh CANSTAT_RO3(2) F0Eh RXF3EIDH F6Dh RXB0D7 F4Dh TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’.  2003-2013 Microchip Technology Inc. DS30491D-page 323

18F8680.book Page 324 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name EFFh —(4) EDFh —(4) EBFh —(4) E9Fh —(4) EFEh —(4) EDEh —(4) EBEh —(4) E9Eh —(4) EFDh —(4) EDDh —(4) EBDh —(4) E9Dh —(4) EFCh —(4) EDCh —(4) EBCh —(4) E9Ch —(4) EFBh —(4) EDBh —(4) EBBh —(4) E9Bh —(4) EFAh —(4) EDAh —(4) EBAh —(4) E9Ah —(4) EF9h —(4) ED9h —(4) EB9h —(4) E99h —(4) EF8h —(4) ED8h —(4) EB8h —(4) E98h —(4) EF7h —(4) ED7h —(4) EB7h —(4) E97h —(4) EF6h —(4) ED6h —(4) EB6h —(4) E96h —(4) EF5h —(4) ED5h —(4) EB5h —(4) E95h —(4) EF4h —(4) ED4h —(4) EB4h —(4) E94h —(4) EF3h —(4) ED3h —(4) EB3h —(4) E93h —(4) EF2h —(4) ED2h —(4) EB2h —(4) E92h —(4) EF1h —(4) ED1h —(4) EB1h —(4) E91h —(4) EF0h —(4) ED0h —(4) EB0h —(4) E90h —(4) EEFh —(4) ECFh —(4) EAFh —(4) E8Fh —(4) EEEh —(4) ECEh —(4) EAEh —(4) E8Eh —(4) EEDh —(4) ECDh —(4) EADh —(4) E8Dh —(4) EECh —(4) ECCh —(4) EACh —(4) E8Ch —(4) EEBh —(4) ECBh —(4) EABh —(4) E8Bh —(4) EEAh —(4) ECAh —(4) EAAh —(4) E8Ah —(4) EE9h —(4) EC9h —(4) EA9h —(4) E89h —(4) EE8h —(4) EC8h —(4) EA8h —(4) E88h —(4) EE7h —(4) EC7h —(4) EA7h —(4) E87h —(4) EE6h —(4) EC6h —(4) EA6h —(4) E86h —(4) EE5h —(4) EC5h —(4) EA5h —(4) E85h —(4) EE4h —(4) EC4h —(4) EA4h —(4) E84h —(4) EE3h —(4) EC3h —(4) EA3h —(4) E83h —(4) EE2h —(4) EC2h —(4) EA2h —(4) E82h —(4) EE1h —(4) EC1h —(4) EA1h —(4) E81h —(4) EE0h —(4) EC0h —(4) EA0h —(4) E80h —(4) Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. DS30491D-page 324  2003-2013 Microchip Technology Inc.

18F8680.book Page 325 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name E7Fh CANCON_RO4(2) E5Fh CANCON_RO6(2) E3Fh CANCON_RO8(2) E1Fh —(4) E7Eh CANSTAT_RO4(2) E5Eh CANSTAT_RO6(2) E3Eh CANSTAT_RO8(2) E1Eh —(4) E7Dh B5D7 E5Dh B3D7 E3Dh B1D7 E1Dh —(4) E7Ch B5D6 E5Ch B3D6 E3Ch B1D6 E1Ch —(4) E7Bh B5D5 E5Bh B3D5 E3Bh B1D5 E1Bh —(4) E7Ah B5D4 E5Ah B3D4 E3Ah B1D4 E1Ah —(4) E79h B5D3 E59h B3D3 E39h B1D3 E19h —(4) E78h B5D2 E58h B3D2 E38h B1D2 E18h —(4) E77h B5D1 E57h B3D1 E37h B1D1 E17h —(4) E76h B5D0 E56h B3D0 E36h B1D0 E16h —(4) E75h B5DLC E55h B3DLC E35h B1DLC E15h —(4) E74h B5EIDL E54h B3EIDL E34h B1EIDL E14h —(4) E73h B5EIDH E53h B3EIDH E33h B1EIDH E13h —(4) E72h B5SIDL E52h B3SIDL E32h B1SIDL E12h —(4) E71h B5SIDH E51h B3SIDH E31h B1SIDH E11h —(4) E70h B5CON E50h B3CON E30h B1CON E10h —(4) E6Fh CANCON_RO5 E4Fh CANCON_RO7 E2Fh CANCON_RO9 E0Fh —(4) E6Eh CANSTAT_RO5 E4Eh CANSTAT_RO7 E2Eh CANSTAT_RO9 E0Eh —(4) E6Dh B4D7 E4Dh B2D7 E2Dh B0D7 E0Dh —(4) E6Ch B4D6 E4Ch B2D6 E2Ch B0D6 E0Ch —(4) E6Bh B4D5 E4Bh B2D5 E2Bh B0D5 E0Bh —(4) E6Ah B4D4 E4Ah B2D4 E2Ah B0D4 E0Ah —(4) E69h B4D3 E49h B2D3 E29h B0D3 E09h —(4) E68h B4D2 E48h B2D2 E28h B0D2 E08h —(4) E67h B4D1 E47h B2D1 E27h B0D1 E07h —(4) E66h B4D0 E46h B2D0 E26h B0D0 E06h —(4) E65h B4DLC E45h B2DLC E25h B0DLC E05h —(4) E64h B4EIDL E44h B2EIDL E24h B0EIDL E04h —(4) E63h B4EIDH E43h B2EIDH E23h B0EIDH E03h —(4) E62h B4SIDL E42h B2SIDL E22h B0SIDL E02h —(4) E61h B4SIDH E41h B2SIDH E21h B0SIDH E01h —(4) E60h B4CON E40h B2CON E20h B0CON E00h —(4) Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’.  2003-2013 Microchip Technology Inc. DS30491D-page 325

18F8680.book Page 326 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name Address Name Address Name Address Name DFFh —(4) DDFh —(4) DBFh —(4) D9Fh —(4) DFEh —(4) DDEh —(4) DBEh —(4) D9Eh —(4) DFDh —(4) DDDh —(4) DBDh —(4) D9Dh —(4) DFCh TXBIE DDCh —(4) DBCh —(4) D9Ch —(4) DFBh —(4) DDBh —(4) DBBh —(4) D9Bh —(4) DFAh BIE0 DDAh —(4) DBAh —(4) D9Ah —(4) DF9h —(4) DD9h —(4) DB9h —(4) D99h —(4) DF8h BSEL0 DD8h SDFLC DB8h —(4) D98h —(4) DF7h —(4) DD7h —(4) DB7h —(4) D97h —(4) DF6h —(4) DD6h —(4) DB6h —(4) D96h —(4) DF5h —(4) DD5h RXFCON1 DB5h —(4) D95h —(4) DF4h —(4) DD4h RXFCON0 DB4h —(4) D94h —(4) DF3h MSEL3 DD3h —(4) DB3h —(4) D93h RXF15EIDL DF2h MSEL2 DD2h —(4) DB2h —(4) D92h RXF15EIDH DF1h MSEL1 DD1h —(4) DB1h —(4) D91h RXF15SIDL DF0h MSEL0 DD0h —(4) DB0h —(4) D90h RXF15SIDH DEFh —(4) DCFh —(4) DAFh —(4) D8Fh —(4) DEEh —(4) DCEh —(4) DAEh —(4) D8Eh —(4) DEDh —(4) DCDh —(4) DADh —(4) D8Dh —(4) DECh —(4) DCCh —(4) DACh —(4) D8Ch —(4) DEBh —(4) DCBh —(4) DABh —(4) D8Bh RXF14EIDL DEAh —(4) DCAh —(4) DAAh —(4) D8Ah RXF14EIDH DE9h —(4) DC9h —(4) DA9h —(4) D89h RXF14SIDL DE8h —(4) DC8h —(4) DA8h —(4) D88h RXF14SIDH DE7h RXFBCON7 DC7h —(4) DA7h —(4) D87h RXF13EIDL DE6h RXFBCON6 DC6h —(4) DA6h —(4) D86h RXF13EIDH DE5h RXFBCON5 DC5h —(4) DA5h —(4) D85h RXF13SIDL DE4h RXFBCON4 DC4h —(4) DA4h —(4) D84h RXF13SIDH DE3h RXFBCON3 DC3h —(4) DA3h —(4) D83h RXF12EIDL DE2h RXFBCON2 DC2h —(4) DA2h —(4) D82h RXF12EIDH DE1h RXFBCON1 DC1h —(4) DA1h —(4) D81h RXF12SIDL DE0h RXFBCON0 DC0h —(4) DA0h —(4) D80h RXF12SIDH Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’. DS30491D-page 326  2003-2013 Microchip Technology Inc.

18F8680.book Page 327 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 23-1: CAN CONTROLLER REGISTER MAP (CONTINUED) Address(1) Name D7Fh —(4) D7Eh —(4) D7Dh —(4) D7Ch —(4) D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL D70h RXF9SIDH D6Fh —(4) D6Eh —(4) D6Dh —(4) D6Ch —(4) D6Bh RXF8EIDL D6Ah RXF8EIDH D69h RXF8SIDL D68h RXF8SIDH D67h RXF7EIDL D66h RXF7EIDH D65h RXF7SIDL D64h RXF7SIDH D63h RXF6EIDL D62h RXF6EIDH D61h RXF6SIDL D60h RXF6SIDH Note 1: Shaded registers are available in Access Bank low area while the rest are available in Bank 15. 2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the controller register due to the Microchip header file requirement. 3: These registers are not CAN registers. 4: Unimplemented registers are read as ‘0’.  2003-2013 Microchip Technology Inc. DS30491D-page 327

18F8680.book Page 328 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.3 CAN Modes of Operation In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the inter- The PIC18F6585/8585/6680/8680 has six main modes rupt flags remain unchanged. The programmer will of operation: have access to configuration registers that are access • Configuration mode restricted in other modes. • Disable mode 23.3.2 DISABLE MODE • Normal Operation mode In Disable mode, the module will not transmit or • Listen Only mode receive. The module has the ability to set the WAKIF bit • Loopback mode due to bus activity; however, any pending interrupts will • Error Recognition mode remain and the error counters will retain their value. All modes, except Error Recognition, are requested by If REQOP<2:0> is set to ‘001’, the module will enter the setting the REQOP bits (CANCON<7:5>); Error Recog- Module Disable mode. This mode is similar to disabling nition is requested through the RXM bits of the Receive other peripheral modules by turning off the module Buffer register(s). Entry into a mode is Acknowledged enables. This causes the module internal clock to stop by monitoring the OPMODE bits. unless the module is active (i.e., receiving or transmit- When changing modes, the mode will not actually ting a message). If the module is active, the module will change until all pending message transmissions are wait for 11 recessive bits on the CAN bus, detect that complete. Because of this, the user must verify that the condition as an Idle bus, then accept the module device has actually changed into the requested mode disable command. OPMODE<2:0> = 001 indicates before further operations are executed. whether the module successfully went into Module Disable mode. 23.3.1 CONFIGURATION MODE The WAKIE interrupt is the only module interrupt that is The CAN module must be initialized before the still active in the Module Disable mode. If wake-up from activation. This is only possible if the module is in the CAN bus activity is required, the CAN module must be Configuration mode. The Configuration mode is put into Disable mode before putting the core to Sleep. requested by setting the REQOP2 bit. Only when the If the WAKDIS is cleared and WAKIE is set, the proces- status bit, OPMODE2, has a high level can the initial- sor will receive an interrupt whenever the module ization be performed. Once in Configuration mode, detects recessive to dominant transition. On wake-up, registers such as baud rate control, acceptance mask/ the module will automatically be set to the previous filter and ECAN mode selection can be modified. A new mode of operation. For example, if the module was ECAN mode selection does not take into effect until switched from Normal to Disable mode on bus activity Configuration mode is exited. The module is activated wake-up, the module will automatically enter into by setting the REQOP control bits to zero. Normal mode and the first message that caused the module to wake-up is lost. The module will not gener- The module will protect the user from accidentally ate any error frame. Firmware logic must detect this violating the CAN protocol through programming condition and make sure that retransmission is errors. All registers which control the configuration of requested. If the processor receives a wake-up inter- the module can not be modified while the module is rupt while it is sleeping, more than one message may online. The CAN module will not be allowed to enter the get lost. The actual number of messages lost would Configuration mode while a transmission or reception depend on the processor oscillator start-up time and is taking place. The CAN module will also not be incoming message bit rate. allowed, if the CANRX pin is low (i.e., the CAN bus is busy). The CAN module waits for 11 recessive bits on The I/O pins will revert to normal I/O function when the the CAN bus (bus Idle condition) before switching to module is in the Module Disable mode. Configuration mode. The Configuration mode serves Note: CAN module must be put in Disable or as a lock to protect the following registers: Configuration mode prior to putting the • Configuration registers processor to sleep. Failure to do that may • Functional Mode Selection registers put the CAN module in indeterminate • Bit Timing registers state. • Identifier Acceptance Filter registers • Identifier Acceptance Mask registers • Filter and Mask Control registers • Mask Selection registers DS30491D-page 328  2003-2013 Microchip Technology Inc.

18F8680.book Page 329 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.3.3 NORMAL MODE 23.3.6 ERROR RECOGNITION MODE This is the standard operating mode of the The module can be set to ignore all errors and receive PIC18F6585/8585/6680/8680 devices. In this mode, any message. In functional Mode 0, the Error Recogni- the device actively monitors all bus messages and gen- tion mode is activated by setting the RXM<1:0> bits in erates Acknowledge bits, error frames, etc. This is also the RXBnCON registers to ‘11’. In this mode, the data the only mode in which the PIC18F6585/8585/6680/ which is in the message assembly buffer until the error 8680 devices will transmit messages over the CAN time, is copied in the receive buffer and can be read via bus. the CPU interface. 23.3.4 LISTEN ONLY MODE 23.4 CAN Module Functional Modes Listen Only mode provides a means for the In addition to CAN modes of operation, the ECAN PIC18F6585/8585/6680/8680 devices to receive all module offers a total of three functional modes. Each of messages, including messages with errors. This mode these modes are identified as Mode 0, Mode 1 and can be used for bus monitor applications or for Mode 2. detecting the baud rate in ‘hot plugging’ situations. For auto-baud detection, it is necessary that there are at 23.4.1 MODE 0 – LEGACY MODE least two other nodes which are communicating with each other. The baud rate can be detected empirically Mode 0 is designed to be fully compatible with CAN by testing different values until valid messages are modules used in PIC18CXX8 and PIC18FXX8 devices. received. The Listen Only mode is a silent mode, This is the default mode of operation on all Reset meaning no messages will be transmitted while in this conditions. As a result, module code written for the state, including error flags or Acknowledge signals. The PIC18XX8 CAN module may be used on the ECAN filters and masks can be used to allow only particular module without any code changes. messages to be loaded into the receive registers, or the The following is the list of resources available in Mode 0: filter masks can be set to all zeros to allow a message • Three transmit buffers: TXB0, TXB1 and TXB2 with any identifier to pass. The error counters are reset and deactivated in this state. The Listen Only mode is • Two receive buffers: RXB0 and RXB1 activated by setting the mode request bits in the • Two acceptance masks, one for each receive CANCON register. buffer: RXM0, RXM1 • Six acceptance filters, 2 for RXB0 and 4 for RXB1: 23.3.5 LOOPBACK MODE RXF0, RXF1, RXF2, RXF3, RXF4, RXF5 This mode will allow internal transmission of messages 23.4.2 MODE 1 – ENHANCED LEGACY from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus. This MODE mode can be used in system development and testing. Mode 1 is similar to Mode 0, with the exception that In this mode, the ACK bit is ignored and the device will more resources are available in Mode 1. There are allow incoming messages from itself, just as if they 16acceptance filters and two Acceptance Mask regis- were coming from another node. The Loopback mode ters. Acceptance Filter 15 can be used as either an is a silent mode, meaning no messages will be trans- acceptance filter or an Acceptance Mask register. In mitted while in this state, including error flags or addition to three transmit and two receive buffers, there Acknowledge signals. The CANTX pin will revert to port are six more message buffers. One or more of these I/O while the device is in this mode. The filters and additional buffers can be programmed as transmit or masks can be used to allow only particular messages receive buffers. These additional buffers can also be to be loaded into the receive registers. The masks can programmed to automatically handle RTR messages. be set to all zeros to provide a mode that accepts all Fourteen of 16 Acceptance Filter registers can be messages. The Loopback mode is activated by setting dynamically associated to any receive buffer and the mode request bits in the CANCON register. Acceptance Mask register. This capability can be used to associate more than one filter to any one buffer.  2003-2013 Microchip Technology Inc. DS30491D-page 329

18F8680.book Page 330 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 When a receive buffer is programmed to use standard 23.5 CAN Message Buffers identifier messages, part of the full Acceptance Filter register can be used as data byte filter. The length of 23.5.1 DEDICATED TRANSMIT BUFFERS data byte filter is programmable from 0 to 18 bits. This The PIC18F6585/8585/6680/8680 devices implement functionality simplifies implementation of high-level three dedicated transmit buffers – TXB0, TXB1 and protocols, such as DeviceNet. TXB2. Each of these buffers occupies 14 bytes of The following is the list of resources available in Mode 1: SRAM and are mapped into the SFR memory map. • Three transmit buffers: TXB0, TXB1 and TXB2 These are the only transmit buffers available in Mode0. Mode 1 and 2 may access these and other • Two receive buffers: RXB0 and RXB1 additional buffers. • Six buffers programmable as TX or RX: B0-B5 Each transmit buffer contains one Control register • Automatic RTR handling on B0-B5 (TXBnCON), four Identifier registers (TXBnSIDL, • Sixteen dynamically assigned acceptance filters: TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length RXF0-RXF15 Count register (TXBnDLC) and eight Data Byte • Two dedicated Acceptance Mask registers; registers (TXBnDm). RXF15 programmable as third mask: RXM0-RXM1, RXF15 23.5.2 DEDICATED RECEIVE BUFFERS • Programmable data filter on standard identifier The PIC18F6585/8585/6680/8680 devices implement messages: SDFLC two dedicated receive buffers – RXB0 and RXB1. Each of these buffers occupies 14 bytes of SRAM and are 23.4.3 MODE 2 – ENHANCED FIFO MODE mapped into SFR memory map. These are the only In Mode 2, two or more receive buffers are used to form receive buffers available in Mode 0. Mode 1 and 2 may the receive FIFO (First In First Out) buffer. There is no access these and other additional buffers. one-to-one relation between the receive buffer and Each receive buffer contains one Control register Acceptance Filter registers. Any filter that is enabled (RXBnCON), four Identifier registers (RXBnSIDL, and linked to any FIFO receive buffer can generate RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length acceptance and cause FIFO to be updated. Count register (RXBnDLC) and eight Data Byte FIFO length is user programmable, from 2-8 buffers registers (RXBnDm). deep. FIFO length is determined by the very first There is also a separate Message Assembly Buffer programmable buffer that is configured as a transmit (MAB) which acts as an additional receive buffer. MAB buffer. For example, if Buffer 2 (B2) is programmed as is always committed to receiving the next message a transmit buffer, FIFO consists of RXB0, RXB1, B0 from the bus and is not directly accessible to user firm- and B1 – creating a FIFO length of 4. If all programma- ware. The MAB assembles all incoming messages one ble buffers are configured as receive buffers, FIFO will by one. A message is transferred to appropriate have the maximum length of 8. receive buffers only if the corresponding acceptance The following is the list of resources available in Mode 2: filter criteria is met. • Three transmit buffers: TXB0, TXB1 and TXB2 • Two receive buffers: RXB0 and RXB1 • Six buffers programmable as TX or RX; receive buffers form FIFO: B0-B5 • Automatic RTR handling on B0-B5 • Sixteen acceptance filters: RXF0-RXF15 • Two dedicated Acceptance Mask registers; RXF15 programmable as third mask: RXM0-RXM1, RXF15 • Programmable data filter on standard identifier messages: SDFLC, useful for DeviceNet protocol DS30491D-page 330  2003-2013 Microchip Technology Inc.

18F8680.book Page 331 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.5.3 PROGRAMMABLE TRANSMIT/ The following outlines the steps required to RECEIVE BUFFERS automatically handle RTR messages: The ECAN module implements six new buffers: B0-B5. 1. Set buffer to Transmit mode by setting TXnEN These buffers are individually programmable as either bit to ‘1’ in BSEL0 register. transmit or receive buffers. These buffers are available 2. At least one acceptance filter must be associ- only in Mode 1 and 2. As with dedicated transmit and ated with this buffer and preloaded with receive buffers, each of these programmable buffers expected RTR identifier. occupies 14 bytes of SRAM and are mapped into SFR 3. Bit RTREN in BnCON register must be set to ‘1’. memory map. 4. Buffer must be preloaded with the data to be Each buffer contains one Control register (BnCON), sent as a RTR response. four Identifier registers (BnSIDL, BnSIDH, BnEIDL, Normally, user firmware will keep Buffer Data registers BnEIDH), one Data Length Count register (BnDLC) up to date. If firmware attempts to update buffer while and eight Data Byte registers (BnDm). Each of these an automatic RTR response is in process of registers contains two sets of control bits. Depending transmission, all writes to buffers are ignored. on whether the buffer is configured as transmit or receive, one would use the corresponding control bit 23.6 CAN Message Transmission set. By default, all buffers are configured as receive buffers. Each buffer can be individually configured as 23.6.1 INITIATING TRANSMISSION transmit or receive buffers by setting the corresponding TXENn bit in the BSEL0 register. For the MCU to have write access to the message buffer, the TXREQ bit must be clear, indicating that the When configured as transmit buffers, user firmware message buffer is clear of any pending message to be may access transmit buffers in any order similar to transmitted. At a minimum, the SIDH, SIDL, and DLC accessing dedicated transmit buffers. In receive config- registers must be loaded. If data bytes are present in uration, with Mode 1 enabled, user firmware may also the message, the data registers must also be loaded. If access receive buffers in any order required. But in the message is to use extended identifiers, the Mode 2, all receive buffers are combined to form a sin- EIDH:EIDL registers must also be loaded and the gle FIFO. Actual FIFO length is programmable by user EXIDE bit set. firmware. Access to FIFO must be done through the FIFO pointer bits (FP<4:0>) in the CANCON register. It To initiate message transmission, the TXREQ bit must must be noted that there is no hardware protection be set for each buffer to be transmitted. When TXREQ against out of order FIFO reads. is set, the TXABT, TXLARB and TXERR bits will be cleared. To successfully complete the transmission, 23.5.4 PROGRAMMABLE AUTO-RTR there must be at least one node with matching baud BUFFERS rate on the network. In Mode 1 and 2, any of six programmable transmit/ Setting the TXREQ bit does not initiate a message receive buffers may be programmed to automatically transmission, it merely flags a message buffer as ready respond to predefined RTR messages without user for transmission. Transmission will start when the firmware intervention. Automatic RTR handling is device detects that the bus is available. The device will enabled by setting the TXnEN bit in the BSEL0 register then begin transmission of the highest priority message and the RTREN bit in the BnCON register. After this that is ready. setup, when an RTR request is received, the TXREQ When the transmission has completed successfully, the bit is automatically set and current buffer content is TXREQ bit will be cleared, the TXBnIF bit will be set, and automatically queued for transmission as a RTR an interrupt will be generated if the TXBnIE bit is set. response. As with all transmit buffers, once the TXREQ If the message transmission fails, the TXREQ will bit is set, buffer registers become read-only and any remain set, indicating that the message is still pending writes to them will be ignored. for transmission and one of the following condition flags will be set. If the message started to transmit but encountered an error condition, the TXERR and the IRXIF bits will be set and an interrupt will be generated. If the message lost arbitration, the TXLARB bit will be set.  2003-2013 Microchip Technology Inc. DS30491D-page 331

18F8680.book Page 332 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.6.2 ABORTING TRANSMISSION Once an abort is requested by setting ABAT or TXABT bits, it cannot be cleared to cancel the abort request. The MCU can request to abort a message by clearing Only CAN module hardware or a POR condition can the TXREQ bit associated with the corresponding mes- clear it. sage buffer (TXBnCON<3> or BnCON<3>). Setting the ABAT bit (CANCON<4>) will request an abort of all 23.6.3 TRANSMIT PRIORITY pending messages. If the message has not yet started transmission or if the message started but is inter- Transmit priority is a prioritization within the rupted by loss of arbitration or an error, the abort will be PIC18F6585/8585/6680/8680 devices of the pending processed. The abort is indicated when the module transmittable messages. This is independent from and sets the TXABT bit for the corresponding buffer not related to any prioritization implicit in the message (TXBnCON<6> or BnCON<6>). If the message has arbitration scheme built into the CAN protocol. Prior to started to transmit, it will attempt to transmit the current sending the SOF, the priority of all buffers that are message fully. If the current message is transmitted queued for transmission is compared. The transmit fully and is not lost to arbitration or an error, the TXABT buffer with the highest priority will be sent first. If more bit will not be set because the message was transmit- than one buffer has the same priority setting, the mes- ted successfully. Likewise, if a message is being sage is transmitted in the order of TXB2, TXB1, TXB0, transmitted during an abort request and the message is B5, B4, B3, B2, B1, B0. There are four levels of transmit lost to arbitration or an error, the message will not be priority. If TXP bits for a particular message buffer are retransmitted and the TXABT bit will be set, indicating set to ‘11’, that buffer has the highest possible priority. that the message was successfully aborted. If TXP bits for a particular message buffer are ‘00’, that buffer has the lowest possible priority. FIGURE 23-2: TRANSMIT BUFFERS TXB0 TXB1 TXB2 TXB3-TXB8 E E E E TXREQ TXABT TXLARB TXERR TXB0IF MESSAG TXREQ TXABT TXLARB TXERR TXB1IF MESSAG TXREQ TXABT TXLARB TXERR TXB2IF MESSAG TXREQ TXABT TXLARB TXERR TXB2IF MESSAG Message Queue Control Transmit Byte Sequencer DS30491D-page 332  2003-2013 Microchip Technology Inc.

18F8680.book Page 333 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.7 Message Reception Each receive buffer contains RXM bits to set special Receive modes. In Mode 0, RXM<1:0> bits in 23.7.1 RECEIVING A MESSAGE RXBnCON define a total of four Receive modes. In Mode 1 and 2, RXM1 bit in combination with the EXID Of all receive buffers, the MAB is always committed to mask and filter bit define the same four Receive receiving the next message from the bus. The MCU modes. Normally, these bits are set to ‘00’ to enable can access one buffer while the other buffer is available reception of all valid messages as determined by the for message reception, or holding a previously received appropriate acceptance filters. In this case, the deter- message. mination of whether or not to receive standard or Note: The entire contents of the MAB are moved extended messages is determined by the EXIDE bit in into the receive buffer once a message is the Acceptance Filter register. In Mode 0, if the RXM accepted. This means that regardless of bits are set to ‘01’ or ‘10’, the receiver will accept only the type of identifier (standard or messages with standard or extended identifiers, extended) and the number of data bytes respectively. If an acceptance filter has the EXIDE bit received, the entire receive buffer is over- set such that it does not correspond with the RXM written with the MAB contents. Therefore, mode, that acceptance filter is rendered useless. In the contents of all registers in the buffer Mode 1 and 2, setting EXID in the SIDL Mask register must be assumed to have been modified will ensure that only standard or extended identifiers when any message is received. are received. These two modes of RXM bits can be used in systems where it is known that only standard or When a message is moved into either of the receive extended messages will be on the bus. If the RXM bits buffers, the associated RXFUL bit is set. This bit must are set to ‘11’ (RXM1 = 1 in Mode 1 and 2), the buffer be cleared by the MCU when it has completed process- will receive all messages regardless of the values of ing the message in the buffer in order to allow a new the acceptance filters. Also, if a message has an error message to be received into the buffer. This bit before the end of frame, that portion of the message provides a positive lockout to ensure that the firmware assembled in the MAB before the error frame, will be has finished with the message before the module loaded into the buffer. This mode may serve as a valu- attempts to load a new message into the receive buffer. able debugging tool for a given CAN network. It should If the receive interrupt is enabled, an interrupt will be not be used in an actual system environment as the generated to indicate that a valid message has been actual system will always have some bus errors and all received. nodes on the bus are expected to ignore them. Once a message is loaded into any matching buffer, In Mode 1 and 2, when a programmable buffer is user firmware may determine exactly what filter caused configured as a transmit buffer and one or more accep- this reception by checking the filter hit bits in the tance filters are associated with it, all incoming mes- RXBnCON or BnCON registers. In Mode 0, FILHIT<3:0> sages matching this acceptance filter criteria will be of RXBnCON serve as filter hit bits. In Mode 1 and 2, discarded. To avoid this scenario, user firmware must FILHIT<4:0> of BnCON serve as filter hit bits. The same make sure that there are no acceptance filters associ- registers also indicate whether the current message is ated with a buffer configured as a transmit buffer. RTR frame or not. A received message is considered a standard identifier message if the EXID bit in RXBnSIDL 23.7.2 RECEIVE PRIORITY or the BnSIDL register is cleared. Conversely, a set EXID bit indicates an extended identifier message. If the When in Mode 0, RXB0 is the higher priority buffer and received message is a standard identifier message, user has two message acceptance filters associated with it. firmware needs to read the SIDL and SIDH registers. In RXB1 is the lower priority buffer and has four acceptance the case of an extended identifier message, firmware filters associated with it. The lower number of acceptance should read the SIDL, SIDH, EIDL and EIDH registers. If filters makes the match on RXB0 more restrictive and the RXBnDLC or BnDLC register contain non-zero data implies a higher priority for that buffer. Additionally, the count, user firmware should also read the corresponding RXB0CON register can be configured such that if RXB0 number of data bytes by accessing the RXBnDm or contains a valid message and another valid message is BnDm registers. When a received message is RTR and received, an overflow error will not occur and the new if the current buffer is not configured for automatic RTR message will be moved into RXB1 regardless of the handling, user firmware must take appropriate action acceptance criteria of RXB1. There are also two and respond manually. programmable acceptance filter masks available, one for each receive buffer (see Section 4.5).  2003-2013 Microchip Technology Inc. DS30491D-page 333

18F8680.book Page 334 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 In Mode 1 and 2, there are a total of 16 acceptance fil- 23.7.4 TIME-STAMPING ters available and each can be dynamically assigned to The CAN module can be programmed to generate a any of the receive buffers. A buffer with a lower number time-stamp for every message that is received. When has higher priority. Given this, if an incoming message enabled, the module generates a capture signal for matches with two or more receive buffer acceptance CCP1, which in turn captures the value of either Timer1 criteria, the buffer with the lower number will be loaded or Timer3. This value can be used as the message with that message. time-stamp. 23.7.3 ENHANCED FIFO MODE To use the time-stamp capability, the CANCAP bit (CIOCAN<4>) must be set. This replaces the capture When configured for Mode 2, two of the dedicated input for CCP1 with the signal generated from the CAN receive buffers, in combination with one or more pro- module. In addition, CCP1CON<3:0> must be set to grammable transmit/receive buffers, are used to create ‘0011’ to enable the CCP special event trigger for CAN a maximum of 8 buffers deep FIFO (First In First Out) events. buffer. In this mode, there is no direct correlation between filters and receive buffer registers. Any filter 23.8 Message Acceptance Filters that has been enabled can generate an acceptance. When a message has been accepted, it is stored in the and Masks next available receive buffer register and an internal The message acceptance filters and masks are used to write pointer is incremented. The FIFO can be a maxi- determine if a message in the message assembly mum of 8 buffers deep. The entire FIFO must consist of buffer should be loaded into any of the receive buffers. contiguous receive buffers. The FIFO head begins at Once a valid message has been received into the MAB, RXB0 buffer and its tail spans toward B5. The maxi- the identifier fields of the message are compared to the mum length of the FIFO is limited by the presence or filter values. If there is a match, that message will be absence of the first transmit buffer starting from B0. If a loaded into the appropriate receive buffer. The filter buffer is configured as a transmit buffer, the FIFO masks are used to determine which bits in the identifier length is reduced accordingly. For instance, if B3 is are examined with the filters. A truth table is shown configured as transmit buffer, the actual FIFO will con- below in Table23-2 that indicates how each bit in the sist of RXB0, RXB1, B0, B1 and B2, a total of 5 buffers. identifier is compared to the masks and filters to deter- If B0 is configured as a transmit buffer, the FIFO length mine if a message should be loaded into a receive will be 2. If none of the programmable buffers are con- buffer. The mask essentially determines which bits to figured as a transmit buffer, the FIFO will be 8 buffers apply the acceptance filters to. If any mask bit is set to deep. A system that requires more transmit buffers a zero, then that bit will automatically be accepted should try to locate transmit buffers at the very end of regardless of the filter bit. B0-B5 buffers to maximize available FIFO length. When a message is received in FIFO mode, the Inter- TABLE 23-2: FILTER/MASK TRUTH TABLE rupt Flag Code bits (EICODE<4:0>) in the CANSTAT register will have a value of ‘10000’, indicating the Mask Filter Message Accept or FIFO has received a message. FIFO pointer bits bit n bit n Identifier Reject FP<3:0> in the CANCON register point to the buffer bit n001 bit n that contains data not yet read. The FIFO pointer bits, 0 x x Accept in this sense, serve as the FIFO read pointer. The user 1 0 0 Accept should use FP bits and read corresponding buffer data. When receive data is no longer needed, the RXFUL bit 1 0 1 Reject in the current buffer must be cleared, causing FP<3:0> 1 1 0 Reject to be updated by the module. 1 1 1 Accept To determine whether FIFO is empty or not, the user Legend: x = don’t care may use FP<3:0> bits to access RXFUL bit in the cur- rent buffer. If RXFUL is cleared, the FIFO is considered In Mode 0, acceptance filters RXF0 and RXF1 and filter to be empty. If it is set, the FIFO may contain one or mask RXM0 are associated with RXB0. Filters RXF2, more messages. In Mode 2, the module also provides RXF3, RXF4 and RXF5 and mask RXM1 are a bit called FIFO High Water Mark (FIFOWM) in the associated with RXB1. ECANCON register. This bit can be used to cause an interrupt whenever the FIFO contains only one or four empty buffers. The FIFO high water mark interrupt can serve as an early warning to a full FIFO condition. DS30491D-page 334  2003-2013 Microchip Technology Inc.

18F8680.book Page 335 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 In Mode 1 and 2, there are an additional 10 acceptance The coding of the RXB0DBEN bit enables these three filters, RXF6-RXF15, creating a total of 16 available bits to be used similarly to the FILHIT bits and to distin- filters. RXF15 can be used either as an acceptance guish a hit on filter RXF0 and RXF1, in either RXB0 or filter or acceptance mask register. Each of these after a rollover into RXB1. acceptance filters can be individually enabled or • 111 = Acceptance Filter 1 (RXF1) disabled by setting or clearing RXFENn bit in the • 110 = Acceptance Filter 0 (RXF0) RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive • 001 = Acceptance Filter 1 (RXF1) buffers. Actual association is made by setting appropri- • 000 = Acceptance Filter 0 ate bits in the RXFBCONn register. Each RXFBCONn If the RXB0DBEN bit is clear, there are six codes cor- register contains a nibble for each filter. This nibble can responding to the six filters. If the RXB0DBEN bit is set, be used to associate a specific filter to any of available there are six codes corresponding to the six filters plus receive buffers. User firmware may associate more two additional codes corresponding to RXF0 and RXF1 than one filter to any one specific receive buffer. filters that rollover into RXB1. In addition to dynamic filter to buffer association, in In Mode 1 and 2, each buffer control register contains Mode 1 and 2, each filter can also be dynamically asso- 5 bits of filter hit bits FILHIT<4:0>. A binary value of ‘0’ ciated to available acceptance mask registers. FILn_m indicates a hit from RXF0 and 15 indicates RXF15. bits in the MSELn register can be used to link a specific If more than one acceptance filter matches, the FILHIT acceptance filter to an acceptance mask register. As bits will encode the binary value of the lowest with filter to buffer association, one can also associate numbered filter that matched. In other words, if filter more than one mask to a specific acceptance filter. RXF2 and filter RXF4 match, FILHIT will be loaded with When a filter matches and a message is loaded into the the value for RXF2. This essentially prioritizes the receive buffer, the filter number that enabled the acceptance filters with a lower number filter having message reception is loaded into the FILHIT bit(s). In higher priority. Messages are compared to filters in Mode0 for RXB1, the RXB1CON register contains the ascending order of filter number. FILHIT<2:0> bits. They are coded as follows: The mask and filter registers can only be modified • 101 = Acceptance Filter 5 (RXF5) when the PIC18F6585/8585/6680/8680 devices are in • 100 = Acceptance Filter 4 (RXF4) Configuration mode. • 011 = Acceptance Filter 3 (RXF3) • 010 = Acceptance Filter 2 (RXF2) • 001 = Acceptance Filter 1 (RXF1) • 000 = Acceptance Filter 0 (RXF0) Note: ‘000’ and ‘001’ can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to rollover into RXB1. FIGURE 23-3: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXFn0 RXMn0 RXFn1 RXMn1 RxRqst RXFnn RXMnn Message Assembly Buffer Identifier  2003-2013 Microchip Technology Inc. DS30491D-page 335

18F8680.book Page 336 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.9 Baud Rate Setting The Nominal Bit Time is defined as: All nodes on a given CAN bus must have the same EQUATION 23-1: nominal bit rate. The CAN protocol uses Non-Return- TBIT = 1/Nominal Bit Rate to-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and The Nominal Bit Time can be thought of as being synchronized to the transmitter’s clock. divided into separate, non-overlapping time segments. These segments (Figure23-4) include: As oscillators and transmission time may vary from node to node, the receiver must have some type of • Synchronization Segment (Sync_Seg) Phase Lock Loop (PLL) synchronized to data transmis- • Propagation Time Segment (Prop_Seg) sion edges to synchronize and maintain the receiver • Phase Buffer Segment 1 (Phase_Seg1) clock. Since the data is NRZ coded, it is necessary to • Phase Buffer Segment 2 (Phase_Seg2) include bit stuffing to ensure that an edge occurs at The time segments (and thus the Nominal Bit Time) are least every six bit times to maintain the Digital Phase in turn made up of integer units of time called Time Lock Loop (DPLL) synchronization. Quanta or TQ (see Figure23-4). By definition, the Nom- The bit timing of the PIC18F6585/8585/6680/8680 is inal Bit Time is programmable from a minimum of 8 TQ implemented using a DPLL that is configured to syn- to a maximum of 25 TQ. Also by definition, the minimum chronize to the incoming data and provides the nominal Nominal Bit Time is 1 s, corresponding to a maximum timing for the transmitted data. The DPLL breaks each 1 Mb/s rate. The actual duration is given by the bit time into multiple segments made up of minimal relationship: periods of time called the Time Quanta (TQ). EQUATION 23-2: Bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + transmission delay compensation, and sample point Phase_Seg1 + Phase_Seg2) positioning, are defined by the programmable bit timing logic of the DPLL. The Time Quantum is a fixed unit derived from the All devices on the CAN bus must use the same bit rate. oscillator period. It is also defined by the programmable However, all devices are not required to have the same baud rate prescaler with integer values from 1 to 64 in master oscillator clock frequency. For the different clock addition to a fixed divide-by-two for clock generation. frequencies of the individual devices, the bit rate has to Mathematically, this is: be adjusted by appropriately setting the baud rate EQUATION 23-3: prescaler and number of time quanta in each segment. The Nominal Bit Rate is the number of bits transmitted TQ (s) = (2 * (BRP+1))/FOSC (MHz) per second, assuming an ideal transmitter with an ideal or oscillator, in the absence of resynchronization. The TQ (s) = (2 * (BRP+1)) * TOSC (s) nominal bit rate is defined to be a maximum of 1 Mb/s. where FOSC is the clock frequency, TOSC is the corre- sponding oscillator period, and BRP is an integer (0 through 63) represented by the binary values of BRGCON1<5:0>. FIGURE 23-4: BIT TIME PARTITIONING Input Signal Sync Propagation Phase Phase Bit Segment Segment Segment 1 Segment 2 Time Intervals TQ Sample Point Nominal Bit Time DS30491D-page 336  2003-2013 Microchip Technology Inc.

18F8680.book Page 337 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.9.1 TIME QUANTA 23.9.2 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit This part of the bit time is used to synchronize the derived from the oscillator period and baud rate various CAN nodes on the bus. The edge of the input prescaler. Its relationship to TBIT and the Nominal Bit signal is expected to occur during the sync segment. Rate is shown in Example23-6. The duration is 1 TQ. EXAMPLE 23-6: CALCULATING TQ, 23.9.3 PROPAGATION SEGMENT NOMINAL BIT RATE AND This part of the bit time is used to compensate for phys- NOMINAL BIT TIME ical delay times within the network. These delay times consist of the signal propagation time on the bus line TQ (s) = (2 * (BRP+1))/FOSC (MHz) and the internal delay time of the nodes. The length of TBIT (s) = TQ (s) * number of TQ per bit interval the Propagation Segment can be programmed from Nominal Bit Rate (bits/s) = 1/TBIT 1TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits. 23.9.4 PHASE BUFFER SEGMENTS CASE 1: The phase buffer segments are used to optimally For FOSC = 16 MHz, BRP<5:0> = 00h and locate the sampling point of the received bit within the Nominal Bit Time = 8 TQ: nominal bit time. The sampling point occurs between TQ = (2*1)/16 = 0.125s (125ns) Phase Segment 1 and Phase Segment 2. These segments can be lengthened or shortened by the TBIT = 8 * 0.125 = 1s (10-6s) resynchronization process. The end of Phase Segment Nominal Bit Rate = 1/10-6 = 106 bits/s (1 Mb/s) 1 determines the sampling point within a bit time. Phase Segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase Segment 2 provides delay before CASE 2: the next transmitted data transition and is also For FOSC = 20 MHz, BRP<5:0> = 01h and programmable from 1 TQ to 8 TQ in duration. However, Nominal Bit Time = 8 TQ: due to IPT requirements, the actual minimum length of TQ = (2*2)/20 = 0.2s (200ns) Peqhuaasle tSoe gthmee ngtr e2a itse r2 oTfQ ,P ohra ist em aSye gbme ednetf in1e do rto tbhee TBIT = 8 * 0.2 = 1.6s (1.6 * 10-6s) Information Processing Time (IPT). Nominal Bit Rate = 1/1.6 * 10-6s =625,000bits/s 23.9.5 SAMPLE POINT (625Kb/s) The sample point is the point of time at which the bus level is read and the value of the received bit is deter- CASE 3: mined. The sampling point occurs at the end of Phase For FOSC = 25 MHz, BRP<5:0> = 3Fh and Segment1. If the bit timing is slow and contains many Nominal Bit Time = 25 TQ: TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is TQ = (2*64)/25 = 5.12s determined to be the value of the majority decision of TBIT = 25 * 5.12 = 128s (1.28 * 10-4s) three values. The three samples are taken at the sam- Nominal Bit Rate = 1/1.28 * 10-4 =7813 bits/s ple point and twice before, with a time of TQ/2 between (7.8Kb/s) each sample. 23.9.6 INFORMATION PROCESSING TIME The frequencies of the oscillators in the different nodes must be coordinated in order to provide a system wide The Information Processing Time (IPT) is the time specified nominal bit time. This means that all oscilla- segment starting at the sample point that is reserved tors must have a TOSC that is an integral divisor of TQ. for calculation of the subsequent bit level. The CAN It should also be noted that although the number of TQ specification defines this time to be less than or equal is programmable from 4 to 25, the usable minimum is to 2TQ. The PIC18F6585/8585/6680/8680 devices 8TQ. A bit time of less than 8 TQ in length is not define this time to be 2TQ. Thus, Phase Segment 2 guaranteed to operate correctly. must be at least 2 TQ long.  2003-2013 Microchip Technology Inc. DS30491D-page 337

18F8680.book Page 338 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.10 Synchronization The phase error of an edge is given by the position of the edge relative to Sync_Seg, measured in TQ. The To compensate for phase shifts between the oscillator phase error is defined in magnitude of TQ as follows: frequencies of each of the nodes on the bus, each CAN • e = 0 if the edge lies within Sync_Seg. controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in • e > 0 if the edge lies before the sample point. the transmitted data is detected, the logic will compare • e < 0 if the edge lies after the sample point of the the location of the edge to the expected time previous bit. (Sync_Seg). The circuit will then adjust the values of If the magnitude of the phase error is less than, or equal Phase Segment 1 and Phase Segment 2 as necessary. to the programmed value of the synchronization jump There are two mechanisms used for synchronization. width, the effect of a resynchronization is the same as that of a hard synchronization. 23.10.1 HARD SYNCHRONIZATION If the magnitude of the phase error is larger than the Hard synchronization is only done when there is a synchronization jump width, and if the phase error is recessive to dominant edge during a bus Idle condition, positive, then Phase Segment 1 is lengthened by an indicating the start of a message. After hard synchroni- amount equal to the synchronization jump width. zation, the bit time counters are restarted with Sync_Seg. Hard synchronization forces the edge If the magnitude of the phase error is larger than the which has occurred to lie within the synchronization resynchronization jump width, and if the phase error is segment of the restarted bit time. Due to the rules of negative, then Phase Segment 2 is shortened by an synchronization, if a hard synchronization occurs there amount equal to the synchronization jump width. will not be a resynchronization within that bit time. 23.10.3 SYNCHRONIZATION RULES 23.10.2 RESYNCHRONIZATION • Only one synchronization within one bit time is As a result of resynchronization, Phase Segment 1 allowed. may be lengthened or Phase Segment 2 may be short- • An edge will be used for synchronization only if ened. The amount of lengthening or shortening of the the value detected at the previous sample point phase buffer segments has an upper bound given by (previously read bus value) differs from the bus the Synchronization Jump Width (SJW). The value of value immediately after the edge. the SJW will be added to Phase Segment 1 (see • All other recessive to dominant edges fulfilling Figure23-5) or subtracted from Phase Segment 2 (see rules 1 and 2 will be used for resynchronization, Figure23-6). The SJW is programmable between 1 TQ with the exception that a node transmitting a and 4 TQ. dominant bit will not perform a resynchronization Clocking information will only be derived from reces- as a result of a recessive to dominant edge with a sive to dominant transitions. The property that only a positive phase error. fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. DS30491D-page 338  2003-2013 Microchip Technology Inc.

18F8680.book Page 339 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 23-5: LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1) Input Signal Bit Prop Phase Phase Time Sync  SJW Segments Segment Segment 1 Segment 2 TQ Sample Point Nominal Bit Length Actual Bit Length FIGURE 23-6: SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Phase Phase Sync Segment Segment 1 Segment 2  SJW TQ Sample Point Actual Bit Length Nominal Bit Length  2003-2013 Microchip Technology Inc. DS30491D-page 339

18F8680.book Page 340 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.11 Programming Time Segments 23.13.2 BRGCON2 Some requirements for programming of the time The PRSEG bits set the length of the propagation seg- segments: ment in terms of TQ. The SEG1PH bits set the length of Phase Segment 1 in TQ. The SAM bit controls how • Prop_Seg + Phase_Seg 1  Phase_Seg 2 many times the RXCAN pin is sampled. Setting this bit • Phase_Seg 2  Sync Jump Width. to a ‘1’ causes the bus to be sampled three times; twice For example, assume that a 125 kHz CAN baud rate is at TQ/2 before the sample point and once at the normal desired, using 20MHz for FOSC. With a TOSC of 50 ns, sample point (which is at the end of Phase Segment 1). a baud rate prescaler value of 04h gives a TQ of 500ns. The value of the bus is determined to be the value read To obtain a Nominal Bit Rate of 125 kHz, the Nominal during at least two of the samples. If the SAM bit is set Bit Time must be 8s or 16 TQ. to a ‘0’, then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the Using 1 TQ for the Sync_Seg, 2 TQ for the Prop_Seg length of Phase Segment 2 is determined. If this bit is and 7 TQ for Phase Segment 1, would place the sample set to a ‘1’, then the length of Phase Segment 2 is point at 10 TQ after the transition. This leaves 6 TQ for determined by the SEG2PH bits of BRGCON3. If the Phase Segment 2. SEG2PHTS bit is set to a ‘0’, then the length of Phase By the rules above, the Sync Jump Width could be the Segment 2 is the greater of Phase Segment 1 and the maximum of 4 TQ. However, normally a large SJW is information processing time (which is fixed at 2 TQ for only necessary when the clock generation of the the PIC18F6585/8585/6680/8680). different nodes is inaccurate or unstable, such as using ceramic resonators. Typically, an SJW of 1 is enough. 23.13.3 BRGCON3 The PHSEG2<2:0> bits set the length (in TQ) of Phase 23.12 Oscillator Tolerance Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0> As a rule of thumb, the bit timing requirements allow bits have no effect. ceramic resonators to be used in applications with transmission rates of up to 125 Kbit/sec. For the full bus 23.14 Error Detection speed range of the CAN protocol, a quartz oscillator is required. A maximum node-to-node oscillator variation The CAN protocol provides sophisticated error of 1.7% is allowed. detection mechanisms. The following errors can be detected. 23.13 Bit Timing Configuration Registers 23.14.1 CRC ERROR With the Cyclic Redundancy Check (CRC), the trans- The Configuration registers (BRGCON1, BRGCON2, mitter calculates special check bits for the bit BRGCON3) control the bit timing for the CAN bus sequence, from the start of a frame until the end of the interface. These registers can only be modified when data field. This CRC sequence is transmitted in the the PIC18F6585/8585/6680/8680 devices are in CRC field. The receiving node also calculates the CRC Configuration mode. sequence using the same formula and performs a 23.13.1 BRGCON1 comparison to the received sequence. If a mismatch is detected, a CRC error has occurred and an error frame The BRP bits control the baud rate prescaler. The is generated. The message is repeated. SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. DS30491D-page 340  2003-2013 Microchip Technology Inc.

18F8680.book Page 341 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.14.2 ACKNOWLEDGE ERROR node can transmit messages and activate error frames (made of dominant bits) without any restrictions. In the In the Acknowledge field of a message, the transmitter error-passive state, messages and passive error checks if the Acknowledge slot (which was sent out as frames (made of recessive bits) may be transmitted. a recessive bit) contains a dominant bit. If not, no other The bus-off state makes it temporarily impossible for node has received the frame correctly. An Acknowl- the station to participate in the bus communication. edge error has occurred; an error frame is generated During this state, messages can neither be received and the message will have to be repeated. nor transmitted. 23.14.3 FORM ERROR 23.14.7 ERROR MODES AND ERROR If a node detects a dominant bit in one of the four COUNTERS segments, including end of frame, interframe space, The PIC18F6585/8585/6680/8680 devices contain two Acknowledge delimiter, or CRC delimiter, then a form error counters: the Receive Error Counter error has occurred and an error frame is generated. (RXERRCNT), and the Transmit Error Counter The message is repeated. (TXERRCNT). The values of both counters can be read 23.14.4 BIT ERROR by the MCU. These counters are incremented or decremented in accordance with the CAN bus A bit error occurs if a transmitter sends a dominant bit specification. and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual The PIC18F6585/8585/6680/8680 devices are error- bus level and comparing it to the just transmitted bit. In active if both error counters are below the error-passive the case where the transmitter sends a recessive bit limit of 128. They are error-passive if at least one of the and a dominant bit is detected during the arbitration error counters equals or exceeds 128. They go to bus- field and the Acknowledge slot, no bit error is off if the transmit error counter equals or exceeds the generated because normal arbitration is occurring. bus-off limit of 256. The devices remain in this state until the bus-off recovery sequence is received. The 23.14.5 STUFF BIT ERROR bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure23-7). lf between the start of frame and the CRC delimiter, six Note that the CAN module, after going bus-off, will consecutive bits with the same polarity are detected, recover back to error-active without any intervention by the bit stuffing rule has been violated. A stuff bit error the MCU if the bus remains Idle for 128 x 11 bit times. occurs and an error frame is generated. The message If this is not desired, the error Interrupt Service Routine is repeated. should address this. The current Error mode of the CAN module can be read by the MCU via the 23.14.6 ERROR STATES COMSTAT register. Detected errors are made public to all other nodes via Additionally, there is an error state warning flag bit, error frames. The transmission of the erroneous mes- EWARN, which is set if at least one of the error sage is aborted and the frame is repeated as soon as counters equals or exceeds the error warning limit of possible. Furthermore, each CAN node is in one of the 96. EWARN is reset if both error counters are less than three error states “error-active”, “error-passive” or “bus- the error warning limit. off” according to the value of the internal error counters. The error-active state is the usual state where the bus  2003-2013 Microchip Technology Inc. DS30491D-page 341

18F8680.book Page 342 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 23-7: ERROR MODES STATE DIAGRAM Reset RXERRCNT < 127 or Error- TXERRCNT < 127 Active 128 occurrences of 11 consecutive RXERRCNT > 127 or “recessive” bits TXERRCNT > 127 Error- Passive TXERRCNT > 255 Bus- Off 23.15 CAN Interrupts The transmit related interrupts are: • Transmit Interrupts The module has several sources of interrupts. Each of these interrupts can be individually enabled or dis- • Transmitter Warning Interrupt abled. The PIR3 register contains interrupt flags. The • Transmitter Error-Passive Interrupt PIE3 register contains the enables for the 8 main inter- • Bus-Off Interrupt rupts. A special set of read-only bits in the CANSTAT register, the ICODE bits, can be used in combination 23.15.1 INTERRUPT CODE BITS with a jump table for efficient handling of interrupts. To simplify the interrupt handling process in user firm- All interrupts have one source with the exception of the ware, the ECAN module encodes a special set of bits. In error interrupt and buffer interrupts in Mode 1 and 2. Any Mode0, these bits are ICODE<2:0> in the CANSTAT of the error interrupt sources can set the error interrupt register. In Mode 1 and 2, these bits are EICODE<3:0> flag. The source of the error interrupt can be determined in the CANSTAT register. Interrupts are internally priori- by reading the Communication Status register, tized such that the higher priority interrupts are assigned COMSTAT. In Mode 1 and 2, there are two interrupt lower values. Once the highest priority interrupt condi- enable/disable and flag bits – one for all transmit buffers tion has been cleared, the code for the next highest and the other for all receive buffers. priority interrupt that is pending (if any) will be reflected The interrupts can be broken up into two categories: by the ICODE bits. Note that only those interrupt sources receive and transmit interrupts. that have their associated interrupt enable bit set will be reflected in the ICODE bits. The receive related interrupts are: In Mode 2, when a receive message interrupt occurs, • Receive Interrupts EICODE bits will always consist of ‘10000’. User • Wake-up Interrupt firmware may use FIFO pointer bits to actually access • Receiver Overrun Interrupt the next available buffer. • Receiver Warning Interrupt • Receiver Error-Passive Interrupt DS30491D-page 342  2003-2013 Microchip Technology Inc.

18F8680.book Page 343 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.15.2 TRANSMIT INTERRUPT 23.15.5 BUS ACTIVITY WAKE-UP INTERRUPT When the transmit interrupt is enabled, an interrupt will be generated when the associated transmit buffer When the PIC18F6585/8585/6680/8680 devices are in becomes empty and is ready to be loaded with a new Sleep mode and the bus activity wake-up interrupt is message. In Mode 0, there are separate interrupt enabled, an interrupt will be generated and the WAKIF enable/disable and flag bits for each of the three bit will be set when activity is detected on the CAN bus. dedicated transmit buffers. The TXBnIF bit will be set to This interrupt causes the PIC18F6585/8585/6680/ indicate the source of the interrupt. The interrupt is 8680 devices to exit Sleep mode. The interrupt is reset cleared by the MCU resetting the TXBnIF bit to a ‘0’. In by the MCU, clearing the WAKIF bit. Mode 1 and 2, all transmit buffers share one interrupt enable/disable and flag bits. In Mode 1 and 2, TXBIE in 23.15.6 ERROR INTERRUPT PIE3 and TXBIF in PIR3 indicate when a transmit buffer When the error interrupt is enabled, an interrupt is has completed transmission of its message. TXBnIF, generated if an overflow condition occurs or if the error TXBnIE and TXBnIP in PIR3, PIE3 and IPR3, respec- state of the transmitter or receiver has changed. The tively, are not used in Mode 1 and 2. Individual transmit error flags in COMSTAT will indicate one of the buffer interrupts can be enabled or disabled by setting or following conditions. clearing TXBIE and BnIE register bits. When a shared interrupt occurs, user firmware must poll the TXREQ bit 23.15.6.1 Receiver Overflow of all transmit buffers to detect the source of interrupt. An overflow condition occurs when the MAB has 23.15.3 RECEIVE INTERRUPT assembled a valid received message (the message meets the criteria of the acceptance filters) and the When the receive interrupt is enabled, an interrupt will receive buffer associated with the filter is not available be generated when a message has been successfully for loading of a new message. The associated received and loaded into the associated receive buffer. COMSTAT.RXnOVFL bit will be set to indicate the This interrupt is activated immediately after receiving overflow condition. This bit must be cleared by the the End Of Frame (EOF) field. MCU. In Mode 0, the RXBnIF bit is set to indicate the source of the interrupt. The interrupt is cleared by the MCU 23.15.6.2 Receiver Warning resetting the RXBnIF bit to a ‘0’. The receive error counter has reached the MCU In Mode 1 and 2, all receive buffers share one interrupt. warning limit of 96. Individual receive buffer interrupts can be controlled by the RXBnIE and BIEn registers. In Mode 1, when a 23.15.6.3 Transmitter Warning shared receive interrupt occurs, user firmware must The transmit error counter has reached the MCU poll the RXFUL bit of each receive buffer to detect the warning limit of 96. source of interrupt. In Mode 2, a receive interrupt indicates that the new message is loaded into FIFO. 23.15.6.4 Receiver Bus Passive FIFO can be read by using FIFO pointer bits, FP. The receive error counter has exceeded the error- In Mode 2, the FIFOWMIF bit indicates if the FIFO high passive limit of 127 and the device has gone to watermark is reached. The FIFO high watermark is error-passive state. defined by the FIFOWM bit in the ECANCON register. 23.15.6.5 Transmitter Bus Passive 23.15.4 MESSAGE ERROR INTERRUPT The transmit error counter has exceeded the error- passive limit of 127 and the device has gone to When an error occurs during transmission or reception error-passive state. of a message, the message error flag, IRXIF, will be set and if the IRXIE bit is set, an interrupt will be generated. 23.15.6.6 Bus-Off This is intended to be used to facilitate baud rate determination when used in conjunction with Listen The transmit error counter has exceeded 255 and the Only mode. device has gone to bus-off state. 23.15.6.7 Interrupt Acknowledge Interrupts are directly associated with one or more sta- tus flags in the PIR register. Interrupts are pending as long as one of the flags is set. Once an interrupt flag is set by the device, the flag can not be reset by the microcontroller until the interrupt condition is removed.  2003-2013 Microchip Technology Inc. DS30491D-page 343

18F8680.book Page 344 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 344  2003-2013 Microchip Technology Inc.

18F8680.book Page 345 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.0 SPECIAL FEATURES OF THE 24.1 Configuration Bits CPU The configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various There are several features intended to maximize sys- device configurations. These bits are mapped, starting tem reliability, minimize cost through elimination of at program memory location 300000h. external components, provide power saving operating modes and offer code protection. These are: The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the • OSC Selection configuration memory space (300000h through • Reset 3FFFFFh) which can only be accessed using table - Power-on Reset (POR) reads and table writes. - Power-up Timer (PWRT) Programming the Configuration registers is done in a - Oscillator Start-up Timer (OST) manner similar to programming the Flash memory. The - Brown-out Reset (BOR) EECON1 register WR bit starts a self-timed write to the • Interrupts Configuration register. In normal Operation mode, a • Watchdog Timer (WDT) TBLWT instruction with the TBLPTR pointed to the Con- figuration register sets up the address and the data for • Sleep the Configuration register write. Setting the WR bit • Code Protection starts a long write to the Configuration register. The • ID Locations Configuration registers are written a byte at a time. To • In-Circuit Serial Programming write or erase a configuration cell, a TBLWT instruction can write a ‘1’ or a ‘0’ into the cell. All PIC18F6585/8585/6680/8680 devices have a Watchdog Timer which is permanently enabled via the configuration bits or software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT) which pro- vides a fixed delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low current Power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options.  2003-2013 Microchip Technology Inc. DS30491D-page 345

18F8680.book Page 346 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 24-1: CONFIGURATION BITS AND DEVICE IDS Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H — — OSCSEN — FOSC3 FOSC2 FOSC1 FOSC0 --1- 1111 300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300004h(1) CONFIG3L WAIT — — — — — PM1 PM0 1--- --11 300005h CONFIG3H MCLRE — — — — — ECCPMX(4) CCP2MX 1--- --11 300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1 300008h CONFIG5L — — — — CP3(2) CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3(2) WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3(2) EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 (Note 3) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1010 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F6X8X devices; maintain this bit set. 2: Unimplemented in PIC18FX585 devices; maintain this bit set. 3: See Register24-13 for DEVID1 values. 4: Reserved in PIC18F6X8X devices; maintain this bit set. DS30491D-page 346  2003-2013 Microchip Technology Inc.

18F8680.book Page 347 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — OSCSEN — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4 Unimplemented: Read as ‘0’ bit 3-0 FOSC3:FOSC0: Oscillator Selection bits 1111 = RC oscillator with OSC2 configured as RA6 1110 = HS oscillator with SW enabled 4x PLL 1101 = EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL 1100 = EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL 1011 = Reserved; do not use 1010 = Reserved; do not use 1001 = Reserved; do not use 1000 = Reserved; do not use 0111 = RC oscillator with OSC2 configured as RA6 0110 = HS oscillator with HW enabled 4x PLL 0101 = EC oscillator with OSC2 configured as RA6 0100 = EC oscillator with OSC2 configured as divide by 4 clock output 0011 = RC oscillator with OSC2 configured as divide by 4 clock output 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS30491D-page 347

18F8680.book Page 348 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30491D-page 348  2003-2013 Microchip Technology Inc.

18F8680.book Page 349 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode Note1: This register is unimplemented for PIC18F6X8X devices; maintain these bits set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS30491D-page 349

18F8680.book Page 350 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 MCLRE — — — — — ECCPMX CCP2MX bit 7 bit 0 bit 7 MCLRE: MCLR Enable bit(1) 1 = MCLR pin enabled, RG5 input pin disabled 0 = RG5 input enabled, MCLR disabled bit 6-2 Unimplemented: Read as ‘0’ bit 1 ECCPMX: CCP1 PWM outputs P1B, P1C mux bit (PIC18F8X8X devices only)(2) 1 = P1B, P1C are multiplexed with RE6, RE5 0 = P1B, P1C are multiplexed with RH7, RH6 bit 0 CCP2MX: CCP2 Mux bit In Microcontroller mode: 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RE7 In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes (PIC18F8X8X devices only): 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Note1: If MCLR is disabled, either disable low-voltage ICSP or hold RB5/PGM low to ensure proper entry into ICSP mode. 2: Reserved for PIC18F6X8X devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. bit 6-3 Unimplemented: Read as ‘0’ bit 2 LVP: Low-Voltage ICSP Enable bit 1 = Low-voltage ICSP enabled 0 = Low-voltage ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30491D-page 350  2003-2013 Microchip Technology Inc.

18F8680.book Page 351 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2 CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected Note1: Unimplemented in PIC18FX585 devices; maintain this bit set. bit 2 CP2: Code Protection bit 1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800-003FFFh) not code-protected 0 = Block 0 (000800-003FFFh) code-protected Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) not code-protected 0 = Boot block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS30491D-page 351

18F8680.book Page 352 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1) WRT2 WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected Note1: Unimplemented in PIC18FX585 devices; maintain this bit set. bit 2 WRT2: Write Protection bit 1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected bit 0 WR0: Write Protection bit 1 = Block 0 (000800-003FFFh) not write-protected 0 = Block 0 (000800-003FFFh) write-protected Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) not write-protected 0 = Boot block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30491D-page 352  2003-2013 Microchip Technology Inc.

18F8680.book Page 353 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks Note1: Unimplemented in PIC18FX585 devices; maintain this bit set. bit 2 EBTR2: Table Read Protection bit 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800-003FFFh) protected from table reads executed in other blocks Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state  2003-2013 Microchip Technology Inc. DS30491D-page 353

18F8680.book Page 354 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-13: DEVICE ID REGISTER 1 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F8680 001 = PIC18F6680 010 = PIC18F8585 011 = PIC18F6585 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 24-14: DEVICE ID REGISTER 2 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFFh) R-0 R-0 R-0 R-0 R-1 R-0 R-1 R-0 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 1010 = PIC18F6585/8585/6680/8680 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30491D-page 354  2003-2013 Microchip Technology Inc.

18F8680.book Page 355 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.2 Watchdog Timer (WDT) The WDT time-out period values may be found in Section27.0 “Electrical Characteristics” under The Watchdog Timer is a free-running, on-chip RC parameter #31. Values for the WDT postscaler may be oscillator which does not require any external compo- assigned using the configuration bits. nents. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the Note1: The CLRWDT and SLEEP instructions WDT will run even if the clock on the OSC1/CLKI and clear the WDT and the postscaler if OSC2/CLKO/RA6 pins of the device has been stopped, assigned to the WDT and prevent it from for example, by execution of a SLEEP instruction. timing out and generating a device Reset condition. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset). If the device is 2: When a CLRWDT instruction is executed in Sleep mode, a WDT time-out causes the device to and the postscaler is assigned to the wake-up and continue with normal operation (Watch- WDT, the postscaler count will be cleared dog Timer wake-up). The TO bit in the RCON register but the postscaler assignment is not will be cleared upon a WDT time-out. changed. The Watchdog Timer is enabled/disabled by a device 24.2.1 CONTROL REGISTER configuration bit. If the WDT is enabled, software execution may not disable this function. When the Register24-15 shows the WDTCON register. This is a WDTEN configuration bit is cleared, the SWDTEN bit readable and writable register which contains a control enables/disables the operation of the WDT. bit that allows software to override the WDT enable configuration bit, only when the configuration bit has disabled the WDT. REGISTER 24-15: WDTCON REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2003-2013 Microchip Technology Inc. DS30491D-page 355

18F8680.book Page 356 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming by the value written to the CONFIG2H Configuration register. FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 16 16-to-1 MUX WDTPS3:WDTPS0 WDTEN SWDTEN bit Configuration bit WDT Time-out Note: WDPS3:WDPS0 are bits in register CONFIG2H. TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2H — — — WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN RCON IPEN — — RI TO PD POR BOR WDTCON — — — — — — — SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. DS30491D-page 356  2003-2013 Microchip Technology Inc.

18F8680.book Page 357 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.3 Power-down Mode (Sleep) Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. Power-down mode is entered by executing a SLEEP External MCLR Reset will cause a device Reset. All instruction. other events are considered a continuation of program If enabled, the Watchdog Timer will be cleared but execution and will cause a “wake-up”. The TO and PD keeps running, the PD bit (RCON<3>) is cleared, the bits in the RCON register can be used to determine the TO (RCON<4>) bit is set and the oscillator driver is cause of the device Reset. The PD bit which is set on turned off. The I/O ports maintain the status they had power-up is cleared when Sleep is invoked. The TO bit before the SLEEP instruction was executed (driving is cleared if a WDT time-out occurred (and caused high, low, or high-impedance). wake-up). For lowest current consumption in this mode, place all When the SLEEP instruction is being executed, the next I/O pins at either VDD or VSS, ensure no external cir- instruction (PC + 2) is pre-fetched. For the device to cuitry is drawing current from the I/O pin, power-down wake-up through an interrupt event, the corresponding the A/D and disable external clocks. Pull all I/O pins interrupt enable bit must be set (enabled). Wake-up is that are high-impedance inputs, high or low externally regardless of the state of the GIE bit. If the GIE bit is to avoid switching currents caused by floating inputs. clear (disabled), the device continues execution at the The T0CKI input should also be at VDD or VSS for low- instruction after the SLEEP instruction. If the GIE bit is est current consumption. The contribution from on-chip set (enabled), the device executes the instruction after pull-ups on PORTB should be considered. the SLEEP instruction and then branches to the inter- The MCLR pin must be at a logic high level (VIHMC). rupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user 24.3.1 WAKE-UP FROM SLEEP should have a NOP after the SLEEP instruction. The device can wake-up from Sleep through one of the 24.3.2 WAKE-UP USING INTERRUPTS following events: When global interrupts are disabled (GIE cleared) and 1. External Reset input on MCLR pin. any interrupt source has both its interrupt enable bit 2. Watchdog Timer Wake-up (if WDT was and interrupt flag bit set, one of the following will occur: enabled). • If an interrupt condition (interrupt flag bit and 3. Interrupt from INT pin, RB port change or a interrupt enable bits are set) occurs before the peripheral interrupt. execution of a SLEEP instruction, the SLEEP The following peripheral interrupts can wake the device instruction will complete as a NOP. Therefore, the from Sleep: WDT and WDT postscaler will not be cleared, the 1. PSP read or write. TO bit will not be set and PD bits will not be cleared. 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. • If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device 3. TMR3 interrupt. Timer3 must be operating as an will immediately wake-up from Sleep. The SLEEP asynchronous counter. instruction will be completely executed before the 4. CCP Capture mode interrupt. wake-up. Therefore, the WDT and WDT 5. Special event trigger (Timer1 in Asynchronous postscaler will be cleared, the TO bit will be set mode using an external clock). and the PD bit will be cleared. 6. MSSP (Start/Stop) bit detect interrupt. Even if the flag bits were checked before executing a 7. MSSP transmit or receive in Slave mode SLEEP instruction, it may be possible for flag bits to (SPI/I2C). become set before the SLEEP instruction completes. To 8. USART RX or TX (Synchronous Slave mode). determine whether a SLEEP instruction executed, test 9. A/D conversion (when A/D clock source is RC). the PD bit. If the PD bit is set, the SLEEP instruction 10. EEPROM write operation complete. was executed as a NOP. 11. LVD interrupt. To ensure that the WDT is cleared, a CLRWDT 12. CAN wake-up interrupt. instruction should be executed before a SLEEP instruction.  2003-2013 Microchip Technology Inc. DS30491D-page 357

18F8680.book Page 358 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 24-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKO(4) TOST(2) INT pin INTF Flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC PC+2 PC+4 PC+4 PC + 4 0008h 000Ah IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 2) Inst(PC + 4) Inst(0008h) Inst(000Ah) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 2) Dummy Cycle Dummy Cycle Inst(0008h) Note 1: XT, HS or LP Oscillator mode assumed. 2: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes. 4: CLKO is not available in these oscillator modes but shown here for timing reference. DS30491D-page 358  2003-2013 Microchip Technology Inc.

18F8680.book Page 359 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.4 Program Verification and Figure24-3 shows the program memory organization Code Protection for 48 and 64-Kbyte devices and the specific code protection bit associated with each block. The actual The overall structure of the code protection on the locations of the bits are summarized in Table24-3. PIC18 Flash devices differs significantly from other PIC® devices. The user program memory is divided on binary bound- aries into four blocks of 16 Kbytes each. The first block is further divided into a boot block of 2048 bytes and a second block (Block 0) of 14 Kbytes. Each of the blocks has three code protection bits associated with them. They are: • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) FIGURE 24-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8X DEVICES MEMORY SIZE/DEVICE Block Code Protection 48Kbytes 64Kbytes Address Controlled By: (PIC18FX585 (PIC18FX680) Range 000000h Boot Block Boot Block CPB, WRTB, EBTRB 0007FFh 000800h Block 0 Block 0 CP0, WRT0, EBTR0 003FFFh 004000h Block 1 Block 1 CP1, WRT1, EBTR1 007FFFh 008000h Block 2 Block 2 CP2, WRT2, EBTR2 00BFFFh 00C000h Unimplemented Read ‘0’ Block 3 CP3, WRT3, EBTR3 00FFFFh TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1) WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18FX585 devices.  2003-2013 Microchip Technology Inc. DS30491D-page 359

18F8680.book Page 360 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.4.1 PROGRAM MEMORY that block is not allowed to read and will result in read- CODE PROTECTION ing ‘0’s. Figures24-4 through24-6 illustrate table write and table read protection. The user memory may be read to or written from any location using the table read and table write instruc- Note: Code protection bits may only be written to tions. The device ID may be read with table reads. The a ‘0’ from a ‘1’ state. It is not possible to Configuration registers may be read and written with write a ‘1’ to a bit in the ‘0’ state. Code the table read and table write instructions. protection bits are only set to ‘1’ by a full chip erase or block erase function. The full In User mode, the CPn bits have no direct effect. CPn chip erase and block erase functions can bits inhibit external reads and writes. A block of user only be initiated via ICSP or an external memory may be protected from table writes if the WRTn configuration bit is ‘0’. The EBTRn bits control programmer. table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that exe- cutes from within that block is allowed to read. A table read instruction that executes from a location outside of FIGURE 24-4: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 000FFFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT * 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 008FFEh TBLWT * WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes disabled to Block n whenever WRTn = 0. DS30491D-page 360  2003-2013 Microchip Technology Inc.

18F8680.book Page 361 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 000FFFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 004FFEh TBLRD * WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 24-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 000FFFh WRT0, EBTR0 = 10 PC = 003FFEh TBLRD * 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Block n even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.  2003-2013 Microchip Technology Inc. DS30491D-page 361

18F8680.book Page 362 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.4.2 DATA EEPROM CODE 24.7 In-Circuit Debugger PROTECTION When the DEBUG bit in Configuration register, The entire data EEPROM is protected from external CONFIG4L, is programmed to a ‘0’, the in-circuit reads and writes by two bits: CPD and WRTD. CPD debugger functionality is enabled. This function allows inhibits external reads and writes of data EEPROM. simple debugging functions when used with MPLAB® WRTD inhibits external writes to data EEPROM. The IDE. When the microcontroller has this feature CPU can continue to read and write data EEPROM enabled, some of the resources are not available for regardless of the protection bit settings. general use. Table24-4 shows which features are consumed by the background debugger. 24.4.3 CONFIGURATION REGISTER PROTECTION TABLE 24-4: DEBUGGER RESOURCES The Configuration registers can be write-protected. The I/O pins RB6, RB7 WRTC bit controls protection of the Configuration regis- ters. In User mode, the WRTC bit is readable only. WRTC Stack 2 levels can only be written via ICSP or an external programmer. Program Memory 512 bytes Data Memory 10 bytes 24.5 ID Locations To use the in-circuit debugger function of the micro- Eight memory locations (200000h-200007h) are controller, the design must implement In-Circuit Serial designated as ID locations where the user can store Programming connections to MCLR/VPP, VDD, GND, checksum or other code identification numbers. These RB7 and RB6. This will interface to the in-circuit locations are accessible during normal execution debugger module available from Microchip or one of through the TBLRD and TBLWT instructions or during the third party development tool companies. program/verify. The ID locations can be read when the device is code-protected. 24.6 In-Circuit Serial Programming PIC18FXX80/XX85 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. DS30491D-page 362  2003-2013 Microchip Technology Inc.

18F8680.book Page 363 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.8 Low-Voltage ICSP Programming If Low-Voltage Programming mode is not used, the LVP bit can be programmed to a ‘0’ and RB5/KBI1/PGM The LVP bit in Configuration register, CONFIG4L, becomes a digital I/O pin. However, the LVP bit may enables Low-Voltage ICSP Programming. This mode only be programmed when programming is entered allows the microcontroller to be programmed via ICSP with VIHH on RG5/MCLR/VPP. using a VDD source in the operating voltage range. This It should be noted that once the LVP bit is programmed only means that VPP does not have to be brought to VIHH to ‘0’, only the High-Voltage Programming mode is but can instead be left at the normal operating voltage. available and only High-Voltage Programming mode In this mode, the RB5/KBI1/PGM pin is dedicated to the can be used to program the device. programming function and ceases to be a general pur- pose I/O pin. During programming, VDD is applied to the When using low-voltage ICSP, the part must be sup- RG5/MCLR/VPP pin. To enter Programming mode, VDD plied 4.5V to 5.5V if a bulk erase will be executed. This must be applied to the RB5/KBI1/PGM pin, provided the includes reprogramming of the code-protect bits from LVP bit is set. The LVP bit defaults to a ‘1’ from the an on-state to an off-state. For all other cases of low- factory. voltage ICSP, the part may be programmed at the normal operating voltage. This means unique user IDs Note1: The High-Voltage Programming mode is or user code can be reprogrammed or added. always available regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low-Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O pin and should be held low during normal operation. 3: When using Low-Voltage ICSP Program- ming (LVP) and the pull-ups on PORTB are enabled, bit 5 in the TRISB register must be cleared to disable the pull-up on RB5 and ensure the proper operation of the device. 4: If the device Master Clear is disabled, verify that either of the following is done to ensure proper entry into ICSP mode: a) disable Low-Voltage Programming (CONFIG4L<2> = 0); or b) make certain that RB5/KBI1/PGM is held low during entry into ICSP.  2003-2013 Microchip Technology Inc. DS30491D-page 363

18F8680.book Page 364 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 364  2003-2013 Microchip Technology Inc.

18F8680.book Page 365 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 25.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18 instruction set adds many enhancements to • A literal value to be loaded into a file register the previous PIC MCU instruction sets, while maintain- (specified by ‘k’) ing an easy migration from these PIC MCU instruction sets. • The desired FSR register to load the literal value into (specified by ‘f’) Most instructions are a single program memory word • No operand required (specified by ‘—’) (16 bits) but there are three instructions that require two program memory locations. The control instructions may use some of the following operands: Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and • A program memory address (specified by ‘n’) one or more operands, which further specify the • The mode of the call or return instructions operation of the instruction. (specified by ‘s’) The instruction set is highly orthogonal and is grouped • The mode of the table read and table write into four basic categories: instructions (specified by ‘m’) • Byte-oriented operations • No operand required (specified by ‘—’) • Bit-oriented operations All instructions are a single word except for three • Literal operations double-word instructions. These three instructions were made double-word instructions so that all the • Control operations required information is available in these 32 bits. In the The PIC18 instruction set summary in Table25-2 lists second word, the 4 MSbs are ‘1’s. If this second word byte-oriented, bit-oriented, literal and control is executed as an instruction (by itself), it will execute operations. Table25-1 shows the opcode field as a NOP. descriptions. All single-word instructions are executed in a single Most byte-oriented instructions have three operands: instruction cycle unless a conditional test is true or the 1. The file register (specified by ‘f’) program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction 2. The destination of the result (specified by ‘d’) cycles with the additional instruction cycle(s) executed 3. The accessed memory (specified by ‘a’) as a NOP. The file register designator ‘f’ specifies which file The double-word instructions execute in two instruction register is to be used by the instruction. cycles. The destination designator ‘d’ specifies where the One instruction cycle consists of four oscillator periods. result of the operation is to be placed. If ‘d’ is zero, the Thus, for an oscillator frequency of 4 MHz, the normal result is placed in the WREG register. If ‘d’ is one, the instruction execution time is 1 s. If a conditional test is result is placed in the file register specified in the true or the program counter is changed as a result of an instruction. instruction, the instruction execution time is 2 s. All bit-oriented instructions have three operands: Two-word branch instructions (if true) would take 3 s. 1. The file register (specified by ‘f’) Figure25-1 shows the general formats that the 2. The bit in the file register (specified by ‘b’) instructions can have. 3. The accessed memory (specified by ‘a’) All examples use the format ‘nnh’ to represent a hexa- The bit field designator ‘b’ selects the number of the bit decimal number, where ‘h’ signifies a hexadecimal affected by the operation, while the file register desig- digit. nator ‘f’ represents the number of the file in which the The Instruction Set Summary, shown in Table25-2, bit is located. lists the instructions recognized by the Microchip Assembler (MPASMTM). Section25.1 “Instruction Set” provides a description of each instruction.  2003-2013 Microchip Technology Inc. DS30491D-page 365

18F8680.book Page 366 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location. f 8-bit register file address (0x00 to 0xFF). fs 12-bit register file address (0x000 to 0xFFF). This is the source address. fd 12-bit register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes). *+ Post-Increment register (such as TBLPTR with table reads and writes). *- Post-Decrement register (such as TBLPTR with table reads and writes). +* Pre-Increment register (such as TBLPTR with table reads and writes). n The relative address (2’s complement number) for relative branch instructions, or the direct address for call/branch and return instructions. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or unchanged. WREG Working register (accumulator). x Don’t care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TOS Top-of-Stack. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. GIE Global Interrupt Enable bit. WDT Watchdog Timer. TO Time-out bit. PD Power-down bit. C, DC, Z, OV, N ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative. [ ] Optional. ( ) Contents.  Assigned to. < > Register bit field.  In the set of. italics User defined term (font is courier). DS30491D-page 366  2003-2013 Microchip Technology Inc.

18F8680.book Page 367 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 0x7F k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2003-2013 Microchip Technology Inc. DS30491D-page 367

18F8680.book Page 368 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 25-2: PIC18FXXX INSTRUCTION SET Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N 1, 2 RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N 1, 2 RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N 1, 2 borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N 1, 2 borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. DS30491D-page 368  2003-2013 Microchip Technology Inc.

18F8680.book Page 369 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED) Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated.  2003-2013 Microchip Technology Inc. DS30491D-page 369

18F8680.book Page 370 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 25-2: PIC18FXXX INSTRUCTION SET (CONTINUED) Mnemonic, 16-Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. DS30491D-page 370  2003-2013 Microchip Technology Inc.

18F8680.book Page 371 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 25.1 Instruction Set ADDLW ADD literal to W ADDWF ADD W to f Syntax: [ label ] ADDLW k Syntax: [ label ] ADDWF f [,d [,a] f [,d [,a] Operands: 0  k  255 Operands: 0  f  255 Operation: (W) + k  W d  [0,1] a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the 8-bit literal ‘k’ and the result is Encoding: 0010 01da ffff ffff placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the Words: 1 result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘d’ Cycles: 1 (default). If ‘a’ is ‘0’, the Access Q Cycle Activity: Bank will be selected. If ‘a’ is ‘1’, Q1 Q2 Q3 Q4 the BSR is used. Decode Read Process Write to W Words: 1 literal ‘k’ Data Cycles: 1 Q Cycle Activity: Example: ADDLW 0x15 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to W = 0x10 register ‘f’ Data destination After Instruction W = 0x25 Example: ADDWF REG, 0, 0 Before Instruction W = 0x17 REG = 0xC2 After Instruction W = 0xD9 REG = 0xC2  2003-2013 Microchip Technology Inc. DS30491D-page 371

18F8680.book Page 372 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC f [,d [,a]] Syntax: [ label ] ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with Encoding: 0010 00da ffff ffff the 8-bit literal ‘k’. The result is Description: Add W, the Carry Flag and data placed in W. memory location ‘f’. If ‘d’ is ‘0’, the Words: 1 result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory loca- Cycles: 1 tion ‘f’. If ‘a’ is ‘0’, the Access Bank Q Cycle Activity: will be selected. If ‘a’ is ‘1’, the BSR Q1 Q2 Q3 Q4 will not be overridden. Decode Read literal Process Write to W Words: 1 ‘k’ Data Cycles: 1 Example: ANDLW 0x5F Q Cycle Activity: Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to W = 0xA3 register ‘f’ Data destination After Instruction W = 0x03 Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 0x02 W = 0x4D After Instruction Carry bit = 0 REG = 0x02 W = 0x50 DS30491D-page 372  2003-2013 Microchip Technology Inc.

18F8680.book Page 373 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 ANDWF AND W with f BC Branch if Carry Syntax: [ label ] ANDWF f [,d [,a]] Syntax: [ label ] BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if carry bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the Description: The contents of W are AND’ed with program will branch. register ‘f’. If ‘d’ is ‘0’, the result is The 2’s complement number ‘2n’ is stored in W. If ‘d’ is ‘1’, the result is added to the PC. Since the PC will stored back in register ‘f’ (default). have incremented to fetch the next If ‘a’ is ‘0’, the Access Bank will be instruction, the new address will be selected. If ‘a’ is ‘1’, the BSR will PC+2+2n. This instruction is then not be overridden (default). a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 If Jump: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read literal Process Write to PC ‘n’ Data Example: ANDWF REG, 0, 0 No No No No operation operation operation operation Before Instruction If No Jump: W = 0x17 Q1 Q2 Q3 Q4 REG = 0xC2 Decode Read literal Process No After Instruction ‘n’ Data operation W = 0x02 REG = 0xC2 Example: HERE BC 5 Before Instruction PC = address (HERE) After Instruction If Carry = 1; PC = address (HERE+12) If Carry = 0; PC = address (HERE+2)  2003-2013 Microchip Technology Inc. DS30491D-page 373

18F8680.book Page 374 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BCF Bit Clear f BN Branch if Negative Syntax: [ label ] BCF f,b[,a] Syntax: [ label ] BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if negative bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ program will branch. is ‘0’, the Access Bank will be The 2’s complement number ‘2n’ is selected, overriding the BSR value. added to the PC. Since the PC will If ‘a’ = 1, then the bank will be have incremented to fetch the next selected as per the BSR value instruction, the new address will be (default). PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: If Jump: Decode Read Process Write register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example: BCF FLAG_REG, 7, 0 ‘n’ Data No No No No Before Instruction operation operation operation operation FLAG_REG = 0xC7 If No Jump: After Instruction Q1 Q2 Q3 Q4 FLAG_REG = 0x47 Decode Read literal Process No ‘n’ Data operation Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE+2) DS30491D-page 374  2003-2013 Microchip Technology Inc.

18F8680.book Page 375 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC n Syntax: [ label ] BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if carry bit is ‘0’ Operation: if negative bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the Description: If the Negative bit is ‘0’, then the program will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE+2) PC = address (HERE+2)  2003-2013 Microchip Technology Inc. DS30491D-page 375

18F8680.book Page 376 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV n Syntax: [ label ] BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if overflow bit is ‘0’ Operation: if zero bit is ‘0’ (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will added to the PC. Since the PC will have incremented to fetch the next have incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then PC+2+2n. This instruction is then a two-cycle instruction. a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE+2) PC = address (HERE+2) DS30491D-page 376  2003-2013 Microchip Technology Inc.

18F8680.book Page 377 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA n Syntax: [ label ] BSF f,b[,a] Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number Encoding: 1000 bbba ffff ffff ‘2n’ to the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’, instruction, the new address will be Access Bank will be selected, over- PC+2+2n. This instruction is a riding the BSR value. If ‘a’ = 1, then two-cycle instruction. the bank will be selected as per the BSR value. Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process Write to PC Q1 Q2 Q3 Q4 ‘n’ Data Decode Read Process Write No No No No register ‘f’ Data register ‘f’ operation operation operation operation Example: BSF FLAG_REG, 7, 1 Example: HERE BRA Jump Before Instruction FLAG_REG = 0x0A Before Instruction After Instruction PC = address (HERE) FLAG_REG = 0x8A After Instruction PC = address (Jump)  2003-2013 Microchip Technology Inc. DS30491D-page 377

18F8680.book Page 378 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. next instruction is skipped. If bit ‘b’ is ‘0’, then the next If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction fetched during the instruction execution is discarded current instruction execution is and a NOP is executed instead, discarded and a NOP is executed making this a two-cycle instruction. If instead, making this a two-cycle ‘a’ is ‘0’, the Access Bank will be instruction. If ‘a’ is ‘0’, the Access selected, overriding the BSR value. If Bank will be selected, overriding the ‘a’ = 1, then the bank will be selected BSR value. If ‘a’ = 1, then the bank as per the BSR value (default). will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process No Q1 Q2 Q3 Q4 register ‘f’ Data operation Decode Read Process No If skip: register ‘f’ Data operation Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 FALSE : Example: HERE BTFSS FLAG, 1, 0 TRUE : FALSE : Before Instruction TRUE : PC = address (HERE) Before Instruction After Instruction PC = address (HERE) If FLAG<1> = 0; After Instruction PC = address (TRUE) If FLAG<1> = 0; If FLAG<1> = 1; PC = address (FALSE) PC = address (FALSE) If FLAG<1> = 1; PC = address (TRUE) DS30491D-page 378  2003-2013 Microchip Technology Inc.

18F8680.book Page 379 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if overflow bit is ‘1’ a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. If ‘a’ is ‘0’, the Access Bank The 2’s complement number ‘2n’ is will be selected, overriding the BSR added to the PC. Since the PC will value. If ‘a’ = 1, then the bank will be have incremented to fetch the next selected as per the BSR value instruction, the new address will be (default). PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: If Jump: Decode Read Process Write register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Example: BTG PORTC, 4, 0 ‘n’ Data No No No No Before Instruction: operation operation operation operation PORTC = 0111 0101 [0x75] If No Jump: After Instruction: Q1 Q2 Q3 Q4 PORTC = 0110 0101 [0x65] Decode Read literal Process No ‘n’ Data operation Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE+2)  2003-2013 Microchip Technology Inc. DS30491D-page 379

18F8680.book Page 380 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ n Syntax: [ label ] CALL k [,s] Operands: -128  n  127 Operands: 0  k  1048575 Operation: if Zero bit is ‘1’ s [0,1] (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the (STATUS)  STATUSS, program will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next instruction, the new address will be 1st word (k<7:0>) 1110 110s k7kkk kkkk0 PC+2+2n. This instruction is then 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 a two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return Words: 1 address (PC+ 4) is pushed onto the Cycles: 1(2) return stack. If ‘s’ = 1, the W, Q Cycle Activity: Status and BSR registers are also If Jump: pushed into their respective Q1 Q2 Q3 Q4 shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no update Decode Read literal Process Write to PC occurs (default). Then, the 20-bit ‘n’ Data value ‘k’ is loaded into PC<20:1>. No No No No CALL is a two-cycle instruction. operation operation operation operation If No Jump: Words: 2 Q1 Q2 Q3 Q4 Cycles: 2 Decode Read literal Process No Q Cycle Activity: ‘n’ Data operation Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal Example: HERE BZ Jump ‘k’<7:0>, stack ‘k’<19:8>, Before Instruction Write to PC PC = address (HERE) No No No No After Instruction operation operation operation operation If Zero = 1; PC = address (Jump) Example: HERE CALL THERE,1 If Zero = 0; PC = address (HERE+2) Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS = STATUS DS30491D-page 380  2003-2013 Microchip Technology Inc.

18F8680.book Page 381 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRF f [,a] Syntax: [ label ] CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Description: CLRWDT instruction resets the Bank will be selected, overriding Watchdog Timer. It also resets the the BSR value. If ‘a’ = 1, then the postscaler of the WDT. Status bits bank will be selected as per the TO and PD are set. BSR value (default). Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode No Process No Decode Read Process Write operation Data operation register ‘f’ Data register ‘f’ Example: CLRWDT Example: CLRF FLAG_REG,1 Before Instruction Before Instruction WDT Counter = ? FLAG_REG = 0x5A After Instruction After Instruction WDT Counter = 0x00 FLAG_REG = 0x00 WDT Postscaler = 0 TO = 1 PD = 1  2003-2013 Microchip Technology Inc. DS30491D-page 381

18F8680.book Page 382 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: [ label ] COMF f [,d [,a]] Syntax: [ label ] CPFSEQ f [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), Operation: (f)  dest skip if (f) = (W) (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are com- plemented. If ‘d’ is ‘0’, the result is Description: Compares the contents of data stored in W. If ‘d’ is ‘1’, the result is memory location ‘f’ to the contents stored back in register ‘f’ (default). of W by performing an unsigned If ‘a’ is ‘0’, the Access Bank will be subtraction. selected, overriding the BSR value. If ‘f’ = W, then the fetched If ‘a’ = 1, then the bank will be instruction is discarded and a NOP selected as per the BSR value is executed instead, making this a (default). two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, Words: 1 overriding the BSR value. If ‘a’ = 1, Cycles: 1 then the bank will be selected as Q Cycle Activity: per the BSR value (default). Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed Example: COMF REG, 0, 0 by a 2-word instruction. Before Instruction Q Cycle Activity: REG = 0x13 Q1 Q2 Q3 Q4 After Instruction Decode Read Process No REG = 0x13 register ‘f’ Data operation W = 0xEC If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS30491D-page 382  2003-2013 Microchip Technology Inc.

18F8680.book Page 383 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT f [,a] Syntax: [ label ] CPFSLT f [,a] Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data Description: Compares the contents of data memory location ‘f’ to the contents memory location ‘f’ to the contents of the W by performing an of W by performing an unsigned unsigned subtraction. subtraction. If the contents of ‘f’ are greater than If the contents of ‘f’ are less than the contents of WREG, then the the contents of W, then the fetched fetched instruction is discarded and instruction is discarded and a NOP a NOP is executed instead, making is executed instead, making this a this a two-cycle instruction. If ‘a’ is two-cycle instruction. If ‘a’ is ‘0’, the ‘0’, the Access Bank will be Access Bank will be selected. If ’a’ selected, overriding the BSR value. is ‘1’, the BSR will not be overrid- If ‘a’ = 1, then the bank will be den (default). selected as per the BSR value Words: 1 (default). Cycles: 1(2) Words: 1 Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed Q Cycle Activity: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process No Q1 Q2 Q3 Q4 register ‘f’ Data operation Decode Read Process No If skip: register ‘f’ Data operation Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSLT REG, 1 NLESS : Example: HERE CPFSGT REG, 0 LESS : NGREATER : Before Instruction GREATER : PC = Address (HERE) Before Instruction W = ? PC = Address (HERE) After Instruction W = ? If REG < W; After Instruction PC = Address (LESS) If REG  W; If REG  W; PC = Address (NLESS) PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2003-2013 Microchip Technology Inc. DS30491D-page 383

18F8680.book Page 384 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> >9] or [DC = 1] then a  [0,1] (W<3:0>) + 6  W<3:0>; else Operation: (f) – 1  dest (W<3:0>)  W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then Encoding: 0000 01da ffff ffff (W<7:4>) + 6  W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, else the result is stored in W. If ‘d’ is ‘1’, (W<7:4>)  W<7:4>; the result is stored back in register Status Affected: C ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding Encoding: 0000 0000 0000 0111 the BSR value. If ‘a’ = 1, then the Description: DAW adjusts the eight-bit value in bank will be selected as per the W, resulting from the earlier BSR value (default). addition of two variables (each in Words: 1 packed BCD format) and produces a correct packed BCD result. Cycles: 1 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write Example: DECF CNT, 1, 0 register W Data W Before Instruction CNT = 0x01 Example1: DAW Z = 0 Before Instruction After Instruction W = 0xA5 CNT = 0x00 Z = 1 C = 0 DC = 0 After Instruction W = 0x05 C = 1 DC = 0 Example 2: Before Instruction W = 0xCE C = 0 DC = 0 After Instruction W = 0x34 C = 1 DC = 0 DS30491D-page 384  2003-2013 Microchip Technology Inc.

18F8680.book Page 385 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ f [,d [,a]] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ is placed back in register ‘f’ (default). (default). If the result is ‘0’, the next If the result is not ‘0’, the next instruction which is already fetched instruction which is already fetched is discarded and a NOP is executed is discarded and a NOP is executed instead, making it a two-cycle instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the the BSR value. If ‘a’ = 1, then the bank will be selected as per the bank will be selected as per the BSR value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 Example: HERE DCFSNZ TEMP, 1, 0 GOTO LOOP ZERO : CONTINUE NZERO : Before Instruction Before Instruction PC = Address (HERE) TEMP = ? After Instruction After Instruction CNT = CNT - 1 TEMP = TEMP - 1, If CNT = 0; If TEMP = 0; PC = Address (CONTINUE) PC = Address (ZERO) If CNT  0; If TEMP  0; PC = Address (HERE+2) PC = Address (NZERO)  2003-2013 Microchip Technology Inc. DS30491D-page 385

18F8680.book Page 386 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f [,d [,a]] Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k7kkk kkkk0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff Description: GOTO allows an unconditional Description: The contents of register ‘f’ are branch anywhere within entire incremented. If ‘d’ is ‘0’, the result 2-Mbyte memory range. The 20-bit is placed in W. If ‘d’ is ‘1’, the result value ‘k’ is loaded into PC<20:1>. is placed back in register ‘f’ GOTO is always a two-cycle (default). If ‘a’ is ‘0’, the Access instruction. Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the Words: 2 bank will be selected as per the Cycles: 2 BSR value (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal No Read literal ‘k’<7:0>, operation ‘k’<19:8>, Q Cycle Activity: Write to PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write to operation operation operation operation register ‘f’ Data destination Example: GOTO THERE Example: INCF CNT, 1, 0 After Instruction Before Instruction PC = Address (THERE) CNT = 0xFF Z = 0 C = ? DC = ? After Instruction CNT = 0x00 Z = 1 C = 1 DC = 1 DS30491D-page 386  2003-2013 Microchip Technology Inc.

18F8680.book Page 387 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] INCFSZ f [,d [,a]] Syntax: [ label ] INFSNZ f [,d [,a]] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0011 11da ffff ffff Encoding: 0100 10da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ is placed back in register ‘f’ (default). (default). If the result is ‘0’, the next instruc- If the result is not ‘0’, the next tion which is already fetched is instruction which is already fetched discarded and a NOP is executed is discarded and a NOP is executed instead, making it a two-cycle instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the the BSR value. If ‘a’ = 1, then the bank will be selected as per the bank will be selected as per the BSR value (default). BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note:3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2003-2013 Microchip Technology Inc. DS30491D-page 387

18F8680.book Page 388 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] IORLW k Syntax: [ label ] IORWF f [,d [,a]] Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are OR’ed with Encoding: 0001 00da ffff ffff the eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If Words: 1 ‘d’ is ‘1’, the result is placed back in Cycles: 1 register ‘f’ (default). If ‘a’ is ‘0’, the Q Cycle Activity: Access Bank will be selected, Q1 Q2 Q3 Q4 overriding the BSR value. If ‘a’ = 1, then the bank will be selected as Decode Read Process Write to W per the BSR value (default). literal ‘k’ Data Words: 1 Example: IORLW 0x35 Cycles: 1 Before Instruction Q Cycle Activity: W = 0x9A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to W = 0xBF register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 DS30491D-page 388  2003-2013 Microchip Technology Inc.

18F8680.book Page 389 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 LFSR Load FSR MOVF Move f Syntax: [ label ] LFSR f,k Syntax: [ label ] MOVF f [,d [,a]] Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k11kkk 1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff Description: The 12-bit literal ‘k’ is loaded into Description: The contents of register ‘f’ are the file select register pointed to moved to a destination dependent by ‘f’. upon the status of ‘d’. If ‘d’ is ‘0’, the Words: 2 result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ Cycles: 2 (default). Location ‘f’ can be any- Q Cycle Activity: where in the 256-byte bank. If ‘a’ is Q1 Q2 Q3 Q4 ‘0’, the Access Bank will be Decode Read literal Process Write selected, overriding the BSR value. ‘k’ MSB Data literal ‘k’ If ‘a’ = 1, then the bank will be MSB to selected as per the BSR value FSRfH (default). Decode Read literal Process Write literal Words: 1 ‘k’ LSB Data ‘k’ to FSRfL Cycles: 1 Example: LFSR 2, 0x3AB Q Cycle Activity: Q1 Q2 Q3 Q4 After Instruction FSR2H = 0x03 Decode Read Process Write W FSR2L = 0xAB register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 0x22 W = 0xFF After Instruction REG = 0x22 W = 0x22  2003-2013 Microchip Technology Inc. DS30491D-page 389

18F8680.book Page 390 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] MOVFF f ,f Syntax: [ label ] MOVLB k s d Operands: 0  fs  4095 Operands: 0  k  255 0  fd  4095 Operation: k  BSR Operation: (fs)  fd Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The 8-bit literal ‘k’ is loaded into 1st word (source) 1100 ffff ffff ffffs the Bank Select Register (BSR). 2nd word (destin.) 1111 ffff ffff ffffd Words: 1 Description: The contents of source register ‘f’ s are moved to destination register Cycles: 1 ‘fd’. Location of source ‘fs’ can be Q Cycle Activity: anywhere in the 4096-byte data Q1 Q2 Q3 Q4 space (000h to FFFh) and location Decode Read literal Process Write of destination ‘f ’ can also be d ‘k’ Data literal ‘k’ to anywhere from 000h to FFFh. BSR Either source or destination can be W (a useful special situation). Example: MOVLB 5 MOVFF is particularly useful for transferring a data memory location Before Instruction to a peripheral register (such as the BSR register = 0x02 transmit buffer or an I/O port). After Instruction The MOVFF instruction cannot use BSR register = 0x05 the PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 0x33 REG2 = 0x11 After Instruction REG1 = 0x33, REG2 = 0x33 DS30491D-page 390  2003-2013 Microchip Technology Inc.

18F8680.book Page 391 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] MOVLW k Syntax: [ label ] MOVWF f [,a] Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Location ‘f’ can be anywhere in the Words: 1 256-byte bank. If ‘a’ is ‘0’, the Cycles: 1 Access Bank will be selected, over- Q Cycle Activity: riding the BSR value. If ‘a’ = 1, then Q1 Q2 Q3 Q4 the bank will be selected as per the BSR value (default). Decode Read Process Write to W literal ‘k’ Data Words: 1 Cycles: 1 Example: MOVLW 0x5A Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 0x5A Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 0x4F REG = 0xFF After Instruction W = 0x4F REG = 0x4F  2003-2013 Microchip Technology Inc. DS30491D-page 391

18F8680.book Page 392 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] MULLW k Syntax: [ label ] MULWF f [,a] Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents Description:’ An unsigned multiplication is of W and the 8-bit literal ‘k’. The carried out between the contents 16-bit result is placed in of W and the register file location PRODH:PRODL register pair. ‘f’. The 16-bit result is stored in PRODH contains the high byte. the PRODH:PRODL register W is unchanged. pair. PRODH contains the high None of the status flags are byte. affected. Both W and ‘f’ are unchanged. Note that neither overflow nor None of the status flags are carry is possible in this affected. operation. A zero result is Note that neither overflow nor possible but not detected. carry is possible in this operation. A zero result is Words: 1 possible but not detected. If ‘a’ is Cycles: 1 ‘0’, the Access Bank will be Q Cycle Activity: selected, overriding the BSR Q1 Q2 Q3 Q4 value. If ‘a’ = 1, then the bank will be selected as per the BSR Decode Read Process Write value (default). literal ‘k’ Data registers PRODH: Words: 1 PRODL Cycles: 1 Example: MULLW 0xC4 Q Cycle Activity: Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write W = 0xE2 register ‘f’ Data registers PRODH = ? PRODH: PRODL = ? PRODL After Instruction W = 0xE2 Example: MULWF REG, 1 PRODH = 0xAD PRODL = 0x08 Before Instruction W = 0xC4 REG = 0xB5 PRODH = ? PRODL = ? After Instruction W = 0xC4 REG = 0xB5 PRODH = 0x8A PRODL = 0x94 DS30491D-page 392  2003-2013 Microchip Technology Inc.

18F8680.book Page 393 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NEGF Negate f NOP No Operation Syntax: [ label ] NEGF f [,a] Syntax: [ label ] NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in Words: 1 the data memory location ‘f’. If ‘a’ is Cycles: 1 ‘0’, the Access Bank will be selected, overriding the BSR value. Q Cycle Activity: If ‘a’ = 1, then the bank will be Q1 Q2 Q3 Q4 selected as per the BSR value. Decode No No No Words: 1 operation operation operation Cycles: 1 Example: Q Cycle Activity: Q1 Q2 Q3 Q4 None. Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6]  2003-2013 Microchip Technology Inc. DS30491D-page 393

18F8680.book Page 394 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] POP Syntax: [ label ] PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC+2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the Description: The PC+2 is pushed onto the top of return stack and is discarded. The the return stack. The previous TOS TOS value then becomes the value is pushed down on the stack. previous value that was pushed This instruction allows implement- onto the return stack. ing a software stack by modifying This instruction is provided to TOS, and then pushing it onto the enable the user to properly manage return stack. the return stack to incorporate a Words: 1 software stack. Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode PUSH PC+2 No No Q1 Q2 Q3 Q4 onto return operation operation Decode No POP TOS No stack operation value operation Example: PUSH Example: POP Before Instruction GOTO NEW TOS = 00345Ah Before Instruction PC = 000124h TOS = 0031A2h Stack (1 level down)= 014332h After Instruction PC = 000126h After Instruction TOS = 000126h Stack (1 level down)= 00345Ah TOS = 014332h PC = NEW DS30491D-page 394  2003-2013 Microchip Technology Inc.

18F8680.book Page 395 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL n Syntax: [ label ] RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that (PC) + 2 + 2n  PC are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to Description: This instruction provides a way to 1K from the current location. First, execute a MCLR Reset in software. return address (PC+2) is pushed Words: 1 onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Cycles: 1 Since the PC will have incremented Q Cycle Activity: to fetch the next instruction, the Q1 Q2 Q3 Q4 new address will be PC+2+2n. This Decode Start No No instruction is a two-cycle Reset operation operation instruction. Words: 1 Example: RESET Cycles: 2 After Instruction Q Cycle Activity: Registers= Reset Value Flags* = Reset Value Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC ‘n’ Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE+2)  2003-2013 Microchip Technology Inc. DS30491D-page 395

18F8680.book Page 396 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] RETFIE [s] Syntax: [ label ] RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL, (TOS)  PC, if s = 1 PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the eight-bit literal Status Affected: GIE/GIEH, PEIE/GIEL. ‘k’. The program counter is loaded from the top of the stack (the return Encoding: 0000 0000 0001 000s address). The high address latch Description: Return from interrupt. Stack is (PCLATH) remains unchanged. popped and Top-of-Stack (TOS) is Words: 1 loaded into the PC. Interrupts are enabled by setting either the high Cycles: 2 or low priority global interrupt Q Cycle Activity: enable bit. If ‘s’ = 1, the contents of Q1 Q2 Q3 Q4 the shadow registers WS, Decode Read Process Pop PC from STATUSS and BSRS are loaded literal ‘k’ Data stack, Write into their corresponding registers, to W W, Status and BSR. If ‘s’ = 0, no No No No No update of these registers occurs operation operation operation operation (default). Words: 1 Example: Cycles: 2 CALL TABLE ; W contains table Q Cycle Activity: ; offset value Q1 Q2 Q3 Q4 ; W now has Decode No No Pop PC from ; table value operation operation stack : TABLE Set GIEH or ADDWF PCL ; W = offset GIEL RETLW k0 ; Begin table No No No No RETLW k1 ; operation operation operation operation : : Example: RETFIE 1 RETLW kn ; End of table After Interrupt PC = TOS Before Instruction W = WS W = 0x07 BSR = BSRS STATUS = STATUSS After Instruction GIE/GIEH, PEIE/GIEL = 1 W = value of kn DS30491D-page 396  2003-2013 Microchip Technology Inc.

18F8680.book Page 397 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] RETURN [s] Syntax: [ label ] RLCF f [,d [,a]] Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC, if s = 1 a  [0,1] (WS)  W, Operation: (f<n>)  dest<n+1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are Description: Return from subroutine. The stack rotated one bit to the left through is popped and the top of the stack the Carry flag. If ‘d’ is ‘0’, the result (TOS) is loaded into the program is placed in W. If ‘d’ is ‘1’, the result counter. If ‘s’ = 1, the contents of is stored back in register ‘f’ the shadow registers WS, (default). If ‘a’ is ‘0’, the Access STATUSS and BSRS are loaded Bank will be selected, overriding into their corresponding registers, the BSR value. If ‘a’ = 1, then the W, Status and BSR. If ‘s’ = 0, no bank will be selected as per the update of these registers occurs BSR value (default). (default). C register f Words: 1 Cycles: 2 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode No Process Pop PC Q1 Q2 Q3 Q4 operation Data from stack Decode Read Process Write to No No No No register ‘f’ Data destination operation operation operation operation Example: RLCF REG, 0, 0 Before Instruction Example: RETURN REG = 1110 0110 C = 0 After Interrupt PC = TOS After Instruction REG = 1110 0110 W = 1100 1100 C = 1  2003-2013 Microchip Technology Inc. DS30491D-page 397

18F8680.book Page 398 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] RLNCF f [,d [,a]] Syntax: [ label ] RRCF f [,d [,a]] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n+1>, Operation: (f<n>)  dest<n-1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0,’ Description: The contents of register ‘f’ are the result is placed in W. If ‘d’ is ‘1’, rotated one bit to the right through the result is stored back in register the Carry flag. If ‘d’ is ‘0’, the result ‘f’ (default). If ‘a’ is ‘0’, the Access is placed in W. If ‘d’ is ‘1’, the result Bank will be selected, overriding is placed back in register ‘f’ the BSR value. If ‘a’ is ‘1’, then the (default). If ‘a’ is ‘0’, the Access bank will be selected as per the Bank will be selected, overriding BSR value (default). the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the register f BSR value (default). Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to Example: RLNCF REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS30491D-page 398  2003-2013 Microchip Technology Inc.

18F8680.book Page 399 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] RRNCF f [,d [,a]] Syntax: [ label ] SETF f [,a] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n-1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified Encoding: 0100 00da ffff ffff register are set to FFh. If ‘a’ is ‘0’, Description:’ The contents of register ‘f’ are the Access Bank will be selected, rotated one bit to the right. If ‘d’ is overriding the BSR value. If ‘a’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, then the bank will be selected ‘1’, the result is placed back in as per the BSR value (default). register ‘f’ (default). If ‘a’ is ‘0’, the Words: 1 Access Bank will be selected, overriding the BSR value. If ‘a’ is Cycles: 1 ‘1’, then the bank will be selected Q Cycle Activity: as per the BSR value (default). Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction REG = 0x5A Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to REG = 0xFF register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2003-2013 Microchip Technology Inc. DS30491D-page 399

18F8680.book Page 400 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SLEEP Enter Sleep mode SUBFWP Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB f [,d [,a]] Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and carry flag Description: The Power-down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit method). If ‘d’ is ‘0’, the result is (TO) is set. Watchdog Timer and stored in W. If ‘d’ is ‘1’, the result is its postscaler are cleared. stored in register ‘f’ (default). If ‘a’ The processor is put into Sleep is ‘0’, the Access Bank will be mode with the oscillator stopped. selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will Words: 1 be selected as per the BSR value Cycles: 1 (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode No Process Go to operation Data SLEEP Q Cycle Activity: Q1 Q2 Q3 Q4 Example: SLEEP Decode Read Process Write to register ‘f’ Data destination Before Instruction TO = ? Example 1: SUBFWB REG, 1, 0 PD = ? Before Instruction After Instruction REG = 3 TO = 1 † W = 2 C = 1 PD = 0 After Instruction † If WDT causes wake-up, this bit is cleared. REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS30491D-page 400  2003-2013 Microchip Technology Inc.

18F8680.book Page 401 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF f [,d [,a]] Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, Words: 1 the result is stored in W. If ‘d’ is Cycles: 1 ‘1’, the result is stored back in Q Cycle Activity: register ‘f’ (default). If ‘a’ is ‘0’, the Q1 Q2 Q3 Q4 Access Bank will be selected, overriding the BSR value. If ‘a’ is Decode Read Process Write to W ‘1’, then the bank will be selected literal ‘k’ Data as per the BSR value (default). Example 1: SUBLW 0x02 Words: 1 Before Instruction Cycles: 1 W = 1 C = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 1 Decode Read Process Write to C = 1 ; result is positive Z = 0 register ‘f’ Data destination N = 0 Example 1: SUBWF REG, 1, 0 Example 2: SUBLW 0x02 Before Instruction Before Instruction REG = 3 W = 2 W = 2 C = ? C = ? After Instruction After Instruction W = 0 REG = 1 C = 1 ; result is zero W = 2 Z = 1 C = 1 ; result is positive N = 0 Z = 0 N = 0 Example 3: SUBLW 0x02 Example 2: SUBWF REG, 0, 0 Before Instruction Before Instruction W = 3 C = ? REG = 2 W = 2 After Instruction C = ? W = FF ; (2’s complement) After Instruction C = 0 ; result is negative Z = 0 REG = 2 N = 1 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2003-2013 Microchip Technology Inc. DS30491D-page 401

18F8680.book Page 402 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB f [,d [,a]] Syntax: [ label ] SWAPF f [,d [,a]] Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, (f<7:4>)  dest<3:0> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0101 10da ffff ffff Encoding: 0011 10da ffff ffff Description: Subtract W and the Carry flag (bor- row) from register ‘f’ (2’s complement Description: The upper and lower nibbles of method). If ‘d’ is ‘0’, the result is register ‘f’ are exchanged. If ‘d’ is stored in W. If ‘d’ is ‘1’, the result is ‘0’, the result is placed in W. If ‘d’ is stored back in register ‘f’ (default). If ‘1’, the result is placed in register ‘f’ ‘a’ is ‘0’, the Access Bank will be (default). If ‘a’ is ‘0’, the Access selected, overriding the BSR value. If Bank will be selected, overriding ‘a’ is ‘1’, then the bank will be the BSR value. If ‘a’ is ‘1’, then the selected as per the BSR value bank will be selected as per the (default). BSR value (default). Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination Example 1: SUBWFB REG, 1, 0 Example: SWAPF REG, 1, 0 Before Instruction Before Instruction REG = 0x19 (0001 1001) W = 0x0D (0000 1101) REG = 0x53 C = 1 After Instruction After Instruction REG = 0x35 REG = 0x0C (0000 1011) W = 0x0D (0000 1101) C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 0x1B (0001 1011) W = 0x1A (0001 1010) C = 0 After Instruction REG = 0x1B (0001 1011) W = 0x00 C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 0x03 (0000 0011) W = 0x0E (0000 1101) C = 1 After Instruction REG = 0xF5 (1111 0100) ; [2’s comp] W = 0x0E (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS30491D-page 402  2003-2013 Microchip Technology Inc.

18F8680.book Page 403 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TBLRD Table Read TBLRD Table Read (Continued) Syntax: [ label ] TBLRD ( *; *+; *-; +*) Example1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 0x55 Operation: if TBLRD *, TBLPTR = 0x00A356 (Prog Mem (TBLPTR))  TABLAT; MEMORY(0x00A356) = 0x34 TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 0x34 (Prog Mem (TBLPTR))  TABLAT; TBLPTR = 0x00A357 (TBLPTR) + 1  TBLPTR; if TBLRD *-, Example2: TBLRD +* ; (Prog Mem (TBLPTR))  TABLAT; Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = 0xAA if TBLRD +*, TBLPTR = 0x01A357 (TBLPTR) + 1  TBLPTR; MEMORY(0x01A357) = 0x12 (Prog Mem (TBLPTR))  TABLAT; MEMORY(0x01A358) = 0x34 After Instruction Status Affected:None TABLAT = 0x34 Encoding: 0000 0000 0000 10nn TBLPTR = 0x01A358 nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read operation (Write Program Memory) TABLAT)  2003-2013 Microchip Technology Inc. DS30491D-page 403

18F8680.book Page 404 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] TBLWT ( *; *+; *-; +*) Words: 1 Operands: None Cycles: 2 Operation: if TBLWT*, Q Cycle Activity: (TABLAT)  Holding Register; Q1 Q2 Q3 Q4 TBLPTR – No Change; if TBLWT*+, Decode No No No (TABLAT)  Holding Register; operation operation operation (TBLPTR) + 1  TBLPTR; No No No No if TBLWT*-, operation operation operation operation (TABLAT)  Holding Register; (Read (Write to (TBLPTR) – 1  TBLPTR; TABLAT) Holding if TBLWT+*, Register ) (TBLPTR) + 1  TBLPTR; (TABLAT)  Holding Register; Example1: TBLWT *+; Status Affected: None Before Instruction Encoding: 0000 0000 0000 11nn nn=0 * TABLAT = 0x55 TBLPTR = 0x00A356 =1 *+ HOLDING REGISTER =2 *- (0x00A356) = 0xFF =3 +* After Instructions (table write completion) Description: This instruction uses the 3 LSBs of TABLAT = 0x55 TBLPTR = 0x00A357 TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is (0x00A356) = 0x55 written to. The holding registers are Example 2: TBLWT +*; used to program the contents of Program Memory (P.M.). (Refer Before Instruction to Section5.0 “Flash Program TABLAT = 0x34 TBLPTR = 0x01389A Memory” for additional details on HOLDING REGISTER programming Flash memory.) (0x01389A) = 0xFF HOLDING REGISTER The TBLPTR (a 21-bit pointer) points (0x01389B) = 0xFF to each byte in the program memory. After Instruction (table write completion) TBLPTR has a 2-MBtye address TABLAT = 0x34 range. The LSb of the TBLPTR TBLPTR = 0x01389B selects which byte of the program HOLDING REGISTER (0x01389A) = 0xFF memory location to access. HOLDING REGISTER TBLPTR[0] = 0:Least Significant (0x01389B) = 0x34 Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment DS30491D-page 404  2003-2013 Microchip Technology Inc.

18F8680.book Page 405 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed Description: If ‘f’ = 0, the next instruction, with the 8-bit literal ‘k’. The result fetched during the current is placed in W. instruction execution is discarded Words: 1 and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, Cycles: 1 the Access Bank will be selected, Q Cycle Activity: overriding the BSR value. If ‘a’ is Q1 Q2 Q3 Q4 ‘1’, then the bank will be selected Decode Read Process Write to W as per the BSR value (default). literal ‘k’ Data Words: 1 Cycles: 1(2) Example: XORLW 0xAF Note: 3 cycles if skip and followed Before Instruction by a 2-word instruction. W = 0xB5 Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = 0x1A Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 0x00, PC = Address (ZERO) If CNT  0x00, PC = Address (NZERO)  2003-2013 Microchip Technology Inc. DS30491D-page 405

18F8680.book Page 406 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 XORWF Exclusive OR W with f Syntax: [ label ] XORWF f [,d [,a]] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS30491D-page 406  2003-2013 Microchip Technology Inc.

18F8680.book Page 407 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software • Integrated Development Environment development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software based application that contains: • Assemblers/Compilers/Linkers • An interface to debugging tools - MPASMTM Assembler - simulator - MPLAB C17 and MPLAB C18 C Compilers - programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - emulator (sold separately) - MPLAB C30 C Compiler - in-circuit debugger (sold separately) - MPLAB ASM30 Assembler/Linker/Library • A full-featured editor with color coded context • Simulators • A multiple project manager - MPLAB SIM Software Simulator • Customizable data windows with direct edit of contents - MPLAB dsPIC30 Software Simulator • High-level source code debugging • Emulators • Mouse over variable inspection - MPLAB ICE 2000 In-Circuit Emulator • Extensive on-line help - MPLAB ICE 4000 In-Circuit Emulator • In-Circuit Debugger The MPLAB IDE allows you to: - MPLAB ICD 2 • Edit your source files (either assembly or C) • Device Programmers • One touch assemble (or compile) and download - PRO MATE® II Universal Device Programmer to PIC MCU emulator and simulator tools (automatically updates all project information) - PICSTART® Plus Development Programmer • Debug using: - MPLAB PM3 Device Programmer - source files (assembly or C) • Low-Cost Demonstration Boards - mixed assembly and C - PICDEMTM 1 Demonstration Board - machine code - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective - PICDEM 3 Demonstration Board simulators, through low-cost in-circuit debuggers, to - PICDEM 4 Demonstration Board full-featured emulators. This eliminates the learning - PICDEM 17 Demonstration Board curve when upgrading to tools with increasing flexibility - PICDEM 18R Demonstration Board and power. - PICDEM LIN Demonstration Board 26.2 MPASM Assembler - PICDEM USB Demonstration Board • Evaluation Kits The MPASM assembler is a full-featured, universal - KEELOQ® macro assembler for all PIC MCUs. - PICDEM MSC The MPASM assembler generates relocatable object - microID® files for the MPLINK object linker, Intel® standard HEX files, MAP files to detail memory usage and symbol ref- - CAN erence, absolute LST files that contain source lines and - PowerSmart® generated machine code and COFF files for - Analog debugging. The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process  2003-2013 Microchip Technology Inc. DS30491D-page 407

18F8680.book Page 408 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.3 MPLAB C17 and MPLAB C18 26.6 MPLAB ASM30 Assembler, Linker C Compilers and Librarian The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable Systems are complete ANSI C compilers for machine code from symbolic assembly language for Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler integration capabilities, superior code optimization and generates relocatable object files that can then be ease of use not found with other compilers. archived or linked with other relocatable object files and archives to create an executable file. Notable features For easy source level debugging, the compilers provide of the assembler include: symbol information that is optimized to the MPLAB IDE debugger. • Support for the entire dsPIC30F instruction set • Support for fixed-point and floating-point data 26.4 MPLINK Object Linker/ • Command line interface MPLIB Object Librarian • Rich directive set The MPLINK object linker combines relocatable • Flexible macro language objects created by the MPASM assembler and the • MPLAB IDE compatibility MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using 26.7 MPLAB SIM Software Simulator directives from a linker script. The MPLAB SIM software simulator allows code devel- The MPLIB object librarian manages the creation and opment in a PC hosted environment by simulating the modification of library files of precompiled code. When PIC series microcontrollers on an instruction level. On a routine from a library is called from a source file, only any given instruction, the data areas can be examined the modules that contain that routine will be linked in or modified and stimuli can be applied from a file, or with the application. This allows large libraries to be user defined key press, to any pin. The execution can used efficiently in many different applications. be performed in Single-Step, Execute Until Break or The object linker/library features include: Trace mode. • Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic smaller files debugging using the MPLAB C17 and MPLAB C18 • Enhanced code maintainability by grouping CCompilers, as well as the MPASM assembler. The related modules together software simulator offers the flexibility to develop and debug code outside of the laboratory environment, • Flexible creation of libraries with easy module making it an excellent, economical software listing, replacement, deletion and extraction development tool. 26.5 MPLAB C30 C Compiler 26.8 MPLAB SIM30 Software Simulator The MPLAB C30 C compiler is a full-featured, ANSI The MPLAB SIM30 software simulator allows code compliant, optimizing compiler that translates standard development in a PC hosted environment by simulating ANSI C programs into dsPIC30F assembly language the dsPIC30F series microcontrollers on an instruction source. The compiler also supports many command level. On any given instruction, the data areas can be line options and language extensions to take full examined or modified and stimuli can be applied from advantage of the dsPIC30F device hardware capabili- a file, or user defined key press, to any of the pins. ties and afford fine control of the compiler code generator. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB C30 is distributed with a complete ANSI C MPLAB ASM30 assembler. The simulator runs in either standard library. All library functions have been vali- a Command Line mode for automated tasks, or from dated and conform to the ANSI C library standard. The MPLAB IDE. This high-speed simulator is designed to library includes functions for string manipulation, debug, analyze and optimize time intensive DSP dynamic memory allocation, data conversion, time- routines. keeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE. DS30491D-page 408  2003-2013 Microchip Technology Inc.

18F8680.book Page 409 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.9 MPLAB ICE 2000 26.11 MPLAB ICD 2 In-Circuit Debugger High-Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 universal in-circuit emulator is USB interface. This tool is based on the Flash PIC intended to provide the product development engineer MCUs and can be used to develop for these and other with a complete microcontroller design tool set for PIC PIC microcontrollers. The MPLAB ICD2 utilizes the in- microcontrollers. Software control of the MPLAB ICE circuit debugging capability built into the Flash devices. 2000 in-circuit emulator is advanced by the MPLAB This feature, along with Microchip’s In-Circuit Serial Integrated Development Environment, which allows ProgrammingTM (ICSPTM) protocol, offers cost effective editing, building, downloading and source debugging in-circuit Flash debugging from the graphical user inter- from a single environment. face of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator sys- Environment. This enables a designer to develop and tem with enhanced trace, trigger and data monitoring debug source code by setting breakpoints, single- features. Interchangeable processor modules allow the stepping and watching variables, CPU status and system to be easily reconfigured for emulation of differ- peripheral registers. Running at full speed enables test- ent processors. The universal architecture of the ing hardware and applications in real-time. MPLAB MPLAB ICE in-circuit emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with 26.12 PRO MATE II Universal Device advanced features that are typically found on more Programmer expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at chosen to best make these features available in a simple, unified application. VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages 26.10 MPLAB ICE 4000 and a modular detachable socket assembly to support High-Performance Universal various package types. In Stand-Alone mode, the PROMATE II device programmer can read, verify and In-Circuit Emulator program PIC devices without a PC connection. It can The MPLAB ICE 4000 universal in-circuit emulator is also set code protection in this mode. intended to provide the product development engineer with a complete microcontroller design tool set for high- 26.13 MPLAB PM3 Device Programmer end PIC microcontrollers. Software control of the The MPLAB PM3 is a universal, CE compliant device MPLAB ICE in-circuit emulator is provided by the programmer with programmable voltage verification at MPLAB Integrated Development Environment, which allows editing, building, downloading and source VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error debugging from a single environment. messages and a modular detachable socket assembly The MPLAB ICD 4000 is a premium emulator system, to support various package types. The ICSP™ cable providing the features of MPLAB ICE 2000, but with assembly is included as a standard item. In Stand- increased emulation memory and high-speed perfor- Alone mode, the MPLAB PM3 device programmer can mance for dsPIC30F and PIC18XXXX devices. Its read, verify and program PIC devices without a PC advanced emulator features include complex triggering connection. It can also set code protection in this mode. and timing, up to 2 Mb of emulation memory and the MPLAB PM3 connects to the host PC via an RS-232 ability to view variables in real-time. or USB cable. MPLAB PM3 has high-speed communi- The MPLAB ICE 4000 in-circuit emulator system has cations and optimized algorithms for quick program- been designed as a real-time emulation system with ming of large memory devices and incorporates an SD/ advanced features that are typically found on more MMC card for file storage and secure data applications. expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2003-2013 Microchip Technology Inc. DS30491D-page 409

18F8680.book Page 410 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.14 PICSTART Plus Development 26.17 PICDEM 2 Plus Programmer Demonstration Board The PICSTART Plus development programmer is an The PICDEM 2 Plus demonstration board supports easy-to-use, low-cost, prototype programmer. It con- many 18, 28 and 40-pin microcontrollers, including nects to the PC via a COM (RS-232) port. MPLAB PIC16F87X and PIC18FXX2 devices. All the neces- Integrated Development Environment software makes sary hardware and software is included to run the dem- using the programmer simple and efficient. The onstration programs. The sample microcontrollers PICSTART Plus development programmer supports provided with the PICDEM 2 demonstration board can most PIC devices up to 40 pins. Larger pin count be programmed with a PRO MATE II device program- devices, such as the PIC16C92X and PIC17C76X, mer, PICSTART Plus development programmer, or may be supported with an adapter socket. The MPLAB ICD 2 with a Universal Programmer Adapter. PICSTART Plus development programmer is CE The MPLAB ICD 2 and MPLAB ICE in-circuit emulators compliant. may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the 26.15 PICDEM 1 PIC MCU circuitry for additional application components. Some Demonstration Board of the features include an RS-232 interface, a 2x16 LCD display, a piezo speaker, an on-board temperature The PICDEM 1 demonstration board demonstrates the sensor, four LEDs and sample PIC18F452 and capabilities of the PIC16C5X (PIC16C54 to PIC16F877 Flash microcontrollers. PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All 26.18 PICDEM 3 PIC16C92X necessary hardware and software is included to run Demonstration Board basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can The PICDEM 3 demonstration board supports the be programmed with a PRO MATE II device program- PIC16C923 and PIC16C924 in the PLCC package. All mer or a PICSTART Plus development programmer. the necessary hardware and software is included to run The PICDEM 1 demonstration board can be connected the demonstration programs. to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional appli- 26.19 PICDEM 4 8/14/18-Pin cation components. Features include an RS-232 Demonstration Board interface, a potentiometer for simulated analog input, push button switches and eight LEDs. The PICDEM 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin PIC16XXXX and 26.16 PICDEM.net Internet/Ethernet PIC18XXXX MCUs, including the PIC16F818/819, Demonstration Board PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to The PICDEM.net demonstration board is an Internet/ showcase the many features of these low pin count Ethernet demonstration board using the PIC18F452 parts, including LIN and Motor Control using ECCP. microcontroller and TCP/IP firmware. The board Special provisions are made for low-power operation supports any 40-pin DIP device that conforms to the with the supercapacitor circuit and jumpers allow on- standard pinout used by the PIC16F877 or board hardware to be disabled to eliminate current PIC18C452. This kit features a user friendly TCP/IP draw in this mode. Included on the demo board are pro- stack, web server with HTML, a 24L256 Serial visions for Crystal, RC or Canned Oscillator modes, a EEPROM for Xmodem download to web pages into five volt regulator for use with a nine volt wall adapter Serial EEPROM, ICSP/MPLAB ICD 2 interface con- or battery, DB-9 RS-232 interface, ICD connector for nector, an Ethernet interface, RS-232 interface and a programming via ICSP and development with MPLAB 16 x 2 LCD display. Also included is the book and ICD 2, 2 x 16 liquid crystal display, PCB footprints for CD-ROM “TCP/IP Lean, Web Servers for Embedded H-Bridge motor driver, LIN transceiver and EEPROM. Systems,” by Jeremy Bentham Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. DS30491D-page 410  2003-2013 Microchip Technology Inc.

18F8680.book Page 411 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.20 PICDEM 17 Demonstration Board 26.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several The PICDEM USB Demonstration Board shows off the Microchip microcontrollers, including PIC17C752, capabilities of the PIC16C745 and PIC16C765 USB PIC17C756A, PIC17C762 and PIC17C766. A pro- microcontrollers. This board provides the basis for grammed sample is included. The PRO MATE II device future USB products. programmer, or the PICSTART Plus development pro- grammer, can be used to reprogram the device for user 26.25 Evaluation and tailored application development. The PICDEM 17 Programming Tools demonstration board supports program download and execution from external on-board Flash memory. A In addition to the PICDEM series of circuits, Microchip generous prototype area is available for user hardware has a line of evaluation kits and demonstration software expansion. for these products. • KEELOQ evaluation and programming tools for 26.21 PICDEM 18R PIC18C601/801 Microchip’s HCS Secure Data Products Demonstration Board • CAN developers kit for automotive network The PICDEM 18R demonstration board serves to assist applications development of the PIC18C601/801 family of Microchip • Analog design boards and filter design software microcontrollers. It provides hardware implementation • PowerSmart battery charging evaluation/ of both 8-bit Multiplexed/Demultiplexed and 16-bit calibration kits Memory modes. The board includes 2 Mb external • IrDA® development kit Flash memory and 128 Kb SRAM memory, as well as • microID development and rfLabTM development serial EEPROM, allowing access to the wide range of software memory types supported by the PIC18C601/801. • SEEVAL® designer kit for memory evaluation and 26.22 PICDEM LIN PIC16C43X endurance calculations Demonstration Board • PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma The powerful LIN hardware and software kit includes a ADC and flow rate sensor series of boards and three PIC microcontrollers. The Check the Microchip web page and the latest Product small footprint PIC16C432 and PIC16C433 are used Selector Guide for the complete list of demonstration as slaves in the LIN communication and feature on- and evaluation kits. board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three micro- controllers are programmed with firmware to provide LIN bus communication. 26.23 PICkitTM 1 Flash Starter Kit A complete “development system in a box”, the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC® microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User’s Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB® IDE (Integrated Development Environment) software, software and hardware “Tips 'n Tricks for 8-pin Flash PIC® Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.  2003-2013 Microchip Technology Inc. DS30491D-page 411

18F8680.book Page 412 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 412  2003-2013 Microchip Technology Inc.

18F8680.book Page 413 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk byall ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2003-2013 Microchip Technology Inc. DS30491D-page 413

18F8680.book Page 414 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-1: PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FXX8X 4.5V e g 4.2V a 4.0V t ol 3.5V V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 40 MHz for PIC18F6X8X and PIC18F8X8X in Microcontroller mode. FMAX = 25 MHz for PIC18F8X8X in modes other than Microcontroller mode. FIGURE 27-2: PIC18LF6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LFXX8X 4.5V e g 4.2V a 4.0V t ol 3.5V V 3.0V 2.5V 2.0V 4 MHz FMAX Frequency For PIC18F6X8X and PIC18F8X8X in Microcontroller mode: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 40 MHz, if VDDAPPMIN > 4.2V. For PIC18F8X8X in modes other than Microcontroller mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. DS30491D-page 414  2003-2013 Microchip Technology Inc.

18F8680.book Page 415 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-3: PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V 5.0V PIC18FXX8X 4.5V e g 4.2V a 4.0V t ol 3.5V V 3.0V 2.5V 2.0V 25 MHz Frequency  2003-2013 Microchip Technology Inc. DS30491D-page 415

18F8680.book Page 416 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.1 DC Characteristics: Supply Voltage PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) PIC18LFXX8X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX8X Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param. Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage PIC18LFXX8X 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode PIC18FXX8X 4.2 — 5.5 V D001A AVDD Analog Supply VDD – 0.3 — VDD + 0.3 V Voltage D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for to ensure internal details Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for to ensure internal details Power-on Reset signal D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 1.96 — 2.18 V BORV1:BORV0 = 10 2.64 — 2.92 V BORV1:BORV0 = 01 4.11 — 4.55 V BORV1:BORV0 = 00 4.41 — 4.87 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. DS30491D-page 416  2003-2013 Microchip Technology Inc.

18F8680.book Page 417 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.2 DC Characteristics: Power-down and Supply Current PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) PIC18LFXX8X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX8X Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param. Device Typ Max Units Conditions No. Power-down Current (IPD)(1) D020 PIC18LFXX8X 0.2 1 A -40°C VDD = 2.0V, 0.2 1 A +25°C (Sleep mode) 5.0 10 A +85°C D020A PIC18LFXX8X 0.4 1 A -40°C VDD = 3.0V, 0.4 1 A +25°C (Sleep mode) 3.0 18 A +85°C D020B All devices 0.7 2 A -40°C VDD = 5.0V, 0.7 2 A +25°C (Sleep mode) 15.0 32 A +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2003-2013 Microchip Technology Inc. DS30491D-page 417

18F8680.book Page 418 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.2 DC Characteristics: Power-down and Supply Current PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued) PIC18LFXX8X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX8X Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param. Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) D010 PIC18LFXX8X 500 500 A -40°C 300 500 A +25°C VDD = 2.0V 850 1000 A +85°C PIC18LFXX8X 500 900 A -40°C FOSC = 1MHZ, 500 900 A +25°C VDD = 3.0V EC oscillator 1 1.5 mA +85°C All devices 1 2 mA -40°C 1 2 mA +25°C VDD = 5.0V 1.3 3 mA +85°C PIC18LFXX8X 1 2 mA -40°C 1 2 mA +25°C VDD = 2.0V 1.5 2.5 mA +85°C PIC18LFXX8X 1.5 2 mA -40°C FOSC = 4MHz, 1.5 2 mA +25°C VDD = 3.0V EC oscillator 2 2.5 mA +85°C All devices 3 5 mA -40°C 3 5 mA +25°C VDD = 5.0V 4 6 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS30491D-page 418  2003-2013 Microchip Technology Inc.

18F8680.book Page 419 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.2 DC Characteristics: Power-down and Supply Current PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued) PIC18LFXX8X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX8X Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param. Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18FXX8X 13 27 mA -40°C 15 27 mA +25°C VDD = 4.2V 19 29 mA +85°C FOSC = 25MHZ, PIC18FXX8X 17 31 mA -40°C EC oscillator 21 31 mA +25°C VDD = 5.0V 23 34 mA +85°C PIC18FXX8X 20 34 mA -40°C 24 34 mA +25°C VDD = 4.2V 29 44 mA +85°C FOSC = 40MHZ, PIC18FXX8X 28 46 mA -40°C EC oscillator 33 46 mA +25°C VDD = 5.0V 40 51 mA +85°C D014 PIC18LFXX8X 27 45 A -10°C 30 50 A +25°C VDD = 2.0V 32 54 A +70°C PIC18LFXX8X 33 55 A -10°C FOSC = 32kHz, 36 60 A +25°C VDD = 3.0V Timer1 as clock 39 65 A +70°C All devices 75 125 A -10°C 90 150 A +25°C VDD = 5.0V 113 188 A +70°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2003-2013 Microchip Technology Inc. DS30491D-page 419

18F8680.book Page 420 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.2 DC Characteristics: Power-down and Supply Current PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued) PIC18LFXX8X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18FXX8X Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param. Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 Watchdog Timer <1 1.5 A -40C (IWDT) <1 2 A +25C VDD = 2.0V 5 20 A +85C 3 10 A -40C 3 20 A +25C VDD = 3.0V 10 35 A +85C 12 25 A -40C 15 35 A +25C VDD = 5.0V 20 50 A +85C D022A Brown-out Reset 55 115 A -40C to +85C VDD = 3.0V (IBOR) 105 175 A -40C to +85C VDD = 5.0V D022B Low-Voltage Detect 45 125 A -40C to +85C VDD = 2.0V (ILVD) 45 150 A -40C to +85C VDD = 3.0V 45 225 A -40C to +85C VDD = 5.0V D025 Timer1 Oscillator 20 27 A -10C (IOSCB) 20 30 A +25C VDD = 2.0V 32kHz on Timer1 25 35 A +70C 22 60 A -10C 22 65 A +25C VDD = 3.0V 32kHz on Timer1 25 75 A +70C 30 75 A -10C 30 85 A +25C VDD = 5.0V 32kHz on Timer1 35 100 A +70C D026 A/D Converter <1 2 A +25C VDD = 2.0V (IAD) <1 2 A +25C VDD = 3.0V A/D on, not converting <1 2 A +25C VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS30491D-page 420  2003-2013 Microchip Technology Inc.

18F8680.book Page 421 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V  VDD 5.5V D031 with Schmitt Trigger buffer VSS 0.2 VDD V RC3 and RC4 VSS 0.3 VDD V D032 MCLR VSS 0.2 VDD V D032A OSC1 (in XT, HS and LP modes) VSS 0.3 VDD V and T1OSI D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + VDD V VDD < 4.5V 0.8V D040A 2.0 VDD V 4.5V  VDD 5.5V D041 with Schmitt Trigger buffer 0.8 VDD VDD V RC3 and RC4 0.7 VDD VDD V D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V D042A OSC1 (in XT, HS and LP modes) 0.7 VDD VDD V and T1OSI D043 OSC1 (RC mode)(1) 0.9 VDD VDD V IIL Input Leakage Current(2,3) D060 I/O ports — 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR — 5 A Vss VPIN VDD D063 OSC1 — 5 A Vss VPIN VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested.  2003-2013 Microchip Technology Inc. DS30491D-page 421

18F8680.book Page 422 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC mode) -40C to +85C D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD – 0.7 — V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC mode) -40C to +85C D092A VDD – 0.7 — V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF In I2C mode Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS30491D-page 422  2003-2013 Microchip Technology Inc.

18F8680.book Page 423 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB 300 TRESP Response Time(1) — 150 400 ns PIC18FXX8X 300A 600 ns PIC18LFXX8X 301 TMC2OV Comparator Mode Change to — — 10 s Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD. TABLE 27-2: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/4 LSb Low Range (VRR = 1) — — 1/2 LSb High Range (VRR = 0) D312 VRUR Unit Resistor Value (R) — 2k —  310 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.  2003-2013 Microchip Technology Inc. DS30491D-page 423

18F8680.book Page 424 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-4: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be VLVD cleared in software) (LVDIF set by hardware) LVDIF TABLE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D420 LVD Voltage on LVV = 0000 — — — V VDD transition high LVV = 0001 1.96 2.06 2.16 V to low LVV = 0010 2.16 2.27 2.38 V LVV = 0011 2.35 2.47 2.59 V LVV = 0100 2.46 2.58 2.71 V LVV = 0101 2.64 2.78 2.92 V LVV = 0110 2.75 2.89 3.03 V LVV = 0111 2.95 3.1 3.26 V LVV = 1000 3.24 3.41 3.58 V LVV = 1001 3.43 3.61 3.79 V LVV = 1010 3.53 3.72 3.91 V LVV = 1011 3.72 3.92 4.12 V LVV = 1100 3.92 4.13 4.33 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.41 4.64 4.87 V D423 VBG Band Gap Reference Voltage — 1.22 — V Value † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. DS30491D-page 424  2003-2013 Microchip Technology Inc.

18F8680.book Page 425 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-4: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications (Note 1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.25 V (Note 2) D112 IPP Current into MCLR/VPP pin — — 5 A D113 IDDP Supply Current during — — 10 mA Programming Data EEPROM Memory D120 ED Cell Endurance 100K 1M — E/W -40C to +85C D120A ED Cell Endurance 10K 100K — E/W +85C to +125C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write, VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year -40C to +85C (Note 3) D123A TRETD Characteristic Retention 100 — — Year 25C (Note 3) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40C to +85C D130A EP Cell Endurance 1000 10K — E/W +85C to +125C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase 4.5 — 5.5 V Using ICSP port or Write D132B VPEW VDD for Self-timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time — 5 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time 1 — — ms VDD > 4.5V (externally timed) D133A TIW Self-timed Write Cycle Time — 2.5 — ms D134 TRETD Characteristic Retention 40 — — Year -40C to +85C (Note 3) D134A TRETD Characteristic Retention 100 — — Year 25C (Note 3) † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: The pin may be kept in this range at times other than programming but it is not recommended. 3: Retention time is valid provided no other specifications are violated.  2003-2013 Microchip Technology Inc. DS30491D-page 425

18F8680.book Page 426 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.4 AC (Timing) Characteristics 27.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS30491D-page 426  2003-2013 Microchip Technology Inc.

18F8680.book Page 427 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.4.2 TIMING CONDITIONS The temperature and voltages specified in Table27-5 apply to all timing specifications unless otherwise noted. Figure27-5 specifies the load conditions for the timing specifications. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial -40°C  TA  +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section27.1 and Section27.3. LC parts operate for industrial temperatures only. FIGURE 27-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS Pin CL RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports  2003-2013 Microchip Technology Inc. DS30491D-page 427

18F8680.book Page 428 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO, -40°C to +85°C DC 25 MHz EC,ECIO, -40°C to +85°C, EMA Oscillator Frequency(1) DC 25 MHz EC, ECIO, +85°C to +125°C DC 16 MHz EC, ECIO, +85°C to +125°C, EMA DC 4 MHz RC oscillator 0.1 4 MHz XT oscillator 4 25 MHz HS oscillator, -40°C to +85°C 4 25 MHz HS oscillator, -40°C to +85°C, EMA 4 25 MHz HS oscillator, +85°C to +125°C 4 16 MHz HS oscillator, +85°C to +125°C, EMA 4 10 MHz HS + PLL oscillator, -40°C to +85°C 4 6.25 MHz HS + PLL oscillator, +85°C to +125°C DC 200 kHz LP oscillator 1 TOSC External CLKI Period(1) 25 — ns EC, ECIO, -40°C to +85°C Oscillator Period(1) 40 — ns EC,ECIO, -40°C to +85°C, EMA 40 — ns EC, ECIO, +85°C to +125°C 62.5 — ns EC, ECIO, +85°C to +125°C, EMA 250 — ns RC oscillator 250 10,000 ns XT oscillator 40 — ns HS oscillator, -40°C to +85°C 40 — ns HS oscillator, -40°C to +85°C, EMA 40 — ns HS oscillator, +85°C to +125°C 62.5 — ns HS oscillator, +85°C to +125°C, EMA 100 250 ns HS + PLL oscillator, -40°C to +85°C 160 250 ns HS + PLL oscillator, +85°C to +125°C 5 200 s LP oscillator 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, -40°C to +85°C 160 — ns TCY = 4/FOSC, +85°C to +125°C 3 TOSL, External Clock in (OSC1) 30 — ns XT oscillator TOSH High or Low Time 2.5 — s LP oscillator 10 — ns HS oscillator 4 TOSR, External Clock in (OSC1) — 20 ns XT oscillator TOSF Rise or Fall Time — 50 ns LP oscillator — 7.5 ns HS oscillator Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS30491D-page 428  2003-2013 Microchip Technology Inc.

18F8680.book Page 429 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Param. Sym Characteristic Min Typ† Max Units Conditions No. — FOSC Oscillator Frequency Range 4 — 10 MHz HS mode — FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode — trc PLL Start-up Time (Lock Time) — — 2 ms — CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 27-7: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O Pin (Input) 17 15 I/O Pin Old Value New Value (Output) 20, 21 Note: Refer to Figure27-5 for load conditions.  2003-2013 Microchip Technology Inc. DS30491D-page 429

18F8680.book Page 430 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (1) 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (1) 12 TCKR CLKO Rise Time — 35 100 ns (1) 13 TCKF CLKO Fall Time — 35 100 ns (1) 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns (1) 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns (1) 16 TCKH2IOI Port In Hold after CLKO  0 — — ns (1) 17 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port PIC18FXX8X 100 — — ns 18A Input Invalid PIC18LFXX8X 200 — — ns (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns 20 TIOR Port Output Rise Time PIC18FXX8X — 10 25 ns 20A PIC18LFXX8X — — 60 ns 21 TIOF Port Output Fall Time PIC18FXX8X — 10 25 ns 21A PIC18LFXX8X — — 60 ns 22† TINP INT pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INT High or Low Time TCY — — ns 24† TRCP RC7:RC4 Change INT High or Low Time 20 ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 ALE 168 164 169 171 CE 171A OE 165 DS30491D-page 430  2003-2013 Microchip Technology Inc.

18F8680.book Page 431 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-9: PROGRAM MEMORY READ TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V) Param. Symbol Characteristics Min Typ Max Units No 150 TADV2ALL Address Out Valid to ALE (address 0.25 TCY – 10 — — ns setup time) 151 TALL2ADL ALE  to Address Out Invalid (address 5 — — ns hold time) 155 TALL2OEL ALE to OE  10 0.125 TCY — ns 160 TADZ2OEL AD High-Z to OE (bus release to OE) 0 — — ns 161 TOEH2ADD OE  to AD Driven 0.125 TCY – 5 — — ns 162 TADV2OEH LS Data Valid before OE (data setup time) 20 — — ns 163 TOEH2ADL OE  to Data In Invalid (data hold time) 0 — — ns 164 TALH2ALL ALE Pulse Width — 0.25 TCY — ns 165 TOEL2OEH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TALH2ALH ALE  to ALE  (cycle time) — 1 TCY — ns 167 TACC Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 TOE OE  to Data Valid — 0.5 TCY – 25 ns 169 TALL2OEH ALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TALH2CSL Chip Select Active to ALE  — — 10 ns 171A TUBL2OEH AD Valid to Chip Select Active 0.25 TCY – 20 — — ns FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB  2003-2013 Microchip Technology Inc. DS30491D-page 431

18F8680.book Page 432 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V) Param. Symbol Characteristics Min Typ Max Units No. 150 TADV2ALL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 — — ns 151 TALL2ADL ALE  to Address Out Invalid (address hold time) 5 — — ns 153 TWRH2ADL WRn  to Data Out Invalid (data hold time) 5 — — ns 154 TWRL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TADV2WRH Data Valid before WRn (data setup time) 0.5 TCY – 10 — — ns 157 TBSV2WRL Byte Select Valid before WRn (byte select setup time) 0.25 TCY — — ns 157A TWRH2BSI WRn  to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TALH2ALH ALE  to ALE  (cycle time) — 0.25 TCY — ns 171 TALH2CSL Chip Enable Active to ALE  — — 10 ns 171A TUBL2OEH AD Valid to Chip Enable Active 0.25 TCY – 20 — — ns FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure27-5 for load conditions. DS30491D-page 432  2003-2013 Microchip Technology Inc.

18F8680.book Page 433 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-11: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference 36 Voltage Stable TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period 7 18 33 ms (No Postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power up Timer Period 28 72 132 ms 34 TIOZ I/O High-Impedance from MCLR Low — 2 — s or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — s VDD  BVDD (see ) 36 TIVRST Time for Internal Reference — 20 50 s Voltage to become stable 37 TLVD Low-Voltage Detect Pulse Width 200 — — s VDD  VLVD FIGURE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure27-5 for load conditions.  2003-2013 Microchip Technology Inc. DS30491D-page 433

18F8680.book Page 434 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20 nS or TCY + 40 value N (1, 2, 4,..., 256) 45 TT1H T1CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, PIC18FXX8X 10 — ns with prescaler PIC18LFXX8X 25 — ns Asynchronous PIC18FXX8X 30 — ns PIC18LFXX8X 50 — ns 46 TT1L T1CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, PIC18FXX8X 10 — ns with prescaler PIC18LFXX8X 25 — ns Asynchronous PIC18FXX8X 30 — ns PIC18LFXX8X TBD TBD ns 47 TT1P T1CKI Synchronous Greater of: — ns N = prescale Input 20 nS or TCY + 40 value Period N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T1CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T1CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment DS30491D-page 434  2003-2013 Microchip Technology Inc.

18F8680.book Page 435 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-13: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure27-5 for load conditions. TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXX8X 10 — ns prescaler PIC18LFXX8X 20 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With PIC18FXX8X 10 — ns prescaler PIC18LFXX8X 20 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1,4 or 16) 53 TCCR CCPx Output Rise Time PIC18FXX8X — 25 ns PIC18LFXX8X — 45 ns 54 TCCF CCPx Output Fall Time PIC18FXX8X — 25 ns PIC18LFXX8X — 45 ns  2003-2013 Microchip Technology Inc. DS30491D-page 435

18F8680.book Page 436 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-14: PARALLEL SLAVE PORT TIMING (PIC18FXX8X) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure27-5 for load conditions. TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18FXX8X) Param. Symbol Characteristic Min Max Units Conditions No. 62 TDTV2WRH Data In Valid before WR  or CS  20 — ns (setup time) 25 — ns Extended Temp. range 63 TWRH2DTI WR  or CS  to Data–In PIC18FXX8X 20 — ns Invalid (hold time) PIC18LFXX8X 35 — ns 64 TRDL2DTV RD  and CS  to Data–Out Valid — 80 ns — 90 ns Extended Temp. range 65 TRDH2DTI RD  or CS  to Data–Out Invalid 10 30 ns 66 TIBFINH Inhibit of the IBF flag bit being cleared from — 3 TCY WR  or CS  DS30491D-page 436  2003-2013 Microchip Technology Inc.

18F8680.book Page 437 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-15: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure27-5 for load conditions. TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param. Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX8X — 25 ns PIC18LFXX8X — 45 ns 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXX8X — 25 ns (Master mode) PIC18LFXX8X — 45 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after PIC18FXX8X — 50 ns TSCL2DOV SCK Edge PIC18LFXX8X — 100 ns Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2003-2013 Microchip Technology Inc. DS30491D-page 437

18F8680.book Page 438 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-16: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure27-5 for load conditions. TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX8X — 25 ns PIC18LFXX8X 45 ns 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXX8X — 25 ns (Master mode) PIC18LFXX8X 45 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after PIC18FXX8X — 50 ns TSCL2DOV SCK Edge PIC18LFXX8X 100 ns 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns TDOV2SCL Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS30491D-page 438  2003-2013 Microchip Technology Inc.

18F8680.book Page 439 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-17: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure27-5 for load conditions. TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param. Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX8X — 25 ns PIC18LFXX8X 45 ns 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-Impedance 10 50 ns 78 TSCR SCK oUtput Rise Time (Master mode) PIC18FXX8X — 25 ns PIC18LFXX8X 45 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX8X — 50 ns TSCL2DOV PIC18LFXX8X 100 ns 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2003-2013 Microchip Technology Inc. DS30491D-page 439

18F8680.book Page 440 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-18: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure27-5 for load conditions. TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXX8X — 25 ns PIC18LFXX8X 45 ns 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-Impedance 10 50 ns 78 TSCR SCK Output Rise Time PIC18FXX8X — 25 ns (Master mode) PIC18LFXX8X — 45 ns 79 TSCF SCK Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX8X — 50 ns TSCL2DOV Edge PIC18LFXX8X — 100 ns 82 TSSL2DOV SDO Data Output Valid after SS  PIC18FXX8X — 50 ns Edge PIC18LFXX8X — 100 ns 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS30491D-page 440  2003-2013 Microchip Technology Inc.

18F8680.book Page 441 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-19: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure27-5 for load conditions. TABLE 27-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 27-20: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure27-5 for load conditions.  2003-2013 Microchip Technology Inc. DS30491D-page 441

18F8680.book Page 442 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s PIC18FXX8X must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18FXX8X must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s PIC18FXX8X must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s PIC18FXX8X must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 106 THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can Start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line. TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification) before the SCL line is released. DS30491D-page 442  2003-2013 Microchip Technology Inc.

18F8680.book Page 443 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-21: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure27-5 for load conditions. TABLE 27-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 27-22: MASTER SSP I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure27-5 for load conditions.  2003-2013 Microchip Technology Inc. DS30491D-page 443

18F8680.book Page 444 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-22: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start 1 MHz mode(1) TBD — ms D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107250ns, must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released. DS30491D-page 444  2003-2013 Microchip Technology Inc.

18F8680.book Page 445 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-23: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure27-5 for load conditions. TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXX8X — 40 ns PIC18LFXX8X — 100 ns 121 TCKRF Clock Out Rise Time and Fall Time PIC18FXX8X — 20 ns (Master mode) PIC18LFXX8X — 50 ns 122 TDTRF Data Out Rise Time and Fall Time PIC18FXX8X — 20 ns PIC18LFXX8X — 50 ns FIGURE 27-24: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure27-5 for load conditions. TABLE 27-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Hold before CK  (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK  (DT hold time) 15 — ns  2003-2013 Microchip Technology Inc. DS30491D-page 445

18F8680.book Page 446 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-25: A/D CONVERTER CHARACTERISTICS: PIC18F6585/8585/6680/8680 (INDUSTRIAL, EXTENDED) PIC18LF6585/8585/6680/8680 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit VREF = VDD  3.0V — — TBD bit VREF = VDD  3.0V A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD  3.0V — — TBD LSb VREF = VDD  3.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD  3.0V — — TBD LSb VREF = VDD  3.0V A05 EFS Full-Scale Error — — <±1 LSb VREF = VDD  3.0V — — TBD LSb VREF = VDD  3.0V A06 EOFF Offset Error — — <±1 LSb VREF = VDD  3.0V — — TBD LSb VREF = VDD  3.0V A10 — Monotonicity guaranteed(3) — VSS  VAIN  VREF A20 VREF Reference Voltage 0V — — V A20A (VREFH – VREFL) 3V — — V For 10-bit resolution A21 VREFH Reference Voltage High AVss — AVDD + 0.3V V A22 VREFL Reference Voltage Low AVss – 0.3V — AVDD V A25 VAIN Analog Input Voltage AVSS – 0.3V — VREF + 0.3V V A30 ZAIN Recommended Impedance of — — 10.0 k Analog Voltage Source A40 IAD A/D Conversion PIC18FXX8X — 180 — A Average current Current (VDD) PIC18LFXX8X — 90 — A consumption when A/D is on (Note 1) A50 IREF VREF Input Current (Note 2) — — 5 A During VAIN acquisition. — — 150 A During A/D conversion cycle. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected as reference input. 2: Vss  VAIN  VREF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. DS30491D-page 446  2003-2013 Microchip Technology Inc.

18F8680.book Page 447 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-25: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input. TABLE 27-26: A/D CONVERSION REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXX8X 1.6 20(5) s TOSC based, VREF  3.0V PIC18LFXX8X 3.0 20(5) s TOSC based, VREF full range PIC18FXX8X 2.0 6.0 s A/D RC mode PIC18LFXX8X 3.0 9.0 s A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 1) 132 TACQ Acquisition Time (Note 3) 15 — s -40C  Temp  +125C 10 — s 0C  Temp  +125C 135 TSWC Switching Time from Convert  Sample — (Note 4) 136 TAMP Amplifier Settling Time (Note 2) 1 — s This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section19.0 “10-bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.  2003-2013 Microchip Technology Inc. DS30491D-page 447

18F8680.book Page 448 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 448  2003-2013 Microchip Technology Inc.

18F8680.book Page 449 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean–3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 28-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 40 5.5V 36 Typical: statistical mean @ 25°C 32 Maximum: mean + 3 (-40°C to +85°C) 5.0V Minimum: mean – 3 (-40°C to +85°C) 28 4.5V 24 4.0V A) I (mDD20 16 3.5V 12 3.0V 8 4 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 28-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 48 44 5.5V 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) 5.0V Minimum: mean – 3 (-40°C to +85°C) 36 32 4.5V 28 4.0V A) I (mDD24 20 3.5V 16 3.0V 12 8 2.5V 4 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS30491D-page 449

18F8680.book Page 450 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 40 36 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) 32 Minimum: mean – 3 (-40°C to +85°C) 28 24 5.5V A) 5.0V (mDD 20 4.5V I 16 4.2V 12 8 4 0 4 5 6 7 8 9 10 FOSC (MHz) FIGURE 28-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) 45 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) 35 Minimum: mean – 3 (-40°C to +85°C) 30 5.5V 5.0V A)25 m 4.5V (D ID 20 4.2V 15 10 5 0 4 5 6 7 8 9 10 FOSC (MHz) DS30491D-page 450  2003-2013 Microchip Technology Inc.

18F8680.book Page 451 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 5 5.5V Typical: statistical mean @ 25°C 5.0V Maximum: mean + 3 (-40°C to +125°C) 4 Minimum: mean – 3 (-40°C to +125°C) 4.5V 4.0V 3 A) 3.5V m (D ID 3.0V 2 2.5V 2.0V 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FOSC (MHz) FIGURE 28-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 7 5.5V 6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 5.0V Minimum: mean – 3 (-40°C to +125°C) 5 4.5V 4.0V 4 A) m (D 3.5V D I3 3.0V 2.5V 2 2.0V 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS30491D-page 451

18F8680.book Page 452 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 1 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.9 5.5V 0.8 5.0V 4.5V 0.7 A) 4.0V m D (0.6 D 3.5V I 0.5 3.0V 0.4 2.5V 2.0V 0.3 0.2 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 28-8: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 6 5.5V 5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 4 5.0V 4.5V A) m D (3 D I 4.0V 2 3.5V 1 3.0V 2.5V 2.0V 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) DS30491D-page 452  2003-2013 Microchip Technology Inc.

18F8680.book Page 453 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 40 Typical: statistical mean @ 25°C 36 Maximum: mean + 3 (-40°C to +85°C) 5.5V Minimum: mean – 3 (-40°C to +85°C) 32 5.0V 28 4.5V 24 4.2V 4.0V A) (mD 20 D I 16 3.5V 12 3.0V 8 4 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 28-10: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 48 44 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 40 5.0V 36 4.5V 32 4.2V 28 4.0V A) (mD 24 D I 20 3.5V 16 12 3.0V 8 2.5V 4 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz)  2003-2013 Microchip Technology Inc. DS30491D-page 453

18F8680.book Page 454 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-11: TYPICAL AND MAXIMUM IT1OSC vs. VDD (TIMER1 AS SYSTEM CLOCK) 240 220 Typical: statistical mean @ 25°C Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) 200 180 160 140 A) (uD 120 D I 100 80 Max (70°C) 60 Typ (25°C) 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-12: AVERAGE FOSC vs. VDD FOR VARIOUS R’s (RC MODE, C = 20 pF, TEMP = 25°C) 6,000 Operation above 4MHz is not recomended. 5,000 333...333kk k 4,000 Hz) 55..11 kk q (k3,000 e Fr 2,000 1100 kk 1,000 110000 kk 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30491D-page 454  2003-2013 Microchip Technology Inc.

18F8680.book Page 455 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-13: AVERAGE FOSC vs. VDD FOR VARIOUS R’s (RC MODE, C = 100 pF, TEMP = 25°C) 2,200 2,000 1,800 33..33 kk 1,600 1,400 Hz)1,200 55..11 kk k q ( Fre1,000 800 1100 kk 600 400 200 110000k k 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-14: AVERAGE FOSC vs. VDD FOR VARIOUS R’s (RC MODE, C = 300 pF, TEMP = 25°C) 800 700 33..33 kk 600 500 55..11 kk Hz) q (M400 e Fr 300 1100 kk 200 100 110000 kk 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2003-2013 Microchip Technology Inc. DS30491D-page 455

18F8680.book Page 456 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-15: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 1000 Max (-40°C to +125°C) 100 Max (85°C) 10 A) I (uPD MTMyaipnxiiicmmaulu:mm:: msmtaeetaaisnnt i+–ca 33l m ((e--44a00n°° @CC tt2oo5 ++°11C2255°°CC)) 1 Typ (25°C) 0.1 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-16: TYPICAL AND MAXIMUM IBOR vs. VDD OVER TEMPERATURE, VBOR = 2.00V-2.16V 300 Device Typical: statistical mean @ 25°C 250 Held in Maximum: mean + 3 (-40°C to +125°C) Max (+125°C) Reset Minimum: mean – 3 (-40°C to +125°C) 200 Max (+85°C) A) (uD 150 D I Typ (+25°C) 100 Device in Sleep 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30491D-page 456  2003-2013 Microchip Technology Inc.

18F8680.book Page 457 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-17: IT1OSC vs. VDD (SLEEP MODE, TIMER1 AND OSCILLATOR ENABLED) 80 Typical: statistical mean @ 25°C 70 Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) Max (70°C) 60 50 A) (uD40 IP 30 20 Typ (25°C) 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-18: IPD vs. VDD (SLEEP MODE, WDT ENABLED) 1000 Max (-40°C to +125°C) Typical: statistical mean @ 25°C 100 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) Max (85°C) A) (uD 10 P I 1 Typ (25°C) 0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2003-2013 Microchip Technology Inc. DS30491D-page 457

18F8680.book Page 458 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 35 Minimum: mean – 3 (-40°C to +125°C) Max (125°C) 30 Max (85°C) s)25 m d ( erio20 Typ (25°C) P T WD 15 Min (-40°C) 10 5 0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 FIGURE 28-20: ILVD vs. VDD OVER TEMPERATURE, VLVD = 4.5-4.78V 250 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 200 Max (125°C) Max (125°C) 150 A) LVDIF state  is unknown (DD Typ (25°C) I 100 LVDIF can be cleared by firmware 50 Typ (25°C) LVDIF is set by hardware 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30491D-page 458  2003-2013 Microchip Technology Inc.

18F8680.book Page 459 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 MMaaxx 4.0 TTyypp ( +(2255C°C)) 3.5 V)3.0 (H VO 2.5 MMiinn 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 28-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.0 2.5 2.0 MMaaxx V) (H 1.5 O V TyTpy p(+ (2255°CC)) 1.0 MMinin 0.5 0.0 0 5 10 15 20 25 IOH (-mA)  2003-2013 Microchip Technology Inc. DS30491D-page 459

18F8680.book Page 460 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.8 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.2 1.0 V) (OL MMaaxx V0.8 0.6 0.4 TyTpy (p+ (2255°CC)) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 28-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 2.5 Typical: statistical mean @ 25°C 2.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.5 V) (OL V 1.0 MMaaxx TTypyp ( +(2255C°C)) 0.5 0.0 0 5 10 15 20 25 IOL (-mA) DS30491D-page 460  2003-2013 Microchip Technology Inc.

18F8680.book Page 461 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25°C 3.5 Maximum: mean + 3 (-40°C to +125°C) VIH Max Minimum: mean – 3 (-40°C to +125°C) 3.0 2.5 VIH Min V) (N 2.0 VI VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) VTH (Max) 1.2 VTH (Min) 1.0 V) (N 0.8 VI 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2003-2013 Microchip Technology Inc. DS30491D-page 461

18F8680.book Page 462 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-27: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C) 3.5 VIH Max Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.5 2.0 VVILIL MMaaxx V) (N VI VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-28: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) 4 3.5 --4400C°C SB) 3 L earity (2.5 +2255C°C n nli No +8855C°C gral 2 e nt al or I1.5 nti e er Diff 1 0.5 1+2152C5°C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) DS30491D-page 462  2003-2013 Microchip Technology Inc.

18F8680.book Page 463 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-29: A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 2.5 B) S L y ( arilt 2 e n nli o N al 1.5 gr e nt or I MMaaxx ((--4400°CC t oto 1 +2152C5)°C) al nti 1 e Differ TTyypp ((+2255C°)C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V)  2003-2013 Microchip Technology Inc. DS30491D-page 463

18F8680.book Page 464 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 464  2003-2013 Microchip Technology Inc.

18F8680.book Page 465 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX PIC18F6680 XXXXXXXXXX -I/PT XXXXXXXXXX 0410017 YYWWNNN 68-Lead PLCC Example XXXXXXXXXXXXXXXXX PIC18F6680-I/L XXXXXXXXXXXXXXXXX 0410017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F8680-E XXXXXXXXXXXX /PT YYWWNNN 0410017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2013 Microchip Technology Inc. DS30491D-page 465

18F8680.book Page 466 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 29.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A c A2 L   A1 (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 64 64 Pitch p .020 0.50 Pins per Side n1 16 16 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .005 .007 .009 0.13 0.18 0.23 Lead Width B .007 .009 .011 0.17 0.22 0.27 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085 DS30491D-page 466  2003-2013 Microchip Technology Inc.

18F8680.book Page 467 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 68-Lead Plastic Leaded Chip Carrier (L) –Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n12 CH2 x 45 CH1 x 45  A2 A3 A 32 c B1  B p A1 D2 E2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 68 68 Pitch p .050 1.27 Pins per Side n1 17 17 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .985 .990 .995 25.02 25.15 25.27 Overall Length D .985 .990 .995 25.02 25.15 25.27 Molded Package Width E1 .950 .954 .958 24.13 24.23 24.33 Molded Package Length D1 .950 .954 .958 24.13 24.23 24.33 Footprint Width E2 .890 .920 .930 22.61 23.37 23.62 Footprint Length D2 .890 .920 .930 22.61 23.37 23.62 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-049  2003-2013 Microchip Technology Inc. DS30491D-page 467

18F8680.book Page 468 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 B 1 n CH x 45 A  c   A2 L A1 (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 80 80 Pitch p .020 0.50 Pins per Side n1 20 20 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .541 .551 .561 13.75 14.00 14.25 Overall Length D .541 .551 .561 13.75 14.00 14.25 Molded Package Width E1 .463 .472 .482 11.75 12.00 12.25 Molded Package Length D1 .463 .472 .482 11.75 12.00 12.25 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .009 .011 0.17 0.22 0.27 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-092 DS30491D-page 468  2003-2013 Microchip Technology Inc.

18F8680.book Page 469 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (February 2003) The differences between the devices listed in this data Original data sheet for PIC18F6585/8585/6680/8680 sheet are shown in TableB-1. family. Revision B (June 2003) This revision includes updates to the Special Function Registers in Table4-2 and Table23-1 and minor corrections to the data sheet text. Revision C (February 2004) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section27.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text. Revision D (January 2013) Added a note to each package outline drawing. TABLE B-1: DEVICE DIFFERENCES Feature PIC18F6585 PIC18F6680 PIC18F8585 PIC18F8680 On-Chip Program Memory (Kbytes) 48 64 48 64 I/O Ports Ports A, B, C, D, Ports A, B, C, D, Ports A, B, C, D, Ports A, B, C, D, E, F, G E, F, G E, F, G, H, J E, F, G, H, J A/D Channels 12 12 16 16 External Memory Interface No No Yes Yes Package Types 64-pin TQFP, 64-pin TQFP, 80-pin TQFP 80-pin TQFP 68-pin PLCC 68-pin PLCC  2003-2013 Microchip Technology Inc. DS30491D-page 469

18F8680.book Page 470 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS MID-RANGE TO ENHANCED DEVICES This appendix discusses the considerations for con- verting from previous versions of a device to the ones A detailed discussion of the differences between the listed in this data sheet. Typically, these changes are mid-range MCU devices (i.e., PIC16CXXX) and the due to the differences in the process technology used. enhanced devices (i.e., PIC18FXXX) is provided in An example of this type of conversion is from a AN716, “Migrating Designs from PIC16C74A/74B to PIC17C756 to a PIC18F8720. PIC18C442.” The changes discussed, while device Not Applicable specific, are generally applicable to all mid-range to enhanced device migrations. This Application Note is available as Literature Number DS00716. DS30491D-page 470  2003-2013 Microchip Technology Inc.

18F8680.book Page 471 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration.” This Application Note is available as Literature Number DS00726.  2003-2013 Microchip Technology Inc. DS30491D-page 471

18F8680.book Page 472 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 472  2003-2013 Microchip Technology Inc.

18F8680.book Page 473 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 INDEX A ANDLW.............................................................................372 ANDWF.............................................................................373 A/D....................................................................................249 Assembler A/D Converter Interrupt, MPASM Assembler..................................................407 Configuring.......................................................253 Auto-Wake-up on Sync Acquisition Requirements.........................................254 Break Character.......................................................242 Acquisition Time........................................................254 ADCON0 Register.....................................................249 B ADCON1 Register.....................................................249 Baud Rate Generator.......................................................215 ADCON2 Register.....................................................249 BC.....................................................................................373 ADRESH Register.....................................................249 BCF..................................................................................374 ADRESH/ADRESL Registers...................................252 BF Status Flag..................................................................219 ADRESL Register.....................................................249 Bit Timing Configuration Registers Analog Port Pins.......................................................152 BRGCON1................................................................340 Analog Port Pins, BRGCON2................................................................340 Configuring.......................................................255 BRGCON3................................................................340 Associated Register Block Diagrams Summary..........................................................257 16-bit Byte Select Mode.............................................98 Automatic Acquisition Time.......................................255 16-bit Byte Write Mode...............................................96 Calculating Minimum Required 16-bit Word Write Mode..............................................97 Acquisition Time (Example)..............................254 A/D............................................................................252 CCP2 Trigger............................................................256 Analog Input Model...................................................253 Configuring the Module.............................................253 Baud Rate Generator...............................................215 Conversion Clock (TAD)............................................255 CAN Buffers and Protocol Engine............................276 Conversion Requirements........................................447 Capture Mode Operation..........................................170 Conversion Status Comparator (GO/DONE Bit).................................................252 Analog Input Model..........................................263 Conversions..............................................................256 Comparator I/O Operating Modes Converter Characteristics.........................................446 (diagram)..........................................................260 Minimum Charging Time...........................................254 Comparator Output...................................................262 Special Event Trigger Comparator Voltage Reference................................266 (CCP)................................................................171 Compare Mode Operation................................171, 176 Special Event Trigger Enhanced PWM........................................................178 (CCP2)..............................................................256 Low-Voltage Detect (LVD)........................................270 VREF+ and VREF- References...................................254 Low-Voltage Detect (LVD) with Absolute Maximum Ratings..............................................413 External Input...................................................270 AC (Timing) Characteristics..............................................426 MSSP (I2C Master Mode).........................................213 Load Conditions for Device MSSP (I2C Mode).....................................................198 Timing Specifications........................................427 MSSP (SPI Mode)....................................................189 Parameter Symbology..............................................426 On-Chip Reset Circuit.................................................33 Temperature and Voltage PIC18F6X8X Architecture..........................................10 Specifications....................................................427 PIC18F8X8X Architecture..........................................11 Timing Conditions.....................................................427 PLL.............................................................................25 ACKSTAT Status Flag......................................................219 PORT/LAT/TRIS Operation......................................125 ADCON0 Register.............................................................249 PORTA GO/DONE Bit............................................................252 RA3:RA0 and RA5 Pins....................................126 ADCON1 Register.............................................................249 RA4/T0CKI Pin.................................................126 ADCON2 Register.............................................................249 RA6 Pin (When Enabled as I/O).......................126 ADDLW.............................................................................371 PORTB ADDWF.............................................................................371 RB2:RB0 Pins...................................................129 ADDWFC..........................................................................372 RB3 Pin............................................................129 ADRESH Register.............................................................249 RB7:RB4 Pins...................................................128 ADRESH/ADRESL Registers...........................................252 PORTC (Peripheral Output ADRESL Register.............................................................249 Override)...........................................................131 Analog-to-Digital Converter. PORTD and PORTE See A/D. (Parallel Slave Port)..........................................152  2003-2013 Microchip Technology Inc. DS30491D-page 473

18F8680.book Page 474 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 PORTD in I/O Port Mode..........................................133 C PORTD in System Bus Mode...................................134 C Compilers PORTE in I/O Mode..................................................137 MPLAB C17..............................................................408 PORTE in System Bus Mode....................................137 MPLAB C18..............................................................408 PORTF MPLAB C30..............................................................408 RF1/AN6/C2OUT and CALL.................................................................................380 RF2/AN7/C1OUT Pins..............................139 Capture (CCP Module).....................................................169 RF6:RF3 and RF0 Pins.....................................140 CAN Message Time-Stamp......................................170 RF7 Pin.............................................................140 CCP Pin Configuration..............................................169 PORTG CCPRxH:CCPRxL Registers....................................169 RG0/CANTX1 Pin.............................................142 Software Interrupt.....................................................170 RG1/CANTX2 Pin.............................................143 Timer1/Timer3 Mode Selection.................................169 RG2/CANRX Pin...............................................143 Capture, Compare (CCP Module), RG3 Pin............................................................143 Timer1 and Timer3 RG4/P1D Pin....................................................144 Associated Registers................................................172 RG5/MCLR/VPP Pin..........................................144 Capture/Compare/PWM (CCP)........................................167 PORTH Capture Mode. RH3:RH0 Pins in I/O Mode...............................146 See Capture (CCP Module). RH3:RH0 Pins in CCP Module.............................................................169 System Bus Mode.....................................147 CCPRxH Register.....................................................169 RH7:RH4 Pins in I/O Mode...............................146 CCPRxL Register.....................................................169 PORTJ Compare Mode. RJ4:RJ0 Pins in See Compare (CCP Module). System Bus Mode.....................................150 Interaction of CCP1 and RJ7:RJ6 Pins in CCP2 Modules.................................................169 System Bus Mode.....................................150 PWM Mode. PORTJ in I/O Mode...................................................149 See PWM (CCP Module). PWM (CCP Module).................................................173 Timer Resources......................................................169 Reads from Flash Program Capture/Compare/PWM Memory...............................................................87 Requirements...........................................................435 Single Comparator....................................................261 CLKO and I/O Timing Requirements........................430, 431 Table Read Operation.................................................83 Clocking Scheme/Instruction Cycle....................................56 Table Write Operation.................................................84 CLRF................................................................................381 Table Writes to Flash Program CLRWDT..........................................................................381 Memory...............................................................89 Code Examples Timer0 in 16-bit Mode...............................................156 16 x 16 Signed Multiply Routine...............................108 Timer0 in 8-bit Mode.................................................156 16 x 16 Unsigned Multiply Routine...........................108 Timer1.......................................................................160 8 x 8 Signed Multiply Routine...................................107 Timer1 (16-bit Read/Write Mode).............................160 8 x 8 Unsigned Multiply Routine...............................107 Timer2.......................................................................163 Changing Between Capture Timer3.......................................................................165 Prescalers.........................................................170 Timer3 in 16-bit Read/Write Mode............................165 Changing to Configuration Mode..............................281 USART Receive........................................................240 Data EEPROM Read................................................103 USART Transmit.......................................................238 Data EEPROM Refresh Routine...............................104 Voltage Reference Data EEPROM Write................................................103 Output Buffer (example)....................................267 Erasing a Flash Program Watchdog Timer........................................................356 Memory Row......................................................88 BN.....................................................................................374 Fast Register Stack....................................................56 BNC...................................................................................375 How to Clear RAM (Bank 1) Using BNN...................................................................................375 Indirect Addressing.............................................79 BNOV................................................................................376 Initializing PORTA.....................................................125 BNZ...................................................................................376 Initializing PORTB.....................................................128 BOR. See Brown-out Reset. Initializing PORTC....................................................131 BOV...................................................................................379 Initializing PORTD....................................................133 BRA...................................................................................377 Initializing PORTE.....................................................136 Break Character (12-bit) Initializing PORTF.....................................................139 Transmit and Receive...............................................243 Initializing PORTG....................................................142 BRG. See Baud Rate Generator. Initializing PORTH....................................................146 Brown-out Reset (BOR)..............................................34, 345 Initializing PORTJ.....................................................149 BSF...................................................................................377 Loading the SSPBUF (SSPSR) BTFSC..............................................................................378 Register............................................................192 BTFSS...............................................................................378 Reading a Flash Program BTG...................................................................................379 Memory Word.....................................................87 BZ......................................................................................380 DS30491D-page 474  2003-2013 Microchip Technology Inc.

18F8680.book Page 475 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Saving Status, WREG and BSR Registers D in RAM..............................................................124 Data EEPROM Memory Transmitting a CAN Message Using Associated Registers................................................105 Banked Method.................................................289 EEADRH Transmitting a CAN Message Using EEADR Register Pair.......................................101 WIN Bits............................................................290 EECON1 Register....................................................101 WIN and ICODE Bits Usage in Interrupt EECON2 Register....................................................101 Service Routine to Access Operation During TX/RX Buffers...................................................281 Code-Protect....................................................104 Writing to Flash Program Memory........................90–91 Protection Against Code Protection................................................................345 Spurious Write..................................................104 COMF...............................................................................382 Reading....................................................................103 Comparator.......................................................................259 Using........................................................................104 Analog Input Connection Write Verify...............................................................104 Considerations..................................................263 Writing to..................................................................103 Associated Registers................................................264 Data Memory......................................................................59 Configuration.............................................................260 General Purpose Registers........................................59 Effects of a Reset......................................................263 Map for PIC18FXX80/XX85 Interrupts...................................................................262 Devices...............................................................60 Operation..................................................................261 Special Function Registers.........................................59 Operation During Sleep............................................263 DAW.................................................................................384 Outputs.....................................................................261 DC and AC Characteristics Reference.................................................................261 Graphs and Tables...................................................449 External Signal..................................................261 DC Characteristics Internal Signal...................................................261 PIC18FXX8X (Industrial and Response Time.........................................................261 Extended), PIC18LFXX8X Comparator Specifications................................................423 (Industrial).........................................................421 Comparator Voltage Power-down and Reference.................................................................265 Supply Current..................................................417 Accuracy and Error...................................................266 Supply Voltage.........................................................416 Associated Registers................................................267 DCFSNZ...........................................................................385 Configuring................................................................265 DECF................................................................................384 Connection Considerations.......................................266 DECFSZ...........................................................................385 Effects of a Reset......................................................266 Demonstration Boards Operation During Sleep............................................266 PICDEM 1.................................................................410 Compare (CCP Module)...................................................171 PICDEM 17...............................................................411 CCP Pin Configuration..............................................171 PICDEM 18R............................................................411 CCPRx Register........................................................171 PICDEM 2 Plus.........................................................410 Software Interrupt.....................................................171 PICDEM 3.................................................................410 Special Event Trigger................................161, 166, 171 PICDEM 4.................................................................410 Timer1/Timer3 Mode PICDEM LIN.............................................................411 Selection...........................................................171 PICDEM USB...........................................................411 Compare (CCP2 Module) PICDEM.net Internet/ Special Event Trigger................................................256 Ethernet............................................................410 Configuration Bits..............................................................345 Development Support.......................................................407 Configuration Mode...........................................................328 Device Differences............................................................469 Control Registers Device Features....................................................................9 EECON1 and EECON2..............................................84 Device Overview...................................................................9 TABLAT (Table Latch) Direct Addressing...............................................................78 Register..............................................................86 Disable Mode....................................................................328 TBLPTR (Table Pointer) Register..............................................................86 Conversion Considerations...............................................470 CPFSEQ...........................................................................382 CPFSGT...........................................................................383 CPFSLT............................................................................383  2003-2013 Microchip Technology Inc. DS30491D-page 475

18F8680.book Page 476 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 E Information Processing Time (IPT)..................................................................338 ECAN Module...................................................................275 Lengthening a Bit Period..........................................339 Baud Rate Setting.....................................................337 Listen Only Mode......................................................330 Bit Time Partitioning..................................................337 Loopback Mode........................................................330 Bit Timing Configuration Message Acceptance Filters Registers...........................................................340 and Masks................................................306, 335 Calculating TQ, Nominal Bit Rate and Message Acceptance Mask and Nominal Bit Time...............................................338 Filter Operation.................................................336 CAN Baud Rate Registers........................................315 Message Reception..................................................334 CAN Control and Status Enhanced FIFO Mode......................................335 Registers...........................................................277 Priority..............................................................334 CAN Controller Register Map...................................323 Time-Stamping.................................................335 CAN I/O Control Register..........................................318 Normal Mode............................................................328 CAN Interrupt Registers............................................319 Oscillator Tolerance..................................................340 CAN Interrupts..........................................................342 Overview...................................................................275 Acknowledge.....................................................343 Phase Buffer Segments............................................338 Bus Activity Wake-up........................................343 Programmable TX/RX and Bus-Off..............................................................343 Auto-RTR Buffers.............................................297 Code Bits..........................................................342 Programming Time Segments..................................340 Error..................................................................343 Propagation Segment...............................................338 Message Error..................................................343 Sample Point............................................................338 Receive.............................................................343 Shortening a Bit Period.............................................340 Receiver Bus Passive.......................................343 Synchronization........................................................339 Receiver Overflow.............................................343 Hard..................................................................339 Receiver Warning.............................................343 Resynchronization............................................339 Transmit............................................................342 Rules................................................................339 Transmitter Bus Passive...................................343 Synchronization Segment.........................................338 Transmitter Warning.........................................343 Time Quanta.............................................................338 CAN Message Buffers..............................................331 Electrical Characteristics..................................................413 Dedicated Receive............................................331 Enhanced Capture/Compare/PWM Dedicated Transmit...........................................331 (ECCP).....................................................................175 Programmable Auto-RTR.................................332 Outputs.....................................................................176 Programmable Enhanced PWM Mode. Transmit/Receive......................................331 See PWM (ECCP Module). CAN Message Transmission....................................332 Enhanced Universal Synchronous Aborting.............................................................332 Asynchronous Receiver Initiating.............................................................332 Transmitter (USART)................................................229 Priority...............................................................333 Errata....................................................................................7 CAN Modes of Operation..........................................328 Error Recognition Mode....................................................328 CAN Registers..........................................................277 Evaluation and Programming Tools..................................411 Configuration Mode...................................................328 Example SPI Mode Requirements Dedicated CAN Receive (Master Mode, CKE = 0)...........................................437 Buffer Registers................................................291 Example SPI Mode Requirements Dedicated CAN Transmit (Master Mode, CKE = 1)...........................................438 Buffer Registers................................................285 Example SPI Mode Requirements Disable Mode............................................................328 (Slave Mode, CKE = 0).............................................439 Error Detection..........................................................341 Example SPI Slave Mode Requirements Acknowledge.....................................................341 (CKE = 1)..................................................................440 Bit......................................................................341 External Clock Timing CRC..................................................................341 Requirements...........................................................428 Error Modes and Counters................................341 External Memory Interface..................................................93 Error States.......................................................341 16-bit Byte Select Mode..............................................98 Form..................................................................341 16-bit Byte Write Mode...............................................96 Stuff Bit.............................................................341 16-bit Mode.................................................................96 Error Modes State (diagram)....................................342 16-bit Mode Timing.....................................................99 Error Recognition Mode............................................330 16-bit Word Write Mode..............................................97 Filter-Mask Truth (table)............................................335 PIC18F8X8X External Bus - Functional Modes......................................................330 I/O Port Functions...............................................95 Mode 0 - Legacy Mode.....................................330 Program Memory Modes............................................93 Mode 1 - Enhanced Legacy Mode............................................330 Mode 2 - Enhanced FIFO Mode................................................331 DS30491D-page 476  2003-2013 Microchip Technology Inc.

18F8680.book Page 477 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 F Instruction Set...................................................................365 ADDLW.....................................................................371 Firmware Instructions........................................................365 ADDWF....................................................................371 Flash Program Memory......................................................83 ADDWFC..................................................................372 Associated Registers..................................................92 ANDLW.....................................................................372 Control Registers........................................................84 ANDWF....................................................................373 Erase Sequence.........................................................88 BC.............................................................................373 Erasing........................................................................88 BCF..........................................................................374 Operation During Code BN.............................................................................374 Protection............................................................92 BNC..........................................................................375 Reading.......................................................................87 BNN..........................................................................375 Table Pointer BNOV.......................................................................376 Boundaries Based on Operation.........................86 BNZ..........................................................................376 Table Pointer Boundaries...........................................86 BOV..........................................................................379 Table Reads and Table Writes...................................83 BRA..........................................................................377 Write Sequence..........................................................90 BSF...........................................................................377 Writing to.....................................................................89 BTFSC......................................................................378 Protection Against Spurious BTFSS......................................................................378 Writes..........................................................92 BTG..........................................................................379 Unexpected Termination.....................................92 BZ.............................................................................380 Write Verify.........................................................92 CALL.........................................................................380 G CLRF........................................................................381 General Call Address Support..........................................212 CLRWDT..................................................................381 GOTO...............................................................................386 COMF.......................................................................382 CPFSEQ...................................................................382 H CPFSGT...................................................................383 Hardware Multiplier...........................................................107 CPFSLT....................................................................383 Introduction...............................................................107 DAW.........................................................................384 Operation..................................................................107 DCFSNZ...................................................................385 Performance Comparison DECF........................................................................384 (table)................................................................107 DECFSZ...................................................................385 GOTO.......................................................................386 I INCF.........................................................................386 I/O Ports............................................................................125 INCFSZ.....................................................................387 I2C Bus Data Requirements INFSNZ.....................................................................387 (Slave Mode).............................................................442 IORLW......................................................................388 I2C Bus Start/Stop Bits Requirements IORWF......................................................................388 (Slave Mode).............................................................441 LFSR........................................................................389 I2C Mode MOVF.......................................................................389 General Call Address Support..................................212 MOVFF.....................................................................390 Master Mode MOVLB.....................................................................390 Operation..........................................................214 MOVLW....................................................................391 Read/Write Bit Information MOVWF....................................................................391 (R/W Bit)...................................................202, 203 MULLW.....................................................................392 Serial Clock (RC3/SCK/SCL)....................................203 MULWF....................................................................392 ID Locations..............................................................345, 362 NEGF........................................................................393 INCF..................................................................................386 NOP..........................................................................393 INCFSZ.............................................................................387 POP..........................................................................394 In-Circuit Debugger...........................................................362 PUSH........................................................................394 Resources (table)......................................................362 RCALL......................................................................395 In-Circuit Serial Programming RESET......................................................................395 (ICSP)...............................................................345, 362 RETFIE.....................................................................396 Indirect Addressing RETLW.....................................................................396 INDF and FSR Registers............................................79 RETURN...................................................................397 Operation....................................................................79 RLCF........................................................................397 Indirect File Operand..........................................................59 RLNCF......................................................................398 INFSNZ.............................................................................387 RRCF........................................................................398 Instruction Flow/Pipelining..................................................57 RRNCF.....................................................................399 Instruction Format.............................................................367 SETF........................................................................399  2003-2013 Microchip Technology Inc. DS30491D-page 477

18F8680.book Page 478 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SLEEP......................................................................400 M SUBFWP...................................................................400 Master SSP I2C Bus SUBLW.....................................................................401 Data Requirements...................................................444 SUBWF.....................................................................401 Master SSP I2C Bus Start/Stop Bits SUBWFB...................................................................402 Requirements...........................................................443 SWAPF.....................................................................402 Master Synchronous Serial Port (MSSP). TBLRD......................................................................403 See MSSP. TBLWT......................................................................404 Memory Organization TSTFSZ....................................................................405 Data Memory..............................................................59 XORLW.....................................................................405 PIC18F8X8X Program Memory Modes......................51 XORWF.....................................................................406 Extended Microcontroller....................................51 Summary Table.........................................................368 Microcontroller....................................................51 INT Interrupt (RB0/INT). Microprocessor...................................................51 See Interrupt Sources. Microprocessor with INTCON Registers............................................................111 Boot Block..................................................51 Inter-Integrated Circuit. See I2C. Program Memory........................................................51 Interrupt Sources...............................................................345 Memory Programming Requirements...............................425 A/D Conversion Complete........................................253 Migration from High-End to Capture Complete (CCP)..........................................170 Enhanced Devices....................................................471 Compare Complete (CCP)........................................171 Migration from Mid-Range to ECAN Module...........................................................342 Enhanced Devices....................................................470 INT0..........................................................................124 MOVF...............................................................................389 Interrupt-on-Change MOVFF.............................................................................390 (RB7:RB4).........................................................128 MOVLB.............................................................................390 PORTB, Interrupt-on-Change...................................124 MOVLW............................................................................391 RB0/INT Pin, External...............................................124 MOVWF............................................................................391 TMR0........................................................................124 MPLAB ASM30 Assembler, TMR0 Overflow.........................................................157 Linker, Librarian........................................................408 TMR1 Overflow.................................................159, 161 MPLAB ICD 2 In-Circuit Debugger...................................409 TMR2 to PR2 Match.................................................163 MPLAB ICE 2000 High-Performance Universal TMR2 to PR2 Match (PWM).....................162, 173, 177 In-Circuit Emulator....................................................409 TMR3 Overflow.................................................164, 166 MPLAB ICE 4000 High-Performance Universal Interrupts...........................................................................109 In-Circuit Emulator....................................................409 Context Saving During MPLAB Integrated Development Interrupts...........................................................124 Environment Software..............................................407 Control Registers......................................................111 MPLAB PM3 Device Programmer....................................409 Enable Registers.......................................................117 MPLINK Object Linker/ Flag Registers...........................................................114 MPLIB Object Librarian.............................................408 Logic (diagram).........................................................110 MSSP................................................................................189 Priority Registers.......................................................120 ACK Pulse........................................................202, 203 Reset Control Registers............................................123 Clock Stretching........................................................208 Interrupts, Flag Bits 10-bit Slave Receive Mode CCP Flag (CCPxIF Bit).............................169, 170, 171 (SEN = 1)..................................................208 IORLW..............................................................................388 10-bit Slave Transmit Mode..............................208 IORWF..............................................................................388 7-bit Slave Receive Mode IPR Registers....................................................................120 (SEN = 1)..................................................208 L 7-bit Slave Transmit Mode................................208 Clock Synchronization and the LFSR.................................................................................389 CKP Bit.............................................................209 Listen Only Mode..............................................................328 Control Registers (general).......................................189 Look-up Tables I2C Mode..................................................................198 Computed GOTO........................................................58 Acknowledge Sequence Timing.......................222 Table Reads/Table Writes..........................................58 Baud Rate Generator.......................................215 Loopback Mode.................................................................328 Bus Collision Low-Voltage Detect...........................................................269 During a Repeated Characteristics..........................................................424 Start Condition..................................226 Converter Characteristics.........................................424 Bus Collision During a Effects of a Reset......................................................273 Start Condition..........................................224 Operation..................................................................272 Bus Collision During a Current Consumption........................................273 Stop Condition..........................................227 During Sleep.....................................................273 Clock Arbitration...............................................216 Reference Voltage Set Point.............................273 Effect of a Reset...............................................223 Typical Application....................................................269 I2C Clock Rate w/BRG.....................................215 Low-Voltage ICSP Programming......................................363 LVD. See Low-Voltage Detect. DS30491D-page 478  2003-2013 Microchip Technology Inc.

18F8680.book Page 479 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Master Mode.....................................................213 Oscillator Selection...........................................................345 Reception..................................................219 Oscillator Start-up Timer (OST)..................................34, 345 Repeated Start Condition Oscillator Switching Feature Timing...............................................218 System Clock Switch Bit.............................................27 Transmission............................................219 Oscillator, Timer1..............................................159, 161, 166 Master Mode Start Condition............................217 Oscillator, Timer3..............................................................164 Module Operation.............................................202 Oscillator, WDT.................................................................355 Multi-Master Communication, P Bus Collision and Arbitration.................................................223 Packaging.........................................................................465 Multi-Master Mode............................................223 Details.......................................................................466 Registers...........................................................198 Marking.....................................................................465 Slave Mode.......................................................202 Parallel Slave Port (PSP)..........................................133, 152 Slave Mode, Addressing...................................202 Associated Registers................................................154 Slave Mode, Reception.....................................203 RE0/RD/AD8 Pin......................................................152 Slave Mode, Transmission...............................203 RE1/WR/AD9 Pin.....................................................152 Sleep Operation................................................223 RE2/CS/AD10 Pin....................................................152 Stop Condition Timing......................................222 Select (PSPMODE Bit).....................................133, 152 I2C Mode. See I2C. Parallel Slave Port Requirements Overview...................................................................189 (PIC18FXX8X)..........................................................436 SPI Mode..................................................................189 Phase Locked Loop (PLL)..................................................25 Associated Registers........................................197 PICkit 1 Flash Starter Kit..................................................411 Bus Mode Compatibility....................................197 PICSTART Plus Development Effects of a Reset.............................................197 Programmer..............................................................410 Enabling SPI I/O...............................................193 PIE Registers....................................................................117 Master Mode.....................................................194 Pin Functions Operation..........................................................192 AVDD...........................................................................21 Slave Mode.......................................................195 AVSS...........................................................................21 Slave Select OSC1/CLKI.................................................................12 Synchronization........................................195 OSC2/CLKO/RA6.......................................................12 Sleep Operation................................................197 RA0/AN0.....................................................................13 SPI Clock..........................................................194 RA1/AN1.....................................................................13 Typical Connection...........................................193 RA2/AN2/VREF-..........................................................13 SPI Mode. See SPI. RA3/AN3/VREF+.........................................................13 SSPBUF Register.....................................................194 RA4/T0CKI.................................................................13 SSPSR Register.......................................................194 RA5/AN4/LVDIN.........................................................13 MSSP Module RA6.............................................................................13 SPI Master/Slave Connection...................................193 RB0/INT0....................................................................14 MULLW.............................................................................392 RB1/INT1....................................................................14 MULWF.............................................................................392 RB2/INT2....................................................................14 RB3/INT3/CCP2.........................................................14 N RB4/KBI0....................................................................14 NEGF................................................................................393 RB5/KBI1/PGM...........................................................14 NOP..................................................................................393 RB6/KBI2/PGC...........................................................14 Normal Operation Mode....................................................328 RB7/KBI3/PGD...........................................................14 RC0/T1OSO/T13CKI..................................................15 O RC1/T1OSI/CCP2......................................................15 Opcode Field Descriptions................................................366 RC2/CCP1/P1A..........................................................15 OPTION_REG Register RC3/SCK/SCL............................................................15 PSA Bit......................................................................157 RC4/SDI/SDA.............................................................15 T0CS Bit....................................................................157 RC5/SDO....................................................................15 T0PS2:T0PS0 Bits....................................................157 RC6/TX/CK.................................................................15 T0SE Bit....................................................................157 RC7/RX/DT.................................................................15 Oscillator Configuration.......................................................23 RD0/PSP0/AD0..........................................................16 EC...............................................................................23 RD1/PSP1/AD1..........................................................16 ECIO...........................................................................23 RD2/PSP2/AD2..........................................................16 ECIO+PLL...................................................................23 RD3/PSP3/AD3..........................................................16 ECIO+SPLL................................................................23 RD4/PSP4/AD4..........................................................16 HS...............................................................................23 RD5/PSP5/AD5..........................................................16 HS+PLL......................................................................23 RD6/PSP6/AD6..........................................................16 HS+SPLL....................................................................23 RD7/PSP7/AD7..........................................................16 LP................................................................................23 RE0/RD/AD8..............................................................17 RC...............................................................................23 RE1/WR/AD9..............................................................17 RCIO...........................................................................23 XT...............................................................................23  2003-2013 Microchip Technology Inc. DS30491D-page 479

18F8680.book Page 480 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RE2/CS/AD10.............................................................17 PORTD.............................................................................152 RE3/AD11...................................................................17 Associated Registers................................................135 RE4/AD12...................................................................17 Functions..................................................................135 RE5/AD13/P1C...........................................................17 LATD Register..........................................................133 RE6/AD14/P1B...........................................................17 Parallel Slave Port (PSP) RE7/CCP2/AD15........................................................17 Function............................................................133 RF0/AN5.....................................................................18 PORTD Register.......................................................133 RF1/AN6/C2OUT........................................................18 TRISD Register.........................................................133 RF2/AN7/C1OUT........................................................18 PORTE RF3/AN8/C2IN+..........................................................18 Analog Port Pins.......................................................152 RF4/AN9/C2IN-...........................................................18 Associated Registers................................................138 RF5/AN10/C1IN+/CVREF............................................18 Functions..................................................................138 RF6/AN11/C1IN-.........................................................18 LATE Register..........................................................136 RF7/SS.......................................................................18 PORTE Register.......................................................136 RG0/CANTX1.............................................................19 PSP Mode Select RG1/CANTX2.............................................................19 (PSPMODE Bit)........................................133, 152 RG2/CANRX...............................................................19 RE0/RD/AD8 Pin......................................................152 RG3.............................................................................19 RE1/WR/AD9 Pin......................................................152 RG4/P1D.....................................................................19 RE2/CS/AD10 Pin.....................................................152 RG5/MCLR/VPP..........................................................12 TRISE Register.........................................................136 RH0/A16.....................................................................20 PORTF RH1/A17.....................................................................20 Associated Registers................................................141 RH2/A18.....................................................................20 Functions..................................................................141 RH3/A19.....................................................................20 LATF Register...........................................................139 RH4/AN12...................................................................20 PORTF Register.......................................................139 RH5/AN13...................................................................20 TRISF Register.........................................................139 RH6/AN14/P1C...........................................................20 PORTG RH7/AN15/P1B...........................................................20 Associated Registers................................................145 RJ0/ALE......................................................................21 Functions..................................................................145 RJ1/OE.......................................................................21 LATG Register..........................................................142 RJ2/WRL.....................................................................21 PORTG Register.......................................................142 RJ3/WRH....................................................................21 TRISG Register........................................................142 RJ4/BA0......................................................................21 PORTH RJ5/CE........................................................................21 Associated Registers................................................148 RJ6/LB........................................................................21 Functions..................................................................148 RJ7/UB........................................................................21 LATH Register..........................................................146 VDD..............................................................................21 PORTH Register.......................................................146 VSS..............................................................................21 TRISH Register.........................................................146 PIR Registers....................................................................114 PORTJ PLL Clock Timing Specifications.......................................429 Associated Registers................................................151 PLL Lock Time-out..............................................................34 Functions..................................................................151 Pointer, FSR........................................................................79 LATJ Register...........................................................149 POP...................................................................................394 PORTJ Register........................................................149 POR. See Power-on Reset. TRISJ Register.........................................................149 PORTA Postscaler, WDT Associated Registers................................................127 Assignment (PSA Bit)...............................................157 Functions..................................................................127 Rate Select LATA Register...........................................................125 (T0PS2:T0PS0 Bits).........................................157 PORTA Register.......................................................125 Power-down Mode. See Sleep. TRISA Register.........................................................125 Power-on Reset (POR)...............................................34, 345 PORTB Power-up Delays................................................................31 Associated Registers................................................130 Power-up Timer (PWRT)............................................34, 345 Functions..................................................................130 Prescaler LATB Register...........................................................128 Timer2......................................................................177 PORTB Register.......................................................128 Prescaler, Capture............................................................170 RB0/INT Pin, External...............................................124 Prescaler, Timer0.............................................................157 TRISB Register.........................................................128 Assignment (PSA Bit)...............................................157 PORTC Rate Select Associated Registers................................................132 (T0PS2:T0PS0 Bits).........................................157 Functions..................................................................132 Prescaler, Timer2.............................................................173 LATC Register..........................................................131 PRO MATE II Universal Device PORTC Register.......................................................131 Programmer..............................................................409 RC3/SCK/SCL Pin....................................................203 TRISC Register.........................................................131 DS30491D-page 480  2003-2013 Microchip Technology Inc.

18F8680.book Page 481 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Product Identification System...........................................487 Output Relationships Program Counter (Active-Low State)............................................179 PCL, PCLATH and PCLATU Programmable Dead-Band Delay.............................184 Registers.............................................................56 PWM Direction Change (diagram)............................183 Program Memory PWM Direction Change at Near 100% Instructions..................................................................57 Duty Cycle (diagram)........................................183 Two-Word...........................................................58 Setup for Operation..................................................187 Interrupt Vector...........................................................51 Start-up Considerations............................................186 Map and Stack for Q PIC18F6585/8585...............................................52 Map and Stack for Q Clock.....................................................................173, 177 PIC18F6680/8680...............................................52 R Memory Access for PIC18F8X8X Modes...........................................52 RAM. See Data Memory. Memory Maps for RC Oscillator.......................................................................24 PIC18F8X8X Modes...........................................53 RCALL..............................................................................395 Reset Vector...............................................................51 RCON Register.................................................................123 Program Memory Modes RCSTA Register Extended Microcontroller............................................93 SPEN Bit...................................................................229 Microcontroller............................................................93 Register File........................................................................59 Microprocessor...........................................................93 Register File Summary.................................................67–77 Microprocessor with Registers Boot Block...........................................................93 ADCON0 (A/D Control 0)..........................................249 Program Memory Write Timing ADCON1 (A/D Control 1)..........................................250 Requirements............................................................432 ADCON2 (A/D Control 2)..........................................251 Program Verification and BAUDCON (Baud Rate Control)...............................232 Code Protection........................................................359 BIE0 (Buffer Interrupt Enable 0)...............................322 Associated Registers................................................359 BnCON (TX/RX Buffer n Control, Configuration Register Receive Mode).................................................297 Protection..........................................................362 BnCON (TX/RX Buffer n Control, Data EEPROM Code Transmit Mode)................................................298 Protection..........................................................362 BnDLC (TX/RX Buffer n Data Length Memory Code Protection..........................................360 Code in Receive Mode)....................................304 Programming, Device Instructions....................................365 BnDLC (TX/RX Buffer n Data Length PSP. See Parallel Slave Port. Code in Transmit Mode)...................................305 PUSH................................................................................394 BnDm (TX/RX Buffer n Data Field Byte m PWM (CCP Module).........................................................173 in Receive Mode)..............................................303 CCPR1H:CCPR1L Registers....................................177 BnDm (TX/RX Buffer n Data Field Byte m CCPR1L:CCPR1H Registers....................................173 in Transmit Mode).............................................303 Duty Cycle.........................................................173, 177 BnEIDH (TX/RX Buffer n Extended Example Frequencies/ Identifier, High Byte in Resolutions...............................................174, 178 Receive Mode).................................................301 Period................................................................173, 177 BnEIDH (TX/RX Buffer n Extended Registers Associated with PWM Identifier, High Byte in and Timer2........................................................187 Transmit Mode)................................................301 Setup for PWM Operation.........................................174 BnEIDL (TX/RX Buffer n Extended TMR2 to PR2 Match.................................162, 173, 177 Identifier, Low Byte in PWM (CCP Module) and Timer2 Receive Mode).................................................302 Associated Registers................................................174 BnEIDL (TX/RX Buffer n Extended PWM (ECCP Module).......................................................177 Identifier, Low Byte in Effects of a Reset......................................................187 Transmit Mode)................................................302 Enhanced PWM Auto-Shutdown..............................184 BnSIDH (TX/RX Buffer n Standard Full-Bridge Application Identifier, High Byte in Example............................................................182 Receive Mode).................................................299 Full-Bridge Mode.......................................................181 BnSIDH (TX/RX Buffer n Standard Direction Change..............................................182 Identifier, High Byte in Half-Bridge Mode......................................................180 Transmit Mode)................................................299 Half-Bridge Output Mode BnSIDL (TX/RX Buffer n Standard Applications Example.......................................180 Identifier, Low Byte in Output Configurations...............................................177 Receive Mode).................................................300 Output Relationships (Active-High State)............................................178  2003-2013 Microchip Technology Inc. DS30491D-page 481

18F8680.book Page 482 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BnSIDL (TX/RX Buffer n Standard PIR3 (Peripheral Interrupt Identifier, Low Byte in Request 3)........................................................116 Transmit Mode).................................................300 PSPCON (Parallel Slave Port BRGCON1 (Baud Rate Control 1)............................315 Control).............................................................153 BRGCON2 (Baud Rate Control 2)............................316 RCON (Reset Control)..................................35, 82, 123 BRGCON3 (Baud Rate Control 3)............................317 RCSTA (Receive Status and BSEL0 (Buffer Select 0)............................................305 Control).............................................................231 CANCON (CAN Control)...........................................278 RXB0CON (Receive Buffer 0 CANSTAT (CAN Status)...........................................279 Control).............................................................291 CCP1CON (CCP1 Control)...............................167, 175 RXB1CON (Receive Buffer 1 CCP2CON (CCP2 Control).......................................168 Control).............................................................293 CIOCON (CAN I/O Control)......................................318 RXBnDLC (Receive Buffer n CMCON (Comparator Control).................................259 Data Length Code)...........................................295 COMSTAT RXBnDm (Receive Buffer n (CAN Communication Status)...........................284 Data Field Byte m)............................................296 CONFIG1H (Configuration 1 High)...........................347 RXBnEIDH (Receive Buffer n CONFIG2H (Configuration 2 High)...........................349 Extended Identifier, High Byte).........................294 CONFIG2L (Configuration 2 Low).............................348 RXBnEIDL (Receive Buffer n CONFIG3H (Configuration 3 High)...........................350 Extended Identifier, Low Byte)..........................295 CONFIG3L (Configuration 3 Low).............................349 RXBnSIDH (Receive Buffer n CONFIG3L (Configuration Byte).................................53 Standard Indentifier, High Byte).......................294 CONFIG4L (Configuration 4 Low).............................350 RXBnSIDL (Receive Buffer n CONFIG5H (Configuration 5 High)...........................351 Standard Identifier, Low Byte)..........................294 CONFIG5L (Configuration 5 Low).............................351 RXERRCNT (Receive Error Count)..........................296 CONFIG6H (Configuration 6 High)...........................352 RXFnEIDH (Receive Acceptance CONFIG6L (Configuration 6 Low).............................352 Filter n Extended Identifier, CONFIG7H (Configuration 7 High)...........................353 High Byte).........................................................307 CONFIG7L (Configuration 7 Low).............................353 RXFnEIDL (Receive Acceptance CVRCON (Comparator Voltage Filter n Extended Identifier, Reference Control)............................................265 Low Byte)..........................................................307 Device ID 1...............................................................354 RXFnSIDH (Receive Acceptance Device ID 2...............................................................354 Filter n Standard Identifier Filter, ECANCON (Enhanced CAN Control).......................283 High Byte).........................................................306 ECCP1AS (ECCP1 Auto-Shutdown RXFnSIDL (Receive Acceptance Control).............................................................185 Filter n Standard Identifier Filter, ECCP1DEL (ECCP1 Delay).....................................184 Low Byte)..........................................................306 EECON1 (Data EEPROM RXMnEIDH (Receive Acceptance Control 1)....................................................85, 102 Mask n Extended Identifier Mask, INTCON (Interrupt Control).......................................111 High Byte).........................................................308 INTCON2 (Interrupt Control 2)..................................112 RXMnEIDL (Receive Acceptance INTCON3 (Interrupt Control 3)..................................113 Mask n Extended Identifier Mask, IPR1 (Peripheral Interrupt Low Byte)..........................................................308 Priority 1)...........................................................120 RXMnSIDH (Receive Acceptance IPR2 (Peripheral Interrupt Mask n Standard Identifier Mask, Priority 2)...........................................................121 High Byte).........................................................307 IPR3 (Peripheral Interrupt RXMnSIDL (Receive Acceptance Priority 3)...................................................122, 321 Mask n Standard Identifier Mask, LVDCON (LVD Control)............................................271 Low Byte)..........................................................308 MEMCON (Memory Control).......................................94 SSPCON1 (MSSP Control 1 OSCCON (Oscillator Control).....................................27 in SPI Mode).....................................................191 PIE1 (Peripheral Interrupt SSPCON2 (MSSP Control 2 Enable 1)...........................................................117 in I2C Mode).....................................................201 PIE2 (Peripheral Interrupt SSPSTAT (MSSP Status Enable 2)...........................................................118 in SPI Mode)....................................................190 PIE3 (Peripheral Interrupt Status.........................................................................81 Enable 3)...................................................119, 320 STKPTR (Stack Pointer).............................................55 PIR1 (Peripheral Interrupt T0CON (Timer0 Control)..........................................155 Request 1)........................................................114 T1CON (Timer 1 Control).........................................159 PIR2 (Peripheral Interrupt T2CON (Timer2 Control)..........................................162 Request 2)........................................................115 T3CON (Timer3 Control)..........................................164 PIR3 (Peripheral Interrupt Flag 3)...............................................................319 DS30491D-page 482  2003-2013 Microchip Technology Inc.

18F8680.book Page 483 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TXBIE (Transmit Buffers SPI Interrupt Enable)...............................................322 Serial Clock..............................................................189 TXBnCON (Transmit Buffer n Serial Data In............................................................189 Control).............................................................285 Serial Data Out.........................................................189 TXBnDLC (Transmit Buffer n Slave Select..............................................................189 Data Length Code)...........................................288 SPI Mode..................................................................189 TXBnDm (Transmit Buffer n SPI Master/Slave Connection...........................................193 Data Field Byte m)............................................287 SPI Mode TXBnEIDH (Transmit Buffer n Master/Slave Connection.........................................193 Extended Identifier, High Byte).........................286 SS.....................................................................................189 TXBnEIDL (Transmit Buffer n SSP Extended Identifier, Low Byte)..........................287 TMR2 Output for Clock Shift.............................162, 163 TXBnSIDH (Transmit Buffer n SSPOV Status Flag..........................................................219 Standard Identifier, High Byte)..........................286 SSPSTAT Register TXBnSIDL (Transmit Buffer n R/W Bit.............................................................202, 203 Standard Identifier, Low Byte)..........................286 Status Bits TXERRCNT (Transmit Error Count).........................288 Significance and Initialization TXSTA (Transmit Status and Condition for RCON Register.............................35 Control).............................................................230 SUBFWP..........................................................................400 WDTCON (Watchdog Timer SUBLW.............................................................................401 Control).............................................................355 SUBWF.............................................................................401 RESET..............................................................................395 SUBWFB..........................................................................402 Reset...........................................................................33, 345 SWAPF.............................................................................402 Reset, Watchdog Timer, Oscillator T Start-up Timer, Power-up Timer and Brown-out Reset Requirements................................433 Table Pointer Operations RETFIE.............................................................................396 (table).........................................................................86 RETLW.............................................................................396 TBLRD..............................................................................403 RETURN...........................................................................397 TBLWT.............................................................................404 Return Address Stack Time-out in Various and Associated Registers...........................................55 Situations....................................................................35 Stack Pointer (STKPTR).............................................54 Time-out Sequence............................................................34 Top-of-Stack Access...................................................54 Timer0..............................................................................155 Revision History................................................................469 16-bit Mode Timer Reads and RLCF.................................................................................397 Writes...............................................................157 RLNCF..............................................................................398 Associated Registers................................................157 RRCF................................................................................398 Clock Source Edge Select RRNCF.............................................................................399 (T0SE Bit).........................................................157 Clock Source Select S (T0CS Bit).........................................................157 SCK...................................................................................189 Operation..................................................................157 SDI....................................................................................189 Overflow Interrupt.....................................................157 SDO..................................................................................189 Prescaler..................................................................157 Serial Clock, SCK.............................................................189 Switching Assignment......................................157 Serial Data In, SDI............................................................189 Prescaler. See Prescaler, Timer0. Serial Data Out, SDO........................................................189 Timer0 and Timer1 External Clock Serial Peripheral Interface. See SPI. Requirements...........................................................434 SETF.................................................................................399 Timer1..............................................................................159 Slave Select, SS...............................................................189 16-bit Read/Write Mode............................................161 SLEEP..............................................................................400 Associated Registers................................................161 Sleep.........................................................................345, 357 Operation..................................................................160 Software Simulator Oscillator...........................................................159, 161 (MPLAB SIM)............................................................408 Overflow Interrupt.............................................159, 161 Software Simulator Special Event Trigger (MPLAB SIM30)........................................................408 (CCP)........................................................161, 171 Special Event Trigger. See Compare. TMR1H Register.......................................................159 Special Features of the CPU............................................345 TMR1L Register.......................................................159 Configuration Registers....................................347–353 Special Function Registers.................................................59 Map.............................................................................61  2003-2013 Microchip Technology Inc. DS30491D-page 483

18F8680.book Page 484 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Timer2...............................................................................162 Example SPI Slave Mode Associated Registers................................................163 (CKE = 0)..........................................................439 Operation..................................................................162 Example SPI Slave Mode Postscaler. See Postscaler, Timer2. (CKE = 1)..........................................................440 PR2 Register.............................................162, 173, 177 External Clock (All Modes Prescaler. See Prescaler, Timer2. except PLL)......................................................428 SSP Clock Shift.................................................162, 163 External Program Memory Bus TMR2 Register..........................................................162 (16-bit Mode)......................................................99 TMR2 to PR2 Match First Start Bit.............................................................217 Interrupt.....................................162, 163, 173, 177 Full-Bridge PWM Output...........................................181 Timer3...............................................................................164 Half-Bridge PWM Output..........................................180 Associated Registers................................................166 I2C Bus Data.............................................................441 Operation..................................................................165 I2C Bus Start/Stop Bits.............................................441 Oscillator...........................................................164, 166 I2C Master Mode (7 or Overflow Interrupt.............................................164, 166 10-bit Transmission).........................................220 Special Event Trigger I2C Master Mode (CCP)................................................................166 (7-bit Reception)...............................................221 TMR3H Register.......................................................164 I2C Slave Mode (10-bit Reception, TMR3L Register........................................................164 SEN = 0)...........................................................206 Timing Diagrams I2C Slave Mode (10-bit Reception, A/D Conversion.........................................................447 SEN = 1)...........................................................211 Acknowledge Sequence...........................................222 I2C Slave Mode Asynchronous Reception..........................................241 (10-bit Transmission)........................................207 Asynchronous Transmission.....................................238 I2C Slave Mode (7-bit Reception, Asynchronous Transmission SEN = 0)...........................................................204 (Back to Back)...................................................238 I2C Slave Mode (7-bit Reception, Automatic Baud Rate SEN = 1)...........................................................210 Calculation........................................................236 I2C Slave Mode Auto-Wake-up Bit (WUE) During (7-bit Transmission)..........................................205 Normal Operation..............................................242 Low-Voltage Detect..................................................272 Auto-Wake-up Bit (WUE) Master SSP I2C Bus Data.........................................443 During Sleep.....................................................242 Master SSP I2C Bus Baud Rate Generator with Start/Stop Bits...................................................443 Clock Arbitration................................................216 Parallel Slave Port BRG Reset Due to SDA Arbitration During (PIC18FXX8X)..................................................436 Start Condition..................................................225 Parallel Slave Port (PSP) Brown-out Reset (BOR)............................................433 Read.................................................................154 Bus Collision During a Repeated Parallel Slave Port (PSP) Start Condition (Case 1)...................................226 Write.................................................................153 Bus Collision During a Repeated Program Memory Read............................................430 Start Condition (Case 2)...................................226 Program Memory Write.............................................431 Bus Collision During a Stop Condition PWM Auto-Shutdown (PRSEN = 0, (Case 1)............................................................227 Auto-Restart Disabled).....................................186 Bus Collision During a Stop Condition PWM Auto-Shutdown (PRSEN = 1, (Case 2)............................................................227 Auto-Restart Enabled)......................................186 Bus Collision During Start Condition PWM Output.............................................................173 (SCL = 0)..........................................................225 Repeat Start Condition.............................................218 Bus Collision During Start Condition Reset, Watchdog Timer (WDT), (SDA only).........................................................224 Oscillator Start-up Timer (OST) Bus Collision for Transmit and and Power-up Timer (PWRT)...........................432 Acknowledge....................................................223 Send Break Character Sequence.............................243 Capture/Compare/PWM Slave Mode General Call Address (All CCP Modules)............................................435 Sequence (7 or 10-bit CLKO and I/O...........................................................429 Address Mode).................................................212 Clock Synchronization..............................................209 Slave Synchronization..............................................195 Clock/Instruction Cycle...............................................56 Slow Rise Time (MCLR Tied to VDD Example SPI Master Mode via 1 kResistor)...............................................50 (CKE = 0)..........................................................437 SPI Mode (Master Mode)..........................................194 Example SPI Master Mode SPI Mode (Slave Mode with (CKE = 1)..........................................................438 CKE = 0)...........................................................196 DS30491D-page 484  2003-2013 Microchip Technology Inc.

18F8680.book Page 485 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SPI Mode (Slave Mode with Baud Rate Generator (BRG)....................................233 CKE = 1)...........................................................196 Associated Registers........................................233 Stop Condition Receive or Auto-Baud Rate Detect.....................................236 Transmit Mode..................................................222 Baud Rate Error, Calculating............................233 Synchronous Reception Baud Rates, Asynchronous (Master Mode, SREN)......................................246 Modes.......................................................234 Synchronous Transmission.......................................244 High Baud Rate Select Synchronous Transmission (BRGH Bit)...............................................233 (Through TXEN)...............................................245 Sampling..........................................................233 Time-out Sequence on POR w/PLL Serial Port Enable (SPEN Bit)..................................229 Enabled (MCLR Tied to VDD Synchronous Master Mode.......................................244 via 1 kResistor)...............................................50 Associated Registers, Time-out Sequence on Power-up Reception.................................................246 (MCLR Not Tied to VDD) Associated Registers, Case 1................................................................49 Transmit...................................................245 Case 2................................................................49 Reception.........................................................246 Time-out Sequence on Power-up Transmission....................................................244 (MCLR Tied to VDD Synchronous Slave Mode.........................................247 via 1 kResistor)...............................................49 Associated Registers, Timer0 and Timer1 External Clock...........................433 Receive....................................................248 Transition Between Timer1 and OSC1 Associated Registers, (EC with PLL Active, SCS1 = 1).........................29 Transmit...................................................247 Transition Between Timer1 and OSC1 Reception.........................................................248 (HS with PLL Active, SCS1 = 1).........................29 Transmission....................................................247 Transition Between Timer1 and OSC1 USART Synchronous Receive (HS, XT, LP).......................................................28 Requirements...........................................................445 Transition Between Timer1 and USART Synchronous Transmission OSC1 (RC, EC)..................................................30 Requirements...........................................................445 Transition from OSC1 to V Timer1 Oscillator.................................................28 USART Synchronous Receive Voltage Reference Specifications.....................................423 (Master/Slave)..................................................445 W USART Synchronous Transmission (Master/Slave)..................................................445 Wake-up from Sleep.................................................345, 357 Wake-up from Sleep via Interrupt.............................358 Using Interrupts........................................................357 TRISE Register Watchdog Timer (WDT)............................................345, 355 PSPMODE Bit...................................................133, 152 Associated Registers................................................356 TSTFSZ............................................................................405 Control Register........................................................355 Two-Word Instructions Postscaler.........................................................355, 356 Example Cases...........................................................58 Programming Considerations...................................355 TXSTA Register RC Oscillator............................................................355 BRGH Bit..................................................................233 Time-out Period........................................................355 WCOL...............................................................................217 U WCOL Status Flag....................................217, 218, 219, 222 USART WWW, On-Line Support.......................................................7 Asynchronous Mode.................................................237 X 12-bit Break Transmit and Receive.....................................................243 XORLW............................................................................405 Associated Registers, Receive.........................241 XORWF............................................................................406 Associated Registers, Transmit........................239 Auto-Wake-up on Sync Break..........................242 Receiver............................................................240 Setting up 9-bit Mode with Address Detect.........................................240 Transmitter........................................................237  2003-2013 Microchip Technology Inc. DS30491D-page 485

18F8680.book Page 486 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 486  2003-2013 Microchip Technology Inc.

18F8680.book Page 487 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2003-2013 Microchip Technology Inc. DS30491D-page 487

18F8680.book Page 488 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F6585/8585/6680/8680 Literature Number: DS30491D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS30491D-page 488  2003-2013 Microchip Technology Inc.

18F8680.book Page 489 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 PIC18F6585/8585/6680/8680 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF6680 - I/PT 301 = Industrial Range temp., TQFP package, Extended VDD limits, QTP pattern #301. b) PIC18F8585 - I/PT = Industrial temp., Device PIC18FXX8X(1), PIC18FXX8XT(2); TQFP package, normal VDD limits. VDD range 4.2V to 5.5V c) PIC18F8680 - E/PT = Extended temp., PIC18LFXX8X(1), PIC18LFXX8XT(2); TQFP package, standard VDD limits. VDD range 2.0V to 5.5V Temperature I = -40C to+85C (Industrial) Range E = -40C to+125C (Extended) Package PT = TQFP (Thin Quad Flatpack) Note 1:F = Standard Voltage Range LF = Extended Voltage Range Pattern QTP, SQTP, Code or Special Requirements 2:T = in tape and reel (blank otherwise)  2003-2013 Microchip Technology Inc. DS30491D-page 489

18F8680.book Page 490 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 490  2003-2013 Microchip Technology Inc.

18F8680.book Page 491 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES:  2003-2013 Microchip Technology Inc. DS30491D-page 491

18F8680.book Page 492 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 492  2003-2013 Microchip Technology Inc.

18F8680.book Page 493 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES:  2003-2013 Microchip Technology Inc. DS30491D-page 493

18F8680.book Page 494 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 DS30491D-page 494  2003-2013 Microchip Technology Inc.

18F8680.book Page 495 Tuesday, January 29, 2013 1:32 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2003-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769638 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == adreev ifcoer sit,s S PeIrCia®l MEECPURsO aMnds ,d msPicIrCo®p eDrSipChse,r aKlEsE, LnOonQv®o cloadtilee hmoepmpionrgy and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2003-2013 Microchip Technology Inc. DS30491D-page 495

18F8680.book Page 496 Tuesday, January 29, 2013 1:32 PM Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Osaka Germany - Munich Duluth, GA China - Beijing Tel: 81-6-6152-7160 Tel: 49-89-627-144-0 Tel: 86-10-8569-7000 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-6-6152-9310 Fax: 678-957-1455 Fax: 86-10-8528-2104 Japan - Tokyo Italy - Milan China - Chengdu Tel: 39-0331-742611 Boston Tel: 81-3-6880- 3770 Tel: 86-28-8665-5511 Fax: 39-0331-466781 Westborough, MA Fax: 81-3-6880-3771 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Daegu Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 Korea - Seoul Spain - Madrid Tel: 630-285-0071 China - Hangzhou Tel: 82-2-554-7200 Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91 Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham Independence, OH China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 852-2943-5100 Tel: 60-3-6201-9857 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859 Dallas China - Nanjing Malaysia - Penang Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Fax: 972-818-2924 China - Qingdao Philippines - Manila Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Farmington Hills, MI Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Singapore Tel: 86-21-5407-5533 Tel: 65-6334-8870 Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850 Noblesville, IN Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366 Fax: 86-24-2334-2393 Fax: 886-3-5770-955 Los Angeles Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung Tel: 949-462-9523 Tel: 86-755-8864-2200 Tel: 886-7-213-7828 Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Santa Clara China - Wuhan Taiwan - Taipei Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Fax: 408-961-6445 China - Xian Thailand - Bangkok Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 11/29/12 DS30491D-page 496  2003-2013 Microchip Technology Inc.