PIC18F2X1X/4X1X 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Power-Managed Modes: Flexible Oscillator Structure: • Run: CPU On, Peripherals On • Four Crystal modes, Up to 40MHz • Idle: CPU Off, Peripherals On • 4x Phase Lock Loop (PLL) – Available for Crystal • Sleep: CPU Off, Peripherals Off and Internal Oscillators • Idle mode Currents Down to 3.0μA Typical • Two External RC modes, Up to 4 MHz • Sleep mode Currents Down to 20nA Typical • Two External Clock modes, Up to 40 MHz • Timer1 Oscillator: 1.8μA, 32kHz, 2V • Internal Oscillator Block: • Watchdog Timer: 2.1μA - 8 user-selectable frequencies, from 31kHz to • Two-Speed Oscillator Start-up 8MHz - Provides a complete range of clock speeds Peripheral Highlights: from 31kHz to 32MHz when used with PLL - User-tunable to compensate for frequency drift • High-Current Sink/Source 25mA/25mA • Secondary Oscillator using Timer1 @ 32 kHz • Up to 2 Capture/Compare/PWM (CCP) modules, • Fail-Safe Clock Monitor: One with Auto-Shutdown (28-pin devices) - Allows for safe shutdown if peripheral clock stops • Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): Special Microcontroller Features: - One, two or four PWM outputs - Selectable polarity • C Compiler Optimized Architecture: - Programmable dead time - Optional extended instruction set designed to - Auto-shutdown and auto-restart optimize re-entrant code • Master Synchronous Serial Port (MSSP) module • 100,000 Erase/Write Cycle Flash Program Supporting 3-Wire SPI (all 4 modes) and I2C™ Memory Typical Master and Slave modes • Three Programmable External Interrupts • Enhanced Addressable USART module: • Four Input Change Interrupts - Supports RS-485, RS-232 and LIN 1.2 • Priority Levels for Interrupts - RS-232 operation using internal oscillator • 8 x 8 Single-Cycle Hardware Multiplier block (no external crystal required) • Extended Watchdog Timer (WDT): - Auto-wake-up on Start bit - Programmable period from 4ms to 131s - Auto-Baud Detect • Single-Supply 5V In-Circuit Serial • 10-Bit, Up to 13-Channel Analog-to-Digital Programming™ (ICSP™) via Two Pins Converter module (A/D): • In-Circuit Debug (ICD) via Two Pins - Auto-acquisition capability • Wide Operating Voltage Range: 2.0V to 5.5V - Conversion available during Sleep • Programmable Brown-out Reset (BOR) with • Dual Analog Comparators with Input Multiplexing Software Enable Option • Programmable 16-Level High/Low-Voltage Detection (HLVD) module: - Supports interrupt on High/Low-Voltage Detection © 2009 Microchip Technology Inc. DS39636D-page 3

PIC18F2X1X/4X1X Data Program Memory MSSP T Device Flash # Single-Word M SeRmAoMry I/O A1/D0- B(ciht) CC(PPW/EMCC)P Master USAR Comp. 8T/i1m6e-Brsit (bytes) Instructions (bytes) SPI I2C™ E PIC18F2410 16K 8192 768 25 10 2/0 Y Y 1 2 1/3 PIC18F2510 32K 16384 1536 25 10 2/0 Y Y 1 2 1/3 PIC18F2515 48K 24576 3968 25 10 2/0 Y Y 1 2 1/3 PIC18F2610 64K 32768 3968 25 10 2/0 Y Y 1 2 1/3 PIC18F4410 16K 8192 768 36 13 1/1 Y Y 1 2 1/3 PIC18F4510 32K 16384 1536 36 13 1/1 Y Y 1 2 1/3 PIC18F4515 48K 24576 3968 36 13 1/1 Y Y 1 2 1/3 PIC18F4610 64K 32768 3968 36 13 1/1 Y Y 1 2 1/3 DS39636D-page 4 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X Pin Diagrams 28-pin SPDIP, SOIC MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6//KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 25 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 X 24 RB3/AN9/CCP2(1) RA4/T0CKI/C1OUT 6 X1 23 RB2/INT2/AN8 RA5/AN4/SS/HLVDIN/C2OUT 7 2 22 RB1/INT1/AN10 F VSS 8 8 21 RB0/INT0/FLT0/AN12 1 OSC1/CLKI/RA7 9 C 20 VDD OSC2/CLKO/RA6 10 PI 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2(1) 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 28-pin QFN RE3GDGCGMN11 A1/AN1A0/AN0 CLR/V/PPB7/KBI3/PB6/KBI2/PB5/KBI1/PB4KBI0/A RR MRRRR 28272625242322 RA2/AN2/VREF-/CVREF 1 21 RB3/AN9/CCP2(1) RA3/AN3/VREF+ 2 20 RB2/INT2/AN8 RA4/T0CKI/C1OUT 3 PIC18F2410 19 RB1/INT1/AN10 RA5/AN4/SS/HLVDIN/C2OUT 4 PIC18F2510 18 RB0/INT0/FLT0/AN12 VSS 5 17 VDD OSC1/CLKI/RA7 6 16 VSS OSC2/CLKO/RA6 7 15 RC7/RX/DT 8 91011121314 C0/T1OSO/T13CKI(1)C1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CK RR 40-pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 37 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1) RA4/T0CKI/C1OUT 6 35 RB2/INT2/AN8 RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/INT1/AN10 RE0/RD/AN5 8 X 33 RB0/INT0/FLT0/AN12 1 RE1/WR/AN6 9 X 32 VDD RE2/CS/AN7 10 F4 31 VSS VDD 11 8 30 RD7/PSP7/P1D 1 VSS 12 C 29 RD6/PSP6/P1C OSC1/CLKI/RA7 13 PI 28 RD5/PSP5/P1B OSC2/CLKO/RA6 14 27 RD4/PSP4 RC0/T1OSO/T13CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2(1) 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 Note 1: RB3 is the alternate pin for CCP2 multiplexing. © 2009 Microchip Technology Inc. DS39636D-page 5

PIC18F2X1X/4X1X Pin Diagrams (Cont.’d) 44-pin TQFP (1)2 TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCP 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 RC7/RX/DT 1 4444433333333 NC RD4/PSP4 2 32 RC0/T1OSO/T13CKI RD5/PSP5/P1B 3 31 OSC2/CLKO/RA6 RD6/PSP6/P1C 4 30 OSC1/CLKI/RA7 RD7/PSP7/P1D 5 29 VSS VSS 6 PIC18F4X1X 28 VDD VDD 7 27 RE2/CS/AN7 RB0/INT0/FLT0/AN12 8 26 RE1/WR/AN6 RB1/INT1/AN10 9 25 RE0/RD/AN5 RB2/INT2/AN8 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB3/AN9/CCP2(1) 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 CC1MCD301F+ NNRB4/KBI0/AN1RB5/KBI1/PGRB6/KBI2/PGRB7/KBI3/PGMCLR/V/REPPRA0/ANRA1/ANN2/V-/CVREFRERA3/AN3/VREF A 2/ A R (1)2CKI 44-pin QFN TX/CKSDOSDI/SDAPSP3PSP2PSP1PSP0SCK/SCLCCP1/P1AT1OSI/CCPT1OSO/T13 6/5/4/3/2/1/0/3/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 44444333333 RC7/RX/DT 1 33 OSC2/CLKO/RA6 RD4/PSP4 2 32 OSC1/CLKI/RA7 RD5/PSP5/P1B 3 31 VSS RD6/PSP6/P1C 4 30 VSS RD7/PSP7/P1D 5 29 VDD VSS 6 PIC18F4X1X 28 VDD VDD 7 27 RE2/CS/AN7 VDD 8 26 RE1/WR/AN6 RB0/INT0/FLT0/AN12 9 25 RE0/RD/AN5 RB1/INT1/AN10 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB2/INT2/AN8 11 23 RA4/T0CKI/C1OUT 23456789012 11111111222 (1)RB3/AN9/CCP2NCRB4/KBI0/AN11RB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0RA1/AN12/AN2/V-/CVREFREFRA3/AN3/V+REF A R Note 1: RB3 is the alternate pin for CCP2 multiplexing. DS39636D-page 6 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Oscillator Configurations............................................................................................................................................................25 3.0 Power-Managed Modes.............................................................................................................................................................35 4.0 Reset..........................................................................................................................................................................................43 5.0 Memory Organization.................................................................................................................................................................55 6.0 Flash Program Memory..............................................................................................................................................................77 7.0 8 x 8 Hardware Multiplier............................................................................................................................................................81 8.0 Interrupts....................................................................................................................................................................................83 9.0 I/O Ports.....................................................................................................................................................................................97 10.0 Timer0 Module.........................................................................................................................................................................115 11.0 Timer1 Module.........................................................................................................................................................................119 12.0 Timer2 Module.........................................................................................................................................................................125 13.0 Timer3 Module.........................................................................................................................................................................127 14.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................131 15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................139 16.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................153 17.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART).......................................................................................193 18.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................213 19.0 Comparator Module..................................................................................................................................................................223 20.0 Comparator Voltage Reference Module...................................................................................................................................229 21.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................233 22.0 Special Features of the CPU....................................................................................................................................................239 23.0 Instruction Set Summary..........................................................................................................................................................259 24.0 Development Support...............................................................................................................................................................309 25.0 Electrical Characteristics..........................................................................................................................................................313 26.0 DC and AC Characteristics Graphs And Tables......................................................................................................................351 27.0 Packaging Information..............................................................................................................................................................353 Appendix A: Revision History.............................................................................................................................................................361 Appendix B: Device Differences........................................................................................................................................................361 Appendix C: Conversion Considerations...........................................................................................................................................362 Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................362 Appendix E: Migration From Mid-Range to Enhanced Devices.........................................................................................................363 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................363 Index................................................................................................................................................................................................. 365 The Microchip Web Site.....................................................................................................................................................................375 Customer Change Notification Service..............................................................................................................................................375 Customer Support..............................................................................................................................................................................375 Reader Response..............................................................................................................................................................................376 PIC18F2X1X/4X1X Product Identification System.............................................................................................................................377 © 2009 Microchip Technology Inc. DS39636D-page 7

PIC18F2X1X/4X1X TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39636D-page 8 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18F2X1X/4X1X family offer ten different oscillator options, allowing users a wide • PIC18F2410 • PIC18LF2410 range of choices in developing application hardware. • PIC18F2510 • PIC18LF2510 These include: • PIC18F2515 • PIC18LF2515 • Four Crystal modes, using crystals or ceramic resonators • PIC18F2610 • PIC18LF2610 • Two External Clock modes, offering the option of • PIC18F4410 • PIC18LF4410 using two pins (oscillator input and a divide-by-4 • PIC18F4510 • PIC18LF4510 clock output) or one pin (oscillator input, with the • PIC18F4515 • PIC18LF4515 second pin reassigned as general I/O) • PIC18F4610 • PIC18LF4610 • Two External RC Oscillator modes with the same pin options as the External Clock modes This family offers the advantages of all PIC18 microcontrollers – namely, high computational • An internal oscillator block which provides an performance at an economical price – with the addition 8MHz clock and an INTRC source (approxi- of high-endurance, Flash program memory. On top of mately 31kHz), as well as a range of 6 user these features, the PIC18F2X1X/4X1X family introduces selectable clock frequencies, between 125kHz to design enhancements that make these microcontrollers 4MHz, for a total of 8 clock frequencies. This a logical choice for many high-performance, power option frees the two oscillator pins for use as sensitive applications. additional general purpose I/O. • A Phase Lock Loop (PLL) frequency multiplier, 1.1 New Core Features available to both the high-speed crystal and Inter- nal Oscillator modes, which allows clock speeds of 1.1.1 nanoWatt TECHNOLOGY up to 40MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock All of the devices in the PIC18F2X1X/4X1X family speeds, from 31kHz to 32MHz – all without using incorporate a range of features that can significantly an external crystal or clock circuit. reduce power consumption during operation. Key items include: Besides its availability as a clock source, the internal oscillator block provides a stable reference source that • Alternate Run Modes: By clocking the controller gives the family additional features for robust from the Timer1 source or the internal oscillator operation: block, power consumption during code execution can be reduced by as much as 90%. • Fail-Safe Clock Monitor: This option constantly • Multiple Idle Modes: The controller can also run monitors the main clock source against a with its CPU core disabled but the peripherals still reference signal provided by the internal active. In these states, power consumption can be oscillator. If a clock failure occurs, the controller is reduced even further, to as little as 4% of normal switched to the internal oscillator block, allowing operation requirements. for continued low-speed operation or a safe application shutdown. • On-the-fly Mode Switching: The power- managed modes are invoked by user code during • Two-Speed Start-up: This option allows the operation, allowing the user to incorporate power- internal oscillator to serve as the clock source saving ideas into their application’s software from Power-on Reset, or wake-up from Sleep design. mode, until the primary clock source is available. • Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been minimized. See Section25.0 “Electrical Characteristics” for values. © 2009 Microchip Technology Inc. DS39636D-page 9

PIC18F2X1X/4X1X 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Flash cells for program memory are rated to 100,000 erase/write cycles. Devices in the PIC18F2X1X/4X1X family are available Data retention without refresh is conservatively in 28-pin and 40/44-pin packages. Block diagrams for estimated to be greater than 40 years. the two groups are shown in Figure1-1 and Figure1-2. • Extended Instruction Set: The PIC18F2X1X/ The devices are differentiated from each other in five 4X1X family introduces an optional extension to ways: the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. 1. Flash program memory This extension, enabled as a device configuration • 16Kbytes for PIC18F2410/4410 devices option, has been specifically designed to optimize • 32Kbytes for PIC18F2510/4510 devices re-entrant application code originally developed in • 48 Kbytes for PIC18F2515/4515 devices high-level languages, such as C. • 64 Kbytes for PIC18F2610/4610 devices • Enhanced CCP Module: In PWM mode, this 2. A/D channels (10 for 28-pin devices, 13 for module provides 1, 2 or 4 modulated outputs for 40/44-pin devices). controlling half-bridge and full-bridge drivers. 3. I/O ports (3 bidirectional ports on 28-pin devices, Other features include Auto-Shutdown, for 5 bidirectional ports on 40/44-pin devices). disabling PWM outputs on interrupt or other select conditions and Auto-Restart, to reactivate outputs 4. CCP and Enhanced CCP implementation (28-pin once the condition has cleared. devices have 2 standard CCP modules; 40/44-pin devices have one standard CCP module and one • Enhanced Addressable USART: This serial ECCP module). communication module is capable of standard RS-232 operation and provides support for the LIN 5. Parallel Slave Port (present only on 40/44-pin bus protocol. Other enhancements include auto- devices). matic baud rate detection and a 16-bit Baud Rate All other features for devices in this family are identical. Generator for improved resolution. When the These are summarized in Table1-1. microcontroller is using the internal oscillator The pinouts for all devices are listed in Table1-3 and block, the USART provides stable operation for Table1-4. applications that talk to the outside world without using an external crystal (or its accompanying Like all Microchip PIC18 devices, members of the power requirement). PIC18F2X1X/4X1X family are available as both • 10-bit A/D Converter: This module incorporates standard and low-voltage devices. Standard devices programmable acquisition time, allowing for a with Flash memory, designated with an “F” in the part channel to be selected and a conversion to be number (such as PIC18F2610), accommodate an initiated without waiting for a sampling period and operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by “LF” (such as PIC18LF2610), thus, reduce code overhead. function over an extended VDD range of 2.0V to 5.5V. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section25.0 “Electrical Characteristics” for time-out periods. DS39636D-page 10 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 1-1: DEVICE FEATURES (PIC18F2410/2415/2510/2515/2610) Features PIC18F2410 PIC18F2510 PIC18F2515 PIC18F2610 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 49152 65536 Program Memory 8192 16384 24576 32768 (Instructions) Data Memory (Bytes) 768 1536 3968 3968 Interrupt Sources 18 18 18 18 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, (E) Timers 4 4 4 4 Capture/Compare/PWM Modules 2 2 2 2 Enhanced 0 0 0 0 Capture/Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) No No No No 10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 10 Input Channels 10 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Yes Yes Yes Yes High/Low-Voltage Detect Programmable Yes Yes Yes Yes Brown-out Reset Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled Packages 28-pin SPDIP 28-pin SPDIP 28-pin SPDIP 28-pin SPDIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin QFN 28-pin QFN © 2009 Microchip Technology Inc. DS39636D-page 11

PIC18F2X1X/4X1X TABLE 1-2: DEVICE FEATURES (PIC18F4410/4415/4510/4515/4610) Features PIC18F4410 PIC18F4510 PIC18F4515 PIC18F4610 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 49152 65536 Program Memory 8192 16384 24576 32768 (Instructions) Data Memory (Bytes) 768 1536 3968 3968 Interrupt Sources 19 19 19 19 I/O Ports Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM Modules 1 1 1 1 Enhanced 1 1 1 1 Capture/Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) Yes Yes Yes Yes 10-Bit Analog-to-Digital Module 13 Input Channels 13 Input Channels 13 Input Channels 13 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Yes Yes Yes Yes High/Low-Voltage Detect Programmable Yes Yes Yes Yes Brown-out Reset Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled Packages 40-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP DS39636D-page 12 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 1-1: PIC18F2410/2415/2510/2515/2610 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch PORTA inc/dec logic 8 8 Data Memory RA0/AN0 (.7, 1.5, 3.9 RA1/AN1 21 PCLAT U PCLATH Kbytes) RA2/AN2/VREF-/CVREF Address Latch RA3/AN3/VREF+ 20 RA4/T0CKI/C1OUT PCU PCH PCL RA5/AN4/SS/HLVDIN/C2OUT Program Counter 12 OSC2/CLKO(3)/RA6 Data Address<12> OSC1/CLKI(3)/RA7 31 Level Stack Address Latch 4 12 4 Pro(1g6ra/3m2 /M48e/6m4ory STKPTR BSR FSR0 ABcacensks Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/INT0/FLT0/AN12 inc/dec 8 logic RB1/INT1/AN10 Table Latch RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 Address ROM Latch RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(1) RC2/CCP1 BITOP W RC3/SCK/SCL 8 8 8 RC4/SDI/SDA RC5/SDO OSC1(3) Internal Power-up RC6/TX/CK OsBcloillcaktor Timer 8 8 RC7/RX/DT OSC2(3) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog Timer Precision MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBaenfedr eGnacpe PORTE In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor MCLR/VPP/RE3(2) BOR Timer0 Timer1 Timer2 Timer3 HLVD ADC Comparator CCP1 CCP2 MSSP EUSART 10-bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. DS39636D-page 13

PIC18F2X1X/4X1X FIGURE 1-2: PIC18F4410/4415/4510/4515/4610 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 Data Latch RA1/AN1 inc/dec logic 8 8 Data Memory RA2/AN2/VREF-/CVREF (.7, 1.5, 3.9 RA3/AN3/VREF+ 21 PCLAT U PCLATH Kbytes) RA4/T0CKI/C1OUT Address Latch RA5/AN4/SS/HLVDIN/C2OUT 20 PCU PCH PCL OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/INT0/FLT0/AN12 Address Latch 4 12 4 RB1/INT1/AN10 Pro(1g6rKa/3bm2y /tM4e8se/)m64ory STKPTR BSR FFSSRR01 ABcacensks RRBB23//AINNT92//CACNP82(1) Data Latch FSR2 12 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A IR RC3/SCK/SCL RC4/SDI/SDA 8 RC5/SDO Instruction State Machine RC6/TX/CK Decode and Control Signals RC7/RX/DT Control PRODH PRODL 8 x 8 Multiply 3 8 PORTD RD0/PSP0:RD4/PSP4 BITOP W 8 8 8 RD5/PSP5/P1B RD6/PSP6/P1C OSC1(3) Internal Power-up RD7/PSP7/P1D Oscillator Timer 8 8 Block OSC2(3) Oscillator ALU<8> INTRC Start-up Timer T1OSI Oscillator Power-on 8 Reset 8 MHz T1OSO Oscillator Watchdog PORTE Timer Precision RE0/RD/AN5 MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe RREE21//CWSR/A/ANN76 In-Circuit Fail-Safe MCLR/VPP/RE3(2) VDD,VSS Debugger Clock Monitor BOR Timer0 Timer1 Timer2 Timer3 HLVD ADC Comparator ECCP1 CCP2 MSSP EUSART 10-bit Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Configurations” for additional information. DS39636D-page 14 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description SPDIP, Type Type QFN SOIC MCLR/VPP/RE3 1 26 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 9 6 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 10 7 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39636D-page 15

PIC18F2X1X/4X1X TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description SPDIP, Type Type QFN SOIC PORTA is a bidirectional I/O port. RA0/AN0 2 27 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 28 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF-/CVREF 4 1 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 2 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT 6 3 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RA5/AN4/SS/HLVDIN/ 7 4 C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39636D-page 16 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description SPDIP, Type Type QFN SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 21 18 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for CCP1. AN12 I Analog Analog input 12. RB1/INT1/AN10 22 19 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. AN10 I Analog Analog input 10. RB2/INT2/AN8 23 20 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. AN8 I Analog Analog input 8. RB3/AN9/CCP2 24 21 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. RB4/KBI0/AN11 25 22 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog input 11. RB5/KBI1/PGM 26 23 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 27 24 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 28 25 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39636D-page 17

PIC18F2X1X/4X1X TABLE 1-3: PIC18F2410/2415/2510/2515/2610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description SPDIP, Type Type QFN SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 8 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 12 9 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. RC2/CCP1 13 10 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. RC3/SCK/SCL 14 11 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 15 12 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O ST I2C data I/O. RC5/SDO 16 13 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 17 14 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 18 15 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). RE3 — — — — See MCLR/VPP/RE3 pin. VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39636D-page 18 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 1-4: PIC18F4410/4415/4510/4515/4610 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI/RA7 13 32 30 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39636D-page 19

PIC18F2X1X/4X1X TABLE 1-4: PIC18F4410/4415/4510/4515/4610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTA is a bidirectional I/O port. RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF-/CVREF 4 21 21 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT 6 23 23 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RA5/AN4/SS/HLVDIN/ 7 24 24 C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39636D-page 20 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 1-4: PIC18F4410/4415/4510/4515/4610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 33 9 8 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for Enhanced CCP1. AN12 I Analog Analog input 12. RB1/INT1/AN10 34 10 9 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. AN10 I Analog Analog input 10. RB2/INT2/AN8 35 11 10 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. AN8 I Analog Analog input 8. RB3/AN9/CCP2 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. RB4/KBI0/AN11 37 14 14 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog input 11. RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39636D-page 21

PIC18F2X1X/4X1X TABLE 1-4: PIC18F4410/4415/4510/4515/4610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 16 35 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture1 input/Compare1 output/PWM1 output. P1A O — Enhanced CCP1 output. RC3/SCK/SCL 18 37 37 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI/SDA 23 42 42 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O ST I2C data I/O. RC5/SDO 24 43 43 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39636D-page 22 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 1-4: PIC18F4410/4415/4510/4515/4610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0 19 38 38 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. RD1/PSP1 20 39 39 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. RD2/PSP2 21 40 40 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. RD3/PSP3 22 41 41 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. RD4/PSP4 27 2 2 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. RD5/PSP5/P1B 28 3 3 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. P1B O — Enhanced CCP1 output. RD6/PSP6/P1C 29 4 4 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. P1C O — Enhanced CCP1 output. RD7/PSP7/P1D 30 5 5 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. P1D O — Enhanced CCP1 output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39636D-page 23

PIC18F2X1X/4X1X TABLE 1-4: PIC18F4410/4415/4510/4515/4610 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTE is a bidirectional I/O port. RE0/RD/AN5 8 25 25 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port (see also WR and CS pins). AN5 I Analog Analog input 5. RE1/WR/AN6 9 26 26 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port (see CS and RD pins). AN6 I Analog Analog input 6. RE2/CS/AN7 10 27 27 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port (see related RD and WR). AN7 I Analog Analog input 7. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 28, 29 NC — 13 12, 13, — — No connect. 33, 34 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39636D-page 24 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (XT, LP, HS OR HSPLL 2.1 Oscillator Types CONFIGURATION) PIC18F2X1X/4X1X devices can be operated in ten C1(1) OSC1 different oscillator modes. The user can program the To Configuration bits, FOSC3:FOSC0, in Configuration Internal Register 1H to select one of these ten modes: XTAL (3) Logic RF 1. LP Low-Power Crystal Sleep 2. XT Crystal/Resonator RS(2) 3. HS High-Speed Crystal/Resonator C2(1) OSC2 PIC18FXXXX 4. HSPLL High-Speed Crystal/Resonator with PLL enabled Note 1: See Table2-1 and Table2-2 for initial values of 5. RC External Resistor/Capacitor with C1 and C2. FOSC/4 output on RA6 2: A series resistor (RS) may be required for AT strip cut crystals. 6. RCIO External Resistor/Capacitor with I/O on RA6 3: RF varies with the oscillator mode chosen. 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 TABLE 2-1: CAPACITOR SELECTION FOR 8. INTIO2 Internal Oscillator with I/O on RA6 CERAMIC RESONATORS and RA7 9. EC External Clock with FOSC/4 output Typical Capacitor Values Used: 10. ECIO External Clock with I/O on RA6 Mode Freq OSC1 OSC2 XT 3.58 MHz 15 pF 15 pF 2.2 Crystal Oscillator/Ceramic 4.19 MHz 15 pF 15 pF Resonators 4 MHz 30 pF 30 pF 4 MHz 50 pF 50 pF In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and Capacitor values are for design guidance only. OSC2 pins to establish oscillation. Figure2-1 shows Different capacitor values may be required to produce the pin connections. acceptable oscillator operation. The user should test The oscillator design requires the use of a parallel cut the performance of the oscillator over the expected crystal. VDD and temperature range for the application. Note: Use of a series cut crystal may give a See the notes following Table2-2 for additional frequency out of the crystal manufacturer’s information. specifications. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. © 2009 Microchip Technology Inc. DS39636D-page 25

PIC18F2X1X/4X1X TABLE 2-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the CRYSTAL OSCILLATOR OSC1 pin in the HS mode, as shown in Figure2-2. Typical Capacitor Values FIGURE 2-2: EXTERNAL CLOCK INPUT Crystal Tested: Osc Type OPERATION Freq C1 C2 (HS OSCILLATOR CONFIGURATION) LP 32 kHz 30 pF 30 pF XT 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF Clock from OSC1 HS 4 MHz 15 pF 15 pF Ext. System PIC18FXXXX 10 MHz 15 pF 15 pF (HS Mode) Open OSC2 20 MHz 15 pF 15 pF 25 MHz 15 pF 15 pF Capacitor values are for design guidance only. 2.3 External Clock Input Different capacitor values may be required to produce acceptable oscillator operation. The user should test The EC and ECIO Oscillator modes require an external the performance of the oscillator over the expected clock source to be connected to the OSC1 pin. There is VDD and temperature range for the application. no oscillator start-up time required after a Power-on See the notes following this table for additional Reset or after an exit from Sleep mode. information. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other Note1: Higher capacitance increases the stability logic. Figure2-3 shows the pin connections for the EC of the oscillator but also increases the Oscillator mode. start-up time. 2: When operating below 3V VDD, or when FIGURE 2-3: EXTERNAL CLOCK using certain ceramic resonators at any INPUT OPERATION voltage, it may be necessary to use the (EC CONFIGURATION) HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own Clock from OSC1/CLKI characteristics, the user should consult Ext. System PIC18FXXXX the resonator/crystal manufacturer for FOSC/4 OSC2/CLKO appropriate values of external components. 4: Rs may be required to avoid overdriving The ECIO Oscillator mode functions like the EC mode, crystals with low drive level specification. except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of 5: Always verify oscillator performance over PORTA (RA6). Figure2-4 shows the pin connections the VDD and temperature range that is for the ECIO Oscillator mode. expected for the application. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) Clock from OSC1/CLKI Ext. System PIC18FXXXX RA6 I/O (OSC2) DS39636D-page 26 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 2.4 RC Oscillator 2.5 PLL Frequency Multiplier For timing insensitive applications, the “RC” and A Phase Locked Loop (PLL) circuit is provided as an “RCIO” device options offer additional cost savings. option for users who wish to use a lower frequency The actual oscillator frequency is a function of several oscillator circuit or to clock the device up to its highest factors: rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due • supply voltage to high-frequency crystals or users who require higher • values of the external resistor (REXT) and clock speeds from an internal oscillator. capacitor (CEXT) • operating temperature 2.5.1 HSPLL OSCILLATOR MODE Given the same device, operating voltage and tempera- The HSPLL mode makes use of the HS mode oscillator ture and component values, there will also be unit-to-unit for frequencies up to 10 MHz. A PLL then multiplies the frequency variations. These are due to factors such as: oscillator output frequency by 4 to produce an internal • normal manufacturing variation clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. • difference in lead frame capacitance between package types (especially for low CEXT values) The PLL is only available to the crystal oscillator when • variations within the tolerance of limits of REXT the FOSC3:FOSC0 Configuration bits are programmed and CEXT for HSPLL mode (= 0110). In the RC Oscillator mode, the oscillator frequency FIGURE 2-7: PLL BLOCK DIAGRAM divided by 4 is available on the OSC2 pin. This signal (HS MODE) may be used for test purposes or to synchronize other logic. Figure2-5 shows how the R/C combination is HS Oscillator Enable connected. PLL Enable (from Configuration Register 1H) FIGURE 2-5: RC OSCILLATOR MODE VDD OSC2 Phase HS Mode FIN Comparator REXT Internal OSC1 Crystal FOUT OSC1 Osc Clock CEXT Loop PIC18FXXXX Filter VSS OSC2/CLKO FOSC/4 ÷4 VCO Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ SYSCLK X CEXT > 20 pF U M The RCIO Oscillator mode (Figure2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). 2.5.2 PLL AND INTOSC The PLL is also available to the internal oscillator block FIGURE 2-6: RCIO OSCILLATOR MODE in selected oscillator modes. In this configuration, the VDD PLL is enabled in software and generates a clock output of up to 32MHz. The operation of INTOSC with REXT the PLL is described in Section2.6.4 “PLL in INTOSC OSC1 Internal Modes”. Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF © 2009 Microchip Technology Inc. DS39636D-page 27

PIC18F2X1X/4X1X 2.6 Internal Oscillator Block When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The The PIC18F2X1X/4X1X devices include an internal INTRC clock will reach the new frequency within oscillator block which generates two different clock 8clock cycles (approximately 8*32μs=256μs). The signals; either can be used as the microcontroller’s INTOSC clock will stabilize within 1ms. Code execu- clock source. This may eliminate the need for external tion continues during this shift. There is no indication oscillator circuits on the OSC1 and/or OSC2 pins. that the shift has occurred. The main output (INTOSC) is an 8MHz clock source, The OSCTUNE register also implements the INTSRC which can be used to directly drive the device clock. It and PLLEN bits, which control certain features of the also drives a postscaler, which can provide a range of internal oscillator block. The INTSRC bit allows users clock frequencies from 31kHz to 4MHz. The INTOSC to select which internal oscillator provides the clock output is enabled when a clock frequency from 125kHz source when the 31kHz frequency option is selected. to 8MHz is selected. This is covered in greater detail in Section2.7.1 The other clock source is the internal RC oscillator “Oscillator Control Register”. (INTRC), which provides a nominal 31kHz output. The PLLEN bit controls the operation of the frequency INTRC is enabled if it is selected as the device clock multiplier, PLL, in Internal Oscillator modes. source; it is also enabled automatically when any of the following are enabled: 2.6.4 PLL IN INTOSC MODES • Power-up Timer The 4x frequency multiplier can be used with the • Fail-Safe Clock Monitor internal oscillator block to produce faster device clock • Watchdog Timer speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock • Two-Speed Start-up speed of up to 32MHz. These features are discussed in greater detail in Unlike HSPLL mode, the PLL is controlled through Section22.0 “Special Features of the CPU”. software. The control bit, PLLEN (OSCTUNE<6>), is The clock source frequency (INTOSC direct, INTRC used to enable or disable its operation. direct or INTOSC postscaler) is selected by configuring The PLL is available when the device is configured to the IRCF bits of the OSCCON register (page32). use the internal oscillator block as its primary clock 2.6.1 INTIO MODES source (FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL will only function when the selected output fre- Using the internal oscillator as the clock source elimi- quency is either 4MHz or 8MHz (OSCCON<6:4> = 111 nates the need for up to two external oscillator pins, or 110). If both of these conditions are not met, the PLL which can then be used for digital I/O. Two distinct is disabled. configurations are available: The PLLEN control bit is only functional in those • In INTIO1 mode, the OSC2 pin outputs FOSC/4, internal Oscillator modes where the PLL is available. In while OSC1 functions as RA7 for digital input and all other modes, it is forced to ‘0’ and is effectively output. unavailable. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and 2.6.5 INTOSC FREQUENCY DRIFT output. The factory calibrates the internal oscillator block output (INTOSC) for 8MHz. However, this frequency 2.6.2 INTOSC OUTPUT FREQUENCY may drift as VDD or temperature changes, which can The internal oscillator block is calibrated at the factory affect the controller operation in a variety of ways. It is to produce an INTOSC output frequency of 8.0MHz. possible to adjust the INTOSC frequency by modifying The INTRC oscillator operates independently of the the value in the OSCTUNE register. This has no effect INTOSC source. Any changes in INTOSC across on the INTRC clock source frequency. voltage and temperature are not necessarily reflected Tuning the INTOSC source requires knowing when to by changes in INTRC and vice versa. make the adjustment, in which direction it should be made and in some cases, how large a change is 2.6.3 OSCTUNE REGISTER needed. Three compensation techniques are The internal oscillator’s output has been calibrated at discussed in Section2.6.5.1 “Compensating with the factory but can be adjusted in the user’s applica- the USART”, Section2.6.5.2 “Compensating with tion. This is done by writing to the OSCTUNE register the Timers” and Section2.6.5.3 “Compensating (Register2-1). The tuning sensitivity is constant with the CCP Module in Capture Mode”, but other throughout the tuning range. techniques may be used. DS39636D-page 28 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4MHz and 8MHz only) 0 = PLL disabled Note1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes” for details. bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN4:TUN0: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2.6.5.1 Compensating with the USART 2.6.5.3 Compensating with the CCP Module in Capture Mode An adjustment may be required when the USART begins to generate framing errors or receives data with A CCP module can use free running Timer1 (or errors while in Asynchronous mode. Framing errors Timer3), clocked by the internal oscillator block and an indicate that the device clock frequency is too high; to external event with a known period (i.e., AC power adjust for this, decrement the value in OSCTUNE to frequency). The time of the first event is captured in the reduce the clock frequency. On the other hand, errors CCPRxH:CCPRxL registers and is recorded for use in data may suggest that the clock speed is too low; to later. When the second event causes a capture, the compensate, increment OSCTUNE to increase the time of the first event is subtracted from the time of the clock frequency. second event. Since the period of the external event is known, the time difference between events can be 2.6.5.2 Compensating with the Timers calculated. This technique compares device clock speed to some If the measured time is much greater than the calcu- reference clock. Two timers may be used; one timer is lated time, the internal oscillator block is running too clocked by the peripheral clock, while the other is fast; to compensate, decrement the OSCTUNE register. clocked by a fixed reference source, such as the If the measured time is much less than the calculated Timer1 oscillator. time, the internal oscillator block is running too slow; to Both timers are cleared, but the timer clocked by the compensate, increment the OSCTUNE register. reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. DS39636D-page 29

PIC18F2X1X/4X1X 2.7 Clock Sources and Oscillator The secondary oscillators are those external sources Switching not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the Like previous PIC18 devices, the PIC18F2X1X/4X1X controller is placed in a power-managed mode. family includes a feature that allows the device clock PIC18F2X1X/4X1X devices offer the Timer1 oscillator source to be switched from the main oscillator to an as a secondary oscillator. This oscillator, in all power- alternate low-frequency clock source. PIC18F2X1X/ managed modes, is often the time base for functions 4X1X devices offer two alternate clock sources. When such as a real-time clock. an alternate clock source is enabled, the various power-managed operating modes are available. Most often, a 32.768kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI Essentially, there are three clock sources for these pins. Like the LP mode oscillator circuit, loading devices: capacitors are also connected from each pin to ground. • Primary oscillators The Timer1 oscillator is discussed in greater detail in • Secondary oscillators Section11.3 “Timer1 Oscillator”. • Internal oscillator block In addition to being a primary clock source, the internal The primary oscillators include the External Crystal oscillator block is available as a power-managed and Resonator modes, the External RC modes, the mode clock source. The INTRC source is also used as External Clock modes and the internal oscillator block. the clock source for several special features, such as The particular mode is defined by the FOSC3:FOSC0 the WDT and Fail-Safe Clock Monitor. Configuration bits. The details of these modes are The clock sources for the PIC18F2X1X/4X1X devices covered earlier in this chapter. are shown in Figure2-8. See Section22.0 “Special Features of the CPU” for Configuration register details. FIGURE 2-8: PIC18F2X1X/4X1X CLOCK DIAGRAM PIC18F2X1X/4X1X Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep HSPLL, INTOSC/PLL 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator OSCCON<6:4> 8 MHz CPU 111 4 MHz Internal 110 Oscillator 2 MHz IDLEN Block er 1 MHz 101 Clock S8o MurHcze 8 MHz stscal 500 kHz 100101MUX Control INTRC (INTOSC) Po 250 kHz 010 FOSC3:FOS C0 OSCCON< 1:0> Source 125 kHz 001 Clock Source Option 1 31 kHz 31 kHz (INTRC) 000 for other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up DS39636D-page 30 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 2.7.1 OSCILLATOR CONTROL REGISTER The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP The OSCCON register (Register2-2) controls several instruction is executed. aspects of the device clock’s operation, both in full power operation and in power-managed modes. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section3.0 The System Clock Select bits, SCS1:SCS0, select the “Power-Managed Modes”. clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configu- Note1: The Timer1 oscillator must be enabled to ration bits), the secondary clock (Timer1 oscillator) and select the secondary clock source. The the internal oscillator block. The clock source changes Timer1 oscillator is enabled by setting the immediately after one or more of the bits is written to, T1OSCEN bit in the Timer1 Control regis- following a brief clock transition interval. The SCS bits ter (T1CON<3>). If the Timer1 oscillator are cleared on all forms of Reset. is not enabled, then any attempt to select The Internal Oscillator Frequency Select bits a secondary clock source will be ignored. (IRCF2:IRCF0) select the frequency output of the 2: It is recommended that the Timer1 internal oscillator block to drive the device clock. The oscillator be operating and stable before choices are the INTRC source, the INTOSC source selecting the secondary clock source or a (8MHz) or one of the frequencies derived from the very long delay may occur while the INTOSC postscaler (31.25kHz to 4MHz). If the Timer1 oscillator starts. internal oscillator block is supplying the device clock, changing the states of these bits will have an immedi- 2.7.2 OSCILLATOR TRANSITIONS ate change on the internal oscillator’s output. On device Resets, the default output frequency of the PIC18F2X1X/4X1X devices contain circuitry to prevent internal oscillator block is set at 1MHz. clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the When a nominal output frequency of 31kHz is selected clock switch. The length of this pause is the sum of two (IRCF2:IRCF0 = 000), users may choose which inter- cycles of the old clock source and three to four cycles nal oscillator acts as the source. This is done with the of the new clock source. This formula assumes that the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). new clock source is stable. Setting this bit selects INTOSC as a 31.25kHz clock source by enabling the divide-by-256 output of the Clock transitions are discussed in greater detail in INTOSC postscaler. Clearing INTSRC selects INTRC Section3.1.2 “Entering Power-Managed Modes”. (nominally 31kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock in Primary Clock modes. The IOFS bit indicates when the internal oscillator block has stabi- lized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in Secondary Clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2009 Microchip Technology Inc. DS39636D-page 31

PIC18F2X1X/4X1X REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz(3) 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator start-up time-out timer has expired; primary oscillator is running 0 = Oscillator start-up time-out timer is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 32 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 2.8 Effects of Power-Managed Modes time clock. Other features may be operating that do not on the Various Clock Sources require a device clock source (i.e., SSP slave, PSP, INTn pins and others). Peripherals that may add When PRI_IDLE mode is selected, the designated significant current consumption are listed in primary oscillator continues to run without interruption. Section 25.2“DC Characteristics”. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and 2.9 Power-up Delays OSC2 pin, if used by the oscillator) will stop oscillating. Power-up delays are controlled by two timers, so that In Secondary Clock modes (SEC_RUN and no external Reset circuitry is required for most applica- SEC_IDLE), the Timer1 oscillator is operating and tions. The delays ensure that the device is kept in providing the device clock. The Timer1 oscillator may Reset until the device power supply is stable under nor- also run in all power-managed modes if required to mal circumstances and the primary clock is operating clock Timer1 or Timer3. and stable. For additional information on power-up In Internal Oscillator modes (RC_RUN and RC_IDLE), delays, see Section4.5 “Device Reset Timers”. the internal oscillator block provides the device clock The first timer is the Power-up Timer (PWRT), which source. The 31kHz INTRC output can be used directly provides a fixed delay on power-up (parameter 33, to provide the clock and may be enabled to support Table25-10). It is enabled by clearing (=0) the various special features, regardless of the power- PWRTEN Configuration bit. managed mode (see Section22.2 “Watchdog Timer (WDT)”, Section22.3 “Two-Speed Start-up” and The second timer is the Oscillator Start-up Timer Section22.4 “Fail-Safe Clock Monitor” for more (OST), intended to keep the chip in Reset until the information on WDT, Fail-Safe Clock Monitor and Two- crystal oscillator is stable (LP, XT and HS modes). The Speed Start-up). The INTOSC output at 8MHz may be OST does this by counting 1024 oscillator cycles used directly to clock the device or may be divided before allowing the oscillator to clock the device. down by the postscaler. The INTOSC output is disabled When the HSPLL Oscillator mode is selected, the if the clock is provided directly from the INTRC output. device is kept in Reset for an additional 2ms, following If the Sleep mode is selected, all clock sources are the HS mode OST delay, so the PLL can lock to the stopped. Since all the transistor switching currents incoming clock frequency. have been stopped, Sleep mode achieves the lowest There is a delay of interval TCSD (parameter 38, current consumption of the device (only leakage Table25-10), following POR, while the controller currents). becomes ready to execute instructions. This delay runs Enabling any on-chip feature that will operate during concurrently with any other delays. This may be the Sleep will increase the current consumed during Sleep. only delay that occurs when any of the EC, RC or INTIO The INTRC is required to support WDT operation. The modes are used as the primary clock source. Timer1 oscillator may be operating to support a real- TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO Floating, external resistor should pull high Configured as PORTA, bit 6 INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table4-2 in Section4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. DS39636D-page 33

PIC18F2X1X/4X1X NOTES: DS39636D-page 34 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three PIC18F2X1X/4X1X devices offer a total of seven oper- clock sources for power-managed modes. They are: ating modes for more efficient power management. These modes provide a variety of options for selective • the primary clock, as defined by the power conservation in applications where resources FOSC3:FOSC0 Configuration bits may be limited (i.e., battery-powered devices). • the secondary clock (the Timer1 oscillator) There are three categories of power-managed modes: • the internal oscillator block (for RC modes) • Run modes 3.1.2 ENTERING POWER-MANAGED • Idle modes MODES • Sleep mode Switching from one power-managed mode to another These categories define which portions of the device begins by loading the OSCCON register. The are clocked and sometimes, what speed. The Run and SCS1:SCS0 bits select the clock source and determine Idle modes may use any of the three available clock which Run or Idle mode is to be used. Changing these sources (primary, secondary or internal oscillator bits causes an immediate switch to the new clock block); the Sleep mode does not use a clock source. source, assuming that it is running. The switch may The power-managed modes include several power- also be subject to clock transition delays. These are saving features offered on previous PIC® devices. One discussed in Section3.1.3 “Clock Transitions and is the clock switching feature, offered in other PIC18 Status Indicators” and subsequent sections. devices, allowing the controller to use the Timer1 oscil- Entry to the power-managed Idle or Sleep modes is lator in place of the primary oscillator. Also included is triggered by the execution of a SLEEP instruction. The the Sleep mode, offered by all PIC devices, where all actual mode that results depends on the status of the device clocks are stopped. IDLEN bit. Depending on the current mode and the mode being 3.1 Selecting Power-Managed Modes switched to, a change to a power-managed mode does Selecting a power-managed mode requires two not always require setting all of these bits. Many decisions: if the CPU is to be clocked or not and the transitions may be done by changing the oscillator select selection of a clock source. The IDLEN bit bits, or changing the IDLEN bit, prior to issuing a SLEEP (OSCCON<7>) controls CPU clocking, while the instruction. If the IDLEN bit is already configured SCS1:SCS0 bits (OSCCON<1:0>) select the clock correctly, it may only be necessary to perform a SLEEP source. The individual modes, bit settings, clock sources instruction to switch to the desired mode. and affected modules are summarized in Table3-1. TABLE 3-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode IDLEN(1) SCS1:SCS0 Available Clock and Oscillator Source CPU Peripherals <7> <1:0> Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. DS39636D-page 35

PIC18F2X1X/4X1X 3.1.3 CLOCK TRANSITIONS AND 3.2 Run Modes STATUS INDICATORS In the Run modes, clocks to both the core and The length of the transition between clock sources is peripherals are active. The difference between these the sum of two cycles of the old clock source and three modes is the clock source. to four cycles of the new clock source. This formula assumes that the new clock source is stable. 3.2.1 PRI_RUN MODE Three bits indicate the current clock source and its The PRI_RUN mode is the normal, full power execution status. They are: mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up • OSTS (OSCCON<3>) is enabled (see Section22.3 “Two-Speed Start-up” • IOFS (OSCCON<2>) for details). In this mode, the OSTS bit is set. The IOFS • T1RUN (T1CON<6>) bit may be set if the internal oscillator block is the In general, only one of these bits will be set while in a primary clock source (see Section2.7.1 “Oscillator given power-managed mode. When the OSTS bit is Control Register”). set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is 3.2.2 SEC_RUN MODE providing a stable 8MHz clock source to a divider that The SEC_RUN mode is the compatible mode to the actually drives the device clock. When the T1RUN bit is “clock switching” feature offered in other PIC18 set, the Timer1 oscillator is providing the clock. If none devices. In this mode, the CPU and peripherals are of these bits are set, then either the INTRC clock clocked from the Timer1 oscillator. This gives users the source is clocking the device, or the INTOSC source is option of lower power consumption while still using a not yet stable. high accuracy clock source. If the internal oscillator block is configured as the SEC_RUN mode is entered by setting the SCS1:SCS0 primary clock source by the FOSC3:FOSC0 Configura- bits to ‘01’. The device clock source is switched to the tion bits, then both the OSTS and IOFS bits may be set Timer1 oscillator (see Figure3-1), the primary oscilla- when in PRI_RUN or PRI_IDLE modes. This indicates tor is shut down, the T1RUN bit (T1CON<6>) is set and that the primary clock (INTOSC output) is generating a the OSTS bit is cleared. stable 8MHz output. Entering another power-managed RC mode at the same frequency would clear the OSTS Note: The Timer1 oscillator should already be bit. running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the Note1: Caution should be used when modifying a SCS1:SCS0 bits are set to ‘01’, entry to single IRCF bit. If VDD is less than 3V, it is SEC_RUN mode will not occur. If the possible to select a higher clock speed Timer1 oscillator is enabled but not yet than is supported by the low VDD. running, device clocks will be delayed until Improper device operation may result if the oscillator has started. In such situa- the VDD/FOSC specifications are violated. tions, initial oscillator operation is far from 2: Executing a SLEEP instruction does not stable and unpredictable operation may necessarily place the device into Sleep result. mode. It acts as the trigger to place the controller into either the Sleep mode or On transitions from SEC_RUN mode to PRI_RUN, the one of the Idle modes, depending on the peripherals and CPU continue to be clocked from the setting of the IDLEN bit. Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch 3.1.4 MULTIPLE SLEEP COMMANDS back to the primary clock occurs (see Figure3-2). When the clock switch is complete, the T1RUN bit is The power-managed mode that is invoked with the cleared, the OSTS bit is set and the primary clock is SLEEP instruction is determined by the setting of the providing the clock. The IDLEN and SCS bits are not IDLEN bit at the time the instruction is executed. If affected by the wake-up; the Timer1 oscillator another SLEEP instruction is executed, the device will continues to run. enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39636D-page 36 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock(2) Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 bits changed OSTS bit set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 3.2.3 RC_RUN MODE This mode is entered by setting SCS1 to ‘1’. Although it is ignored, it is recommended that SCS0 also be In RC_RUN mode, the CPU and peripherals are cleared; this is to maintain software compatibility with clocked from the internal oscillator block using the future devices. When the clock source is switched to INTOSC multiplexer. In this mode, the primary clock is the INTOSC multiplexer (see Figure3-3), the primary shut down. When using the INTRC source, this mode oscillator is shut down and the OSTS bit is cleared. The provides the best power conservation of all the Run IRCF bits may be modified at any time to immediately modes, while still executing code. It works well for user change the clock speed. applications which are not highly timing sensitive or do not require high-speed clocks at all times. Note: Caution should be used when modifying a If the primary clock source is the internal oscillator single IRCF bit. If VDD is less than 3V, it is block (either INTRC or INTOSC), there are no possible to select a higher clock speed distinguishable differences between PRI_RUN and than is supported by the low VDD. Improper device operation may result if RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from the VDD/FOSC specifications are violated. RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2009 Microchip Technology Inc. DS39636D-page 37

PIC18F2X1X/4X1X If the IRCF bits and the INTSRC bit are all clear, the On transitions from RC_RUN mode to PRI_RUN mode, INTOSC output is not enabled and the IOFS bit will the device continues to be clocked from the INTOSC remain clear; there will be no indication of the current multiplexer while the primary clock is started. When the clock source. The INTRC source is providing the primary clock becomes ready, a clock switch to the device clocks. primary clock occurs (see Figure3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS If the IRCF bits are changed from all clear (thus, bit is set and the primary clock is providing the device enabling the INTOSC output) or if INTSRC is set, the clock. The IDLEN and SCS bits are not affected by the IOFS bit becomes set after the INTOSC output switch. The INTRC source will continue to run if either becomes stable. Clocks to the device continue while the WDT or the Fail-Safe Clock Monitor is enabled. the INTOSC source stabilizes after an interval of TIOBST. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n (1) Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock(2) Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 bits changed OSTS bit set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS39636D-page 38 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 3.3 Sleep Mode 3.4 Idle Modes The power-managed Sleep mode in the PIC18F2X1X/ The Idle modes allow the controller’s CPU to be 4X1X devices is identical to the legacy Sleep mode selectively shut down while the peripherals continue to offered in all other PIC devices. It is entered by clearing operate. Selecting a particular Idle mode allows users the IDLEN bit (the default state on device Reset) and to further manage power consumption. executing the SLEEP instruction. This shuts down the If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is selected oscillator (Figure3-5). All clock source status executed, the peripherals will be clocked from the clock bits are cleared. source selected using the SCS1:SCS0 bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS1:SCS0 bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure3-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator block if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor are enabled (parameter38, Table25-10) while it becomes ready to (see Section22.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39636D-page 39

PIC18F2X1X/4X1X 3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by the fastest resumption of device operation with its more setting the IDLEN bit and executing a SLEEP accurate primary clock source, since the clock source instruction. If the device is in another Run mode, set does not have to “warm up” or transition from another IDLEN first, then set SCS1:SCS0 to ‘01’ and execute oscillator. SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, PRI_IDLE mode is entered from PRI_RUN mode by the OSTS bit is cleared and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC3:FOSC0 Configuration bits. The OSTS IDLEN and SCS bits are not affected by the wake-up; bit remains set (see Figure3-7). the Timer1 oscillator continues to run (see Figure3-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD is running prior to entering SEC_IDLE mode. required between the wake event and when code If the T1OSCEN bit is not set when the execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the wake- instruction will be ignored and entry to up, the OSTS bit remains set. The IDLEN and SCS bits SEC_IDLE mode will not occur. If the are not affected by the wake-up (see Figure3-8). Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS39636D-page 40 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 3.4.3 RC_IDLE MODE On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ In RC_IDLE mode, the CPU is disabled but the periph- GIEH bit (INTCON<7>) is set. Otherwise, code execu- erals continue to be clocked from the internal oscillator tion continues or resumes without branching (see block using the INTOSC multiplexer. This mode allows Section8.0 “Interrupts”). for controllable power conservation during Idle periods. A fixed delay of interval TCSD following the wake event From RC_RUN, this mode is entered by setting the is required when leaving Sleep and Idle modes. This IDLEN bit and executing a SLEEP instruction. If the delay is required for the CPU to prepare for execution. device is in another Run mode, first set IDLEN, then set Instruction execution resumes on the first clock cycle the SCS1 bit and execute SLEEP. Although its value is following this delay. ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future 3.5.2 EXIT BY WDT TIME-OUT devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF A WDT time-out will cause different actions depending bits before executing the SLEEP instruction. When the on which power-managed mode the device is in when clock source is switched to the INTOSC multiplexer, the the time-out occurs. primary oscillator is shut down and the OSTS bit is If the device is not executing code (all Idle modes and cleared. Sleep mode), the time-out will result in an exit from the If the IRCF bits are set to any non-zero value, or the powe-managed mode (see Section3.2 “Run Modes” INTSRC bit is set, the INTOSC output is enabled. The and Section3.3 “Sleep Mode”). If the device is IOFS bit becomes set, after the INTOSC output executing code (all Run modes), the time-out will result becomes stable, after an interval of TIOBST in a WDT Reset (see Section22.2 “Watchdog Timer (parameter39, Table25-10). Clocks to the peripherals (WDT)”). continue while the INTOSC source stabilizes. If the The WDT timer and postscaler are cleared by IRCF bits were previously at a non-zero value, or executing a SLEEP or CLRWDT instruction, the loss of a INTSRC was set before the SLEEP instruction was exe- currently selected clock source (if the Fail-Safe Clock cuted and the INTOSC source was already stable, the Monitor is enabled) and modifying the IRCF bits in the IOFS bit will remain set. If the IRCF bits and INTSRC OSCCON register if the internal oscillator block is the are all clear, the INTOSC output will not be enabled, the device clock source. IOFS bit will remain clear and there will be no indication of the current clock source. 3.5.3 EXIT BY RESET When a wake event occurs, the peripherals continue to Normally, the device is held in Reset by the Oscillator be clocked from the INTOSC multiplexer. After a delay Start-up Timer (OST) until the primary clock becomes of TCSD following the wake event, the CPU begins ready. At that time, the OSTS bit is set and the device executing code being clocked by the INTOSC multi- begins executing code. If the internal oscillator block is plexer. The IDLEN and SCS bits are not affected by the the new clock source, the IOFS bit is set instead. wake-up. The INTRC source will continue to run if The exit delay time from Reset to the start of code either the WDT or the Fail-Safe Clock Monitor is execution depends on both the clock sources before enabled. and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are 3.5 Exiting Idle and Sleep Modes summarized in Table3-2. An exit from Sleep mode or any of the Idle modes is Code execution can begin before the primary clock triggered by an interrupt, a Reset or a WDT time-out. becomes ready. If either the Two-Speed Start-up (see This section discusses the triggers that cause exits Section22.3 “Two-Speed Start-up”) or Fail-Safe from power-managed modes. The clocking subsystem Clock Monitor (see Section22.4 “Fail-Safe Clock actions are discussed in each of the power-managed Monitor”) is enabled, the device may begin execution modes (see Section3.2 “Run Modes”, Section3.3 as soon as the Reset source has cleared. Execution is “Sleep Mode” and Section3.4 “Idle Modes”). clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the 3.5.1 EXIT BY INTERRUPT internal oscillator block until either the primary clock Any of the available interrupt sources can cause the becomes ready or a power-managed mode is entered device to exit from an Idle mode or the Sleep mode to before the primary clock becomes ready; the primary a Run mode. To enable this functionality, an interrupt clock is then shut down. source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. DS39636D-page 41

PIC18F2X1X/4X1X 3.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either START-UP DELAY does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not Certain exits from power-managed modes do not require an oscillator start-up delay (RC, EC and INTIO invoke the OST at all. There are two cases: Oscillator modes). However, a fixed delay of interval • PRI_IDLE mode, where the primary clock source TCSD following the wake event is still required when is not stopped; and leaving Sleep and Idle modes to allow the CPU to • the primary clock source is not any of the LP, XT, prepare for execution. Instruction execution resumes HS or HSPLL modes. on the first clock cycle following this delay. TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Clock Source Clock Ready Status Exit Delay before Wake-up after Wake-up bit (OSCCON) LP, XT, HS HSPLL OSTS Primary Device Clock EC, RC TCSD(2) (PRI_IDLE mode) INTRC(1) — INTOSC(3) IOFS LP, XT, HS TOST(4) T1OSC or INTRC(1) HSPLL TOST + trc(4) OSTS EC, RC TCSD(2) INTOSC(2) TIOBST(5) IOFS LP, XT, HS TOST(5) INTOSC(3) HSPLL TOST + trc(4) OSTS EC, RC TCSD(2) INTOSC(2) None IOFS LP, XT, HS TOST(4) None HSPLL TOST + trc(4) OSTS (Sleep mode) EC, RC TCSD(2) INTOSC(2) TIOBST(5) IOFS Note 1: In this instance, refers specifically to the 31kHz INTRC clock source. 2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section3.4 “Idle Modes”). On Reset, INTOSC defaults to 1MHz. 3: Includes both the INTOSC 8MHz source and postscaler derived frequencies. 4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. 5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period. DS39636D-page 42 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 4.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure4-1. The PIC18F2X1X/4X1X devices differentiate between various kinds of Reset: 4.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register4-1). The lower five bits of the c) MCLR Reset during power-managed modes register indicate that a specific Reset event has d) Watchdog Timer (WDT) Reset (during occurred. In most cases, these bits can only be cleared execution) by the event and must be set by the application after e) Programmable Brown-out Reset (BOR) the event. The state of these flag bits, taken together, f) RESET Instruction can be read to indicate the type of Reset that just occurred. This is described in more detail in g) Stack Full Reset Section4.6 “Reset State of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section8.0 “Interrupts”. BOR is covered in Section5.1.2.4 “Stack Full and Underflow Resets”. Section4.4 “Brown-out Reset (BOR)”. WDT Resets are covered in Section22.2 “Watchdog Timer (WDT)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 μs PWRT 65.5 ms INTRC(1) 11-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table4-2 for time-out situations. © 2009 Microchip Technology Inc. DS39636D-page 43

PIC18F2X1X/4X1X REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section4.6 “Reset State of Registers” for additional information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39636D-page 44 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 4.2 Master Clear (MCLR) FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. The MCLR pin is not driven low by any internal Resets, D R including the WDT. R1 MCLR In PIC18F2X1X/4X1X devices, the MCLR input can be disabled with the MCLRE Configuration bit. When C PIC18FXXXX MCLR is disabled, the pin becomes a digital input. See Section9.5 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 4.3 Power-on Reset (POR) The diode D helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: R < 40kΩ is recommended to make sure that the voltage drop across R does not violate allows the device to start in the initialized state when the device’s electrical specification. VDD is adequate for operation. 3: R1 ≥ 1 kΩ will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR MCLR from external capacitor C, in the event pin through a resistor (1kΩ to 10kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to eliminate external RC components usually needed to Electrostatic Discharge (ESD) or Electrical create a Power-on Reset delay. A minimum rise rate for Overstress (EOS). VDD is specified (parameter D004). For a slow rise time, see Figure4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2009 Microchip Technology Inc. DS39636D-page 45

PIC18F2X1X/4X1X 4.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its PIC18F2X1X/4X1X devices implement a BOR circuit environment without having to reprogram the device to that provides the user with a number of configuration change BOR configuration. It also allows the user to and power-saving options. The BOR is controlled by tailor device power consumption in software by elimi- the BORV1:BORV0 and BOREN1:BOREN0 Configu- nating the incremental current that the BOR consumes. ration bits. There are a total of four BOR configurations While the BOR current is typically very small, it may which are summarized in Table4-1. have some impact in low-power applications. The BOR threshold is set by the BORV1:BORV0 bits. If Note: Even when BOR is under software control, BOR is enabled (any values of BOREN1:BOREN0, the BOR Reset voltage level is still set by except ‘00’), any drop of VDD below VBOR (parameter the BORV1:BORV0 Configuration bits. It D005) for greater than TBOR (parameter 35) will reset cannot be changed in software. the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in 4.4.2 DETECTING BOR Brown-out Reset until VDD rises above VBOR. When BOR is enabled, the BOR bit always resets to ‘0’ If the Power-up Timer is enabled, it will be invoked after on any BOR or POR event. This makes it difficult to VDD rises above VBOR; it then will keep the chip in determine if a BOR event has occurred just by reading Reset for an additional time delay, TPWRT the state of BOR alone. A more reliable method is to (parameter33). If VDD drops below VBOR while the simultaneously check the state of both POR and BOR. Power-up Timer is running, the chip will go back into a This assumes that the POR bit is reset to ‘1’ in software Brown-out Reset and the Power-up Timer will be immediately after any POR event. If BOR is ‘0’ while initialized. Once VDD rises above VBOR, the Power-up POR is ‘1’, it can be reliably assumed that a BOR event Timer will execute the additional time delay. has occurred. BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does 4.4.3 DISABLING BOR IN SLEEP MODE not automatically enable the PWRT. When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously 4.4.1 SOFTWARE ENABLED BOR described. Whenever the device enters Sleep mode, When BOREN1:BOREN0 = 01, the BOR can be however, the BOR is automatically disabled. When the enabled or disabled by the user in software. This is device returns to any other operating mode, BOR is done with the control bit, SBOREN (RCON<6>). automatically re-enabled. Setting SBOREN enables the BOR to function as This mode allows for applications to recover from previously described. Clearing SBOREN disables the brown-out situations, while actively executing code, BOR entirely. The SBOREN bit operates only in this when the device requires BOR protection the most. At mode; otherwise it is read as ‘0’. the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. TABLE 4-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39636D-page 46 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 4.5 Device Reset Timers 4.5.3 PLL LOCK TIME-OUT PIC18F2X1X/4X1X devices incorporate three separate With the PLL enabled in its PLL mode, the time-out on-chip timers that help regulate the Power-on Reset sequence following a Power-on Reset is slightly differ- process. Their main function is to ensure that the ent from other oscillator modes. A separate timer is device clock is stable before code is executed. These used to provide a fixed time-out that is sufficient for the timers are: PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the • Power-up Timer (PWRT) oscillator start-up time-out. • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 4.5.1 POWER-UP TIMER (PWRT) 1. After the POR pulse has cleared, PWRT time-out The Power-up Timer (PWRT) of PIC18F2X1X/4X1X is invoked (if enabled). devices is an 11-bit counter which uses the INTRC 2. Then, the OST is activated. source as the clock input. This yields an approximate time interval of 2048x32μs=65.6ms. While the The total time-out will vary based on oscillator configu- PWRT is counting, the device is held in Reset. ration and the status of the PWRT. Figure4-3, Figure4-4, Figure4-5, Figure4-6 and Figure4-7 all The power-up time delay depends on the INTRC clock depict time-out sequences on power-up, with the and will vary from chip to chip due to temperature and Power-up Timer enabled and the device operating in process variation. See DC parameter 33 for details. HS Oscillator mode. Figures 4-3 through 4-6 also The PWRT is enabled by clearing the PWRTEN apply to devices operating in XT or LP modes. For Configuration bit. devices in RC mode and with the PWRT disabled, there will be no time-out at all. 4.5.2 OSCILLATOR START-UP TIMER Since the time-outs occur from the POR pulse, if MCLR (OST) is kept low long enough, all time-outs will expire. Bring- The Oscillator Start-up Timer (OST) provides a 1024 ing MCLR high will begin execution immediately oscillator cycle (from OSC1 input) delay after the (Figure4-5). This is useful for testing purposes or to PWRT delay is over (parameter 33). This ensures that synchronize more than one PIC18FXXXX device the crystal oscillator or resonator has started and operating in parallel. stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit From Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. DS39636D-page 47

PIC18F2X1X/4X1X FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39636D-page 48 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2009 Microchip Technology Inc. DS39636D-page 49

PIC18F2X1X/4X1X 4.6 Reset State of Registers Table4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table4-3. These bits are used in software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during power-managed 0000h u(2) u 1 u u u u u Run modes MCLR during power-managed 0000h u(2) u 1 0 u u u u Idle modes and Sleep mode WDT time-out during full power 0000h u(2) u 0 u u u u u or power-managed Run mode MCLR during full power 0000h u(2) u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during PC + 2 u(2) u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2(1) u(2) u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’. DS39636D-page 50 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Register Applicable Devices Brown-out RESET WDT Reset Instruction, or Interrupt Stack Resets TOSU 2410 2510 2515 2610 4410 4510 4515 4610 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2410 2510 2515 2610 4410 4510 4515 4610 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2410 2510 2515 2610 4410 4510 4515 4610 ---0 0000 ---0 0000 ---u uuuu PCLATH 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu PCL 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2410 2510 2515 2610 4410 4510 4515 4610 --00 0000 --00 0000 --uu uuuu TBLPTRH 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu TABLAT 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu PRODH 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2410 2510 2515 2610 4410 4510 4515 4610 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2410 2510 2515 2610 4410 4510 4515 4610 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2410 2510 2515 2610 4410 4510 4515 4610 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A POSTINC0 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A POSTDEC0 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A PREINC0 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A PLUSW0 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A FSR0H 2410 2510 2515 2610 4410 4510 4515 4610 ---- 0000 ---- 0000 ---- uuuu FSR0L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A POSTINC1 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A POSTDEC1 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A PREINC1 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A PLUSW1 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 51

PIC18F2X1X/4X1X TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Register Applicable Devices Brown-out RESET WDT Reset Instruction, or Interrupt Stack Resets FSR1H 2410 2510 2515 2610 4410 4510 4515 4610 ---- 0000 ---- 0000 ---- uuuu FSR1L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2410 2510 2515 2610 4410 4510 4515 4610 ---- 0000 ---- 0000 ---- uuuu INDF2 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A POSTINC2 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A POSTDEC2 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A PREINC2 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A PLUSW2 2410 2510 2515 2610 4410 4510 4515 4610 N/A N/A N/A FSR2H 2410 2510 2515 2610 4410 4510 4515 4610 ---- 0000 ---- 0000 ---- uuuu FSR2L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2410 2510 2515 2610 4410 4510 4515 4610 ---x xxxx ---u uuuu ---u uuuu TMR0H 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu TMR0L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111 1111 1111 uuuu uuuu OSCCON 2410 2510 2515 2610 4410 4510 4515 4610 0100 q000 0100 q000 uuuu uuqu HLVDCON 2410 2510 2515 2610 4410 4510 4515 4610 0-00 0101 0-00 0101 u-uu uuuu WDTCON 2410 2510 2515 2610 4410 4510 4515 4610 ---- ---0 ---- ---0 ---- ---u RCON(4) 2410 2510 2515 2610 4410 4510 4515 4610 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 u0uu uuuu uuuu uuuu TMR2 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu PR2 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111 1111 1111 1111 1111 T2CON 2410 2510 2515 2610 4410 4510 4515 4610 -000 0000 -000 0000 -uuu uuuu SSPBUF 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu SSPCON1 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu SSPCON2 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39636D-page 52 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Register Applicable Devices Brown-out RESET WDT Reset Instruction, or Interrupt Stack Resets ADRESH 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2410 2510 2515 2610 4410 4510 4515 4610 --00 0000 --00 0000 --uu uuuu ADCON1 2410 2510 2515 2610 4410 4510 4515 4610 --00 0qqq --00 0qqq --uu uuuu ADCON2 2410 2510 2515 2610 4410 4510 4515 4610 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu 2410 2510 2515 2610 4410 4510 4515 4610 --00 0000 --00 0000 --uu uuuu CCPR2H 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2410 2510 2515 2610 4410 4510 4515 4610 --00 0000 --00 0000 --uu uuuu BAUDCON 2410 2510 2515 2610 4410 4510 4515 4610 01-0 0-00 01-0 0-00 --uu uuuu PWM1CON 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu 2410 2510 2515 2610 4410 4510 4515 4610 0000 00-- 0000 00-- uuuu uu-- CVRCON 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu CMCON 2410 2510 2515 2610 4410 4510 4515 4610 0000 0111 0000 0111 uuuu uuuu TMR3H 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu SPBRG 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu RCREG 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu TXREG 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu TXSTA 2410 2510 2515 2610 4410 4510 4515 4610 0000 0010 0000 0010 uuuu uuuu RCSTA 2410 2510 2515 2610 4410 4510 4515 4610 0000 000x 0000 000x uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 53

PIC18F2X1X/4X1X TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Register Applicable Devices Brown-out RESET WDT Reset Instruction, or Interrupt Stack Resets IPR2 2410 2510 2515 2610 4410 4510 4515 4610 11-- 1111 11-- 1111 uu-- uuuu PIR2 2410 2510 2515 2610 4410 4510 4515 4610 00-- 0000 00-- 0000 uu-- uuuu(1) PIE2 2410 2510 2515 2610 4410 4510 4515 4610 00-- 0000 00-- 0000 uu-- uuuu IPR1 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111 1111 1111 uuuu uuuu 2410 2510 2515 2610 4410 4510 4515 4610 -111 1111 -111 1111 -uuu uuuu PIR1 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu(1) 2410 2510 2515 2610 4410 4510 4515 4610 -000 0000 -000 0000 -uuu uuuu(1) PIE1 2410 2510 2515 2610 4410 4510 4515 4610 0000 0000 0000 0000 uuuu uuuu 2410 2510 2515 2610 4410 4510 4515 4610 -000 0000 -000 0000 -uuu uuuu OSCTUNE 2410 2510 2515 2610 4410 4510 4515 4610 00-0 0000 00-0 0000 uu-u uuuu TRISE 2410 2510 2515 2610 4410 4510 4515 4610 0000 -111 0000 -111 uuuu -uuu TRISD 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111 1111 1111 uuuu uuuu TRISC 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111 1111 1111 uuuu uuuu TRISB 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111 1111 1111 uuuu uuuu TRISA(5) 2410 2510 2515 2610 4410 4510 4515 4610 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATE 2410 2510 2515 2610 4410 4510 4515 4610 ---- -xxx ---- -uuu ---- -uuu LATD 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTE 2410 2510 2515 2610 4410 4510 4515 4610 ---- x000 ---- x000 ---- uuuu PORTD 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2410 2510 2515 2610 4410 4510 4515 4610 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 2410 2510 2515 2610 4410 4510 4515 4610 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39636D-page 54 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization There are two types of memory in PIC18F2X1X/4X1X PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses; this allows for The PIC18F2410/4410 and PIC18F2510 each have concurrent access of the two memory spaces. 16Kbytes of Flash memory and can store up to 8,192 Additional detailed information on the operation of the single-word instructions. The PIC18F2510/4510 each Flash program memory is provided in Section6.0 have 32Kbytes of Flash memory and can store up to “Flash Program Memory”. 16,384 single-word instructions. The PIC18F2515/4515 each have 48Kbytes of Flash memory and can store up to 24,576 single-word instructions. The PIC18F2610/ 4610 each have 64Kbytes of Flash memory and can store up to 32,768 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18F2X1X/4X1X devices is shown in Figure5-1. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2X1X/4X1X DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1 • • • Stack Level 31 Reset Vector 00000h High Priority Interrupt Vector 00008h Low Priority Interrupt Vector 00018h On-Chip On-Chip On-Chip On-Chip Program Memory Program Memory Program Memory Program Memory (16 Kbytes) (32 Kbytes) (48 Kbytes) (64 Kbytes) 03FFFh 04000h e c a p S y 07FFFh or m 08000h e M 0BFFFh er 0C000h s U 0FFFFh 10000h Read ‘0’ Read ‘0’ Read ‘0’ Read ‘0’ 1FFFFFh PIC18F2410/4410 PIC18F2510/4510 PIC18F2515/4515 PIC18F2610/4610 200000h © 2009 Microchip Technology Inc. DS39636D-page 55

PIC18F2X1X/4X1X 5.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the top-of- low byte, known as the PCL register, is both readable stack Special File Registers. Data can also be pushed and writable. The high byte, or PCH register, contains to, or popped from the stack, using these registers. the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the A CALL type instruction causes a push onto the stack; PCLATH register. The upper byte is called PCU. This the Stack Pointer is first incremented and the location register contains the PC<20:16> bits; it is also not pointed to by the Stack Pointer is written with the directly readable or writable. Updates to the PCU contents of the PC (already pointing to the instruction register are performed through the PCLATU register. following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location The contents of PCLATH and PCLATU are transferred pointed to by the STKPTR are transferred to the PC to the program counter by any operation that writes and then the Stack Pointer is decremented. PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an The Stack Pointer is initialized to ‘00000’ after all operation that reads PCL. This is useful for computed Resets. There is no RAM associated with the location offsets to the PC (see Section5.1.4.1 “Computed corresponding to a Stack Pointer value of ‘00000’; this GOTO”). is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word 5.1.2.1 Top-of-Stack Access instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by 2 to address Only the top of the return address stack (TOS) is sequential instructions in the program memory. readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack loca- The CALL, RCALL, GOTO and program branch tion pointed to by the STKPTR register (Figure5-2). This instructions write to the program counter directly. For allows users to implement a software stack if necessary. these instructions, the contents of PCLATH and After a CALL, RCALL or interrupt, the software can read PCLATU are not transferred to the program counter. the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined 5.1.2 RETURN ADDRESS STACK software stack. At return time, the software can return The return address stack allows any combination of up these values to TOSU:TOSH:TOSL and do a return. to 31 program calls and interrupts to occur. The PC is The user must disable the global interrupt enable bits pushed onto the stack when a CALL or RCALL instruc- while accessing the stack to prevent inadvertent stack tion is executed or an interrupt is Acknowledged. The corruption. PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS39636D-page 56 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register5-1) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bits. The value set until cleared by software or until a POR occurs. of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is 5.1.2.3 PUSH and POP Instructions set. The STKFUL bit is cleared by software or by a POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack without disturbing normal program execution flow Reset Enable) Configuration bit. (Refer to is a desirable feature. The PIC18 instruction set Section22.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by decre- Any additional pushes will not overwrite the 31st push menting the Stack Pointer. The previous value pushed and STKPTR will remain at 31. onto the stack then becomes the TOS value. REGISTER 5-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 57

PIC18F2X1X/4X1X 5.1.2.4 Stack Full and Underflow Resets 5.1.4 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.1.4.1 Computed GOTO 5.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A fast register stack is provided for the STATUS, Example5-2. WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only A look-up table can be formed with an ADDWF PCL one level deep and is neither readable nor writable. It is instruction and a group of RETLW nn instructions. The loaded with the current value of the corresponding reg- W register is loaded with an offset into the table before ister when the processor vectors for an interrupt. All executing a call to that table. The first instruction of the interrupt sources will push values into the stack regis- called routine is the ADDWF PCL instruction. The next ters. The values in the registers are then loaded back instruction executed will be one of the RETLW nn into their associated registers if the RETFIE, FAST instructions that returns the value ‘nn’ to the calling instruction is used to return from the interrupt. function. If both low and high priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low priority interrupts. If a high priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low priority interrupt, the stack register In this method, only one data byte may be stored in values stored by the low priority interrupt will be each instruction location and room on the return overwritten. In these cases, users must save the key address stack is required. registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 5-2: COMPUTED GOTO USING fast register stack for returns from interrupt. If no inter- AN OFFSET VALUE rupts are used, the fast register stack can be used to MOVF OFFSET, W restore the STATUS, WREG and BSR registers at the CALL TABLE end of a subroutine call. To use the fast register stack ORG nn00h for a subroutine call, a CALL label, FAST instruction TABLE ADDWF PCL must be executed to save the STATUS, WREG and RETLW nnh BSR registers to the fast register stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the fast register stack. . . Example5-1 shows a source code example that uses . the fast register stack during a subroutine call and return. 5.1.4.2 Table Reads and Table Writes EXAMPLE 5-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word by using table reads and writes. The • Table Pointer (TBLPTR) register specifies the byte • address and the Table Latch (TABLAT) register contains the data that is read from or written to program SUB1 • memory. Data is transferred to or from program • memory one byte at a time. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Table read and table write operations are discussed further in Section6.1 “Table Reads”. DS39636D-page 58 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 5.2 PIC18 Instruction Cycle 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 5.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the pipe- (Q1, Q2, Q3 and Q4). Internally, the program counter is lining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the instruc- change (e.g., GOTO), then two cycles are required to tion register during Q4. The instruction is decoded and complete the instruction (Example5-3). executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC) clocks and instruction execution flow are shown in incrementing in Q1. Figure5-3. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. DS39636D-page 59

PIC18F2X1X/4X1X 5.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two bytes or four bytes in program word address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure5-4 shows how the with an even address (LSb = 0). To maintain alignment instruction GOTO 0006h is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSb will always read ‘0’ (see Section5.1.1 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure5-4 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section23.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 5.2.4 TWO-WORD INSTRUCTIONS some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases The standard PIC18 instruction set has four two-word when the two-word instruction is preceded by a condi- instructions: CALL, MOVFF, GOTO and LSFR. In all tional instruction that changes the PC. Example5-4 cases, the second word of the instructions always has shows how this works. ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. Note: See Section5.6 “PIC18 Instruction Execution and the Extended Instruc- The use of ‘1111’ in the 4 MSbs of an instruction spec- tion Set” for information on two-word ifies a special form of NOP. If the instruction is executed instructions in the extended instruction in proper sequence – immediately after the first word – set. the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for EXAMPLE 5-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS39636D-page 60 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 5.3 Data Memory Organization 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section5.5 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Figures 5-5, 5-6 and 5-7 show the data addressed directly by its full 12-bit address, or an 8-bit memory organization for the PIC18F2X1X/4X1X low-order address and a 4-bit Bank Pointer. devices. Most instructions in the PIC18 instruction set make use The data memory contains Special Function Registers of the Bank Pointer, known as the Bank Select Register (SFRs) and General Purpose Registers (GPRs). The (BSR). This SFR holds the 4 Most Significant bits of a SFRs are used for control and status of the controller location’s address; the instruction itself includes the and peripheral functions, while GPRs are used for data 8Least Significant bits. Only the four lower bits of the storage and scratchpad operations in the user’s BSR are implemented (BSR3:BSR0). The upper four application. Any read of an unimplemented location will bits are unused; they will always read ‘0’ and cannot be read as ‘0’s. written to. The BSR can be loaded directly by using the MOVLB instruction. The instruction set and architecture allow operations across all banks. The entire data memory may be The value of the BSR indicates the bank in data accessed by Direct, Indirect or Indexed Addressing memory; the 8 bits in the instruction show the location modes. Addressing modes are discussed later in this in the bank and can be thought of as an offset from the subsection. bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is To ensure that commonly used registers (SFRs and shown in Figure5-8. select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte Since up to 16 registers may share the same low-order memory space that provides fast access to SFRs and address, the user must always be careful to ensure that the lower portion of GPR Bank 0 without using the the proper bank is selected before performing a data BSR. Section5.3.2 “Access Bank” provides a read or write. For example, writing what should be detailed description of the Access RAM. program data to an 8-bit address of F9h, while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure5-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. DS39636D-page 61

PIC18F2X1X/4X1X FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2410/4410 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 07Fh Bank 0 080h The first 128 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 128 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 7Fh FFh 7FFh Access RAM High 80h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h Unused 900h Bank 9 Read 00h FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF70F0hh Bank 15 F80h FFh SFR FFFh DS39636D-page 62 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2510/4510 DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 07Fh Bank 0 080h The first 128 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 128 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 7Fh FFh 7FFh Access RAM High 80h = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h 900h Bank 9 FFh 9FFh = 1010 00h Unused A00h Bank 10 Read 00h FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF70F0hh Bank 15 F80h FFh SFR FFFh © 2009 Microchip Technology Inc. DS39636D-page 63

PIC18F2X1X/4X1X FIGURE 5-7: DATA MEMORY MAP FOR PIC18F2515/2610/4515/4610 DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 07Fh Bank 0 080h The first 128 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 128 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When a = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 GPR Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 GPR Access RAM Low 7Fh FFh 7FFh Access RAM High 80h = 1000 Bank 8 00h GPR 800h (SFRs) FFh FFh 8FFh = 1001 00h 900h Bank 9 GPR FFh 9FFh = 1010 00h A00h Bank 10 GPR FFh AFFh = 1011 00h B00h Bank 11 GPR FFh BFFh C00h = 1100 00h Bank 12 GPR CFFh FFh D00h = 1101 00h Bank 13 GPR DFFh FFh 00h E00h = 1110 Bank 14 GPR FFh EFFh = 1111 00h GPR FF70F0hh Bank 15 F80h FFh SFR FFFh DS39636D-page 64 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 5-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 5.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without While the use of the BSR with an embedded 8-bit updating the BSR first. For 8-bit addresses of 80h and address allows users to address the entire range of above, this means that users can evaluate and operate data memory, it also means that the user must always on SFRs more efficiently. The Access RAM below 80h ensure that the correct bank is selected. Otherwise, is a good place for data values that the user might need data may be read from or written to the wrong location. to access rapidly, such as immediate computational This can be disastrous if a GPR is the intended target results or common program variables. Access RAM of an operation, but an SFR is written to instead. also allows for faster and more code efficient context Verifying and/or changing the BSR for each read or saving and switching of variables. write to data memory can become very inefficient. The mapping of the Access Bank is slightly different To streamline access for the most commonly used data when the extended instruction set is enabled (XINST memory locations, the data memory is configured with Configuration bit = 1). This is discussed in more detail an Access Bank, which allows users to access a in Section5.5.3 “Mapping the Access Bank in mapped block of memory without specifying a BSR. Indexed Literal Offset Addressing Mode”. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of 5.3.3 GENERAL PURPOSE REGISTER memory (80h-FFh) in Block 15. The lower half is known FILE as the “Access RAM” and is composed of GPRs. This upper half is also where the device’s SFRs are PIC18 devices may have banked memory in the GPR mapped. These two areas are mapped contiguously in area. This is data RAM, which is available for use by all the Access Bank and can be addressed in a linear instructions. GPRs start at the bottom of Bank 0 fashion by an 8-bit address (Figure5-5). (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on The Access Bank is used by core PIC18 instructions Reset and are unchanged on all other Resets. that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2009 Microchip Technology Inc. DS39636D-page 65

PIC18F2X1X/4X1X 5.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those asso- ciated with the “core” device functionality (ALU, Resets The Special Function Registers (SFRs) are registers and interrupts) and those related to the peripheral func- used by the CPU and peripheral modules for controlling tions. The reset and interrupt registers are described in the desired operation of the device. These registers are their respective chapters, while the ALU’s STATUS reg- implemented as static RAM. SFRs start at the top of ister is described later in this section. Registers related data memory (FFFh) and extend downward to occupy to the operation of a peripheral feature are described in the top half of Bank 15 (F80h to FFFh). A list of these the chapter for that peripheral. registers is given in Table5-1 and Table5-2. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X1X/4X1X DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON(3) F97h —(2) FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB FE9h FSR0L FC9h SSPBUF FA9h —(2) F89h LATA FE8h WREG FC8h SSPADD FA8h —(2) F88h —(2) FE7h INDF1(1) FC7h SSPSTAT FA7h —(2) F87h —(2) FE6h POSTINC1(1) FC6h SSPCON1 FA6h —(2) F86h —(2) FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE(3) FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices. DS39636D-page 66 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 51, 56 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 51, 56 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 51, 56 STKPTR STKFUL(6) STKUNF(6) — SP4 SP3 SP2 SP1 SP0 00-0 0000 51, 57 PCLATU — — — Holding Register for PC<20:16> ---0 0000 51, 56 PCLATH Holding Register for PC<15:8> 0000 0000 51, 56 PCL PC Low Byte (PC<7:0>) 0000 0000 51, 56 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 51, 79 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 51, 79 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 51, 79 TABLAT Program Memory Table Latch 0000 0000 51, 79 PRODH Product Register High Byte xxxx xxxx 51, 81 PRODL Product Register Low Byte xxxx xxxx 51, 81 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 51, 85 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 51, 86 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 51, 87 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 51, 72 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 51, 72 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 51, 72 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 51, 72 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 51, 72 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 51, 72 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 51, 72 WREG Working Register xxxx xxxx 51 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 51, 72 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 51, 72 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 51, 72 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 51, 72 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 51, 72 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 52, 72 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 52, 72 BSR — — — — Bank Select Register ---- 0000 52, 61 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 52, 72 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 52, 72 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 52, 72 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 52, 72 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 52, 72 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 52, 72 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 52, 72 STATUS — — — N OV Z DC C ---x xxxx 52, 70 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. © 2009 Microchip Technology Inc. DS39636D-page 67

PIC18F2X1X/4X1X TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TMR0H Timer0 Register High Byte 0000 0000 52, 117 TMR0L Timer0 Register Low Byte xxxx xxxx 52, 117 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 52, 115 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 32, 52 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 52, 233 WDTCON — — — — — — — SWDTEN --- ---0 52, 249 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 44, 50, 94 TMR1H Timer1 Register High Byte xxxx xxxx 52, 123 TMR1L Timer1 Register Low Bytes xxxx xxxx 52, 123 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 52, 119 TMR2 Timer2 Register 0000 0000 52, 126 PR2 Timer2 Period Register 1111 1111 52, 126 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 125 SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 52, 161, 162 SSPADD SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. 0000 0000 52, 162 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 52, 154, 163 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 52, 155, 164 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 52, 165 ADRESH A/D Result Register High Byte xxxx xxxx 53, 222 ADRESL A/D Result Register Low Byte xxxx xxxx 53, 222 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 53, 213 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 53, 214 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 53, 215 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 53, 132 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 53, 132 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53, 131, 139 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 53, 132 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 53, 132 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 53, 131 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 53, 196 PWM1CON PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 53, 148 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 53, 149 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 53, 229 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 53, 223 TMR3H Timer3 Register High Byte xxxx xxxx 53, 129 TMR3L Timer3 Register Low Byte xxxx xxxx 53, 129 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 53, 127 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. DS39636D-page 68 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 53, 197 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 53, 197 RCREG EUSART Receive Register 0000 0000 53, 204 TXREG EUSART Transmit Register 0000 0000 53, 202 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53, 194 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 53, 195 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 54, 93 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 54, 89 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 54, 91 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 54, 92 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 54, 88 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 54, 90 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 29, 54 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 54, 110 TRISD(2) PORTD Data Direction Control Register 1111 1111 54, 106 TRISC PORTC Data Direction Control Register 1111 1111 54, 103 TRISB PORTB Data Direction Control Register 1111 1111 54, 100 TRISA TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA 1111 1111 54, 97 LATE(2) — — — — — PORTE Data Latch Register ---- -xxx 54, 109 (Read and Write to Data Latch) LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 106 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 103 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 100 LATA LATA7(6) LATA6(6) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 54, 97 PORTE — — — — RE3(4) RE2(2) RE1(2) RE0(2) ---- xxxx 54, 109 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 54, 106 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 54, 103 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54, 100 PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 54, 97 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit=0). Otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. © 2009 Microchip Technology Inc. DS39636D-page 69

PIC18F2X1X/4X1X 5.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register5-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Table23-2 and tion that affects the Z, DC, C, OV or N bits, the results Table23-3. of the instruction are not written; instead, the status is updated according to the instruction performed. There- Note: The C and DC bits operate as the borrow fore, the result of an instruction with the STATUS and digit borrow bits, respectively, in register as its destination may be different than subtraction. intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 5-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 70 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 5.4 Data Addressing Modes The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section5.3.1 “Bank Select Register (BSR)”) are core PIC18 instruction set are changed used with the address to determine the complete 12-bit when the PIC18 extended instruction set is address of the register. When ‘a’ is ‘0’, the address is enabled. See Section5.5 “Data Memory interpreted as being a register in the Access Bank. and the Extended Instruction Set” for Addressing that uses the Access RAM is sometimes more information. also known as Direct Forced Addressing mode. The data memory space can be addressed in several A few instructions, such as MOVFF, include the entire ways. For most instructions, the addressing mode is 12-bit address (either source or destination) in their fixed. Other instructions may use up to three modes, opcodes. In these cases, the BSR is ignored entirely. depending on which operands are used and whether or The destination of the operation’s results is determined not the extended instruction set is enabled. by the destination bit ‘d’. When ‘d’ is ‘1’, the results are The addressing modes are: stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Inherent the W register. Instructions without the ‘d’ argument • Literal have a destination that is implicit in the instruction; their • Direct destination is either the target register being operated • Indirect on or the W register. An additional addressing mode, Indexed Literal Offset, 5.4.3 INDIRECT ADDRESSING is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is Indirect addressing allows the user to access a location discussed in greater detail in Section5.5.1 “Indexed in data memory without giving a fixed address in the Addressing with Literal Offset”. instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written 5.4.1 INHERENT AND LITERAL to. Since the FSRs are themselves located in RAM as ADDRESSING Special File Registers, they can also be directly manip- ulated under program control. This makes FSRs very Many PIC18 control instructions do not need any useful in implementing data structures, such as tables argument at all; they either perform an operation that and arrays in data memory. globally affects the device or they operate implicitly on one register. This addressing mode is known as The registers for indirect addressing are also Inherent Addressing. Examples include SLEEP, RESET implemented with Indirect File Operands (INDFs) that and DAW. permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting Other instructions work in a similar way but require an with another value. This allows for efficient code, using additional explicit argument in the opcode. This is loops, such as the example of clearing an entire RAM known as Literal Addressing mode because they bank in Example5-5. require some literal value as an argument. Examples include ADDLW and MOVLW which, respectively, add or EXAMPLE 5-5: HOW TO CLEAR RAM move a literal value to the W register. Other examples (BANK 1) USING include CALL and GOTO, which include a 20-bit INDIRECT ADDRESSING program memory address. LFSR FSR0, 100h ; 5.4.2 DIRECT ADDRESSING NEXT CLRF POSTINC0 ; Clear INDF ; register then Direct addressing specifies all or part of the source ; inc pointer and/or destination address of the operation within the BTFSS FSR0H,1 ; All done with opcode itself. The options are specified by the ; Bank1? arguments accompanying the instruction. BRA NEXT ; NO, clear next In the core PIC18 instruction set, bit-oriented and byte- CONTINUE ; YES, continue oriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section5.3.3 “General Purpose Register File”) or a location in the Access Bank (Section5.3.2 “Access Bank”) as the data source for the instruction. © 2009 Microchip Technology Inc. DS39636D-page 71

PIC18F2X1X/4X1X 5.4.3.1 FSR Registers and the INDF 5.4.3.2 FSR Registers and POSTINC, Operand POSTDEC, PREINC and PLUSW At the core of indirect addressing are three sets of In addition to the INDF operand, each FSR register pair registers: FSR0, FSR1 and FSR2. Each represents a also has four additional indirect operands. Like INDF, pair of 8-bit registers, FSRnH and FSRnL. The four these are “virtual” registers that cannot be indirectly upper bits of the FSRnH register are not used so each read or written to. Accessing these registers actually FSR pair holds a 12-bit value. This represents a value accesses the associated FSR register pair, but also that can address the entire range of the data memory performs a specific action on its stored value. They are: in a linear fashion. The FSR register pairs, then, serve • POSTDEC: accesses the FSR value, then as pointers to data memory locations. automatically decrements it by 1 afterwards Indirect addressing is accomplished with a set of • POSTINC: accesses the FSR value, then Indirect File Operands, INDF0 through INDF2. These automatically increments it by 1 afterwards can be thought of as “virtual” registers: they are • PREINC: increments the FSR value by 1, then mapped in the SFR space but are not physically imple- uses it in the operation mented. Reading or writing to a particular INDF register • PLUSW: adds the signed value of the W register actually accesses its corresponding FSR register pair. (range of -127 to 128) to that of the FSR and uses A read from INDF1, for example, reads the data at the the new value in the operation. address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the In this context, accessing an INDF register uses the contents of their corresponding FSR as a pointer to the value in the FSR registers without changing them. Sim- instruction’s target. The INDF operand is just a ilarly, accessing a PLUSW register gives the FSR value convenient way of using the pointer. offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual Because indirect addressing uses a full 12-bit address, registers changes the value of the FSR registers. data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no Operations on the FSRs with POSTDEC, POSTINC effect on determining the target address. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). FIGURE 5-9: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory DS39636D-page 72 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X The PLUSW register can be used to implement a form 5.5.1 INDEXED ADDRESSING WITH of indexed addressing in the data memory space. By LITERAL OFFSET manipulating the value in the W register, users can Enabling the PIC18 extended instruction set changes reach addresses that are fixed offsets from pointer the behavior of indirect addressing using the FSR2 addresses. In some applications, this can be used to register pair within access RAM. Under the proper implement some powerful program control structure, conditions, instructions that use the Access Bank – that such as software stacks, inside of data memory. is, most bit-oriented and byte-oriented instructions – 5.4.3.3 Operations by FSRs on FSRs can invoke a form of indexed addressing using an offset specified in the instruction. This special address- Indirect addressing operations that target other FSRs ing mode is known as Indexed Addressing with Literal or virtual registers represent special cases. For exam- Offset, or Indexed Literal Offset mode. ple, using an FSR to point to one of the virtual registers When using the extended instruction set, this will not result in successful operations. As a specific addressing mode requires the following: case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the • The use of the Access Bank is forced (‘a’ = 0); INDF1 using INDF0 as an operand will return 00h. and Attempts to write to INDF1 using INDF0 as the operand • The file address argument is less than or equal to will result in a NOP. 5Fh. On the other hand, using the virtual registers to write to Under these conditions, the file address of the instruc- an FSR pair may not occur as planned. In these cases, tion is not interpreted as the lower byte of an address the value will be written to the FSR pair but without any (used with the BSR in direct addressing), or as an 8-bit incrementing or decrementing. Thus, writing to INDF2 address in the Access Bank. Instead, the value is or POSTDEC2 will write the same value to the interpreted as an offset value to an Address Pointer, FSR2H:FSR2L. specified by FSR2. The offset and the contents of Since the FSRs are physical registers mapped in the FSR2 are added to obtain the target address of the SFR space, they can be manipulated through all direct operation. operations. Users should proceed cautiously when 5.5.2 INSTRUCTIONS AFFECTED BY working on these registers, particularly if their code INDEXED LITERAL OFFSET MODE uses indirect addressing. Similarly, operations by indirect addressing are gener- Any of the core PIC18 instructions that can use direct ally permitted on all other SFRs. Users should exercise addressing are potentially affected by the Indexed Literal the appropriate caution that they do not inadvertently Offset Addressing mode. This includes all byte-oriented change settings that might affect the operation of the and bit-oriented instructions, or almost one-half of the device. standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. 5.5 Data Memory and the Extended Additionally, byte-oriented and bit-oriented instructions Instruction Set are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h Enabling the PIC18 extended instruction set (XINST or above. Instructions meeting these criteria will Configuration bit = 1) significantly changes certain continue to execute as before. A comparison of the aspects of data memory and its addressing. Specifi- different possible addressing modes when the cally, the use of the Access Bank for many of the core extended instruction set is enabled is shown in PIC18 instructions is different; this is due to the Figure5-10. introduction of a new addressing mode for the data Those who desire to use bit-oriented or byte-oriented memory space. instructions in the Indexed Literal Offset mode should What does not change is just as important. The size of note the changes to assembler syntax for this mode. the data memory space is unchanged, as well as its This is described in more detail in Section23.2.1 linear addressing. The SFR map remains the same. “Extended Instruction Syntax”. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2009 Microchip Technology Inc. DS39636D-page 73

PIC18F2X1X/4X1X FIGURE 5-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and f ≥ 60h: The instruction executes in 060h 080h Direct Forced mode. ‘f’ is inter- Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations 060h to 07Fh Bank 14 80h (Bank0) and F80h to FFFh Valid range for ‘f’ (Bank 15) of data memory. FFh Locations below 60h are not F00h Access RAM available in this addressing Bank 15 mode. F80h SFRs FFFh Data Memory When ‘a’ = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 080h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F80h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 080h Direct mode (also known as Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F80h SFRs FFFh Data Memory DS39636D-page 74 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 5.5.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET tions using the Indexed Literal Offset Addressing ADDRESSING MODE mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of access 5.6 PIC18 Instruction Execution and RAM (00h to 5Fh) are mapped. Rather than containing the Extended Instruction Set just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user defined Enabling the extended instruction set adds eight “window” that can be located anywhere in the data additional commands to the existing PIC18 instruction memory space. The value of FSR2 establishes the set. These instructions are executed as described in lower boundary of the addresses mapped into the Section23.2 “Extended Instruction Set”. window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section5.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure5-11. FIGURE 5-11: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Bank 0 05Fh FSR2H:FSR2L = 120h 07Fh Locations in the region Bank 0 from the FSR2 Pointer 100h Bank 1 (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Locations in Bank 0 from Bank 0 060h to 07Fh are mapped, 7Fh as usual, to the middle of Bank 2 80h the Access Bank. through SFRs Special File Registers at Bank 14 F80h through FFFh are FFh mapped to 80h through Access Bank FFh, as usual. F00h Bank 0 addresses below Bank 15 5Fh can still be addressed F80h by using the BSR. SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39636D-page 75

PIC18F2X1X/4X1X NOTES: DS39636D-page 76 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 6.0 FLASH PROGRAM MEMORY Table reads work with byte entities. A table block containing data, rather than program instructions, is not In PIC18F2X1X/4X1X devices, the program memory is required to be word-aligned. Therefore, a table block can implemented as read-only Flash memory. It is readable start and end at any byte address. over the entire VDD range during normal operation. A Because the program memory cannot be written to or read from program memory is executed on one byte at erased under normal operation, the TBLWT operation is a time. not discussed here. 6.1 Table Reads Note1: Although it cannot be used in PIC18F2X1X/4X1X devices in normal For PIC18 devices, there are two operations that allow operation, the TBLWT instruction is still the processor to move bytes between the program implemented in the instruction set. memory space and the data RAM: table read (TBLRD) Executing the instruction takes two and table write (TBLWT). instruction cycles, but effectively results Table read operations retrieve data from program in a NOP. memory and place it into the data RAM space. 2: The TBLWT instruction is available only in Figure6-1 shows the operation of a table read with programming modes and is used during program memory and data RAM. In-Circuit Serial Programming™ (ICSP™). The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register, TABLAT. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39636D-page 77

PIC18F2X1X/4X1X 6.2 Control Registers TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD Two control registers are used in conjunction with the INSTRUCTIONS TBLRD instruction: the TABLAT register and the TBLPTR register set. Example Operation on Table Pointer 6.2.1 TABLAT – TABLE LATCH REGISTER TBLRD* TBLPTR is not modified TBLRD*+ TBLPTR is incremented after the read The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to TBLRD*- TBLPTR is decremented after the read hold 8-bit data during data transfers between program TBLRD+* TBLPTR is incremented before the read memory and data RAM. 6.3 Reading the Flash Program 6.2.2 TBLPTR – TABLE POINTER Memory REGISTER The Table Pointer register (TBLPTR) addresses a byte The TBLRD instruction is used to retrieve data from within the program memory. It is comprised of three program memory and place it into data RAM. Table SFR registers: Table Pointer Upper Byte, Table Pointer reads from program memory are performed one byte at High Byte and Table Pointer Low Byte a time. (TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six TBLPTR points to a byte address in program space. bits of TBLPTRU are used with TBLPTRH and Executing TBLRD places the byte pointed to into TBLPTRL, to form a 22-bit wide pointer. TABLAT. In addition, TBLPTR can be modified The contents of TBLPTR indicate a location in program automatically for the next table read operation. memory space. The low-order 21bits allow the device The internal program memory is typically organized by to address the full 2 Mbytes of program memory space. words. The Least Significant bit of the address selects The 22nd bit allows access to the configuration space, between the high and low bytes of the word. Figure6-2 including the Device ID, user ID locations and the shows the interface between the internal program Configuration bits. memory and the TABLAT. The TBLPTR register set is updated when executing a A typical method for reading data from program memory TBLRD in one of four ways, based on the instruction’s is shown in Example6-1. arguments. These are detailed in Table6-1. These operations on the TBLPTR only affect the low-order 21bits. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. FIGURE 6-2: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register DS39636D-page 78 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD TABLE 6-2: REGISTERS ASSOCIATED WITH READING PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte 51 (TBLPTR<20:16>) TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 51 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 51 TABLAT Program Memory Table Latch 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. © 2009 Microchip Technology Inc. DS39636D-page 79

PIC18F2X1X/4X1X NOTES: DS39636D-page 80 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 7.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 7-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 7.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W MULWF ARG2 ; ARG1 * ARG2 -> advantages of higher computational throughput and ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table7-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 7.2 Operation Example7-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example7-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 7-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39636D-page 81

PIC18F2X1X/4X1X Example7-3 shows the sequence to do a 16 x 16 EQUATION 7-2: 16 x 16 SIGNED unsigned multiplication. Equation7-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 7-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 7-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 7-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example7-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation7-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the sign bits of the SIGN_ARG1 arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39636D-page 82 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 8.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18F2X1X/4X1X devices have multiple interrupt compatible with PIC® mid-range devices. In sources and an interrupt priority feature that allows Compatibility mode, the interrupt priority bits for each most interrupt sources to be assigned a high priority source have no effect. INTCON<6> is the PEIE bit, level or a low priority level. The high priority interrupt which enables/disables all peripheral interrupt sources. vector is at 0008h and the low priority interrupt vector is INTCON<7> is the GIE bit, which enables/disables all at 0018h. High priority interrupt events will interrupt any interrupt sources. All interrupts branch to address low priority interrupts that may be in progress. 0008h in Compatibility mode. There are ten registers which are used to control When an interrupt is responded to, the global interrupt interrupt operation. These registers are: enable bit is cleared to disable further interrupts. If the • RCON IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. • INTCON High priority interrupt sources can interrupt a low • INTCON2 priority interrupt. Low priority interrupts are not • INTCON3 processed while high priority interrupts are in progress. • PIR1, PIR2 The return address is pushed onto the stack and the • PIE1, PIE2 PC is loaded with the interrupt vector address (0008h • IPR1, IPR2 or 0018h). Once in the Interrupt Service Routine, the It is recommended that the Microchip header files source(s) of the interrupt can be determined by polling supplied with MPLAB® IDE be used for the symbolic bit the interrupt flag bits. The interrupt flag bits must be names in these registers. This allows the assembler/ cleared in software before re-enabling interrupts to compiler to automatically take care of the placement of avoid recursive interrupts. these bits within the specified register. The “return from interrupt” instruction, RETFIE, exits In general, interrupt sources have three bits to control the interrupt routine and sets the GIE bit (GIEH or GIEL their operation. They are: if priority levels are used), which re-enables interrupts. • Flag bit to indicate that an interrupt event For external interrupt events, such as the INT pins or occurred the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact • Enable bit that allows program execution to latency is the same for one or two-cycle instructions. branch to the interrupt vector address when the Individual interrupt flag bits are set, regardless of the flag bit is set status of their corresponding enable bit or the GIE bit. • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify The interrupt priority feature is enabled by setting the any of the interrupt control registers while IPEN bit (RCON<7>). When interrupt priority is any interrupt is enabled. Doing so may enabled, there are two bits which enable interrupts cause erratic microcontroller behavior. globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vec- tor immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. DS39636D-page 83

PIC18F2X1X/4X1X FIGURE 8-1: PIC18 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU INT1IF Vector to Location INT1IE SSPIF INT1IP 0008h SSPIE INT2IF SSPIP INT2IE INT2IP GIEH/GIE ADIF ADIE ADIP IPEN RCIF IPEN RCIE GIEL/PEIE RCIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation SSPIF SSPIE SSPIP Interrupt to CPU TMR0IF Vector to Location TMR0IE 0018h ADIF TMR0IP ADIE ADIP RBIF RBIE RCIF RBIP GIEH/GIE RCIE GIEL/PEIE RCIP INT1IF INT1IE INT1IP Additional Peripheral Interrupts INT2IF INT2IE INT2IP DS39636D-page 84 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 8.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers, which contain various enable, priority and interrupt enable bit. User software should flag bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 8-1: INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 85

PIC18F2X1X/4X1X REGISTER 8-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39636D-page 86 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 8-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39636D-page 87

PIC18F2X1X/4X1X 8.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1 and PIR2). 2: User software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note1: This bit is unimplemented on 28-pin devices and is read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 88 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the High/Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCPx Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 89

PIC18F2X1X/4X1X 8.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 8-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note1: This bit is unimplemented on 28-pin devices and is read as ‘0’. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 90 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 8-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 91

PIC18F2X1X/4X1X 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 8-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority Note1: This bit is unimplemented on 28-pin devices and is read as ‘0’. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 92 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 8-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 93

PIC18F2X1X/4X1X 8.5 RCON Register The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section4.1 “RCON The RCON register contains flag bits which are used to Register”. determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 8-10: RCON REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(1) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16XXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit(1) For details of bit operation, see Register4-1. Note1: Actual Reset values are determined by device configuration and the nature of the device Reset. See Register4-1 for additional information. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-1. bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register4-1. bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 94 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 8.6 INTn Pin Interrupts 8.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh→00h) will set flag bit TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L regis- interrupt is triggered by a rising edge; if the bit is clear, ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt the trigger is on the falling edge. When a valid edge can be enabled/disabled by setting/clearing enable bit, appears on the RBx/INTx pin, the corresponding flag TMR0IE (INTCON<5>). Interrupt priority for Timer0 is bit INTxF is set. This interrupt can be disabled by clear- determined by the value contained in the interrupt ing the corresponding enable bit INTxE. Flag bit INTxF priority bit, TMR0IP (INTCON2<2>). See Section10.0 must be cleared in software in the Interrupt Service “Timer0 Module” for further details on the Timer0 Routine before re-enabling the interrupt. module. All external interrupts (INT0, INT1 and INT2) can wake- 8.8 PORTB Interrupt-on-Change up the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global An input change on PORTB<7:4> sets flag bit, RBIF Interrupt Enable bit, GIE, is set, the processor will (INTCON<0>). The interrupt can be enabled/disabled branch to the interrupt vector following wake-up. by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for INT1 and INT2 is determined by the Interrupt priority for PORTB interrupt-on-change is value contained in the interrupt priority bits, INT1IP determined by the value contained in the interrupt (INTCON3<6>) and INT2IP (INTCON3<7>). There is priority bit, RBIP (INTCON2<0>). no priority bit associated with INT0. It is always a high priority interrupt source. 8.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section5.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS © 2009 Microchip Technology Inc. DS39636D-page 95

PIC18F2X1X/4X1X NOTES: DS39636D-page 96 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 9.0 I/O PORTS Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. Depending on the device selected and features The Data Latch (LATA) register is also memory mapped. enabled, there are up to five ports available. Some pins Read-modify-write operations on the LATA register read of the I/O ports are multiplexed with an alternate and write the latched output value for PORTA. function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not The RA4 pin is multiplexed with the Timer0 module be used as a general purpose I/O pin. clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and Each port has three registers for its operation. These RA7 are multiplexed with the main oscillator pins; they registers are: are enabled as oscillator or I/O pins by the selection of • TRIS register (data direction register) the main oscillator in the Configuration register (see • PORT register (reads the levels on the pins of the Section22.1 “Configuration Bits” for details). When device) they are not used as port pins, RA6 and RA7 and their • LAT register (output latch) associated TRIS and LAT bits are read as ‘0’. The Data Latch (LAT register) is useful for read-modify- The other PORTA pins are multiplexed with analog write operations on the value that the I/O pins are inputs, the analog VREF+ and VREF- inputs and the com- driving. parator voltage reference output. The operation of pins RA3:RA0 and RA5 as A/D converter inputs is selected A simplified model of a generic I/O port, without the by clearing or setting the control bits in the ADCON1 interfaces to other peripherals, is shown in Figure9-1. register (A/D Control Register 1). FIGURE 9-1: GENERIC I/O PORT Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the OPERATION CMCON register. To use RA3:RA0 as digital inputs, it is also necessary to turn off the comparators. RD LAT Note: On a Power-on Reset, RA5 and RA3:RA0 Data are configured as analog inputs and read Bus D Q as ‘0’. RA4 is configured as a digital input. WR LAT I/O pin(1) orPort The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. CK All other PORTA pins have TTL input levels and full Data Latch CMOS output drivers. D Q The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. WR TRIS CK The user must ensure the bits in the TRISA register are TRIS Latch Input maintained set when using them as analog inputs. Buffer EXAMPLE 9-1: INITIALIZING PORTA RD TRIS CLRF PORTA ; Initialize PORTA by ; clearing output Q D ; data latches CLRF LATA ; Alternate method ENEN ; to clear output ; data latches RD Port MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs Note1: I/O pins have diode protection to VDD and VSS. MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to 9.1 PORTA, TRISA and LATA Registers ; initialize data ; direction PORTA is a 8-bit wide, bidirectional port. The corre- MOVWF TRISA ; Set RA<3:0> as inputs sponding data direction register is TRISA. Setting a ; RA<5:4> as outputs TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2009 Microchip Technology Inc. DS39636D-page 97

PIC18F2X1X/4X1X TABLE 9-1: PORTA I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D input channel 1 and comparator C2- input. Default input configuration on POR; does not affect digital output. RA2/AN2/ RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when VREF-/CVREF CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D input channel 2 and comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3 and comparator C1+ input. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator voltage reference high input. RA4/T0CKI/C1OUT RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI 1 I ST Timer0 clock input. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. RA5/AN4/SS/ RA5 0 O DIG LATA<5> data output; not affected by analog input. HLVDIN/C2OUT 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. SS 1 I TTL Slave select input for SSP (MSSP module). HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. OSC2/CLKO/RA6 RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator modes. OSC1/CLKI/RA7 RA7 0 O DIG LATA<7> data output. Disabled in External Oscillator modes. 1 I TTL PORTA<7> data input. Disabled in External Oscillator modes. OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS39636D-page 98 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 54 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 54 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 54 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 99

PIC18F2X1X/4X1X 9.2 PORTB, TRISB and LATB Four of the PORTB pins (RB7:RB4) have an interrupt- Registers on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin PORTB is an 8-bit wide, bidirectional port. The configured as an output is excluded from the interrupt- corresponding data direction register is TRISB. Setting on-change comparison). The input pins (of RB7:RB4) a TRISB bit (= 1) will make the corresponding PORTB are compared with the old value latched on the last pin an input (i.e., put the corresponding output driver in read of PORTB. The “mismatch” outputs of RB7:RB4 a high-impedance mode). Clearing a TRISB bit (= 0) are ORed together to generate the RB Port Change will make the corresponding PORTB pin an output (i.e., Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from the Sleep The Data Latch register (LATB) is also memory mode, or any of the Idle modes. The user, in the mapped. Read-modify-write operations on the LATB Interrupt Service Routine, can clear the interrupt in the register read and write the latched output value for following manner: PORTB. a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). EXAMPLE 9-2: INITIALIZING PORTB b) Clear flag bit RBIF. CLRF PORTB ; Initialize PORTB by A mismatch condition will continue to set flag bit RBIF. ; clearing output Reading PORTB will end the mismatch condition and ; data latches CLRF LATB ; Alternate method allow flag bit RBIF to be cleared. ; to clear output The interrupt-on-change feature is recommended for ; data latches wake-up on key depression operation and operations MOVLW 0Fh ; Set RB<4:0> as where PORTB is only used for the interrupt-on-change MOVWF ADCON1 ; digital I/O pins feature. Polling of PORTB is not recommended while ; (required if config bit using the interrupt-on-change feature. ; PBADEN is set) MOVLW 0CFh ; Value used to RB3 can be configured by the Configuration bit, ; initialize data CCP2MX, as the alternate peripheral pin for the CCP2 ; direction module (CCP2MX = 0). MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and read as ‘0’; RB7:RB5 are configured as digital inputs. By programming the Configuration bit, PBADEN, RB4:RB0 will alternatively be configured as digital inputs on POR. DS39636D-page 100 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 9-3: PORTB I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RB0/INT0/FLT0/ RB0 0 O DIG LATB<0> data output; not affected by analog input. AN12 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT0 1 I ST External interrupt 0 input. FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. AN12 1 I ANA A/D input channel 12.(1) RB1/INT1/AN10 RB1 0 O DIG LATB<1> data output; not affected by analog input. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT1 1 I ST External interrupt 1 input. AN10 1 I ANA A/D input channel 10.(1) RB2/INT2/AN8 RB2 0 O DIG LATB<2> data output; not affected by analog input. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT2 1 I ST External interrupt 2 input. AN8 1 I ANA A/D input channel 8.(1) RB3/AN9/CCP2 RB3 0 O DIG LATB<3> data output; not affected by analog input. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN9 1 I ANA A/D input channel 9.(1) CCP2(2) 0 O DIG CCP2 compare and PWM output. 1 I ST CCP2 capture input RB4/KBI0/AN11 RB4 0 O DIG LATB<4> data output; not affected by analog input. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) KBI0 1 I TTL Interrupt on pin change. AN11 1 I ANA A/D input channel 11.(1) RB5/KBI1/PGM RB5 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt on pin change. PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP Configuration bit; all other pin functions disabled. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt on pin change. PGC x I ST Serial execution (ICSP) clock input for ICSP and ICD operation.(3) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt on pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(3) x I ST Serial execution data input for ICSP and ICD operation.(3) Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. DS39636D-page 101

PIC18F2X1X/4X1X TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54 LATB PORTB Data Latch Register (Read and Write to Data Latch) 54 TRISB PORTB Data Direction Control Register 54 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 51 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 51 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. DS39636D-page 102 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 9.3 PORTC, TRISC and LATC The contents of the TRISC register are affected by Registers peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device PORTC is an 8-bit wide, bidirectional port. The corre- may be overriding one or more of the pins. sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC EXAMPLE 9-3: INITIALIZING PORTC pin an input (i.e., put the corresponding output driver in CLRF PORTC ; Initialize PORTC by a high-impedance mode). Clearing a TRISC bit (= 0) ; clearing output will make the corresponding PORTC pin an output (i.e., ; data latches put the contents of the output latch on the selected pin). CLRF LATC ; Alternate method The Data Latch register (LATC) is also memory ; to clear output mapped. Read-modify-write operations on the LATC ; data latches MOVLW 0CFh ; Value used to register read and write the latched output value for ; initialize data PORTC. ; direction PORTC is multiplexed with several peripheral functions MOVWF TRISC ; Set RC<3:0> as inputs (Table9-5). The pins have Schmitt Trigger input ; RC<5:4> as outputs buffers. RC1 is normally configured by Configuration ; RC<7:6> as inputs bit, CCP2MX, as the default peripheral pin of the CCP2 module (default/erased state, CCP2MX = 1). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. Note: On a Power-on Reset, these pins are configured as digital inputs. © 2009 Microchip Technology Inc. DS39636D-page 103

PIC18F2X1X/4X1X TABLE 9-5: PORTC I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T13CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input. RC2/CCP1/P1A RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG ECCP1 compare or PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A(2) 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK/SCL RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP module); input type depends on module setting. RC4/SDI/SDA RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI 1 I ST SPI data input (MSSP module). SDA 1 O DIG I2C data output (MSSP module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP module); input type depends on module setting. RC5/SDO RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO 0 O DIG SPI data output (MSSP module); takes priority over port data. RC6/TX/CK RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX 1 O DIG Asynchronous serial transmit data output (USART module); takes priority over port data. User must configure as output. CK 1 O DIG Synchronous serial clock output (USART module); takes priority over port data. 1 I ST Synchronous serial clock input (USART module). RC7/RX/DT RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (USART module). DT 1 O DIG Synchronous serial data output (USART module); takes priority over port data. 1 I ST Synchronous serial data input (USART module). User must configure as an input. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3. 2: Enhanced PWM output is available only on PIC18F4410/4415/4510/4515/4610 devices. DS39636D-page 104 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 54 LATC PORTC Data Latch Register (Read and Write to Data Latch) 54 TRISC PORTC Data Direction Control Register 54 © 2009 Microchip Technology Inc. DS39636D-page 105

PIC18F2X1X/4X1X 9.4 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide micro- Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input Note: PORTD is only available on 40/44-pin buffers are TTL. See Section9.6 “Parallel Slave devices. Port” for additional information on the Parallel Slave Port (PSP). PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a Note: When the enhanced PWM mode is used TRISD bit (= 1) will make the corresponding PORTD with either dual or quad outputs, the PSP pin an input (i.e., put the corresponding output driver in functions of PORTD are automatically a high-impedance mode). Clearing a TRISD bit (= 0) disabled. will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 9-4: INITIALIZING PORTD The Data Latch register (LATD) is also memory CLRF PORTD ; Initialize PORTD by mapped. Read-modify-write operations on the LATD ; clearing output register read and write the latched output value for ; data latches PORTD. CLRF LATD ; Alternate method ; to clear output All pins on PORTD are implemented with Schmitt ; data latches Trigger input buffers. Each pin is individually MOVLW 0CFh ; Value used to configurable as an input or output. ; initialize data ; direction Three of the PORTD pins are multiplexed with outputs MOVWF TRISD ; Set RD<3:0> as inputs P1B, P1C and P1D of the enhanced CCP module. The ; RD<5:4> as outputs operation of these additional PWM output pins is ; RD<7:6> as inputs covered in greater detail in Section15.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39636D-page 106 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 9-7: PORTD I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. RD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. RD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data. x I TTL PSP write data input. RD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/PSP4 RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data. x I TTL PSP write data input. RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data. x I TTL PSP write data input. P1B 0 O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data. x I TTL PSP write data input. P1C 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input. P1D 0 O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. DS39636D-page 107

PIC18F2X1X/4X1X TABLE 9-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54 LATD PORTD Data Latch Register (Read and Write to Data Latch) 54 TRISD PORTD Data Direction Control Register 54 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39636D-page 108 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 9.5 PORTE, TRISE and LATE The fourth pin of PORTE (MCLR/VPP/RE3) is an input Registers only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), Depending on the particular PIC18F2X1X/4X1X device it functions as a digital input only pin; as such, it does not selected, PORTE is implemented in two different ways. have TRIS or LAT bits associated with its operation. For 40/44-pin devices, PORTE is a 4-bit wide port. Otherwise, it functions as the device’s Master Clear Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ input. In either configuration, RE3 also functions as the AN7) are individually configurable as inputs or outputs. programming voltage input during programming. These pins have Schmitt Trigger input buffers. When Note: On a Power-on Reset, RE3 is enabled as selected as an analog input, these pins will read as ‘0’s. a digital input only if Master Clear The corresponding data direction register is TRISE. functionality is disabled. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output EXAMPLE 9-5: INITIALIZING PORTE driver in a high-impedance mode). Clearing a TRISE bit CLRF PORTE ; Initialize PORTE by (= 0) will make the corresponding PORTE pin an output ; clearing output (i.e., put the contents of the output latch on the selected ; data latches pin). CLRF LATE ; Alternate method ; to clear output TRISE controls the direction of the RE pins, even when ; data latches they are being used as analog inputs. The user must MOVLW 0Ah ; Configure A/D make sure to keep the pins configured as inputs when MOVWF ADCON1 ; for digital inputs using them as analog inputs. MOVLW 03h ; Value used to ; initialize data Note: On a Power-on Reset, RE2:RE0 are ; direction configured as analog inputs. MOVWF TRISE ; Set RE<0> as inputs The upper four bits of the TRISE register also control ; RE<1> as outputs ; RE<2> as inputs the operation of the Parallel Slave Port. Their operation is explained in Register9-1. 9.5.1 PORTE IN 28-PIN DEVICES The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE For 28-pin devices, PORTE is only available when register, read and write the latched output value for Master Clear functionality is disabled (MCLRE = 0). In these cases, PORTE is a single bit, input only port PORTE. comprised of RE3 only. The pin operates as previously described. © 2009 Microchip Technology Inc. DS39636D-page 109

PIC18F2X1X/4X1X REGISTER 9-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 110 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 9-9: PORTE I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RE0/RD/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input. 1 I ST PORTE<0> data input; disabled when analog input enabled. RD 1 I TTL PSP read enable input (PSP enabled). AN5 1 I ANA A/D input channel 5; default input configuration on POR. RE1/WR/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST PORTE<1> data input; disabled when analog input enabled. WR 1 I TTL PSP write enable input (PSP enabled). AN6 1 I ANA A/D input channel 6; default input configuration on POR. RE2/CS/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input enabled. CS 1 I TTL PSP write enable input (PSP enabled). AN7 1 I ANA A/D input channel 7; default input configuration on POR. MCLR/VPP/RE3(1) MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is set. VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available, regardless of pin mode. RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE Configuration bit is clear. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices. 2: RE3 does not have a corresponding TRIS bit to control data direction. TABLE 9-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE — — — — RE3(1,2) RE2 RE1 RE0 54 LATE(2) — — — — — LATE Data Output Register 54 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2009 Microchip Technology Inc. DS39636D-page 111

PIC18F2X1X/4X1X 9.6 Parallel Slave Port The timing for the control signals in Write and Read modes is shown in Figure9-3 and Figure9-4, Note: The Parallel Slave Port is only available on respectively. 40/44-pin devices. FIGURE 9-2: PORTD AND PORTE In addition to its function as a general I/O port, PORTD BLOCK DIAGRAM can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is con- (PARALLEL SLAVE PORT) trolled by the 4 upper bits of the TRISE register (Register9-1). Setting control bit, PSPMODE One bit of PORTD (TRISE<4>), enables PSP operation as long as the Data Bus enhanced CCP module is not operating in dual output D Q or quad output PWM mode. In Slave mode, the port is RDx pin asynchronously readable and writable by the external WR LATD CK or world. WR PORTD Data Latch TTL The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can Q D read or write the PORTD latch as an 8-bit latch. Setting the control bit PSPMODE enables the PORTE I/O pins RD PORTD ENEN to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits of RD LATD the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port control bits, Set Interrupt Flag PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a PSPIF (PIR1<7>) value in the range of ‘1010’ through ‘1111’. A write to the PSP occurs when both the CS and WR PORTE Pins lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set Read TTL RD when the write ends. Chip Select A read from the PSP occurs when both the CS and RD TTL CS lines are first detected low. The data in PORTD is read out and the OBF bit is clear. If the user writes new data Write TTL WR to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Note: I/O pins have diode protection to VDD and VSS. PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. DS39636D-page 112 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 9-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 9-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 9-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54 LATD PORTD Data Latch Register (Read and Write to Data Latch) 54 TRISD PORTD Data Direction Control Register 54 PORTE — — — — RE3 RE2 RE1 RE0 54 LATE — — — — — LATE Data Output bits 54 TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54 INTCON GIE/GIEH PEIE/GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 113

PIC18F2X1X/4X1X NOTES: DS39636D-page 114 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 10.0 TIMER0 MODULE The T0CON register (Register10-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-Bit counter in both 8-Bit or 16-Bit modes mode is shown in Figure10-1. Figure10-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-Bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 115

PIC18F2X1X/4X1X 10.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 10.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-Bit Mode is selected (see Section10.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-Bit for the following two instruction cycles. The user can mode; it is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor TMR0 register. writable (refer to Figure10-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising or falling edge of pin RA4/T0CKI. The increment- and low byte were valid, due to a rollover between ing edge is determined by the Timer0 Source Edge successive reads of the high and low byte. Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 10-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS2:T0PS0 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI max. prescale. FIGURE 10-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 0 T0CKI pin 1 ProPgrreasmcamlearble 1 SICynntloecrc nwkasitlh TMR0L HTigMh RB0yte 8 onT OMSvReet0r fIlFow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS2:T0PS0 Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-Bit mode with clock input from T0CKI max. prescale. DS39636D-page 116 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 10.3 Prescaler 10.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS2:T0PS0 bits control and can be changed “on-the-fly” during program (T0CON<3:0>), which determine the prescaler execution. assignment and prescale ratio. 10.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-Bit mode, or from selectable. FFFFh to 0000h in 16-Bit mode. This overflow sets the When assigned to the Timer0 module, all instructions TMR0IF flag bit. The interrupt can be masked by clear- writing to the TMR0 register (e.g., CLRF TMR0, MOVWF ing the TMR0IE bit (INTCON<5>). Before re-enabling TMR0, BSF TMR0, etc.) clear the prescaler count. the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register, Low Byte 52 TMR0H Timer0 Register, High Byte 52 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 52 TRISA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 54 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 117

PIC18F2X1X/4X1X NOTES: DS39636D-page 118 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 11.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure11-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure11-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP special event trigger register (Register11-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 =Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 119

PIC18F2X1X/4X1X 11.1 Timer1 Operation cycle (Fosc/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and RC0/ • Synchronous Counter T1OSO/T13CKI pins become inputs. This means the • Asynchronous Counter values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR3CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 11-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS1:T1CKPS0 T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 11-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS1:T1CKPS0 On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39636D-page 120 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 11.2 Timer1 16-Bit Read/Write Mode TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Timer1 can be configured for 16-bit reads and writes (see Figure11-2). When the RD16 control bit Osc Type Freq C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped LP 32kHz 27pF(1) 27pF(1) to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Note1: Microchip suggests these values as a Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator the user with the ability to accurately read all 16 bits of circuit. Timer1 without having to determine whether a read of 2: Higher capacitance increases the stability the high byte, followed by a read of the low byte, has of the oscillator but also increases the become invalid due to a rollover between reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 11.3.1 USING TIMER1 AS A The prescaler is only cleared on writes to TMR1L. CLOCK SOURCE 11.3 Timer1 Oscillator The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device between pins T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode; both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP low-power circuit rated for 32kHz crystals. It will instruction is executed, the device enter SEC_IDLE continue to run during all power-managed modes. The mode. Additional details are available in Section3.0 circuit for a typical LP oscillator is shown in Figure11-3. “Power-Managed Modes”. Table11-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock oscillator. source, the Timer1 system clock status flag, T1RUN The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe FIGURE 11-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the COMPONENTS FOR THE Timer1 oscillator fails while providing the clock, polling TIMER1 LP OSCILLATOR the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. C1 PIC18FXXXX 27 pF 11.3.2 LOW-POWER TIMER1 OPTION T1OSI The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. XTAL 32.768 kHz When the LPT1OSC Configuration bit is set, the Timer1 oscillator operates in a low-power mode. When T1OSO LPT1OSC is not set, Timer1 operates at a higher power C2 level. Power consumption for a particular mode is rela- 27 pF tively constant, regardless of the device’s operating mode. The default Timer1 configuration is the higher Note: See the Notes with Table11-1 for additional power mode. information about capacitor selection. As the low-power Timer1 mode tends to be more sen- sitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. © 2009 Microchip Technology Inc. DS39636D-page 121

PIC18F2X1X/4X1X 11.3.3 TIMER1 OSCILLATOR LAYOUT 11.5 Resetting Timer1 Using the CCP CONSIDERATIONS Special Event Trigger The Timer1 oscillator circuit draws very little power If either of the CCP modules is configured to use Timer1 during operation. Due to the low-power nature of the and generate a Special Event Trigger in Compare mode oscillator, it may also be sensitive to rapidly changing (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this signals in close proximity. signal will reset Timer1. The trigger from CCP2 will also The oscillator circuit, shown in Figure11-3, should be start an A/D conversion if the A/D module is enabled located as close as possible to the microcontroller. (see Section14.3.4 “Special Event Trigger” for more There should be no circuits passing within the oscillator information). circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a If a high-speed circuit must be located near the oscilla- synchronous counter to take advantage of this feature. tor (such as the CCP1 pin in Output Compare or PWM When used this way, the CCPRH:CCPRL register pair mode, or the primary oscillator using the OSC2 pin), a effectively becomes a period register for Timer1. grounded guard ring around the oscillator circuit, as If Timer1 is running in Asynchronous Counter mode, shown in Figure11-4, may be helpful when used on a this Reset operation may not work. single-sided PCB or in addition to a ground plane. In the event that a write to Timer1 coincides with a special event trigger, the write operation will take FIGURE 11-4: OSCILLATOR CIRCUIT precedence. WITH GROUNDED GUARD RING Note: The special event triggers from the CCP2 module will not set the TMR1IF interrupt VDD flag bit (PIR1<0>). VSS 11.6 Using Timer1 as a Real-Time Clock OSC1 Adding an external LP oscillator to Timer1 (such as the OSC2 one described in Section11.3 “Timer1 Oscillator” above) gives users the option to include RTC function- ality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time RC0 base and several lines of application code to calculate the time. When operating in Sleep mode and using a RC1 battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. RC2 The application code routine, RTCisr, shown in Note: Not drawn to scale. Example11-1, demonstrates a simple method to increment a counter at one-second intervals using an 11.4 Timer1 Interrupt Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls The TMR1 register pair (TMR1H:TMR1L) increments the routine, which increments the seconds counter by from 0000h to FFFFh and rolls over to 0000h. The one; additional counters for minutes and hours are Timer1 interrupt, if enabled, is generated on overflow, incremented as the previous counter overflow. which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled Since the register pair is 16 bits wide, counting up to by setting or clearing the Timer1 Interrupt Enable bit, overflow the register directly from a 32.768kHz clock TMR1IE (PIE1<0>). would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered. Doing so may introduce cumulative errors over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. DS39636D-page 122 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X EXAMPLE 11-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 TMR1L Timer1 Register, Low Byte 52 TMR1H Timer1 Register, High Byte 52 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52 Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 123

PIC18F2X1X/4X1X NOTES: DS39636D-page 124 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 12.0 TIMER2 MODULE 12.1 Timer2 Operation The Timer2 module timer incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- • 8-bit timer and period registers (TMR2 and PR2, 16 prescale options; these are selected by the prescaler respectively) control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The • Readable and writable (both registers) value of TMR2 is compared to that of the period register, • Software programmable prescaler (1:1, 1:4 and PR2, on each clock cycle. When the two values match, 1:16) the comparator generates a match signal as the timer • Software programmable postscaler (1:1 through output. This signal also resets the value of TMR2 to 00h 1:16) on the next cycle and drives the output counter/ • Interrupt on TMR2-to-PR2 match postscaler (see Section12.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSP The TMR2 and PR2 registers are both directly readable module and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The module is controlled through the T2CON register Both the prescaler and postscaler counters are cleared (Register12-1), which enables or disables the timer on the following events: and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure12-1. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 125

PIC18F2X1X/4X1X 12.2 Timer2 Interrupt 12.3 Timer2 Output Timer2 also can generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2-to-PR2 match) the CCP modules, where it is used as a time base for provides the input for the 4-bit output counter/ operations in PWM mode. postscaler. This counter generates the TMR2 match Timer2 can be optionally used as the shift clock source interrupt flag which is latched in TMR2IF (PIR1<1>). for the MSSP module operating in SPI mode. Addi- The interrupt is enabled by setting the TMR2 Match tional information is provided in Section16.0 “Master Interrupt Enable bit, TMR2IE (PIE1<1>). Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>). FIGURE 12-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS3:T2OUTPS0 Set TMR2IF Postscaler 2 T2CKPS1:T2CKPS0 TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 TMR2 Timer2 Register 52 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52 PR2 Timer2 Period Register 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39636D-page 126 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 13.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure13-1. A block diagram of the module’s The Timer3 module timer/counter incorporates these operation in Read/Write mode is shown in Figure13-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register13-1). It also selects the clock source counter options for the CCP modules (see Section14.1.1 • Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more and TMR3L) information). • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP special event trigger REGISTER 13-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x =Timer3 is the capture/compare clock source for the CCP modules 01 =Timer3 is the capture/compare clock source for CCP2; Timer1 is the capture/compare clock source for CCP1 00 =Timer1 is the capture/compare clock source for the CCP modules bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 127

PIC18F2X1X/4X1X 13.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared Timer3 can operate in one of three modes: (= 0), Timer3 increments on every internal instruction • Timer cycle (FOSC/4). When the bit is set, Timer3 increments • Synchronous Counter on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. • Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 13-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS1:T3CKPS0 On/Off T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1/CCP2 Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39636D-page 128 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 13.2 Timer3 16-Bit Read/Write Mode 13.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure13-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 13.5 Resetting Timer3 Using the CCP byte, has become invalid due to a rollover between Special Event Trigger reads. If either of the CCP modules is configured to use Timer3 A write to the high byte of Timer3 must also take place and to generate a special event trigger in Compare mode through the TMR3H Buffer register. The Timer3 high (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this byte is updated with the contents of TMR3H when a signal will reset Timer3. It will also start an A/D conversion write occurs to TMR3L. This allows a user to write all if the A/D module is enabled (see Section14.3.4 16 bits to both the high and low bytes of Timer3 at once. “Special Event Trigger” for more information). The high byte of Timer3 is not directly readable or The module must be configured as either a timer or writable in this mode. All reads and writes must take synchronous counter to take advantage of this feature. place through the Timer3 High Byte Buffer register. When used this way, the CCPR2H:CCPR2L register Writes to TMR3H do not clear the Timer3 prescaler. pair effectively becomes a period register for Timer3. The prescaler is only cleared on writes to TMR3L. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 13.3 Using the Timer1 Oscillator as the Timer3 Clock Source In the event that a write to Timer3 coincides with a special event trigger from a CCP module, the write will The Timer1 internal oscillator may be used as the clock take precedence. source for Timer3. The Timer1 oscillator is enabled by Note: The special event triggers from the CCP2 setting the T1OSCEN (T1CON<3>) bit. To use it as the module will not set the TMR3IF interrupt Timer3 clock source, the TMR3CS bit must also be set. flag bit (PIR1<0>). As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section11.0 “Timer1 Module”. TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54 TMR3L Timer3 Register, Low Byte 53 TMR3H Timer3 Register, High Byte 53 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. DS39636D-page 129

PIC18F2X1X/4X1X NOTES: DS39636D-page 130 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 14.0 CAPTURE/COMPARE/PWM The Capture and Compare operations described in this (CCP) MODULES chapter apply to all standard and Enhanced CCP modules. PIC18F2X1X/4X1X devices all have two CCP Note: Throughout this section and Section15.0 (Capture/Compare/PWM) modules. Each module con- “Enhanced Capture/Compare/PWM (ECCP) tains a 16-bit register which can operate as a 16-bit Module”, references to the register and bit Capture register, a 16-bit Compare register or a PWM names for CCP modules are referred to gener- Master/Slave Duty Cycle register. ically by the use of ‘x’ or ‘y’ in place of the In 28-pin devices, the two standard CCP modules specific module number. Thus, “CCPxCON” (CCP1 and CCP2) operate as described in this chapter. might refer to the control register for CCP1, In 40/44-pin devices, CCP1 is implemented as an CCP2 or ECCP1. “CCPxCON” is used Enhanced CCP module with standard Capture and throughout these sections to refer to the Compare modes and Enhanced PWM modes. The module control register, regardless of whether ECCP implementation is discussed in Section15.0 the CCP module is a standard or Enhanced “Enhanced Capture/Compare/PWM (ECCP) implementation. Module”. REGISTER 14-1: CCPXCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCP module) 0001 =Reserved 0010 =Compare mode, toggle output on match (CCPIF bit is set) 0011 =Reserved 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode: initialize CCP pin low; on compare match, force CCP pin high (CCPIF bit is set) 1001 =Compare mode: initialize CCP pin high; on compare match, force CCP pin low (CCPIF bit is set) 1010 =Compare mode: generate software interrupt on compare match (CCPIF bit is set, CCP pin reflects I/O state) 1011 =Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCPxIF bit is set) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 131

PIC18F2X1X/4X1X 14.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register13-1). Both modules may be with a control register (generically, CCPxCON) and a active at any given time and may share the same timer data register (CCPRx). The data register, in turn, is resource if they are configured to operate in the same comprised of two 8-bit registers: CCPRxL (low byte) mode (Capture/Compare or PWM) at the same time. The and CCPRxH (high byte). All registers are both interactions between the two modules are summarized in readable and writable. Figure14-1 and Figure14-2. In Timer1 in Asynchronous Counter mode, the capture operation will not work. 14.1.1 CCP MODULES AND TIMER RESOURCES 14.1.2 CCP2 PIN ASSIGNMENT The CCP modules utilize Timers 1, 2 or 3, depending The pin assignment for CCP2 (Capture input, Compare on the mode selected. Timer1 and Timer3 are available and PWM output) can change, based on device config- to modules in Capture or Compare modes, while uration. The CCP2MX Configuration bit determines Timer2 is available for modules in PWM mode. which pin CCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the Configuration bit TABLE 14-1: CCP MODE – TIMER is cleared, CCP2 is multiplexed with RB3. RESOURCE Changing the pin assignment of CCP2 does not auto- CCP/ECCP Mode Timer Resource matically change any requirements for configuring the port pin. Users must always verify that the appropriate Capture Timer1 or Timer3 TRIS register is configured correctly for CCP2 Compare Timer1 or Timer3 operation, regardless of where it is located. PWM Timer2 TABLE 14-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the special event trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done. Operation of CCP1 could be affected if it is using the same timer as a time base. Compare Capture CCP1 can be configured for the special event trigger to reset TMR1 or TMR3 (depending upon which time base is used). Operation of CCP2 could be affected if it is using the same timer as a time base. Compare Compare Either module can be configured for the Special Event Trigger to reset the time base. Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if both modules are using the same time base. Capture PWM(1) None Compare PWM(1) None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and Enhanced PWM operation. DS39636D-page 132 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 14.2 Capture Mode 14.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false inter- CCPx pin. An event is defined as one of the following: rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • every falling edge • every rising edge 14.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings in Capture mode; they • every 16th rising edge are specified as part of the operating mode selected by The event is selected by the mode select bits, the mode select bits (CCPxM3:CCPxM0). Whenever the CCP module is turned off or Capture mode is dis- CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture abled, the prescaler counter is cleared. This means is made, the interrupt request flag bit, CCPxIF, is set; it that any Reset will clear the prescaler counter. must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from 14.2.1 CCP PIN CONFIGURATION a non-zero prescaler. Example14-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If RB3/CCP2 or RC1/CCP2 is configured EXAMPLE 14-1: CHANGING BETWEEN as an output, a write to the port can cause CAPTURE PRESCALERS a capture condition. (CCP2 SHOWN) 14.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP2CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load WREG with the The timers that are to be used with the capture feature ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP2CON ; Load CCP2CON with mode, the capture operation will not work. The timer to be ; this value used with each CCP module is selected in the T3CON register (see Section14.1.1 “CCP Modules and Timer Resources”). FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3CCP2 TMR3 Enable CCP1 pin Prescaler and CCPR1H CCPR1L ÷ 1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP1CON<3:0> Set CCP2IF 4 Q1:Q4 4 CCP2CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP2 pin Prescaler and CCPR2H CCPR2L ÷ 1, 4, 16 Edge Detect TMR1 Enable T3CCP2 TMR1H TMR1L T3CCP1 © 2009 Microchip Technology Inc. DS39636D-page 133

PIC18F2X1X/4X1X 14.3 Compare Mode 14.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is Timer1 and/or Timer3 must be running in Timer mode constantly compared against either the TMR1 or TMR3 or Synchronized Counter mode if the CCP module is register pair value. When a match occurs, the CCPx pin using the compare feature. In Asynchronous Counter can be: mode, the compare operation may not work. • driven high 14.3.3 SOFTWARE INTERRUPT MODE • driven low When the Generate Software Interrupt mode is chosen • toggled (high-to-low or low-to-high) (CCPxM3:CCPxM0 = 1010), the corresponding CCPx • remain unchanged (that is, reflects the state of the pin is not affected. Only a CCP interrupt is generated, I/O latch) if enabled and the CCPxIE bit is set. The action on the pin is based on the value of the mode 14.3.4 SPECIAL EVENT TRIGGER select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit CCPxIF is set. Both CCP modules are equipped with a special event trigger. This is an internal hardware signal generated 14.3.1 CCP PIN CONFIGURATION in Compare mode to trigger actions by other modules. The user must configure the CCPx pin as an output by The special event trigger is enabled by selecting the clearing the appropriate TRIS bit. Compare Special Event Trigger mode (CCPxM3:CCPxM0 = 1011). Note: Clearing the CCP2CON register will force For either CCP module, the special event trigger resets the RB3 or RC1 compare output latch the timer register pair for whichever timer resource is (depending on device configuration) to the currently assigned as the module’s time base. This default low level. This is not the PORTB or allows the CCPRx registers to serve as a programma- PORTC I/O data latch. ble period register for either timer. The special event trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP1IF (Timer1/Timer3 Reset) CCPR1H CCPR1L CCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP1CON<3:0> TMR1H TMR1L 0 0 1 TMR3H TMR3L 1 Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) T3CCP1 T3CCP2 Set CCP2IF CCP2 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR2H CCPR2L CCP2CON<3:0> DS39636D-page 134 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 RCON IPEN SBOREN(2) — RI TO PD POR BOR 50 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54 TRISB PORTB Data Direction Control Register 54 TRISC PORTC Data Direction Control Register 54 TMR1L Timer1 Register Low Byte 52 TMR1H Timer1 Register High Byte 52 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52 TMR3H Timer3 Register High Byte 53 TMR3L Timer3 Register Low Byte 53 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53 CCPR1L Capture/Compare/PWM Register 1 Low Byte 53 CCPR1H Capture/Compare/PWM Register 1 High Byte 53 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53 CCPR2L Capture/Compare/PWM Register 2 Low Byte 53 CCPR2H Capture/Compare/PWM Register 2 High Byte 53 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. 2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. © 2009 Microchip Technology Inc. DS39636D-page 135

PIC18F2X1X/4X1X 14.4 PWM Mode 14.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP2 pin is multiplexed with a PORTB or PORTC following formula: data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. EQUATION 14-1: Note: Clearing the CCP2CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC • the RB3 or RC1 output latch (depending (TMR2 Prescale Value) on device configuration) to the default low level. This is not the PORTB or PWM frequency is defined as 1/[PWM period]. PORTC I/O data latch. When TMR2 is equal to PR2, the following three events Figure14-3 shows a simplified block diagram of the occur on the next increment cycle: CCP module in PWM mode. • TMR2 is cleared For a step-by-step procedure on how to set up the CCP • The CCPx pin is set (exception: if PWM duty module for PWM operation, see Section14.4.4 cycle=0%, the CCPx pin will not be set) “Setup for PWM Operation”. • The PWM duty cycle is latched from CCPRxL into CCPRxH FIGURE 14-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscalers (see Section12.0 DIAGRAM “Timer2 Module”) are not used in the CCPxCON<5:4> determination of the PWM frequency. The Duty Cycle Registers postscaler could be used to have a servo CCPRxL update rate at a different frequency than the PWM output. 14.4.2 PWM DUTY CYCLE CCPRxH (Slave) CCPx Output The PWM duty cycle is specified by writing to the Comparator R Q CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the TMR2 (Note 1) two LSbs. This 10-bit value is represented by S CCPRxL:CCPxCON<5:4>. The following equation is Corresponding used to calculate the PWM duty cycle in time: Comparator TRIS bit Clear Timer, CCP1 pin and EQUATION 14-2: latch D.C. PR2 PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • Note1: The 8-bit TMR2 value is concatenated with 2-bit TOSC • (TMR2 Prescale Value) internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCPRxL and CCPxCON<5:4> can be written to at any A PWM output (Figure14-4) has a time base (period) time but the duty cycle value is not latched into and a time that the output stays high (duty cycle). CCPR2H until after a match between PR2 and TMR2 The frequency of the PWM is the inverse of the occurs (i.e., the period is complete). In PWM mode, period (1/period). CCPRxH is a read-only register. FIGURE 14-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39636D-page 136 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X The CCPRxH register and a 2-bit internal latch are EQUATION 14-3: used to double-buffer the PWM duty cycle. This ⎛FOSC⎞ double-buffering is essential for glitchless PWM log⎝F----P---W-----M---⎠ operation. PWM Resolution (max) = -----------------------------bits log(2) When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be The maximum PWM resolution (bits) for a given PWM cleared. frequency is given by the equation: TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 14.4.3 PWM AUTO-SHUTDOWN 14.4.4 SETUP FOR PWM OPERATION (CCP1 ONLY) The following steps should be taken when configuring The PWM auto-shutdown features of the Enhanced the CCP module for PWM operation: CCP module are also available to CCP1 in 28-pin 1. Set the PWM period by writing to the PR2 devices. The operation of this feature is register. discussed in detail in Section 15.4.7 “Enhanced 2. Set the PWM duty cycle by writing to the PWM Auto-Shutdown”. CCPRxL register and CCPxCON<5:4> bits. Auto-shutdown features are not available for CCP2. 3. Make the CCPx pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCPx module for PWM operation. © 2009 Microchip Technology Inc. DS39636D-page 137

PIC18F2X1X/4X1X TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 RCON IPEN SBOREN(2) — RI TO PD POR BOR 50 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 TRISB PORTB Data Direction Control Register 54 TRISC PORTC Data Direction Control Register 54 TMR2 Timer2 Register 52 PR2 Timer2 Period Register 52 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52 CCPR1L Capture/Compare/PWM Register 1 Low Byte 53 CCPR1H Capture/Compare/PWM Register 1 High Byte 53 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53 CCPR2L Capture/Compare/PWM Register 2 Low Byte 53 CCPR2H Capture/Compare/PWM Register 2 High Byte 53 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 53 PWM1CON PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. 2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. DS39636D-page 138 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 15.0 ENHANCED CAPTURE/ and restart. The Enhanced features are discussed in COMPARE/PWM (ECCP) detail in Section15.4 “Enhanced PWM Mode”. Capture, Compare and single-output PWM functions of MODULE the ECCP module are the same as described for the standard CCP module. Note: The ECCP module is implemented only in 40/44-pin devices. The control register for the Enhanced CCP module is shown in Register15-1. It differs from the CCPxCON In PIC18F4410/4415/4510/4515/4610 devices, CCP1 registers in PIC18F2410/2415/2510/2515/2610 is implemented as a standard CCP module with devices in that the two Most Significant bits are enhanced PWM capabilities. These include the implemented to control PWM functionality. provision for 2 or 4 output channels, user selectable polarity, dead-band control and automatic shutdown REGISTER 15-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits If CCP1M3:CCP1M2 = 00, 01, 10: xx =P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M3:CCP1M2 = 11: 00 =Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 =Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 =Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 =Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCP module) 0001 =Reserved 0010 =Compare mode, toggle output on match 0011 =Capture mode 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 =Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 =Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 =Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit) 1100 =PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 =PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 =PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 =PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 139

PIC18F2X1X/4X1X In addition to the expanded range of modes available 15.2 Capture and Compare Modes through the CCP1CON and ECCP1AS registers, the ECCP module has an additional register associated Except for the operation of the special event trigger with Enhanced PWM operation and auto-shutdown discussed below, the Capture and Compare modes of features. This register is: the ECCP module are identical in operation to that of CCP2. These are discussed in detail in Section14.2 • PWM1CON (PWM Configuration register) “Capture Mode” and Section14.3 “Compare Mode”. No changes are required when moving 15.1 ECCP Outputs and Configuration between 28-pin and 40/44-pin devices. The Enhanced CCP module may have up to four PWM 15.2.1 SPECIAL EVENT TRIGGER outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are The special event trigger output of ECCP1 resets the multiplexed with I/O pins on PORTC and PORTD. The TMR1 or TMR3 register pair, depending on which timer outputs that are active depend on the CCP operating resource is currently selected. This allows the CCPR1 mode selected. The pin assignments are summarized register to effectively be a 16-bit programmable period in Table15-1. register for Timer1 or Timer3. To configure the I/O pins as PWM outputs, the proper 15.3 Standard PWM Mode PWM mode must be selected by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits. The When configured in Single Output mode, the ECCP appropriate TRISC and TRISD direction bits for the port module functions identically to the standard CCP pins must also be set as outputs. module in PWM mode, as described in Section14.4 “PWM Mode”. This is also sometimes referred to as 15.1.1 ECCP MODULES AND TIMER “Compatible CCP” mode, as in Table15-1. RESOURCES Note: When setting up single output PWM Like the standard CCP modules, the ECCP module can operations, users are free to use either of utilize Timers 1, 2 or 3, depending on the mode the processes described in Section14.4.4 selected. Timer1 and Timer3 are available for modules “Setup for PWM Operation” or in Capture or Compare modes, while Timer2 is Section15.4.9 “Setup for PWM Opera- available for modules in PWM mode. Interactions tion”. The latter is more generic and will between the standard and Enhanced CCP modules are work for either single or multi-output PWM. identical to those described for standard CCP modules. Additional details on timer resources are provided in Section14.1.1 “CCP Modules and Timer Resources”. TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES CCP1CON ECCP Mode RC2 RD5 RD6 RD7 Configuration All 40/44-pin devices: Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7 Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. DS39636D-page 140 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 15.4 Enhanced PWM Mode 15.4.1 PWM PERIOD The Enhanced PWM mode provides additional PWM The PWM period is specified by writing to the PR2 output options for a broader range of control applica- register. The PWM period can be calculated using the tions. The module is a backward compatible version of following equation. the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to EQUATION 15-1: select the polarity of the signal (either active-high or PWM Period = [(PR2) + 1] • 4 • TOSC • active-low). The module’s output mode and polarity are (TMR2 Prescale Value) configured by setting the P1M1:P1M0 and CCP1M3:CCP1M0 bits of the CCP1CON register. PWM frequency is defined as 1/[PWM period]. When Figure15-1 shows a simplified block diagram of PWM TMR2 is equal to PR2, the following three events occur operation. All control registers are double-buffered and on the next increment cycle: are loaded at the beginning of a new PWM cycle (the • TMR2 is cleared period boundary when Timer2 resets) in order to • The CCP1 pin is set (if PWM duty cycle=0%, the prevent glitches on any of the outputs. The exception is CCP1 pin will not be set) the PWM Delay register, PWM1CON, which is loaded • The PWM duty cycle is copied from CCPR1L into at either the duty cycle boundary or the period bound- CCPR1H ary (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead Note: The Timer2 postscaler (see Section12.0 of starting immediately. This means that Enhanced “Timer2 Module”) is not used in the PWM waveforms do not exactly match the standard determination of the PWM frequency. The PWM waveforms, but are instead offset by one full postscaler could be used to have a servo instruction cycle (4 TOSC). update rate at a different frequency than As before, the user must manually configure the the PWM output. appropriate TRIS bits for output. FIGURE 15-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> P1D P1D Comparator Clear Timer, TRISx<x> set CCP1 pin and latch D.C. PR2 PWM1CON Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39636D-page 141

PIC18F2X1X/4X1X 15.4.2 PWM DUTY CYCLE EQUATION 15-3: The PWM duty cycle is specified by writing to the log(FOSC) CCPR1L register and to the CCP1CON<5:4> bits. Up FPWM PWM Resolution (max) = bits to 10-bit resolution is available. The CCPR1L contains log(2) the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. EQUATION 15-2: PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • 15.4.3 PWM OUTPUT CONFIGURATIONS TOSC • (TMR2 Prescale Value) The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into • Single Output CCPR1H until a match between PR2 and TMR2 occurs • Half-Bridge Output (i.e., the period is complete). In PWM mode, CCPR1H • Full-Bridge Output, Forward mode is a read-only register. • Full-Bridge Output, Reverse mode The CCPR1H register and a 2-bit internal latch are The Single Output mode is the standard PWM mode used to double-buffer the PWM duty cycle. This discussed in Section15.4 “Enhanced PWM Mode”. double-buffering is essential for glitchless PWM The Half-Bridge and Full-Bridge Output modes are operation. When the CCPR1H and 2-bit latch match covered in detail in the sections that follow. TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is The general relationship of the outputs in all cleared. The maximum PWM resolution (bits) for a configurations is summarized in Figure15-2. given PWM frequency is given by the following equation. TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39636D-page 142 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 15-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 PR2 + 1 Duty CCP1CON SIGNAL Cycle <7:6> Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 15-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Duty PR2 + 1 CCP1CON SIGNAL Cycle <7:6> Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPDEL<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section15.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39636D-page 143

PIC18F2X1X/4X1X 15.4.4 HALF-BRIDGE MODE FIGURE 15-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output Period Period signal is output on the P1A pin, while the complemen- Duty Cycle tary PWM output signal is output on the P1B pin (Figure15-4). This mode can be used for half-bridge P1A(2) applications, as shown in Figure15-5, or for full-bridge td applications where four power switches are being td modulated with two PWM signals. P1B(2) In Half-Bridge Output mode, the programmable dead- band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits PDC6:PDC0 sets the number of instruction cycles td = Dead-Band Delay before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section15.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 15-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18F4X1X FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F4X1X FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39636D-page 144 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 15.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The In Full-Bridge Output mode, four pins are used as TRISC<2> and TRISD<7:5> bits must be cleared to outputs; however, only two outputs are active at a time. make the P1A, P1B, P1C and P1D pins outputs. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure15-6. FIGURE 15-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39636D-page 145

PIC18F2X1X/4X1X FIGURE 15-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F4X1X FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 15.4.5.1 Direction Change in Full-Bridge Mode Figure15-9 shows an example where the PWM direction changes from forward to reverse at a near In the Full-Bridge Output mode, the P1M1 bit in the 100% duty cycle. At time t1, the outputs P1A and P1D CCP1CON register allows user to control the forward/ become inactive, while output P1C becomes active. In reverse direction. When the application firmware this example, since the turn-off time of the power changes this direction control bit, the module will devices is longer than the turn-on time, a shoot-through assume the new direction on the next PWM cycle. current may flow through power devices, QC and QD Just before the end of the current PWM period, the (see Figure15-7), for the duration of ‘t’. The same modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices, QA and QB, inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward. P1C) are switched to drive in the opposite direction. If changing PWM direction at high duty cycle is required This occurs in a time interval of 4TOSC * (Timer2 for an application, one of the following requirements Prescale Value) before the next PWM period begins. must be met: The Timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the T2CKPS bit (T2CON<1:0>). 1. Reduce PWM for a PWM period before During the interval from the switch of the unmodulated changing directions. outputs to the beginning of the next period, the 2. Use switch drivers that can drive the switches off modulated outputs (P1B and P1D) remain inactive. faster than they can drive them on. This relationship is shown in Figure15-8. Other options to prevent shoot-through current may Note that in the Full-Bridge Output mode, the CCP1 exist. module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39636D-page 146 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 15-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 15-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. DS39636D-page 147

PIC18F2X1X/4X1X 15.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the DELAY comparator modules, a low level on the Fault input pin (FLT0) or any combination of these three sources. The Note: Programmable dead-band delay is not comparators may be used to monitor a voltage input implemented in 28-pin devices with proportional to a current being monitored in the bridge standard CCP modules. circuit. If the voltage exceeds a threshold, the In half-bridge applications where all power switches are comparator switches state and triggers a shutdown. modulated at the PWM frequency at all times, the Alternatively, a low digital signal on FLT0 can also trigger power switches normally require more time to turn off a shutdown. The auto-shutdown feature can be disabled than to turn on. If both the upper and lower power by not selecting any auto-shutdown sources. The auto- switches are switched at the same time (one turned on shutdown sources to be used are selected using the and the other turned off), both switches may be on for ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS a short period of time until one switch completely turns register). off. During this brief interval, a very high current (shoot- When a shutdown occurs, the output pins are through current) may flow through both power asynchronously placed in their shutdown states, switches, shorting the bridge supply. To avoid this specified by the PSSAC1:PSSAC0 and potentially destructive shoot-through current from PSSBD1:PSSBD0 bits (ECCPAS3:ECCPAS0). Each flowing during switching, turning on either of the power pin pair (P1A/P1C and P1B/P1D) may be set to drive switches is normally delayed to allow the other switch high, drive low or be tri-stated (not driving). The to completely turn off. ECCPASE bit (ECCPAS<7>) is also set to hold the In the Half-Bridge Output mode, a digitally program- Enhanced PWM outputs in their shutdown states. mable dead-band delay is available to avoid shoot- The ECCPASE bit is set by hardware when a shutdown through current from destroying the bridge power event occurs. If automatic restarts are not enabled, the switches. The delay occurs at the signal transition from ECCPASE bit is cleared by firmware when the cause of the non-active state to the active state. See Figure15-4 the shutdown clears. If automatic restarts are enabled, for illustration. Bits PDC6:PDC0 of the PWM1CON the ECCPASE bit is automatically cleared when the register (Register15-2) set the delay period in terms of cause of the auto-shutdown has cleared. microcontroller instruction cycles (TCY or 4 TOSC). If the ECCPASE bit is set when a PWM period begins, These bits are not available on 28-pin devices as the the PWM outputs remain in their shutdown state for that standard CCP module does not support half-bridge entire PWM period. When the ECCPASE bit is cleared, operation. the PWM outputs will return to normal operation at the 15.4.7 ENHANCED PWM AUTO-SHUTDOWN beginning of the next PWM period. When the CCP1 is programmed for any of the Enhanced Note: Writing to the ECCPASE bit is disabled PWM modes, the active output pins may be configured while a shutdown condition is active. for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 15-2: PWM1CON: PWM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC6:PDC0: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note1: Unimplemented on 28-pin devices and read as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 148 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 15-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits 111 = FLT0 or Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits 1x = Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices) 01 = Drive Pins A and C to ‘1’ 00 = Drive Pins A and C to ‘0’ bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1) 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ 00 = Drive Pins B and D to ‘0’ Note1: Unimplemented on 28-pin devices and read as ‘0’. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 149

PIC18F2X1X/4X1X 15.4.7.1 Auto-Shutdown and 15.4.8 START-UP CONSIDERATIONS Automatic Restart When the ECCP module is used in the PWM mode, the The auto-shutdown feature can be configured to allow application hardware must use the proper external pull- automatic restarts of the module following a shutdown up and/or pull-down resistors on the PWM output pins. event. This is enabled by setting the PRSEN bit of the When the microcontroller is released from Reset, all of PWM1CON register (PWM1CON<7>). the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the off In Shutdown mode with PRSEN = 1 (Figure15-10), the state until the microcontroller drives the I/O pins with the ECCPASE bit will remain set for as long as the cause proper signal levels, or activates the PWM output(s). of the shutdown continues. When the shutdown condi- tion clears, the ECCP1ASE bit is cleared. If PRSEN =0 The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow (Figure15-11), once a shutdown condition occurs, the the user to choose whether the PWM output signals are ECCPASE bit will remain set until it is cleared by firm- active-high or active-low for each pair of PWM output ware. Once ECCPASE is cleared, the Enhanced PWM pins (P1A/P1C and P1B/P1D). The PWM output will resume at the beginning of the next PWM period. polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configura- Note: Writing to the ECCPASE bit is disabled tion while the PWM pins are configured as outputs is while a shutdown condition is active. not recommended, since it may result in damage to the Independent of the PRSEN bit setting, if the auto- application circuits. shutdown source is one of the comparators, the The P1A, P1B, P1C and P1D output latches may not be shutdown condition is a level. The ECCPASE bit in the proper states when the PWM module is initialized. cannot be cleared as long as the cause of the shutdown Enabling the PWM pins for output at the same time as persists. the ECCP module may cause damage to the applica- The Auto-Shutdown mode can be forced by writing a ‘1’ tion circuit. The ECCP module must be enabled in the to the ECCPASE bit. proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 15-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period PWM Period PWM Period PWM Activity Dead Time Dead Time Dead Time Duty Cycle Duty Cycle Duty Cycle ShutdownEvent ECCPASE bit FIGURE 15-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period PWM Period PWM Period PWM Activity Dead Time Dead Time Dead Time Duty Cycle Duty Cycle Duty Cycle ShutdownEvent ECCPASE bit ECCPASE Cleared by Firmware DS39636D-page 150 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 15.4.9 SETUP FOR PWM OPERATION 15.4.10 OPERATION IN POWER-MANAGED MODES The following steps should be taken when configuring the ECCP module for PWM operation: In Sleep mode, all clock sources are disabled. Timer2 1. Configure the PWM pins, P1A and P1B (and will not increment and the state of the module will not P1C and P1D, if used), as inputs by setting the change. If the ECCP pin is driving a value, it will corresponding TRIS bits. continue to drive that value. When the device wakes 2. Set the PWM period by loading the PR2 register. up, it will continue from this state. If Two-Speed Start- ups are enabled, the initial start-up frequency from 3. If auto-shutdown is required: INTOSC and the postscaler may not be stable • Disable auto-shutdown (ECCP1AS = 0) immediately. • Configure source (FLT0, Comparator 1 or In PRI_IDLE mode, the primary clock will continue to Comparator 2) clock the ECCP module without change. In all other • Wait for non-shutdown condition power-managed modes, the selected power-managed 4. Configure the ECCP module for the desired mode clock will clock Timer2. Other power-managed PWM mode and configuration by loading the mode clocks will most likely be different than the CCP1CON register with the appropriate values: primary clock frequency. • Select one of the available output configurations and direction with the 15.4.10.1 Operation with Fail-Safe P1M1:P1M0 bits. Clock Monitor • Select the polarities of the PWM output If the Fail-Safe Clock Monitor is enabled, a clock failure signals with the CCP1M3:CCP1M0 bits. will force the device into the power-managed RC_RUN 5. Set the PWM duty cycle by loading the CCPR1L mode and the OSCFIF bit (PIR2<7>) will be set. The register and CCP1CON<5:4> bits. ECCP will then be clocked from the internal oscillator 6. For Half-Bridge Output mode, set the dead- clock source, which may have a different clock band delay by loading ECCPDEL<6:0> with the frequency than the primary clock. appropriate value. See the previous section for additional details. 7. If auto-shutdown operation is required, load the ECCP1AS register: 15.4.11 EFFECTS OF A RESET • Select the auto-shutdown sources using the Both Power-on Reset and subsequent Resets will force ECCPAS2:ECCPAS0 bits. all ports to Input mode and the CCP registers to their • Select the shutdown states of the PWM Reset states. output pins using the PSSAC1:PSSAC0 and This forces the Enhanced CCP module to reset to a PSSBD1:PSSBD0 bits. state compatible with the standard CCP module. • Set the ECCPASE bit (ECCPAS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the PRSEN bit (ECCPDEL<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCPAS<7>). © 2009 Microchip Technology Inc. DS39636D-page 151

PIC18F2X1X/4X1X TABLE 15-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 RCON IPEN SBOREN(2) — RI TO PD POR BOR 50 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54 TRISB PORTB Data Direction Control Register 54 TRISC PORTC Data Direction Control Register 54 TRISD PORTD Data Direction Control Register 54 TMR1L Timer1 Register Low Byte 52 TMR1H Timer1 Register High Byte 52 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52 TMR2 Timer2 Register 52 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52 PR2 Timer2 Period Register 52 TMR3L Timer3 Register Low Byte 53 TMR3H Timer3 Register High Byte 53 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53 CCPR1L Capture/Compare/PWM Register 1 Low Byte 53 CCPR1H Capture/Compare/PWM Register 1 High Byte 53 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 53 PWM1CON PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. 2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. DS39636D-page 152 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.0 MASTER SYNCHRONOUS 16.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four SPI modes are supported. To accomplish communication, 16.1 MSSP Module Overview typically three pins are used: • Serial Data Out (SDO) – RC5/SDO The Master Synchronous Serial Port (MSSP) module is • Serial Data In (SDI) – RC4/SDI/SDA a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral • Serial Clock (SCK) – RC3/SCK/SCL devices may be serial EEPROMs, shift registers, Additionally, a fourth pin may be used when in a Slave display drivers, A/D converters, etc. The MSSP module mode of operation: can operate in one of two modes: • Slave Select (SS) – RA5/SS • Serial Peripheral Interface (SPI) Figure16-1 shows the block diagram of the MSSP • Inter-Integrated Circuit (I2C) module when operating in SPI mode. - Full Master mode - Slave mode (with general address call) FIGURE 16-1: MSSP BLOCK DIAGRAM The I2C interface supports the following modes in (SPIMODE) hardware: Internal Data Bus • Master mode • Multi-Master mode Read Write • Slave mode SSPBUF reg 16.2 Control Registers The MSSP module has three associated registers. RC4/SDI/SDA These include a status register (SSPSTAT) and two SSPSR reg control registers (SSPCON1 and SSPCON2). The use RC5/SDO bit 0 Shift of these registers and their individual Configuration bits Clock differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual RA5/AN4/SS/ sections. HLVDIN/C2OUT SS Control Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE ( ) RC3/SCK/ 4 TMR2 Output SCL 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR TRIS bit © 2009 Microchip Technology Inc. DS39636D-page 153

PIC18F2X1X/4X1X 16.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register and the SSPIF interrupt is set. (SSPBUF) During transmission, the SSPBUF is not double- • MSSP Shift Register (SSPSR) – Not directly buffered. A write to SSPBUF will write to both SSPBUF accessible and SSPSR. SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. REGISTER 16-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI operation is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled; SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write bit Information Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 154 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 16-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 155

PIC18F2X1X/4X1X 16.3.2 OPERATION reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data When initializing SPI operation, several options need to will be ignored and the write collision detect bit, WCOL be specified. This is done by programming the (SSPCON1<7>), will be set. User software must clear appropriate control bits (SSPCON1<5:0> and the WCOL bit so that it can be determined if the follow- SSPSTAT<7:6>). These control bits allow the following ing write(s) to the SSPBUF register completed to be specified: successfully. • Master mode (SCK is the clock output) When the application software is expecting to receive • Slave mode (SCK is the clock input) valid data, the SSPBUF should be read before the next • Clock Polarity (Idle state of SCK) byte of data to transfer is written to the SSPBUF. The • Data Input Sample Phase (middle or end of data Buffer Full bit, BF (SSPSTAT<0>), indicates when output time) SSPBUF has been loaded with the received data • Clock Edge (output data on rising/falling edge of (transmission is complete). When the SSPBUF is read, SCK) the BF bit is cleared. This data may be irrelevant if the SPI interface is only a transmitter. Generally, the MSSP • Clock Rate (Master mode only) interrupt is used to determine when the transmission/ • Slave Select mode (Slave mode only) reception has completed. The SSPBUF must be read The MSSP consists of a Transmit/Receive Shift regis- and/or written. If the interrupt method is not going to be ter (SSPSR) and a Buffer register (SSPBUF). The used, then software polling can be done to ensure that SSPSR shifts the data in and out of the device, MSb a write collision does not occur. Example16-1 shows first. The SSPBUF holds the data that was written to the the loading of the SSPBUF (SSPSR) for data SSPSR until the received data is ready. Once the 8 bits transmission. of data have been received, that byte is moved to the The SSPSR is not directly readable or writable and can SSPBUF register. Then, the Buffer Full detect bit, BF only be accessed by addressing the SSPBUF register. (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are Additionally, the MSSP Status register (SSPSTAT) set. This double-buffering of the received data indicates the various status conditions. (SSPBUF) allows the next byte to start reception before EXAMPLE 16-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS39636D-page 156 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.3.3 ENABLING SPI I/O 16.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN Figure16-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI is automatically controlled by the SPI module depends on the application software. This leads to • SDO must have TRISC<5> bit cleared three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit • Master sends data – Slave sends dummy data cleared • Master sends data – Slave sends data • SCK (Slave mode) must have TRISC<3> bit set • Master sends dummy data – Slave sends data • SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39636D-page 157

PIC18F2X1X/4X1X 16.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCK. The master determines shown in Figure16-3, Figure16-5 and Figure16-6, when the slave (Processor 2, Figure16-2) is to where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPBUF register is written to. If the SPI • FOSC/4 (or TCY) interface is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR • FOSC/16 (or 4 • TCY) register will continue to shift in the signal present on the • FOSC/64 (or 16 • TCY) SDI pin at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPBUF register as This allows a maximum data rate (at 40 MHz) of if a normal received byte (interrupts and status bits 10.00Mbps. appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure16-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 16-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2↓ SSPBUF DS39636D-page 158 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.3.6 SLAVE MODE the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a In Slave mode, the data is transmitted and received as transmitted byte and becomes a floating output. the external clock pulses appear on SCK. When the External pull-up/pull-down resistors may be desirable last bit is latched, the SSPIF interrupt flag bit is set. depending on the application. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock Note1: When the SPI operation is in Slave mode line can be observed by reading the SCK pin. The Idle with SS pin control enabled state is determined by the CKP bit (SSPCON1<4>). (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external 2: If the SPI operation is used in Slave mode clock must meet the minimum high and low times as with CKE set, then the SS pin control specified in the electrical specifications. must be enabled. While in Sleep mode, the slave can transmit/receive When the SPI module resets, the bit counter is forced data. When a byte is received, the device will wake-up to ‘0’. This can be done by either forcing the SS pin to from Sleep. a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can 16.3.7 SLAVE SELECT be connected to the SDI pin. When the SPI module SYNCHRONIZATION needs to operate as a receiver, the SDO pin can be The SS pin allows a Synchronous Slave mode. The configured as an input. This disables transmissions SPI operation must be in Slave mode with SS pin from the SDO. The SDI can always be left as an input control enabled (SSPCON1<3:0> = 04h). When the SS (SDI function) since it cannot create a bus conflict. pin is low, transmission and reception are enabled and FIGURE 16-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF © 2009 Microchip Technology Inc. DS39636D-page 159

PIC18F2X1X/4X1X FIGURE 16-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2↓ SSPBUF FIGURE 16-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF DS39636D-page 160 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.3.8 OPERATION IN POWER-MANAGED 16.3.9 EFFECTS OF A RESET MODES A Reset disables the MSSP module and terminates the In SPI Master mode, module clocks may be operating current transfer. at a different speed than when in full power mode. In 16.3.10 BUS MODE COMPATIBILITY the case of the Sleep mode, all clocks are halted. Table16-1 shows the compatibility between the In Idle modes, a clock is provided to the peripherals. standard SPI modes and the states of the CKP and That clock should be from the primary clock source, the CKE control bits. secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section2.7 “Clock Sources TABLE 16-1: SPI BUS MODES and Oscillator Switching” for additional information. In most cases, the speed that the master clocks SPI Standard SPI Mode Control Bits State data is not important; however, this should be Terminology CKP CKE evaluated for each system. If MSSP interrupts are enabled, they can wake the 0, 0 0 1 controller from Sleep mode, or one of the Idle modes, 0, 1 0 0 when the master completes sending data. If an exit 1, 0 1 1 from Sleep or Idle mode is not desired, MSSP 1, 1 1 0 interrupts should be disabled. There is also an SMP bit which controls when the data If the Sleep mode is selected, all module clocks are is sampled. halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 54 TRISC PORTC Data Direction Control Register 54 SSPBUF SSP Receive Buffer/Transmit Register 52 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 52 SSPSTAT SMP CKE D/A P S R/W UA BF 52 Legend: Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 161

PIC18F2X1X/4X1X 16.4 I2C Mode 16.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial clock (SCL) – RC3/SCK/SCL accessible • Serial data (SDA) – RC4/SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs or outputs SSPCON1, SSPCON2 and SSPSTAT are the control through the TRISC<4:3> bits. and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and FIGURE 16-7: MSSP BLOCK DIAGRAM writable. The lower 6 bits of the SSPSTAT are read-only. (I2C™ MODE) The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to or read from. Read Write SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the RC3/SCK/SCL SSPBUF reg SSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload Shift value. Clock In receive operations, SSPSR and SSPBUF together SSPSR reg create a double-buffered receiver. When SSPSR RC4/SDI/ MSb LSb SDA receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS39636D-page 162 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 16-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: This bit is cleared on Reset and when SSPEN is cleared. bit 2 R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPBUF is full 0 = SSPBUF is empty In Receive mode: 1 = SSPBUF is full (does not include the ACK and Stop bits) 0 = SSPBUF is empty (does not include the ACK and Stop bits) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 163

PIC18F2X1X/4X1X REGISTER 16-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 164 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 16-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(1) 1 = Enables Receive mode for I2C operation 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(1) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 165

PIC18F2X1X/4X1X 16.4.2 OPERATION 16.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The • I2C Master mode clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Idle set (interrupt is generated, if enabled) on the Selection of any I2C mode with the SSPEN bit set, falling edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, In 10-Bit Address mode, two address bytes need to be provided these pins are programmed to inputs by received by the slave. The five Most Significant bits setting the appropriate TRISC bits. To ensure proper (MSbs) of the first address byte specify if this is a 10-bit operation of the module, pull-up resistors must be address. Bit R/W (SSPSTAT<2>) must specify a write so provided externally to the SCL and SDA pins. the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘11110 16.4.3 SLAVE MODE A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the In Slave mode, the SCL and SDA pins must be config- address. The sequence of events for 10-bit address is as ured as inputs (TRISC<4:3> set). The MSSP module follows, with steps 7 through 9 for the slave-transmitter: will override the input state with the output data when 1. Receive first (high) byte of address (bits SSPIF, required (slave-transmitter). BF and UA (SSPSTAT<1>) are set). The I2C Slave mode hardware will always generate an 2. Update the SSPADD register with second (low) interrupt on an address match. Through the mode byte of address (clears bit UA and releases the select bits, the user can also choose to interrupt on SCL line). Start and Stop bits 3. Read the SSPBUF register (clears bit BF) and When an address is matched, or the data transfer after clear flag bit SSPIF. an address match is received, the hardware automati- 4. Receive second (low) byte of address (bits cally will generate the Acknowledge (ACK) pulse and SSPIF, BF and UA are set). load the SSPBUF register with the received value 5. Update the SSPADD register with the first (high) currently in the SSPSR register. byte of address. If match releases SCL line, this Any combination of the following conditions will cause will clear bit UA. the MSSP module not to give this ACK pulse: 6. Read the SSPBUF register (clears bit BF) and • The Buffer Full bit, BF (SSPSTAT<0>), was set clear flag bit SSPIF. before the transfer was received. 7. Receive Repeated Start condition. • The overflow bit, SSPOV (SSPCON<6>), was set 8. Receive first (high) byte of address (bits SSPIF before the transfer was received. and BF are set). In this case, the SSPSR register value is not loaded 9. Read the SSPBUF register (clears bit BF) and into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The clear flag bit SSPIF. BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. DS39636D-page 166 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.3.2 Reception 16.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section16.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more detail). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit BF (SSPSTAT<0>) is until the slave is done preparing the transmit data. The set, or bit SSPOV (SSPCON1<6>) is set. transmit data must be loaded into the SSPBUF register An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then pin RC3/ byte. Flag bit, SSPIF (PIR1<3>), must be cleared in SCK/SCL should be enabled by setting bit CKP software. The SSPSTAT register is used to determine (SSPCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCL input. This ensures that the If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL SDA signal is valid during the SCL high time will be held low (clock stretch) following each data (Figure16-9). transfer. The clock must be released by setting bit CKP The ACK pulse from the master-receiver is latched on (SSPCON<4>). See Section16.4.4 “Clock Stretching” the rising edge of the ninth SCL input pulse. If the SDA for more detail. line is high (not ACK), then the data transfer is com- plete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT regis- ter) and the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. © 2009 Microchip Technology Inc. DS39636D-page 167

PIC18F2X1X/4X1X 2 FIGURE 16-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 = 0 AC W 8 R/ A1 7 A2 6 = ‘’)0 ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e ot r A6 2 s n e A7 1 0>) ON1<6>) (CKP do SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39636D-page 168 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 2 FIGURE 16-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S S D0 8 m o Fr D1 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft CKP is set in software D7 1 PIF S SCL held lowwhile CPUresponds to S K C A 9 0 = W 8 R/ A1 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 3 < 1< AT R T DA CL S SPIF (PI F (SSPS KP S S S B C © 2009 Microchip Technology Inc. DS39636D-page 169

PIC18F2X1X/4X1X FIGURE 16-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACK11110A9A8A7A6A5A4A3A2A1A 1234567891234567 Cleared in softwareCleared in software AT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag PCON1<6>) AT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated (CKP does not reset to ‘’ when SEN = )00 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS39636D-page 170 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 2 FIGURE 16-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W=1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/e First Byte of Address 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON1<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC © 2009 Microchip Technology Inc. DS39636D-page 171

PIC18F2X1X/4X1X 16.4.4 CLOCK STRETCHING 16.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretch- The SEN bit (SSPCON2<0>) allows clock stretching to ing by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 16.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure16-9). ninth clock at the end of the ACK sequence if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be held low. The CKP being cleared to ‘0’ will assert the cleared and clock stretching will not occur. SCL line low. The CKP bit must be set in the user’s 2: The CKP bit can be set in software ISR before reception is allowed to continue. By holding regardless of the state of the BF bit. the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. 16.4.4.4 Clock Stretching for 10-Bit Slave This will prevent buffer overruns from occurring (see Transmit Mode Figure16-13). In 10-Bit Slave Transmit mode, clock stretching is Note1: If the user reads the contents of the controlled during the first two address sequences by SSPBUF before the falling edge of the the state of the UA bit, just as it is in 10-Bit Slave ninth clock, thus clearing the BF bit, the Receive mode. The first two addresses are followed CKP bit will not be cleared and clock by a third address sequence which contains the high- stretching will not occur. order bits of the 10-bit address and the R/W bit set to ‘1’. After the third address sequence is performed, the 2: The CKP bit can be set in software UA bit is not set, the module is now configured in regardless of the state of the BF bit. The Transmit mode and clock stretching is controlled by user should be careful to clear the BF bit the BF flag as in 7-Bit Slave Transmit mode (see in the ISR before the next receive Figure16-11). sequence in order to prevent an overflow condition. 16.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-Bit Slave mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39636D-page 172 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already Figure16-12). sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 16-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON © 2009 Microchip Technology Inc. DS39636D-page 173

PIC18F2X1X/4X1X 2 FIGURE 16-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 2 A 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) 6 A7 1 0>) ON1< SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39636D-page 174 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 16-14: I2C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK D0 89P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s 1 D 7 e Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPADD register beforethe falling edge of the ninth clock will haveno effect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ 1110A9A8 2345678 Cleared in software >) SSPBUF is written withcontents of SSPSR N1<6>) >) UA is set indicating thatthe SSPADD needs to beupdated 1 1 AT<0 PCO AT<1 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C © 2009 Microchip Technology Inc. DS39636D-page 175

PIC18F2X1X/4X1X 16.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually deter- mines which device will be the slave addressed by the When the interrupt is serviced, the source for the master. The exception is the general call address which interrupt can be checked by reading the contents of the can address all devices. When this address is used, all SSPBUF. The value can be used to determine if the devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-Bit Address mode, the SSPADD is required to be The general call address is one of eight addresses updated for the second half of the address to match reserved for specific purposes by the I2C protocol. It and the UA bit is set (SSPSTAT<1>). If the general call consists of all ‘0’s with R/W = 0. address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Address mode, then the The general call address is recognized when the second half of the address is not necessary, the UA bit General Call Enable bit (GCEN) is enabled will not be set and the slave will begin receiving data (SSPCON2<7> set). Following a Start bit detect, 8 bits after the Acknowledge (Figure16-15). are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 16-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39636D-page 176 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start condi- Master mode of operation is supported by interrupt tion is complete. In this case, the SSPBUF generation on the detection of the Start and Stop will not be written to and the WCOL bit will conditions. The Stop (P) and Start (S) bits are cleared be set, indicating that a write to the from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is SSPBUF did not occur. set, or the bus is Idle, with both the S and P bits clear. The following events will cause the SSP Interrupt Flag In Firmware Controlled Master mode, user code bit, SSPIF, to be set (SSP interrupt, if enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 16-16: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM3:SSPM0 Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo abl WCk s SCL Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Clock Arbitration Set SSPIF, BCLIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV © 2009 Microchip Technology Inc. DS39636D-page 177

PIC18F2X1X/4X1X 16.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDA pin until all 8 bits are logic ‘1’. Thus, the first byte transmitted is a 7-bit slave transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDA, while SCL outputs the slave device and writes its value into the serial clock. Serial data is received 8 bits at a time. After SSPCON2 register (SSPCON2<6>). each byte is received, an Acknowledge bit is transmit- ted. Start and Stop conditions indicate the beginning 10. The MSSP module generates an interrupt at the and end of transmission. end of the ninth clock cycle by setting the SSPIF bit. The Baud Rate Generator used for the SPI mode oper- 11. The user generates a Stop condition by setting ation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See the Stop Enable bit, PEN (SSPCON2<2>). Section16.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete. DS39636D-page 178 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.7 BAUD RATE Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure16-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table16-3 demonstrates clock rates based on begin counting. The BRG counts down to ‘0’ and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. FIGURE 16-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 16-3: I2C™ CLOCK RATE W/BRG FSCL FOSC FCY FCY * 2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. © 2009 Microchip Technology Inc. DS39636D-page 179

PIC18F2X1X/4X1X 16.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure16-18). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 16-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39636D-page 180 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.8 I2C MASTER MODE START Note: If at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, the Enable bit, SEN (SSPCON2<0>). If the SDA and SCL SCL line is sampled low before the SDA pins are sampled high, the Baud Rate Generator is line is driven low, a bus collision occurs, reloaded with the contents of SSPADD<6:0> and starts the Bus Collision Interrupt Flag, BCLIF, is its count. If SCL and SDA are both sampled high when set, the Start condition is aborted and the the Baud Rate Generator times out (TBRG), the SDA I2C module is reset into its Idle state. pin is driven low. The action of the SDA being driven 16.4.8.1 WCOL Status Flag low while SCL is high is the Start condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the If the user writes the SSPBUF when a Start sequence Baud Rate Generator is reloaded with the contents of is in progress, the WCOL is set and the contents of the SSPADD<6:0> and resumes its count. When the Baud buffer are unchanged (the write doesn’t occur). Rate Generator times out (TBRG), the SEN bit Note: Because queueing of events is not (SSPCON2<0>) will be automatically cleared by allowed, writing to the lower 5 bits of hardware; the Baud Rate Generator is suspended, SSPCON2 is disabled until the Start leaving the SDA line held low and the Start condition is condition is complete. complete. FIGURE 16-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S © 2009 Microchip Technology Inc. DS39636D-page 181

PIC18F2X1X/4X1X 16.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes the SCL pin is asserted low. When the SCL pin is sam- from low-to-high. pled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting. The • SCL goes low before SDA is SDA pin is released (brought high) for one Baud Rate asserted low. This may indicate that Generator count (TBRG). When the Baud Rate Genera- another master is attempting to tor times out, if SDA is sampled high, the SCL pin will transmit a data ‘1’. be deasserted (brought high). When SCL is sampled Immediately following the SSPIF bit getting set, the user high, the Baud Rate Generator is reloaded with the may write the SSPBUF with the 7-bit address in 7-Bit contents of SSPADD<6:0> and begins counting. SDA Address mode or the default first address in 10-Bit and SCL must be sampled high for one TBRG. This Address mode. After the first eight bits are transmitted action is then followed by assertion of the SDA pin and an ACK is received, the user may then transmit an (SDA = 0) for one TBRG while SCL is high. Following additional eight bits of address (10-Bit Address mode) or this, the RSEN bit (SSPCON2<1>) will be automatically eight bits of data (7-Bit Address mode). cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a 16.4.9.1 WCOL Status Flag Start condition is detected on the SDA and SCL pins, If the user writes the SSPBUF when a Repeated Start the S bit (SSPSTAT<3>) will be set. The SSPIF bit will sequence is in progress, the WCOL is set and the not be set until the Baud Rate Generator has timed out. contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 16-20: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start DS39636D-page 182 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.10 I2C MASTER MODE 16.4.10.3 ACKSTAT Status Flag TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is Transmission of a data byte, a 7-bit address or the cleared when the slave has sent an Acknowledge other half of a 10-bit address is accomplished by simply (ACK=0) and is set when the slave does not Acknowl- writing a value to the SSPBUF register. This action will edge (ACK = 1). A slave sends an Acknowledge when set the Buffer Full flag bit, BF and allow the Baud Rate it has recognized its address (including a general call), Generator to begin counting and start the next trans- or when the slave has properly received its data. mission. Each bit of address/data will be shifted out 16.4.11 I2C MASTER MODE RECEPTION onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification Master mode reception is enabled by programming the parameter106). SCL is held low for one Baud Rate Receive Enable bit, RCEN (SSPCON2<3>). Generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time spec- Note: The MSSP module must be in an Idle state ification parameter 107). When the SCL pin is released before the RCEN bit is set or the RCEN bit high, it is held that way for TBRG. The data on the SDA will be disregarded. pin must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each time after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high-to-low/ bit is shifted out (the falling edge of the eighth clock), low-to-high) and data is shifted into the SSPSR. After the BF flag is cleared and the master releases SDA. the falling edge of the eighth clock, the receive enable This allows the slave device being addressed to flag is automatically cleared, the contents of the respond with an ACK bit during the ninth bit time if an SSPSR are loaded into the SSPBUF, the BF flag bit is address match occurred, or if data was received set, the SSPIF flag bit is set and the Baud Rate Gener- properly. The status of ACK is written into the ACKDT ator is suspended from counting, holding SCL low. The bit on the falling edge of the ninth clock. If the master MSSP is now in Idle state awaiting the next command. receives an Acknowledge, the Acknowledge Status bit, When the buffer is read by the CPU, the BF flag bit is ACKSTAT, is cleared. If not, the bit is set. After the ninth automatically cleared. The user can then send an clock, the SSPIF bit is set and the master clock (Baud Acknowledge bit at the end of reception by setting the Rate Generator) is suspended until the next data byte Acknowledge Sequence Enable bit, ACKEN is loaded into the SSPBUF, leaving SCL low and SDA (SSPCON2<4>). unchanged (Figure16-21). 16.4.11.1 BF Status Flag After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all In receive operation, the BF bit is set when an address seven address bits and the R/W bit are completed. On or data byte is loaded into SSPBUF from SSPSR. It is the falling edge of the eighth clock, the master will cleared when the SSPBUF register is read. deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth 16.4.11.2 SSPOV Status Flag clock, the master will sample the SDA pin to see if the In receive operation, the SSPOV bit is set when 8 bits address was recognized by a slave. The status of the are received into the SSPSR and the BF flag bit is ACK bit is loaded into the ACKSTAT status bit already set from a previous reception. (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the 16.4.11.3 WCOL Status Flag BF flag is cleared and the Baud Rate Generator is If the user writes the SSPBUF when a receive is turned off until another write to the SSPBUF takes already in progress (i.e., SSPSR is still shifting in a data place, holding SCL low and allowing SDA to float. byte), the WCOL bit is set and the contents of the buffer 16.4.10.1 BF Status Flag are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 16.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2009 Microchip Technology Inc. DS39636D-page 183

PIC18F2X1X/4X1X FIGURE 16-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom SSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = ‘’0 SCL held lwhile CPUsponds to CK re W = 0 A R/W, 89 dware R/ A1 ss and 7 d by har ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39636D-page 184 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 16-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = SDA = ACKDT = 10ogramming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer967898756123431245PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 0A1ACK 798 PCON2<0>(SEN = )1condition SEN = 0Write to SSPBUF occurs here,start XMIT Transmit Address to Slave A7A6A5A4A3A2 631245 Cleared in software Write to SSBegin Start SDA SCLS SSPIF SDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN © 2009 Microchip Technology Inc. DS39636D-page 185

PIC18F2X1X/4X1X 16.4.12 ACKNOWLEDGE SEQUENCE 16.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is sam- erate an Acknowledge, then the ACKDT bit should be pled low, the Baud Rate Generator is reloaded and cleared. If not, the user should set the ACKDT bit before counts down to ‘0’. When the Baud Rate Generator starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam- SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF pulled low. Following this, the ACKEN bit is automatically bit is set (Figure16-24). cleared, the Baud Rate Generator is turned off and the 16.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure16-23). If the user writes the SSPBUF when a Stop sequence 16.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 16-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in SSPIF set at Cleared in software the end of receive software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 16-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39636D-page 186 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.14 SLEEP OPERATION 16.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 16.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 16.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure16-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the SSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed in occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user ser- The states where arbitration can be lost are: vices the bus collision Interrupt Service Routine and if • Address Transfer the I2C bus is free, the user can resume communication • Data Transfer by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 16-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data doesn’t match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF © 2009 Microchip Technology Inc. DS39636D-page 187

PIC18F2X1X/4X1X 16.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure16-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure16-26). counts down to 0; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure16-27). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address (Figure16-26). following the Start condition. If the address The Start condition begins with the SDA and SCL pins is the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 16-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39636D-page 188 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 16-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 16-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software © 2009 Microchip Technology Inc. DS39636D-page 189

PIC18F2X1X/4X1X 16.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure16-29). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition, When the user deasserts SDA and the pin is allowed to see Figure16-30. float high, the BRG is loaded with SSPADD<6:0> and If, at the end of the BRG time-out, both SCL and SDA counts down to 0. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 16-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 16-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS39636D-page 190 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 16.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure16-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure16-32). FIGURE 16-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 16-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ © 2009 Microchip Technology Inc. DS39636D-page 191

PIC18F2X1X/4X1X NOTES: DS39636D-page 192 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 17.0 ENHANCED UNIVERSAL The pins of the Enhanced USART are multiplexed with SYNCHRONOUS RECEIVER PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as a USART: TRANSMITTER (EUSART) • bit SPEN (RCSTA<7>) must be set (= 1) The Enhanced Universal Synchronous Asynchronous • bit TRISC<7> must be set (= 1) Receiver Transmitter (EUSART) module is one of the • bit TRISC<6> must be set (= 1) two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) Note: The EUSART control will automatically The EUSART can be configured as a full-duplex reconfigure the pin from input to output as asynchronous system that can communicate with needed. peripheral devices, such as CRT terminals and The operation of the Enhanced USART module is personal computers. It can also be configured as a half- controlled through three registers: duplex synchronous system that can communicate • Transmit Status and Control (TXSTA) with peripheral devices, such as A/D or D/A integrated • Receive Status and Control (RCSTA) circuits, serial EEPROMs, etc. • Baud Rate Control (BAUDCON) The Enhanced USART module implements additional features, including automatic baud rate detection and These are detailed on the following pages in calibration, automatic wake-up on Sync Break recep- Register17-1, Register17-2 and Register17-3, tion and 12-bit Break character transmit. These make it respectively. ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The EUSART can be configured in the following modes: • Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity © 2009 Microchip Technology Inc. DS39636D-page 193

PIC18F2X1X/4X1X REGISTER 17-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 194 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 17-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 195

PIC18F2X1X/4X1X REGISTER 17-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 196 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 17.1 Baud Rate Generator (BRG) advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or The BRG is a dedicated 8-bit or 16-bit generator that achieve a slow baud rate for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGH:SPBRG registers modes of the EUSART. By default, the BRG operates causes the BRG timer to be reset (or cleared). This in 8-Bit mode; setting the BRG16 bit (BAUDCON<3>) ensures the BRG does not wait for a timer overflow selects 16-Bit mode. before outputting the new baud rate. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits 17.1.1 OPERATION IN POWER-MANAGED BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also MODES control the baud rate. In Synchronous mode, BRGH is The device clock is used to generate the desired baud ignored. Table17-1 shows the formula for computation rate. When one of the power-managed modes is of the baud rate for different EUSART modes which entered, the new clock source may be operating at a only apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRG register pair. integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table17-1. From this, 17.1.2 SAMPLING the error in baud rate can be determined. An example The data on the RX pin is sampled three times by a calculation is shown in Example17-1. Typical baud majority detect circuit to determine if a high or a low rates and error values for the various Asynchronous level is present at the RX pin. modes are shown in Table17-2. It may be TABLE 17-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair EXAMPLE 17-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 17-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2009 Microchip Technology Inc. DS39636D-page 197

PIC18F2X1X/4X1X TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — DS39636D-page 198 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — © 2009 Microchip Technology Inc. DS39636D-page 199

PIC18F2X1X/4X1X 17.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure17-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system timing and communication baud rates In the Auto-Baud Rate Detect (ABD) mode, the clock to must be taken into consideration when the BRG is reversed. Rather than the BRG clocking the using the Auto-Baud Rate Detection incoming RX signal, the RX signal is timing the BRG. In feature. ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. TABLE 17-4: BRG COUNTER CLOCK RATES Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate BRG16 BRGH BRG Counter Clock Detect must receive a byte with the value 55h (ASCII “U”, which is also the LIN bus Sync character) in order to 0 0 FOSC/512 calculate the proper bit rate. The measurement is taken 0 1 FOSC/128 over both a low and a high bit time in order to minimize 1 0 FOSC/128 any effects caused by asymmetry of the incoming signal. 1 1 FOSC/32 After a Start bit, the SPBRG begins counting up, using Note: During the ABD sequence, SPBRG and the preselected clock source on the first rising edge of SPBRGH are both used as a 16-bit RX. After eight bits on the RX pin or the fifth rising edge, counter, independent of BRG16 setting. an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th 17.1.3.1 ABD and EUSART Transmission edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- tion, the EUSART transmitter cannot be used during If a rollover of the BRG occurs (an overflow from FFFFh ABD. This means that whenever the ABDEN bit is set, to 0000h), the event is trapped by the ABDOVF status TXREG cannot be written to. Users should also ensure bit (BAUDCON<7>). It is set in hardware by BRG roll- that ABDEN does not become set during a transmit overs and can be set or cleared by the user in software. sequence. Failing to do this may result in unpredictable ABD mode remains active after rollover events and the EUSART operation. ABDEN bit remains set (Figure17-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-Bit modes by checking for 00h in the SPBRGH register. Refer to Table17-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. DS39636D-page 200 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 17-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 17-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h © 2009 Microchip Technology Inc. DS39636D-page 201

PIC18F2X1X/4X1X 17.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty The Asynchronous mode of operation is selected by and the TXIF flag bit (PIR1<4>) is set. This interrupt can clearing the SYNC bit (TXSTA<4>). In this mode, the be enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) enable bit, TXIE (PIE1<4>). TXIF will be set regardless of format (one Start bit, eight or nine data bits and one Stop the state of TXIE; it cannot be cleared in software. TXIF bit). The most common data format is 8 bits. An on-chip is also not cleared immediately upon loading TXREG, but dedicated 8-bit/16-bit Baud Rate Generator can be used becomes valid in the second instruction cycle following to derive standard baud rate frequencies from the the load instruction. Polling TXIF immediately following a oscillator. load of TXREG will return invalid results. The EUSART transmits and receives the LSb first. The While TXIF indicates the status of the TXREG register, EUSART’s transmitter and receiver are functionally independent but use the same data format and baud another bit, TRMT (TXSTA<1>), shows the status of rate. The Baud Rate Generator produces a clock, either the TSR register. TRMT is a read-only bit which is set x16 or x64 of the bit shift rate depending on the BRGH when the TSR register is empty. No interrupt logic is and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity tied to this bit so the user has to poll this bit in order to is not supported by the hardware but can be determine if the TSR register is empty. implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSART memory so it is not available to the user. module consists of the following important elements: 2: Flag bit TXIF is set when enable bit TXEN • Baud Rate Generator is set. • Sampling Circuit To set up an Asynchronous Transmission: • Asynchronous Transmitter 1. Initialize the SPBRGH:SPBRG registers for the • Asynchronous Receiver appropriate baud rate. Set or clear the BRGH • Auto-Wake-up on Sync Break Character and BRG16 bits, as required, to achieve the • 12-bit Break Character Transmit desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 17.2.1 EUSART ASYNCHRONOUS 3. If interrupts are desired, set enable bit TXIE. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit The EUSART transmitter block diagram is shown in TX9. Can be used as address/data bit. Figure17-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit TXEN (Serial) Shift Register (TSR). The Shift register obtains which will also set bit TXIF. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREG. The TXREG register is loaded with data in should be loaded in bit TX9D. software. The TSR register is not loaded until the Stop 7. Load data to the TXREG register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded 8. If using interrupts, ensure that the GIE and PEIE with new data from the TXREG register (if available). bits in the INTCON register (INTCON<7:6>) are set. FIGURE 17-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH SPBRG TX9 Baud Rate Generator TX9D DS39636D-page 202 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 17-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 17-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 17-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 TXREG EUSART Transmit Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 203

PIC18F2X1X/4X1X 17.2.2 EUSART ASYNCHRONOUS 17.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure17-6. This mode would typically be used in RS-485 systems. The data is received on the RX pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the in RS-232 systems. desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGH:SPBRG registers for the the SYNC bit and setting the SPEN bit. appropriate baud rate. Set or clear the BRGH 3. If interrupts are required, set the RCEN bit and and BRG16 bits, as required, to achieve the select the desired priority level with the RCIP bit. desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit SYNC and setting bit SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit RCIE. 7. The RCIF bit will be set when reception is 4. If 9-bit reception is desired, set bit RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit CREN. the RCIE and GIE bits are set. 6. Flag bit RCIF will be set when reception is 8. Read the RCSTA register to determine if any complete and an interrupt will be generated if error occurred during reception, as well as read enable bit RCIE was set. bit 9 of data (if applicable). 7. Read the RCSTA register to get the 9th bit (if 9. Read RCREG to determine if the device is being enabled) and determine if any error occurred addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREG register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 17-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RX RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE DS39636D-page 204 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 17-7: ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 205

PIC18F2X1X/4X1X 17.2.4 AUTO-WAKE-UP ON SYNC BREAK character and cause data or framing errors. To work CHARACTER properly, therefore, the initial character in the transmis- sion must be all ‘0’s. This can be 00h (8 bytes) for During Sleep mode, all clocks to the EUSART are standard RS-232 devices or 000h (12 bits) for LIN bus. suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be per- Oscillator start-up time must also be considered, formed. The auto-wake-up feature allows the controller especially in applications using oscillators with longer to wake-up due to activity on the RX/DT line while the start-up intervals (i.e., XT or HS mode). The Sync EUSART is operating in Asynchronous mode. Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval The auto-wake-up feature is enabled by setting the to allow enough time for the selected oscillator to start WUE bit (BAUDCON<1>). Once set, the typical receive and provide proper initialization of the EUSART. sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event 17.2.4.2 Special Considerations Using independent of the CPU mode. A wake-up event con- the WUE Bit sists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up The timing of WUE and RCIF events may cause some Signal character for the LIN protocol.) confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the Following a wake-up event, the module generates an EUSART in an Idle mode. The wake-up event causes RCIF interrupt. The interrupt is generated synchro- a receive interrupt by setting the RCIF bit. The WUE bit nously to the Q clocks in normal operating modes is cleared after this when a rising edge is seen on (Figure17-8) and asynchronously, if the device is in RX/DT. The interrupt condition is then cleared by Sleep mode (Figure17-9). The interrupt condition is reading the RCREG register. Ordinarily, the data in cleared by reading the RCREG register. RCREG will be dummy data and should be The WUE bit is automatically cleared once a low-to-high discarded. transition is observed on the RX line following the wake- The fact that the WUE bit has been cleared (or is still up event. At this point, the EUSART module is in Idle set) and the RCIF flag is set should not be used as an mode and returns to normal operation. This signals to indicator of the integrity of the data in RCREG. Users the user that the Sync Break event is over. should consider implementing a parallel method in firmware to verify received data integrity. 17.2.4.1 Special Considerations Using Auto-Wake-up To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If Since auto-wake-up functions by sensing rising edge a receive operation is not occurring, the WUE bit may transitions on RX/DT, information with any state then be set just prior to entering the Sleep mode. changes before the Stop bit may signal a false end-of- FIGURE 17-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 17-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX/DT Line Note 1 RCIF Cleared due to user read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS39636D-page 206 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 17.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN bus standard. The Break character transmit 3. Load the TXREG with a dummy character to consists of a Start bit, followed by twelve ‘0’ bits and a initiate transmission (the value is ignored). Stop bit. The frame Break character is sent whenever 4. Write ‘55h’ to TXREG to load the Sync character the SENDB and TXEN bits (TXSTA<3> and into the transmit FIFO buffer. TXSTA<5>) are set while the Transmit Shift register is 5. After the Break has been sent, the SENDB bit is loaded with data. Note that the value of data written to reset by hardware. The Sync character now TXREG will be ignored and all ‘0’s will be transmitted. transmits in the preconfigured mode. The SENDB bit is automatically reset by hardware after When the TXREG becomes empty, as indicated by the the corresponding Stop bit is sent. This allows the user TXIF, the next data byte can be written to TXREG. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 17.2.6 RECEIVING A BREAK CHARACTER character in the LIN specification). The Enhanced USART module can receive a Break Note that the data value written to the TXREG for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling active or Idle, just as it does during normal transmis- location (13 bits for Break versus Start bit and 8 data sion. See Figure17-10 for the timing of the Break bits for typical data). character sequence. The second method uses the auto-wake-up feature 17.2.5.1 Break and Sync Transmit Sequence described in Section17.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on RX/DT, header made up of a Break, followed by an Auto-Baud cause an RCIF interrupt and receive the next data byte Sync byte. This sequence is typical of a LIN bus followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 17-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) © 2009 Microchip Technology Inc. DS39636D-page 207

PIC18F2X1X/4X1X 17.3 EUSART Synchronous Once the TXREG register transfers the data to the TSR Master Mode register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTA<7>). In this mode, the data is enable bit, TXIE (PIE1<4>). TXIF is set regardless of transmitted in a half-duplex manner (i.e., transmission the state of enable bit TXIE; it cannot be cleared in and reception do not occur at the same time). When software. It will reset only when new data is loaded into transmitting data, the reception is inhibited and vice the TXREG register. versa. Synchronous mode is entered by setting bit While flag bit TXIF indicates the status of the TXREG SYNC (TXSTA<4>). In addition, enable bit SPEN register, another bit, TRMT (TXSTA<1>), shows the (RCSTA<7>) is set in order to configure the TX and RX status of the TSR register. TRMT is a read-only bit which pins to CK (clock) and DT (data) lines, respectively. is set when the TSR is empty. No interrupt logic is tied to The Master mode indicates that the processor trans- this bit so the user has to poll this bit in order to deter- mits the master clock on the CK line. Clock polarity is mine if the TSR register is empty. The TSR is not selected with the SCKP bit (BAUDCON<4>); setting mapped in data memory so it is not available to the user. SCKP sets the Idle state on CK as high, while clearing To set up a Synchronous Master Transmission: the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 17.3.1 EUSART SYNCHRONOUS MASTER bit, as required, to achieve the desired baud rate. TRANSMISSION 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in Figure17-3. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit TXIE. (Serial) Shift Register (TSR). The Shift register obtains 4. If 9-bit transmission is desired, set bit TX9. its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit TXEN. TXREG. The TXREG register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the last should be loaded in bit TX9D. bit has been transmitted from the previous load. As 7. Start transmission by loading data to the TXREG soon as the last bit is transmitted, the TSR is loaded register. with new data from the TXREG (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 17-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. DS39636D-page 208 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 17-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 TXREG EUSART Transmit Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 209

PIC18F2X1X/4X1X 17.3.2 EUSART SYNCHRONOUS 3. Ensure bits CREN and SREN are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit SREN. SREN (RCSTA<5>), or the Continuous Receive For continuous reception, set bit CREN. Enable bit, CREN (RCSTA<4>). Data is sampled on the 7. Interrupt flag bit RCIF will be set when reception RX pin on the falling edge of the clock. is complete and an interrupt will be generated if the enable bit RCIE was set. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous 8. Read the RCSTA register to get the 9th bit (if until CREN is cleared. If both bits are set, then CREN enabled) and determine if any error occurred takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREG register. 1. Initialize the SPBRGH:SPBRG registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE 2. Enable the synchronous master serial port by bits in the INTCON register (INTCON<7:6>) are setting bits SYNC, SPEN and CSRC. set. FIGURE 17-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC7/TX/CK pin (SCKP = 0) RC7/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39636D-page 210 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 17.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTA<7>). This mode differs from the 2. Clear bits CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CK pin (instead of being supplied 3. If interrupts are desired, set enable bit TXIE. internally in Master mode). This allows the device to 4. If 9-bit transmission is desired, set bit TX9. transfer or receive data while in any low-power mode. 5. Enable the transmission by setting enable bit TXEN. 17.4.1 EUSART SYNCHRONOUS 6. If 9-bit transmission is selected, the ninth bit SLAVE TRANSMIT should be loaded in bit TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes are identical, except in the case of the Sleep TXREGx register. mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREG and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 TXREG EUSART Transmit Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 211

PIC18F2X1X/4X1X 17.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits SYNC and SPEN and clearing bit modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit RCIE. Slave mode. 3. If 9-bit reception is desired, set bit RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit RCIF will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit RCIE was set. RCREG register; if the RCIE enable bit is set, the inter- 6. Read the RCSTA register to get the 9th bit (if rupt generated will wake the chip from the low-power enabled) and determine if any error occurred mode. If the global interrupt is enabled, the program will during reception. branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. DS39636D-page 212 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 18.0 10-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register18-1, CONVERTER (A/D) MODULE controls the operation of the A/D module. The ADCON1 register, shown in Register18-2, configures The Analog-to-Digital (A/D) converter module has the functions of the port pins. The ADCON2 register, 10inputs for the 28-pin devices and 13 for the 40/44-pin shown in Register18-3, configures the A/D clock devices. This module allows conversion of an analog source, programmed acquisition time and justification. input signal to a corresponding 10-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 18-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) Note1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 213

PIC18F2X1X/4X1X REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: 12 11 10 9 8 (2)7 (2)6 (2)5 4 3 2 1 0 PCFG0 N N N N N N N N N N N N N A A A A A A A A A A A A A 0000(1) A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111(1) D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only on 40/44-pin devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39636D-page 214 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 18-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 215

PIC18F2X1X/4X1X The analog reference voltage is software selectable A device Reset forces all registers to their Reset state. to either the device’s positive and negative supply This forces the A/D module to be turned off and any voltage (VDD and VSS), or the voltage level on the conversion in progress is aborted. RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D converter can The A/D converter has a unique feature of being able be configured as an analog input, or as a digital I/O. to operate while the device is in Sleep mode. To oper- The ADRESH and ADRESL registers contain the ate in Sleep, the A/D conversion clock must be derived result of the A/D conversion. When the A/D from the A/D’s internal RC oscillator. conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit The output of the sample and hold is the input into the (ADCON0 register) is cleared and A/D Interrupt Flag converter, which generates the result via successive bit ADIF is set. The block diagram of the A/D module approximation. is shown in Figure18-1. FIGURE 18-1: A/D BLOCK DIAGRAM CHS3:CHS0 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 10-bit (Input Voltage) 0011 AN3 Converter A/D 0010 AN2 0001 VCFG1:VCFG0 AN1 VDD 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X VSS Note 1: Channels AN5 through AN7 are not available on 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39636D-page 216 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X The value in the ADRESH:ADRESL registers is not 5. Wait for A/D conversion to complete, by either: modified for a Power-on Reset. The ADRESH:ADRESL • Polling for the GO/DONE bit to be cleared registers will contain unknown data after a Power-on OR Reset. • Waiting for the A/D interrupt After the A/D module has been configured as desired, 6. Read A/D Result registers (ADRESH:ADRESL); the selected channel must be acquired before the con- version is started. The analog input channels must clear bit ADIF, if required. have their corresponding TRIS bits selected as an 7. For next conversion, go to step 1 or step 2, as input. To determine acquisition time, see Section18.1 required. The A/D conversion time per bit is “A/D Acquisition Requirements”. After this acquisi- defined as TAD. A minimum wait of 2 TAD is tion time has elapsed, the A/D conversion can be required before the next acquisition starts. started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual FIGURE 18-2: A/D TRANSFER FUNCTION start of the conversion. To perform an A/D conversion, do the following steps: 3FFh 1. Configure the A/D module: 3FEh • Configure analog pins, voltage reference and digital I/O (ADCON1) ut p • Select A/D input channel (ADCON0) Out e • Select A/D acquisition time (ADCON2) d o • Select A/D conversion clock (ADCON2) al C003h git • Turn on A/D module (ADCON0) Di 002h 2. Configure A/D interrupt (if desired): • Clear ADIF bit 001h • Set ADIE bit • Set GIE bit 000h B B B B B B B B B B 3. Wait the required acquisition time (if required). S S S S S S S S S S L L L L L L L L L L 5 1 5 2 5 3 2 5 3 5 4. S•taSret tc GonOv/eDrsOioNnE: bit (ADCON0 register) 0. 1. 2. 102 1022. 102 1023. Analog Input Voltage FIGURE 18-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L E1A0K0A nGAE CHOLD = 25 pF VSS Legend: CPIN = input capacitance VT = threshold voltage 6V ILEAKAGE = leakage current at the pin due to 5V various junctions VDD 4V 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 1 2 3 4 RSS = sampling switch resistance SamplingSwitch(kΩ) © 2009 Microchip Technology Inc. DS39636D-page 217

PIC18F2X1X/4X1X 18.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation18-1 may be used. This equation assumes For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure18-3. The Example18-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5 kΩ. After the analog input channel is VDD = 5V → Rss = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 18-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 18-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 18-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) 1.05 μs TACQ = 0.2 μs + 1 μs + 1.2 μs 2.4 μs DS39636D-page 218 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 18.2 Selecting and Configuring 18.3 Selecting the A/D Conversion Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion. bit is set. It also gives users the option to use an The source of the A/D conversion clock is software automatically determined acquisition time. selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT2:ACQT0 • 2 TOSC bits (ADCON2<5:3>), which provides a range of 2 to • 4 TOSC 20TAD. When the GO/DONE bit is set, the A/D module • 8 TOSC continues to sample the input for the selected acquisi- • 16 TOSC tion time, then automatically begins a conversion. Since the acquisition time is programmed, there may • 32 TOSC be no need to wait for an acquisition time between • 64 TOSC selecting a channel and setting the GO/DONE bit. • Internal RC Oscillator Manual acquisition is selected when For correct A/D conversions, the A/D conversion clock ACQT2:ACQT0=000. When the GO/DONE bit is set, (TAD) must be as short as possible, but greater than the sampling is stopped and a conversion begins. The user minimum TAD (see parameter 130 for more is responsible for ensuring the required acquisition time information). has passed between selecting the desired input channel Table18-1 shows the resultant TAD times derived from and setting the GO/DONE bit. This option is also the the device operating frequencies and the A/D clock default Reset state of the ACQT2:ACQT0 bits and is source selected. compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18FXXXX PIC18LFXXXX(4) 2 TOSC 000 2.86 MHz 1.43 kHz 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 0.9μs. 2: The RC source has a typical TAD time of 1.2μs. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LFXXXX) devices only. © 2009 Microchip Technology Inc. DS39636D-page 219

PIC18F2X1X/4X1X 18.4 Operation in Power-Managed 18.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISB and TRISE registers all The selection of the automatic acquisition time and A/ configure the A/D port pins. The port pins needed as D conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed set (input). If the TRIS bit is cleared (output), the digital mode. output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in The A/D operation is independent of the state of the a power-managed mode, the ACQT2:ACQT0 and CHS3:CHS0 bits and the TRIS bits. ADCS2:ADCS0 bits in ADCON2 should be updated in Note1: When reading the Port register, all pins accordance with the clock source to be used in that configured as analog input channels will mode. After entering the mode, an A/D acquisition or read as cleared (a low level). Pins config- conversion may be started. Once started, the device ured as digital inputs will convert as should continue to be clocked by the same clock analog inputs. Analog levels on a digitally source until the conversion has been completed. configured input will be accurately If desired, the device may be placed into the converted. corresponding Idle mode during the conversion. If the 2: Analog levels on any pin defined as a device clock frequency is less than 1MHz, the A/D RC digital input may cause the digital input clock source should be selected. buffer to consume current out of the Operation in the Sleep mode requires the A/D FRC device’s specification limits. clock to be selected. If bits ACQT2:ACQT0 are set to 3: The PBADEN bit in Configuration ‘000’ and a conversion is started, the conversion will be Register 3H configures PORTB pins to delayed one instruction cycle to allow execution of the reset as analog or digital pins by control- SLEEP instruction and entry to Sleep mode. The IDLEN ling how the PCFG0 bits in ADCON1 are bit (OSCCON<7>) must have already been cleared reset. prior to starting the conversion. DS39636D-page 220 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 18.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TAD wait is required before the next acquisition can be Figure18-4 shows the operation of the A/D converter started. After this wait, acquisition on the selected after the GO bit has been set and the ACQT2:ACQT0 channel is automatically started. bits are cleared. A conversion is started after the follow- ing instruction to allow entry into Sleep mode before the Note: The GO/DONE bit should NOT be set in conversion begins. the same instruction that turns on the A/D. Figure18-5 shows the operation of the A/D converter 18.7 Discharge after the GO bit has been set and the ACQT2:ACQT0 bits are set to ‘010’ and selecting a 4 TAD acquisition The discharge phase is used to initialize the value of time before the conversion starts. the capacitor array. The array is discharged before Clearing the GO/DONE bit during a conversion will every sample. This feature helps to optimize the unity- abort the current conversion. The A/D Result register gain amplifier, as the circuit always needs to charge the pair will NOT be updated with the partially completed capacitor array, rather than charge/discharge based on A/D conversion sample. This means the previous measure values. ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). FIGURE 18-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 18-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected) Set GO bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2009 Microchip Technology Inc. DS39636D-page 221

PIC18F2X1X/4X1X 18.8 Use of the CCP2 Trigger software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input An A/D conversion can be started by the special event channel must be selected and the minimum acquisition trigger of the CCP2 module. This requires that the period is either timed by the user, or an appropriate CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- TACQ time selected before the special event trigger sets grammed as ‘1011’ and that the A/D module is enabled the GO/DONE bit (starts a conversion). (ADON bit is set). When the trigger occurs, the GO/ If the A/D module is not enabled (ADON is cleared), the DONE bit will be set, starting the A/D acquisition and special event trigger will be ignored by the A/D module conversion and the Timer1 (or Timer3) counter will be but will still reset the Timer1 (or Timer3) counter. reset to zero. Timer1 (or Timer3) is reset to automati- cally repeat the A/D acquisition period with minimal TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54 ADRESH A/D Result Register, High Byte 53 ADRESL A/D Result Register, Low Byte 53 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 53 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 53 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 53 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 54 TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 54 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54 TRISB PORTB Data Direction Control Register 54 LATB PORTB Data Latch Register (Read and Write to Data Latch) 54 PORTE(4) — — — — RE3(3) RE2 RE1 RE0 54 TRISE(4) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54 LATE(4) — — — — — PORTE Data Latch Register 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: These registers are not implemented on 28-pin devices. DS39636D-page 222 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 19.0 COMPARATOR MODULE The CMCON register (Register19-1) selects the comparator input and output configuration. Block The analog comparator module contains two compara- diagrams of the various comparator configurations are tors that can be configured in a variety of ways. The shown in Figure19-1. inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip volt- age reference (see Section20.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 19-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN+ connects to RA3/AN3/VREF+ C2 VIN+ connects to RA2/AN2/VREF-/CVREF 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 bit 2-0 CM2:CM0: Comparator Mode bits Figure19-1 shows the Comparator modes and the CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 223

PIC18F2X1X/4X1X 19.1 Comparator Configuration changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section25.0 “Electrical Characteristics”. tors, shown in Figure19-1. Bits CM2:CM0 of the CMCON register are used to select these modes. The Note: Comparator interrupts should be disabled TRISA register controls the data direction of the com- during a Comparator mode change; parator pins for each mode. If the Comparator mode is otherwise, a false interrupt may occur. FIGURE 19-1: COMPARATOR I/O OPERATING MODES Comparators Reset Comparators Off (POR Default Value) CM2:CM0 = 000 CM2:CM0 = 111 RA0/AN0 A VIN- RA0/AN0 D VIN- RA3/AN3/ A VIN+ C1 Off (Read as ‘0’) RA3/AN3/ D VIN+ C1 Off (Read as ‘0’) VREF+ VREF+ RA1/AN1 A VIN- RA1/AN1 D VIN- RA2/AN2/ A VIN+ C2 Off (Read as ‘0’) RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) VREF-/CVREF VREF-/CVREF Two Independent Comparators Two Independent Comparators with Outputs CM2:CM0 = 010 CM2:CM0 = 011 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RA4/T0CKI/C1OUT* RA1/AN1 A VIN- RA2/AN2/ A VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ A VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS/HLVDIN/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM2:CM0 = 100 CM2:CM0 = 101 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RA4/T0CKI/C1OUT* RA1/AN1 A VIN- RA2/AN2/ D VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ D VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS/HLVDIN/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM2:CM0 = 001 CM2:CM0 = 110 RA0/AN0 A VIN- RA0/AN0 A CIS = 0 VIN- RVRAE3F/A+N3/ A VIN+ C1 C1OUT RVRAE3F/A+N3/ A CIS = 1 VIN+ C1 C1OUT RA4/T0CKI/C1OUT* RA1/AN1 A CIS = 0 VIN- RA1/AN1 D VIN- RVRAE2F/A-/CNV2/REFA CIS = 1 VIN+ C2 C2OUT RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) CVREF VREF-/CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs. DS39636D-page 224 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 19.2 Comparator Operation 19.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure19-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section20.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure19-2 represent (CM2:CM0=110). In this mode, the internal voltage the uncertainty, due to input offsets and response time. reference is applied to the VIN+ pin of both comparators. 19.3 Comparator Reference 19.4 Comparator Response Time Depending on the comparator operating mode, either an external or internal voltage reference may be used. Response time is the minimum time, after selecting a The analog signal present at VIN- is compared to the new reference voltage or input source, before the signal at VIN+ and the digital output of the comparator comparator output has a valid level. If the internal is adjusted accordingly (Figure19-2). reference is changed, the maximum delay of the internal voltage reference must be considered when FIGURE 19-2: SINGLE COMPARATOR using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section25.0 “Electrical Characteristics”). VIN+ + 19.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the VIN- comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN+ the response time given in the specifications. Figure19-3 shows the comparator output block diagram. Output The TRISA bits will still function as an output enable/ disable for the RA4 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed 19.3.1 EXTERNAL REFERENCE SIGNAL using the C2INV and C1INV bits (CMCON<4:5>). When external voltage references are used, the Note1: When reading the Port register, all pins comparator module can be configured to have the com- configured as analog inputs will read as a parators operate from the same or different reference ‘0’. Pins configured as digital inputs will sources. However, threshold detector applications may convert an analog input according to the require the same reference. The reference signal must Schmitt Trigger input specification. be between VSS and VDD and can be applied to either 2: Analog levels on any pin defined as a pin of the comparator(s). digital input may cause the input buffer to consume more current than is specified. © 2009 Microchip Technology Inc. DS39636D-page 225

PIC18F2X1X/4X1X FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port pins P TI To RA4 or UL - RA5 pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From other Reset Comparator 19.6 Comparator Interrupts 19.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM2:CM0=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit Sleep. If the device wakes up from Sleep, the contents (INTCON<6>) must be set to enable the interrupt. In of the CMCON register are not affected. addition, the GIE bit (INTCON<7>) must also be set. If 19.8 Effects of a Reset any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM2:CM0=111). However, the input pins (RA0 (C1OUT or C2OUT) should occur when a through RA3) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR pins is determined by the setting of the PCFG3:PCFG0 registers) interrupt flag may not get set. bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset The user, in the Interrupt Service Routine, can clear the time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. DS39636D-page 226 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 19.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure19-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 19-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OCSFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 54 LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 54 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 227

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PIC18F2X1X/4X1X 20.0 COMPARATOR VOLTAGE used is selected by the CVRR bit (CVRCON<5>). The REFERENCE MODULE primary difference between the ranges is the size of the steps selected by the CVREF selection bits The comparator voltage reference is a 16-tap resistor (CVR3:CVR0), with one range offering finer resolution. ladder network that provides a selectable reference The equations used to calculate the output of the voltage. Although its primary purpose is to provide a comparator voltage reference are as follows: reference for the analog comparators, it may also be If CVRR = 1: used independently of them. CVREF = ((CVR3:CVR0)/24) x CVRSRC A block diagram of the module is shown in Figure20-1. If CVRR = 0: The resistor ladder is segmented to provide two ranges CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x of CVREF values and has a power-down function to CVRSRC) conserve power when the reference is not being used. The comparator reference supply voltage can come The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 20.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The voltage reference module is controlled through the must be considered when changing the CVREF CVRCON register (Register20-1). The comparator output (see Table25-3 in Section25.0 “Electrical voltage reference provides two ranges of output Characteristics”). voltage, each with 16 distinct levels. The range to be REGISTER 20-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin Note1: CVROE overrides the TRISA<2> bit setting. bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 229

PIC18F2X1X/4X1X FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR3:CVR0 R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 20.2 Voltage Reference Accuracy/Error 20.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure20-1) keep CVREF from approaching the refer- bit CVROE (CVRCON<6>) and selects the high-voltage ence source rails. The voltage reference is derived range by clearing bit CVRR (CVRCON<5>). The CVR from the reference source; therefore, the CVREF output value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 20.5 Connection Considerations found in Section25.0 “Electrical Characteristics”. The voltage reference module operates independently 20.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RA2 pin if the When the device wakes up from Sleep through an CVROE bit is set. Enabling the voltage reference out- interrupt or a Watchdog Timer time-out, the contents of put onto RA2 when it is configured as a digital input will the CVRCON register are not affected. To minimize increase current consumption. Connecting RA2 as a current consumption in Sleep mode, the voltage digital output with CVRSS enabled will also increase reference should be disabled. current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure20-2 shows an example buffering technique. DS39636D-page 230 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF R(1) Module + Voltage RA2 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 54 Legend: Shaded cells are not used with the comparator voltage reference. Note 1: PORTA pins are enabled based on oscillator configuration. © 2009 Microchip Technology Inc. DS39636D-page 231

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PIC18F2X1X/4X1X 21.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register21-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned PIC18F2X1X/4X1X devices have a High/Low-Voltage off” by the user under software control, which Detect module (HLVD). This is a programmable circuit minimizes the current consumption for the device. that allows the user to specify both a device voltage trip The block diagram for the HLVD module is shown in point and the direction of change from that point. If the Figure21-1. device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to the interrupt. REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0) 0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note: See Table25-4 in Section25.0 “Electrical Characteristics” for the specifications. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2009 Microchip Technology Inc. DS39636D-page 233

PIC18F2X1X/4X1X The module is enabled by setting the HLVDEN bit. event, depending on the configuration of the module. Each time that the HLVD module is enabled, the When the supply voltage is equal to the trip point, the circuitry requires some time to stabilize. The IRVST bit voltage tapped off of the resistor array is equal to the is a read-only bit and is used to indicate when the circuit internal reference voltage generated by the voltage is stable. The module can only generate an interrupt reference module. The comparator then generates an after the circuit is stable and IRVST is set. interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of The trip point voltage is software programmable to any the module. When VDIRMAG is cleared, the module one of 16 values. The trip point is selected by monitors for drops in VDD below a predetermined set programming the HLVDL3:HLVDL0 bits point. When the bit is set, the module monitors for rises (HLVDCON<3:0>). in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 21.1 Operation external source. This mode is enabled when bits HLVDL3:HLVDL0 are set to ‘1111’. In this state, the When the HLVD module is enabled, a comparator uses comparator input is multiplexed from the external input an internally generated reference voltage as the set pin, HLVDIN. This gives users flexibility because it point. The set point is compared with the trip point, allows them to configure the High/Low-Voltage Detect where each node in the resistor divider represents a interrupt to occur at any voltage in the valid operating trip point voltage. The “trip point” voltage is the voltage range. level at which the device detects a high or low-voltage FIGURE 21-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL3:HLVDL0 HLVDCON Register HLVDIN HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o 6 t 1 HLVDEN Internal Voltage BOREN Reference DS39636D-page 234 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 21.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module (HLVDCON<4>). may be disabled. 2. Write the value to the HLVDL3:HLVDL0 bits that selects the desired HLVD trip point. 21.4 HLVD Start-up Time 3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module, (VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification parameter D420, 4. Enable the HLVD module by setting the may be used by other internal circuitry, such as the HLVDEN bit. Programmable Brown-out Reset. If the HLVD or other 5. Clear the HLVD interrupt flag (PIR2<2>), which circuits using the voltage reference are disabled to may have been set from a previous interrupt. lower the device’s current consumption, the reference 6. Enable the HLVD interrupt if interrupts are voltage circuit will require time to become stable before desired by setting the HLVDIE and GIE bits a low or high-voltage condition can be reliably (PIE<2> and INTCON<7>). An interrupt will not detected. This start-up time, TIRVST, is an interval that be generated until the IRVST bit is set. is independent of device clock speed. It is specified in electrical specification parameter 36. 21.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may and voltage divider are enabled and will consume static not be detected during this interval. Refer to current. The total current consumption, when enabled, Figure21-2 or Figure21-3. is specified in electrical specification parameter D022B. FIGURE 21-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VLVD HLVDIF Enable HLVD TIVRST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VLVD HLVDIF Enable HLVD IRVST TIVRST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists © 2009 Microchip Technology Inc. DS39636D-page 235

PIC18F2X1X/4X1X FIGURE 21-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD IRVST TIVRST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD IRVST TIVRST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 21.5 Applications FIGURE 21-4: TYPICAL HIGH/LOW-VOLTAGE In many applications, the ability to detect a drop below DETECT APPLICATION or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect a Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for VA example, 3.3V to 5V (the voltage on USB) and vice VB versa for a detach. This feature could save a design a e few extra components and an attach signal (input pin). ag For general battery applications, Figure21-4 shows a Volt possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, which would allow the application to perform “house- Time TA TB keeping tasks” and perform a controlled shutdown before the device voltage exits the valid operating Legend: VA = HLVD trip point range at TB. The HLVD thus would give the application VB = Minimum valid device a time window, represented by the difference between operating voltage TA and TB, to safely exit. DS39636D-page 236 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 21.6 Operation During Sleep 21.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 21-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 52 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OCSFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 54 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2009 Microchip Technology Inc. DS39636D-page 237

PIC18F2X1X/4X1X NOTES: DS39636D-page 238 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 22.0 SPECIAL FEATURES OF A complete discussion of device Resets and interrupts THE CPU is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up PIC18F2X1X/4X1X devices include several features Timers provided for Resets, PIC18F2X1X/4X1X intended to maximize reliability and minimize cost devices have a Watchdog Timer, which is either through elimination of external components. These are: permanently enabled via the Configuration bits or • Oscillator Selection software controlled (if configured as disabled). • Resets: The inclusion of an internal RC oscillator also provides - Power-on Reset (POR) the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for - Power-up Timer (PWRT) background monitoring of the peripheral clock and - Oscillator Start-up Timer (OST) automatic switchover in the event of its failure. Two- - Brown-out Reset (BOR) Speed Start-up enables code to be executed almost • Interrupts immediately on start-up, while the primary clock source • Watchdog Timer (WDT) completes its start-up delays. • Fail-Safe Clock Monitor All of these features are enabled and configured by • Two-Speed Start-up setting the appropriate Configuration register bits. • Code Protection 22.1 Configuration Bits • ID Locations • In-Circuit Serial Programming The Configuration bits can be programmed (read as The oscillator can be configured for the application ‘0’) or left unprogrammed (read as ‘1’) to select various depending on frequency, power, accuracy and cost. All device configurations. These bits are mapped starting of the options are discussed in detail in Section2.0 at program memory location 300000h. “Oscillator Configurations”. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads. TABLE 22-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011 300006h CONFIG4L DEBUG XINST — — — LVP — STVREN 10-- -1-1 300008h CONFIG5L — — — — CP3(1,2) CP2(1) CP1 CP0 ---- 1111 300009h CONFIG5H — CPB — — — — — — -1-- ---- 30000Ah CONFIG6L — — — — WRT3(1,2) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CONFIG6H — WRTB WRTC — — — — — -11- ---- 30000Ch CONFIG7L — — — — EBTR3(1,2) EBTR2(1) EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(3) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(3) 3FFFFFh DEVID2(3) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100 Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F2410/4410 devices; maintain this bit set. 2: Unimplemented in PIC18F2515/4515 devices, maintain this bit set. 3: See Register22-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. © 2009 Microchip Technology Inc. DS39636D-page 239

PIC18F2X1X/4X1X REGISTER 22-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC3:FOSC0: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39636D-page 240 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 22-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . . 00 = Maximum setting bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note1: See Section 25.1 “DC Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39636D-page 241

PIC18F2X1X/4X1X REGISTER 22-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39636D-page 242 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 22-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1 MCLRE — — — — LPT1OSC PBADEN CCP2MX bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.) 1 = PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39636D-page 243

PIC18F2X1X/4X1X REGISTER 22-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1,2) CP2(1) CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not code-protected(3) 0 = Block 3 (006000-007FFFh) code-protected(3) 1 = Block 3 (00C000-00FFFFh) not code-protected(4) 0 = Block 3 (00C000-00FFFFh) code-protected(4) bit 2 CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code-protected(3) 0 = Block 2 (004000-005FFFh) code-protected(3) 1 = Block 2 (008000-00BFFFh) not code-protected(4) 0 = Block 2 (008000-00BFFFh) code-protected(4) bit 1 CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code-protected(3) 0 = Block 1 (002000-003FFFh) code-protected(3) 1 = Block 1 (004000-007FFFh) not code-protected(4) 0 = Block 1 (004000-007FFFh) code-protected(4) bit 0 CP0: Code Protection bit 1 = Block 0 (000800-001FFFh) not code-protected(3) 0 = Block 0 (000800-001FFFh) code-protected(3) 1 = Block 0 (000800-003FFFh) not code-protected(4) 0 = Block 0 (000800-003FFFh) code-protected(4) Note1: Unimplemented in PIC18F2410/4410 devices; maintain this bit set. 2: Unimplemented in PIC18F2515/4515 devices; maintain this bit set. 3: Address range for 16K and 32K devices. 4: Address range for 48K and 64K devices. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — CPB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) not code-protected 0 = Boot block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39636D-page 244 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 22-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3(1,2) WRT2(1) WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not write-protected(3) 0 = Block 3 (006000-007FFFh) write-protected(3) 1 = Block 3 (00C000-00FFFFh) not write-protected(4) 0 = Block 3 (00C000-00FFFFh) write-protected(4) bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write-protected(3) 0 = Block 2 (004000-005FFFh) write-protected(3) 1 = Block 2 (008000-00BFFFh) not write-protected(4) 0 = Block 2 (008000-00BFFFh) write-protected(4) bit 1 WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) not write-protected(3) 0 = Block 1 (002000-003FFFh) write-protected(3) 1 = Block 1 (004000-007FFFh) not write-protected(4) 0 = Block 1 (004000-007FFFh) write-protected(4) bit 0 WRT0: Write Protection bit 1 = Block 0 (000800-001FFFh) not write-protected(3) 0 = Block 0 (000800-001FFFh) write-protected(3) 1 = Block 0 (000800-003FFFh) not write-protected(4) 0 = Block 0 (000800-003FFFh) write-protected(4) Note1: Unimplemented in PIC18F2410/4410 devices; maintain this bit set. 2: Unimplemented in PIC18F2515/4515 devices; maintain this bit set. 3: Address range for 16K and 32K devices. 4: Address range for 48K and 64K devices. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-9: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) U-0 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 — WRTB WRTC(1) — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) not write-protected 0 = Boot block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit(1) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note 1: This bit is read-only in Normal Execution mode; it can be written only in Program mode. bit 4-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39636D-page 245

PIC18F2X1X/4X1X REGISTER 22-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3(1,2) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1,2) 1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks(3) 0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks(3) 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks(4) 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks(4) bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks(3) 0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks(3) 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks(4) 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks(4) bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks(3) 0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks(3) 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks(4) 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks(4) bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks(3) 0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks(3) 1 = Block 0 (000800-003FFFh) not protected from table reads executed in other blocks(4) 0 = Block 0 (000800-003FFFh) protected from table reads executed in other blocks(4) Note1: Unimplemented in PIC18F2410/4410 devices; maintain this bit set. 2: Unimplemented in PIC18F2515/4515 devices; maintain this bit set. 3: Address range for 16K and 32K devices. 4: Address range for 48K and 64K devices. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39636D-page 246 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 22-12: DEVICE ID REGISTER 1 FOR PIC18F2X1X/4X1X DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 011 = PIC18F2410 001 = PIC18F2510 111 = PIC18F2515 101 = PIC18F2610 111 = PIC18F4410 101 = PIC18F4510 011 = PIC18F4515 001 = PIC18F4610 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state REGISTER 22-13: DEVICE ID REGISTER 2 FOR PIC18F2X1X/4X1X DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0000 1100 = PIC18F4610/2610/4515/2515 devices 0001 0001 = PIC18F2510/2410 devices 0000 1100 = PIC18F4510/4410 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state © 2009 Microchip Technology Inc. DS39636D-page 247

PIC18F2X1X/4X1X 22.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F2X1X/4X1X devices, the WDT is driven by when executed. the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period 2: Changing the setting of the IRCF bits is 4ms and has the same stability as the INTRC (OSCCON<6:4>) clears the WDT and oscillator. postscaler counts. The 4ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed, postscaler. Any output of the WDT postscaler is the postscaler count will be cleared. selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms 22.2.1 CONTROL REGISTER to 131.072seconds (2.18 minutes). The WDT and Register22-14 shows the WDTCON register. This is a postscaler are cleared when any of the following events readable and writable register which contains a control occur: a SLEEP or CLRWDT instruction is executed, the bit that allows software to override the WDT Configura- IRCF bits (OSCCON<6:4>) are changed or a clock tion bit, but only if the Configuration bit has disabled the failure has occurred. WDT. FIGURE 22-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT WDTEN WDT Counter Wake-up From INTRC Source ÷128 Power-Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets 4 WDTPS<3:0> Sleep DS39636D-page 248 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X REGISTER 22-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note1: This bit has no effect if the Configuration bit, WDTEN, is enabled. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR TABLE 22-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page RCON IPEN SBOREN(1) — RI TO PD POR BOR 50 WDTCON — — — — — — — SWDTEN(2) 52 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section4.4 “Brown-out Reset (BOR)”. 2: This bit has no effect if the Configuration bit, WDTEN, is enabled. © 2009 Microchip Technology Inc. DS39636D-page 249

PIC18F2X1X/4X1X 22.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Start- up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period from oscillator start-up to code execution source becomes available. The setting of the IESO bit by allowing the microcontroller to use the INTOSC is ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 22.3.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTOSC oscillator in Two-Speed Start- Primary Oscillator mode is LP, XT, HS or HSPLL up, the device still obeys the normal command (Crystal-Based modes). Other sources do not require sequences for entering power-managed modes, an OST start-up delay; for these, Two-Speed Start-up including multiple SLEEP instructions (refer to should be disabled. Section3.1.4 “Multiple Sleep Commands”). In When enabled, Resets and wake-ups from Sleep mode practice, this means that user code can change the cause the device to configure itself to run from the SCS1:SCS0 bit settings or issue SLEEP instructions internal oscillator block as the clock source, following before the OST times out. This would allow an the time-out of the Power-up Timer after a Power-on application to briefly wake-up, perform routine Reset is enabled. This allows almost immediate code “housekeeping” tasks and return to Sleep before the execution while the primary oscillator starts and the device starts to operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the To use a higher clock speed on wake-up, the INTOSC status of the OSTS bit (OSCCON<3>). If the bit is set, or postscaler clock sources can be selected to provide the primary oscillator is providing the clock. Otherwise, a higher clock speed by setting bits IRCF2:IRCF0 the internal oscillator block is providing the clock during immediately after Reset. For wake-ups from Sleep, the wake-up from Reset or Sleep mode. INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. FIGURE 22-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 Wake from Interrupt Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS39636D-page 250 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 22.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF2:IRCF0, microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF2:IRCF0 bits prior to entering Sleep function is enabled by setting the FCMEN Configuration mode. bit. The FSCM will detect failures of the primary or second- When FSCM is enabled, the INTRC oscillator runs at ary clock sources only. If the internal oscillator block all times to monitor clocks to peripherals and provide a fails, no failure would be detected, nor would any action backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure22-3) is accomplished by creating a sample clock signal, which is the INTRC out- 22.4.1 FSCM AND THE WATCHDOG TIMER put divided by 64. This allows ample time between Both the FSCM and the WDT are clocked by the FSCM sample clocks for a peripheral clock edge to INTRC oscillator. Since the WDT operates with a occur. The peripheral device clock and the sample separate divider and counter, disabling the WDT has clock are presented as inputs to the Clock Monitor latch no effect on the operation of the INTRC oscillator when (CM). The CM is set on the falling edge of the device the FSCM is enabled. clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 22-3: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change Clock Monitor in the speed of code execution. If the WDT is enabled Latch (CM) (edge-triggered) with a small prescale value, a decrease in clock speed Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and INTRC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 22.4.2 EXITING FAIL-SAFE OPERATION (32 μs) 488 Hz (2.048 ms) The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the oscil- lator mode, such as OST or PLL timer). The INTOSC Clock failure is tested for on the falling edge of the multiplexer provides the device clock until the primary sample clock. If a sample clock falling edge occurs clock source becomes ready (similar to a Two-Speed while CM is still set, a clock failure has been detected Start-up). The clock source is then switched to the pri- (Figure22-4). This causes the following: mary clock (indicated by the OSTS bit in the OSCCON • the FSCM generates an oscillator fail interrupt by register becoming set). The Fail-Safe Clock Monitor setting bit OSCFIF (PIR2<7>); then resumes monitoring the peripheral clock. • the device clock source is switched to the internal The primary clock source may never become ready oscillator block (OSCCON is not updated to show during start-up. In this case, operation is clocked by the the current clock source – this is the fail-safe INTOSC multiplexer. The OSCCON register will remain condition); and in its Reset state until a power-managed mode is • the WDT is reset. entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section3.1.4 “Multiple Sleep Commands” and Section22.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. © 2009 Microchip Technology Inc. DS39636D-page 251

PIC18F2X1X/4X1X FIGURE 22-4: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 22.4.3 FSCM INTERRUPTS IN 22.4.4 POR OR WAKE FROM SLEEP POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any By entering a power-managed mode, the clock point after the device has exited Power-on Reset multiplexer selects the clock source selected by the (POR) or low-power Sleep mode. When the primary OSCCON register. Fail-Safe Monitoring of the power- device clock is EC, RC or INTRC modes, monitoring managed clock source resumes in the power-managed can begin immediately following these events. mode. For oscillator modes involving a crystal or resonator If an oscillator failure occurs during power-managed (HS, HSPLL, LP or XT), the situation is somewhat operation, the subsequent events depend on whether different. Since the oscillator may require a start-up or not the oscillator failure interrupt is enabled. If time considerably longer than the FCSM sample clock enabled (OSCFIF=1), code execution will be clocked time, a false clock failure may be detected. To prevent by the INTOSC multiplexer. An automatic transition this, the internal oscillator block is automatically config- back to the failed clock source will not occur. ured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed If the interrupt is disabled, subsequent interrupts while out). This is identical to Two-Speed Start-up mode. in Idle mode will cause the CPU to begin executing Once the primary clock is stable, the INTRC returns to instructions while being clocked by the INTOSC its role as the FSCM source. source. Note: The same logic that prevents false oscilla- tor failure interrupts on POR or wake from Sleep, will also prevent the detection of the oscillator’s failure to start at all follow- ing these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section22.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power- managed mode is selected, the primary clock is disabled. DS39636D-page 252 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 22.5 Program Verification and • Code-Protect bit (CPn) Code Protection • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The overall structure of the code protection on the PIC18 Flash devices differs significantly from other Figure22-5 shows the program memory organization PIC® devices. for 16- and 32-Kbyte devices and the specific code protection bit associated with each block. The user program memory is divided into five blocks. One of these is a boot block of 2 Kbytes. The remainder Figure22-6 shows the program memory organization of the memory is divided into four blocks on binary for 48 and 64-Kbyte devices and the specific code boundaries. protection bit associated with each block. The actual locations of the bits are summarized in Table22-3. Each of the five blocks has three code protection bits associated with them. They are: FIGURE 22-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2410/2510/4410/4510 MEMORY SIZE/DEVICE Block Code Protection 16Kbytes 32Kbytes Address Controlled By: (PIC18F2410/4410) (PIC18F2510/4510) Range 000000h Boot Block Boot Block CPB, WRTB, EBTRB 0007FFh 000800h Block 0 Block 0 CP0, WRT0, EBTR0 001FFFh 002000h Block 1 Block 1 CP1, WRT1, EBTR1 003FFFh 004000h Block 2 CP2, WRT2, EBTR2 005FFFh 006000h Block 3 CP3, WRT3, EBTR3 007FFFh Unimplemented Read ‘0’s Unimplemented Read ‘0’s (Unimplemented Memory Space) 1FFFFFh © 2009 Microchip Technology Inc. DS39636D-page 253

PIC18F2X1X/4X1X FIGURE 22-6: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2515/2610/4515/4610 MEMORY SIZE/DEVICE Block Code Protection 48Kbytes 64Kbytes Address Controlled By: (PIC18F2515/4515) (PIC18F2610/4610) Range 000000h Boot Block Boot Block CPB, WRTB, EBTRB 0007FFh 000800h Block 0 Block 0 CP0, WRT0, EBTR0 003FFFh 004000h Block 1 Block 1 CP1, WRT1, EBTR1 007FFFh 008000h Block 2 Block 2 CP2, WRT2, EBTR2 00BFFFh 00C000h Block 3 CP3, WRT3, EBTR3 00FFFFh 010000h Unimplemented Read ‘0’s Unimplemented Read ‘0’s (Unimplemented Memory Space) 1FFFFFh TABLE 22-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1,2) CP2(1) CP1 CP0 300009h CONFIG5H — CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3(1,2) WRT2(1) WRT1 WRT0 30000Bh CONFIG6H — WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3(1,2) EBTR2(1) EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18F2410/4410 devices; maintain this bit set. 2: Unimplemented in PIC18F2515/4515 devices; maintain this bit set. DS39636D-page 254 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 22.5.1 PROGRAM MEMORY from a location outside of that block is not allowed to CODE PROTECTION read and will result in reading ‘0’s. Figures22-7 through22-10 illustrate table write and table read The program memory may be read to or written from protection. any location using the table read and table write instructions. The Device ID may be read with table Note: Code protection bits may only be written to reads. The Configuration registers may be read and a ‘0’ from a ‘1’ state. It is not possible to written with the table read and table write instructions. write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full In Normal Execution mode, the CPn bits have no direct chip erase or block erase function. The full effect. CPn bits inhibit external reads and writes. The chip erase and block erase functions can EBTRn bits control table reads. For a block of user only be initiated via ICSP or an external memory with the EBTRn bit set to ‘0’, a table read programmer. instruction that executes from within that block is allowed to read. A table read instruction that executes FIGURE 22-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED (16-KBYTE AND 32-KBYTE DEVICES) Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. © 2009 Microchip Technology Inc. DS39636D-page 255

PIC18F2X1X/4X1X FIGURE 22-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED (16-KBYTE AND 32-KBYTE DEVICES) Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 001FFEh TBLRD* 001FFFh 002000h WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. FIGURE 22-9: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED (48-KBYTE AND 64-KBYTE DEVICES) Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. DS39636D-page 256 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 22-10: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED (48-KBYTE AND 64-KBYTE DEVICES) Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 001FFEh TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. 22.5.2 CONFIGURATION REGISTER 22.8 In-Circuit Debugger PROTECTION When the DEBUG Configuration bit is programmed to The Configuration registers can be write-protected. a ‘0’, the In-Circuit Debugger functionality is enabled. The WRTC bit controls protection of the Configuration This function allows simple debugging functions when registers. In Normal Execution mode, the WRTC bit is used with MPLAB® IDE. When the microcontroller has readable only. WRTC can only be written via ICSP or this feature enabled, some resources are not available an external programmer. for general use. Table22-4 shows which resources are required by the background debugger. 22.6 ID Locations TABLE 22-4: DEBUGGER RESOURCES Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store I/O pins: RB6, RB7 checksum or other code identification numbers. These Stack: 2 levels locations are both readable and writable during normal Program Memory: 512 bytes execution through the TBLRD instruction; during Data Memory: 10 bytes program/verify these locations are readable and writable. The ID locations can be read when the device To use the In-Circuit Debugger function of the micro- is code-protected. controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RE3, VDD, 22.7 In-Circuit Serial Programming VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of PIC18F2X1X/4X1X microcontrollers can be serially the third party development tool companies. programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. © 2009 Microchip Technology Inc. DS39636D-page 257

PIC18F2X1X/4X1X 22.9 Single-Supply ICSP Programming If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared. RB5/KBI1/PGM then The LVP Configuration bit enables Single-Supply ICSP becomes available as the digital I/O pin, RB5. The LVP Programming (formerly known as Low-Voltage ICSP bit may be set or cleared only when using standard Programming or LVP). When Single-Supply Program- high-voltage programming (VIHH applied to the MCLR/ ming is enabled, the microcontroller can be programmed VPP/RE3 pin). Once LVP has been disabled, only the without requiring high voltage being applied to the standard high-voltage programming is available and MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then must be used to program the device. dedicated to controlling Program mode entry and is not Memory that is not code-protected can be erased using available as a general purpose I/O pin. either a block erase, or erased row by row, then written While programming, using Single-Supply Program- at any specified VDD. If code-protected memory is to be ming mode, VDD is applied to the MCLR/VPP/RE3 pin erased, a block erase is required. If a block erase is to as in Normal Execution mode. To enter Programming be performed when using Low-Voltage Programming, mode, VDD is applied to the PGM pin. the device must be supplied with VDD of 4.5V to 5.5V. Note1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: By default, Single-Supply ICSP is enabled in unprogrammed devices (as supplied from Microchip) and erased devices. 3: When Single-Supply Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 4: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. DS39636D-page 258 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 23.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18F2X1X/4X1X devices incorporate the standard • A literal value to be loaded into a file register set of 75 PIC18 core instructions, as well as an (specified by ‘k’) extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 23.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table23-2 lists cycles, with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table23-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1μs. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 μs. The file register designator ‘f’ specifies which file regis- Two-word branch instructions (if true) would take 3 μs. ter is to be used by the instruction. The destination Figure23-1 shows the general formats that the instruc- designator ‘d’ specifies where the result of the opera- tions can have. All examples use the convention ‘nnh’ tion is to be placed. If ‘d’ is zero, the result is placed in to represent a hexadecimal number. the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table23-2, lists the standard instructions recognized by the All bit-oriented instructions have three operands: Microchip MPASM™ Assembler. 1. The file register (specified by ‘f’) Section23.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register desig- nator ‘f’ represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39636D-page 259

PIC18F2X1X/4X1X TABLE 23-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for call/branch and return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User defined term (font is Courier). DS39636D-page 260 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 23-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39636D-page 261

PIC18F2X1X/4X1X TABLE 23-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N borrow SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39636D-page 262 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 23-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2009 Microchip Technology Inc. DS39636D-page 263

PIC18F2X1X/4X1X TABLE 23-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39636D-page 264 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 23.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: ADDLW 15h Section23.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 10h After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39636D-page 265

PIC18F2X1X/4X1X ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are AND’ed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction Words: 1 W = 03h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39636D-page 266 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the program Description: The contents of W are AND’ed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section23.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39636D-page 267

PIC18F2X1X/4X1X BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f ≤ 95 (5Fh). See Words: 1 Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39636D-page 268 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’ Operation: if Negative bit is ‘0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39636D-page 269

PIC18F2X1X/4X1X BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’ Operation: if Zero bit is ‘0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39636D-page 270 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incre- mented to fetch the next instruction, the Description: Bit ‘b’ in register ‘f’ is set. new address will be PC + 2 + 2n. This If ‘a’ is ‘0’, the Access Bank is selected. instruction is a two-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section23.2.3 “Byte-Oriented and Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed ‘n’ Data Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39636D-page 271

PIC18F2X1X/4X1X BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and See Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39636D-page 272 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39636D-page 273

PIC18F2X1X/4X1X BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC + 2 + 2n. This instruction is then a 19 8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to PC 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If Zero = 1; Example: HERE CALL THERE,1 PC = address (Jump) If Zero = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39636D-page 274 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits TO GPR bank (default). and PD are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section23.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Decode No Process No operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG,1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39636D-page 275

PIC18F2X1X/4X1X COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f) → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f ≤ 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section23.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f ≤ 95 (5Fh). See Words: 1 Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39636D-page 276 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) − (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched If the contents of ‘f’ are less than the instruction is discarded and a NOP is contents of W, then the fetched executed instead, making this a instruction is discarded and a NOP is two-cycle instruction. executed instead, making this a If ‘a’ is ‘0’, the Access Bank is selected. two-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section23.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process No Note: 3 cycles if skip and followed register ‘f’ Data operation by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction Example: HERE CPFSGT REG, 0 PC = Address (HERE) W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) PC = Address (HERE) If REG ≥ W; W = ? PC = Address (NLESS) After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39636D-page 277

PIC18F2X1X/4X1X DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else Operation: (f) – 1 → dest ( W<3:0>) → W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then Encoding: 0000 01da ffff ffff ( W<7:4>) + 6 + DC → W<7:4> ; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the else result is stored in W. If ‘d’ is ‘1’, the (W<7:4>) + DC → W<7:4> result is stored back in register ‘f’ Status Affected: C (default). If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the Description: DAW adjusts the eight-bit value in W, GPR bank (default). resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Example 1: Decode Read Process Write to DAW register ‘f’ Data destination Before Instruction W = A5h Example: DECF CNT, 1, 0 C = 0 DC = 0 Before Instruction After Instruction CNT = 01h Z = 0 W = 05h C = 1 After Instruction DC = 0 CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39636D-page 278 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section23.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section23.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39636D-page 279

PIC18F2X1X/4X1X GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. placed back in register ‘f’ (default). GOTO is always a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section23.2.3 “Byte-Oriented and Decode Read literal No Read literal Bit-Oriented Instructions in Indexed ‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details. Write to PC Words: 1 No No No No operation operation operation operation Cycles: 1 Q Cycle Activity: Example: GOTO THERE Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC = Address (THERE) register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39636D-page 280 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39636D-page 281

PIC18F2X1X/4X1X IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction Words: 1 W = BFh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39636D-page 282 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ GPR bank (default). MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates Decode Read literal Process Write literal in Indexed Literal Offset Addressing ‘k’ LSB Data ‘k’ to FSRfL mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h FSR2L = ABh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39636D-page 283

PIC18F2X1X/4X1X MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39636D-page 284 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39636D-page 285

PIC18F2X1X/4X1X MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the status flags are affected. high byte. Both W and ‘f’ are Note that neither overflow nor carry is unchanged. possible in this operation. A zero result None of the status flags are affected. is possible but not detected. Note that neither overflow nor carry is possible in this operation. A zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction Words: 1 W = E2h PRODH = ? Cycles: 1 PRODL = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = E2h PRODH = ADh Decode Read Process Write PRODL = 08h register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39636D-page 286 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39636D-page 287

PIC18F2X1X/4X1X POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39636D-page 288 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC+2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a two-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39636D-page 289

PIC18F2X1X/4X1X RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL, (TOS) → PC, if s = 1 PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged. Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from Interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into their corresponding registers, W, Decode Read Process POP PC STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack, of these registers occurs (default). Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS W = WS RETLW kn ; End of table BSR = BSRS STATUS = STATUSS GIE/GIEH, PEIE/GIEL = 1 Before Instruction W = 07h After Instruction W = value of kn DS39636D-page 290 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC, a ∈ [0,1] if s = 1 (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank (default). ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs (default). set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f ≤ 95 (5Fh). See Section23.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39636D-page 291

PIC18F2X1X/4X1X RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default). GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank (default). in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section23.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39636D-page 292 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value (default). Section23.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39636D-page 293

PIC18F2X1X/4X1X SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down Status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out Status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever Q1 Q2 Q3 Q4 f ≤ 95 (5Fh). See Section23.2.3 Decode No Process Go to “Byte-Oriented and Bit-Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? After Instruction Q1 Q2 Q3 Q4 TO = 1 † Decode Read Process Write to PD = 0 register ‘f’ Data destination Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39636D-page 294 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used literal ‘k’ Data to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction Before Instruction operates in Indexed Literal Offset W = 01h Addressing mode whenever C = ? f ≤ 95 (5Fh). See Section23.2.3 After Instruction W = 01h “Byte-Oriented and Bit-Oriented C = 1 ; result is positive Instructions in Indexed Literal Offset Z = 0 Mode” for details. N = 0 Words: 1 Example 2: SUBLW 02h Cycles: 1 Before Instruction W = 02h Q Cycle Activity: C = ? Q1 Q2 Q3 Q4 After Instruction W = 00h Decode Read Process Write to C = 1 ; result is zero register ‘f’ Data destination Z = 1 N = 0 Example 1: SUBWF REG, 1, 0 Example 3: SUBLW 02h Before Instruction REG = 3 Before Instruction W = 2 W = 03h C = ? C = ? After Instruction After Instruction REG = 1 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative C = 1 ; result is positive Z = 0 Z = 0 N = 1 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39636D-page 295

PIC18F2X1X/4X1X SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) C = 1 REG = 35h Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39636D-page 296 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT; MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT; TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1 → TBLPTR; MEMORY (01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT; After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) © 2009 Microchip Technology Inc. DS39636D-page 297

PIC18F2X1X/4X1X TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register; TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register; TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register; (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1 → TBLPTR; Before Instruction (TABLAT) → Holding Register; TABLAT = 34h TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register ) DS39636D-page 298 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = B5h Words: 1 After Instruction Cycles: 1(2) W = 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39636D-page 299

PIC18F2X1X/4X1X XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section23.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39636D-page 300 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 23.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table23-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section23.2.2 “Extended Instruction instruction set, PIC18F2X1X/4X1X devices also Set”. The opcode field descriptions in Table23-1 provide an optional extension to the core CPU function- (page260) apply to both the standard and extended ality. The added features include eight additional PIC18 instruction sets. instructions that augment indirect and indexed addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing mode for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C. The user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are disabled by default. To enable them, users must set The syntax for these commands is pro- the XINST Configuration bit. vided as a reference for users who may be The instructions in the extended set (with the exception reviewing code that has been generated of CALLW, MOVSF and MOVSS) can all be classified as by a compiler. literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. 23.2.1 EXTENDED INSTRUCTION SYNTAX Two of the instructions, ADDFSR and SUBFSR, each Most of the extended instructions use indexed have an additional special instantiation for using FSR2. arguments, using one of the File Select Registers and These versions (ADDULNK and SUBULNK) allow for some offset to specify a source or destination register. automatic return after execution. When an argument for an instruction serves as part of The extended instructions are specifically implemented indexed addressing, it is enclosed in square brackets to optimize re-entrant program code (that is, code that (“[ ]”). This is done to indicate that the argument is used is recursive or that uses a software stack) written in as an index or offset. The MPASM™ Assembler will high-level languages, particularly C. Among other flag an error if it determines that an index or offset value things, they allow users working in high-level is not bracketed. languages to perform certain operations on data When the extended instruction set is enabled, brackets structures more efficiently. These include: are also used to indicate index arguments in byte- • Dynamic allocation and deallocation of software oriented and bit-oriented instructions. This is in addition stack space when entering and leaving to other changes in their syntax. For more details, see subroutines Section23.2.3.1 “Extended Instruction Syntax with • Function Pointer invocation Standard PIC18 Commands”. • Software Stack Pointer manipulation Note: In the past, square brackets have been • Manipulation of variables located in a software used to denote optional arguments in the stack PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 23-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination)2nd word 1111 xxxx xzzz zzzz PUSHL k Store literal at FSR2, 1 1110 1010 kkkk kkkk None decrement FSR2 SUBFSR f, k Subtract literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None return © 2009 Microchip Technology Inc. DS39636D-page 301

PIC18F2X1X/4X1X 23.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: ADDFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). DS39636D-page 302 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘f ’ in the second word. Both addresses d new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39636D-page 303

PIC18F2X1X/4X1X MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39636D-page 304 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2 Operation: FSR(f) – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified by contents of the FSR2. A RETURN is then ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; a NOP is performed during the Cycles: 1 second cycle. Q Cycle Activity: This may be thought of as a special case of Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary Decode Read Process Write to ‘11’); it operates only on FSR2. register ‘f’ Data destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction FSR2 = 03FFh Decode Read Process Write to register ‘f’ Data destination After Instruction FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39636D-page 305

PIC18F2X1X/4X1X 23.2.3 BYTE-ORIENTED AND 23.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and extension may cause legacy applications bit-oriented commands is replaced with the literal offset to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section5.5.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (‘a’ = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (‘a’ = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and ‘a’ = 0, instruction set disabled) when ‘a’ is set on the basis of however, a file register argument of 5Fh or less is the target address. Declaring the Access RAM bit in interpreted as an offset from the pointer value in FSR2 this mode will also generate an error in the MPASM and not as a literal address. For practical purposes, this Assembler. means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit- The destination argument, ‘d’, functions as before. oriented instructions, or almost half of the core PIC18 In the latest versions of the MPASM Assembler, instructions – may behave differently when the language support for the extended instruction set must extended instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the Access RAM are essentially remapped to their original source listing. values. This may be useful in creating backward 23.2.4 CONSIDERATIONS WHEN compatible code. If this technique is used, it may be ENABLING THE EXTENDED necessary to save the value of FSR2 and restore it INSTRUCTION SET when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc- must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular, extended instruction set (see Section23.2.3.1 users who are not writing code that uses a software “Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these programming must keep in mind that when the addresses are interpreted as literal offsets to FSR2 extended instruction set is enabled, register addresses when the instruction set extension is enabled, the of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data Addressing. addresses. Representative examples of typical byte-oriented and When porting an application to the PIC18F2X1X/4X1X, bit-oriented instructions in the Indexed Literal Offset it is very important to consider the type of code. A large, Addressing mode are provided on the following page to re-entrant application that is written in ‘C’ and would show how execution is affected. The operand condi- benefit from efficient compilation will do well when tions shown in the examples are applicable to all using the instruction set extensions. Legacy applica- instructions of these types. tions that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39636D-page 306 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X Add W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’ (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST],0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Set Indexed Contents SETF of 0A2Ch = 20h (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39636D-page 307

PIC18F2X1X/4X1X 23.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set of the PIC18F2X1X/4X1X family of devices. This • A menu option, or dialog box within the includes the MPLAB C18 C compiler, MPASM environment, that allows the user to configure the assembly language and MPLAB Integrated language tool and its settings for the project Development Environment (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing mode. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS39636D-page 308 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 24.0 DEVELOPMENT SUPPORT 24.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39636D-page 309

PIC18F2X1X/4X1X 24.2 MPLAB C Compilers for Various 24.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 24.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 24.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 24.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39636D-page 310 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 24.7 MPLAB SIM Software Simulator 24.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 24.10 PICkit 3 In-Circuit Debugger/ Programmer and 24.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. © 2009 Microchip Technology Inc. DS39636D-page 311

PIC18F2X1X/4X1X 24.11 PICkit 2 Development 24.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 24.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39636D-page 312 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39636D-page 313

PIC18F2X1X/4X1X FIGURE 25-1: PIC18F2X1X/4X1X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F2X1X/4X1X 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 25-2: PIC18F2X1X/4X1X VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V 5.0V PIC18F2X1X/4X1X 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 25 MHz Frequency DS39636D-page 314 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 25-3: PIC18LF2X1X/4X1X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2X1X/4X1X 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 40 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2009 Microchip Technology Inc. DS39636D-page 315

PIC18F2X1X/4X1X 25.1 DC Characteristics: Supply Voltage PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage PIC18LF2X1X/4X1X 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode PIC18F2X1X/4X1X 4.2 — 5.5 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for details to ensure internal Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for details to ensure internal Power-on Reset signal VBOR Brown-out Reset Voltage D005 PIC18LF2X1X/4X1X BORV1:BORV0 = 11 NA 2.05 2.16 V BORV1:BORV0 = 10 2.65 2.79 2.93 V D005 All devices BORV1:BORV0 = 01 4.11 4.33 4.55 V BORV1:BORV0 = 00 4.36 4.59 4.82 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. DS39636D-page 316 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Power-down Current (IPD)(1) PIC18LF2X1X/4X1X 0.1 950 nA -40°C VDD = 2.0V, 0.1 1.0 μA +25°C (Sleep mode) 0.2 5 μA +85°C PIC18LF2X1X/4X1X 0.1 1.4 μA -40°C VDD = 3.0V, 0.1 2 μA +25°C (Sleep mode) 0.3 8 μA +85°C All devices 0.1 1.9 μA -40°C 0.1 2.0 μA +25°C VDD = 5.0V, 0.4 15 μA +85°C (Sleep mode) Extended devices only 10 120 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39636D-page 317

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 15 31.5 μA -40°C 15 30 μA +25°C VDD = 2.0V 15 28.5 μA +85°C PIC18LF2X1X/4X1X 40 63 μA -40°C 35 60 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_RUN mode, 30 57 μA +85°C INTRC source) All devices 105 168 μA -40°C 90 160 μA +25°C VDD = 5.0V 80 152 μA +85°C Extended devices only 80 250 μA +125°C PIC18LF2X1X/4X1X 0.32 1 mA -40°C 0.33 1 mA +25°C VDD = 2.0V 0.33 1 mA +85°C PIC18LF2X1X/4X1X 0.6 1.3 mA -40°C 0.55 1.2 mA +25°C VDD = 3.0V FOSC = 1MHz (RC_RUN mode, 0.6 1.1 mA +85°C INTOSC source) All devices 1.1 2.3 mA -40°C 1.1 2.2 mA +25°C VDD = 5.0V 1.0 2.1 mA +85°C Extended devices only 1 3.3 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39636D-page 318 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 0.8 2.1 μA -40°C 0.8 2.0 μA +25°C VDD = 2.0V 0.8 1.9 μA +85°C PIC18LF2X1X/4X1X 1.3 3.0 mA -40°C 1.3 3.0 mA +25°C VDD = 3.0V FOSC = 4MHz (RC_RUN mode, 1.3 3.0 mA +85°C INTOSC source) All devices 2.5 5.3 mA -40°C 2.5 5.0 mA +25°C VDD = 5.0V 2.5 4.8 mA +85°C Extended devices only 2.5 10 mA +125°C PIC18LF2X1X/4X1X 2.9 8 μA -40°C 3.1 8 μA +25°C VDD = 2.0V 3.6 11 μA +85°C PIC18LF2X1X/4X1X 4.5 11 μA -40°C 4.8 11 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_IDLE mode, 5.8 15 μA +85°C INTRC source) All devices 9.2 16 μA -40°C 9.8 16 μA +25°C VDD = 5.0V 11.4 36 μA +85°C Extended devices only 21 180 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39636D-page 319

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 165 350 μA -40°C 175 350 μA +25°C VDD = 2.0V 190 350 μA +85°C PIC18LF2X1X/4X1X 250 500 μA -40°C 270 500 μA +25°C VDD = 3.0V FOSC = 1MHz (RC_IDLE mode, 290 500 μA +85°C INTOSC source) All devices 500 1 mA -40°C 520 1 mA +25°C VDD = 5.0V 550 1 mA +85°C Extended devices only 0.6 2.9 mA +125°C PIC18LF2X1X/4X1X 340 500 μA -40°C 350 500 μA +25°C VDD = 2.0V 360 500 μA +85°C PIC18LF2X1X/4X1X 520 900 μA -40°C 540 900 μA +25°C VDD = 3.0V FOSC = 4MHz (RC_IDLE mode, 580 900 μA +85°C INTOSC source) All devices 1.0 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.1 1.4 mA +85°C Extended devices only 1.1 5.0 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39636D-page 320 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 250 500 μA -40°C 260 500 μA +25°C VDD = 2.0V 250 500 μA +85°C PIC18LF2X1X/4X1X 550 650 μA -40°C 480 650 μA +25°C VDD = 3.0V FOSC = 1MHZ (PRI_RUN, 460 650 μA +85°C EC oscillator) All devices 1.2 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.0 1.4 mA +85°C Extended devices only 1.0 3.5 mA +125°C PIC18LF2X1X/4X1X 0.72 2.0 mA -40°C 0.74 2.0 mA +25°C VDD = 2.0V 0.74 2.0 mA +85°C PIC18LF2X1X/4X1X 1.3 3.0 mA -40°C 1.3 3.0 mA +25°C VDD = 3.0V FOSC = 4MHz (PRI_RUN, 1.3 3.0 mA +85°C EC oscillator) All devices 2.7 6.0 mA -40°C 2.6 6.0 mA +25°C VDD = 5.0V 2.5 6.0 mA +85°C Extended devices only 2.6 7.0 mA +125°C Extended devices only 8.4 21 mA +125°C VDD = 4.2V FOSC = 25MHz 11 28 mA +125°C VDD = 5.0V (PRI_RUN, EC oscillator) All devices 15 35 mA -40°C 16 35 mA +25°C VDD = 4.2V 16 35 mA +85°C FOSC = 40MHZ (PRI_RUN, All devices 21 40 mA -40°C EC oscillator) 21 40 mA +25°C VDD = 5.0V 21 40 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39636D-page 321

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) All devices 7.5 16 mA -40°C 7.4 15 mA +25°C FOSC = 4MHZ VDD = 4.2V 7.3 14 mA +85°C (PRI_RUN HS+PLL) Extended devices only 8.0 25 mA +125°C All devices 10 21 mA -40°C 10 20 mA +25°C FOSC = 4MHZ VDD = 5.0V 9.7 19 mA +85°C (PRI_RUN HS+PLL) Extended devices only 10 35 mA +125°C All devices 17 35 mA -40°C FOSC = 10MHZ 17 35 mA +25°C VDD = 4.2V (PRI_RUN HS+PLL) 17 35 mA +85°C All devices 23 40 mA -40°C FOSC = 10MHZ 23 40 mA +25°C VDD = 5.0V (PRI_RUN HS+PLL) 23 40 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39636D-page 322 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 65 130 μA -40°C 65 120 μA +25°C VDD = 2.0V 70 115 μA +85°C PIC18LF2X1X/4X1X 120 270 μA -40°C 120 250 μA +25°C VDD = 3.0V FOSC = 1MHz (PRI_IDLE mode, 130 240 μA +85°C EC oscillator) All devices 300 480 μA -40°C 240 450 μA +25°C VDD = 5.0V 300 430 μA +85°C Extended devices only 320 900 μA +125°C PIC18LF2X1X/4X1X 260 475 μA -40°C 255 450 μA +25°C VDD = 2.0V 270 430 μA +85°C PIC18LF2X1X/4X1X 420 900 μA -40°C 430 850 μA +25°C VDD = 3.0V FOSC = 4MHz (PRI_IDLE mode, 450 810 μA +85°C EC oscillator) All devices 0.9 1.5 mA -40°C 0.9 1.4 mA +25°C VDD = 5.0V 0.9 1.3 mA +85°C Extended devices only 1 1.2 mA +125°C Extended devices only 2.8 7.0 mA +125°C VDD = 4.2V FOSC = 25MHz 4.3 11 mA +125°C VDD = 5.0V (PRI_IDLE mode, EC oscillator) All devices 6.0 16 mA -40°C 6.2 16 mA +25°C VDD = 4.2V 6.6 16 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All devices 8.1 18 mA -40°C EC oscillator) 9.1 18 mA +25°C VDD = 5.0V 8.3 18 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39636D-page 323

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X1X/4X1X 14 40 μA -40°C 15 40 μA +25°C VDD = 2.0V 16 40 μA +85°C PIC18LF2X1X/4X1X 40 74 μA -40°C FOSC = 32kHz(4) 35 70 μA +25°C VDD = 3.0V (SEC_RUN mode, 31 67 μA +85°C Timer1 as clock) All devices 99 150 μA -40°C 81 150 μA +25°C VDD = 5.0V 75 150 μA +85°C PIC18LF2X1X/4X1X 2.5 12 μA -40°C 3.7 12 μA +25°C VDD = 2.0V 4.5 12 μA +85°C PIC18LF2X1X/4X1X 5.0 15 μA -40°C FOSC = 32kHz(4) 5.4 15 μA +25°C VDD = 3.0V (SEC_IDLE mode, 6.3 15 μA +85°C Timer1 as clock) All devices 8.5 25 μA -40°C 9.0 25 μA +25°C VDD = 5.0V 10.5 36 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39636D-page 324 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F2X1X/4X1X Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended ParamNo. Device Typ Max Units Conditions Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 Watchdog Timer 1.3 3.8 μA -40°C (ΔIWDT) 1.4 3.8 μA +25°C VDD = 2.0V 2.0 3.8 μA +85°C 1.9 4.6 μA -40°C 2.0 4.6 μA +25°C VDD = 3.0V 2.8 4.6 μA +85°C 4.0 10 μA -40°C 5.5 10 μA +25°C VDD = 5.0V 5.6 10 μA +85°C 13 13 μA +125°C D022A Brown-out Reset(5) 35 40 μA -40°C to +85°C VDD = 3.0V (ΔIBOR) 40 45 μA -40°C to +85°C 55 45 μA -40°C to +125°C VDD = 5.0V 0 5 μA -40°C to +125°C Sleep mode, BOREN1:BOREN0 = 10 D022B High/Low-Voltage 22 38 μA -40°C to +85°C VDD = 2.0V (ΔILVD) Detect(5) 25 40 μA -40°C to +85°C VDD = 3.0V 29 45 μA -40°C to +85°C VDD = 5.0V 30 45 μA -40°C to +125°C D025 Timer1 Oscillator 2.1 4.5 μA -40°C (ΔIOSCB) 1.8 4.5 μA +25°C VDD = 2.0V 32kHz on Timer1(4) 2.1 4.5 μA +85°C 2.2 6.0 μA -40°C 2.6 6.0 μA +25°C VDD = 3.0V 32kHz on Timer1(4) 2.9 6.0 μA +85°C 3.0 8.0 μA -40°C 3.2 8.0 μA +25°C VDD = 5.0V 32kHz on Timer1(4) 3.4 8.0 μA +85°C D026 A/D Converter 1.0 2.0 μA -40°C to +85°C VDD = 2.0V (ΔIAD) 1.0 2.0 μA -40°C to +85°C VDD = 3.0V A/D on, not converting 1.0 2.0 μA -40°C to +85°C VDD = 5.0V 2.0 8.0 μA -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 4: Low-power Timer1 oscillator selected. 5: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2009 Microchip Technology Inc. DS39636D-page 325

PIC18F2X1X/4X1X 25.3 DC Characteristics: PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS 0.2 VDD V RC3 and RC4 VSS 0.3 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes(1) D033B OSC1 VSS 0.3 VDD V XT, LP modes D034 T13CKI VSS 0.3 VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger buffer 0.8 VDD VDD V RC3 and RC4 0.7 VDD VDD V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes D044 T13CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O ports — ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±5 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±5 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 μA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. DS39636D-page 326 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.3 DC Characteristics: PIC18F2X1X/4X1X (Industrial) PIC18LF2X1X/4X1X (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Parameter is characterized but not tested. © 2009 Microchip Technology Inc. DS39636D-page 327

PIC18F2X1X/4X1X TABLE 25-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE3 pin VDD + 4 — 12.5 V (Note 2) D113 IDDP Supply Current during — 10 — mA Programming Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP™ port D132A VIW VDD for Externally Timed Erase 4.5 — 5.5 V Using ICSP port or Write D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time 1 — — ms VDD > 4.5V (externally timed) D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Required only if Single-Supply programming is disabled. DS39636D-page 328 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 25-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio* 55 — — dB 300 TRESP Response Time(1)* — 150 400 ns PIC18FXXXX 300A — 150 600 ns PIC18LFXXXX, VDD = 2.0V 301 TMC2OV Comparator Mode Change to — — 10 μs Output Valid* * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 25-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated). Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R)* — 2k — Ω 310 TSET Settling Time(1)* — — 10 μs * These parameters are characterized but not tested. Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. © 2009 Microchip Technology Inc. DS39636D-page 329

PIC18F2X1X/4X1X FIGURE 25-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be VLVD cleared in software) (HLVDIF set by hardware) HLVDIF(1) Note1: VDIRMAG = 0. TABLE 25-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Typ† Max Units Conditions No. D420 HLVD Voltage on VDD LVV = 0000 2.06 2.17 2.28 V Transition High to Low LVV = 0001 2.12 2.23 2.34 V LVV = 0010 2.24 2.36 2.48 V LVV = 0011 2.32 2.44 2.56 V LVV = 0100 2.47 2.60 2.73 V LVV = 0101 2.65 2.79 2.93 V LVV = 0110 2.74 2.89 3.04 V LVV = 0111 2.96 3.12 3.28 V LVV = 1000 3.22 3.39 3.56 V LVV = 1001 3.37 3.55 3.73 V LVV = 1010 3.52 3.71 3.90 V LVV = 1011 3.70 3.90 4.10 V LVV = 1100 3.90 4.11 4.32 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.36 4.59 4.82 V † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. DS39636D-page 330 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.4 AC (Timing) Characteristics 25.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition © 2009 Microchip Technology Inc. DS39636D-page 331

PIC18F2X1X/4X1X 25.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic The temperature and voltages specified in Table25-5 terms “PIC18FXXXX” and “PIC18LFXXXX” apply to all timing specifications unless otherwise are used throughout this section to refer to noted. Figure25-5 specifies the load conditions for the the PIC18F2X1X/4X1X and PIC18LF2X1X/ timing specifications. 4X1X families of devices specifically and only those devices. TABLE 25-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section 25.1 and Section 25.3. LF parts operate for industrial temperatures only. FIGURE 25-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports DS39636D-page 332 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 25.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 25-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 25-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 20 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 20 MHz HS Oscillator mode 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 1000 — ns XT, RC Oscillator mode 50 — ns HS Oscillator mode 32 — μs LP Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 1 μs XT Oscillator mode 100 250 ns HS Oscillator mode 50 250 ns HS Oscillator mode 5 — μs LP Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 160 — ns TCY = 4/FOSC, Extended 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — μs LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. © 2009 Microchip Technology Inc. DS39636D-page 333

PIC18F2X1X/4X1X TABLE 25-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 25-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F2X1X/4X1X (INDUSTRIAL) PIC18LF2X1X/4X1X (INDUSTRIAL) PIC18LF2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F2X1X/4X1X Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1) PIC18LF2X1X/4X1X -2 +/-1 2 % +25°C VDD = 2.7-3.3V -5 — 5 % -10°C to +85°C VDD = 2.7-3.3V -10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V PIC18F2X1X/4X1X -2 +/-1 2 % +25°C VDD = 4.5-5.5V -5 — 5 % -10°C to +85°C VDD = 4.5-5.5V -10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz(2) PIC18LF2X1X/4X1X 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC18F2X1X/4X1X 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration. 3: Change of INTRC frequency as VDD changes. DS39636D-page 334 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 25-7: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure25-5 for load conditions. TABLE 25-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TckR CLKO Rise Time — 35 100 ns (Note 1) 13 TckF CLKO Fall Time — 35 100 ns (Note 1) 14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TckH2ioI Port In Hold after CLKO ↑ 0 — — ns (Note 1) 17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TosH2ioI OSC1 ↑ (Q2 cycle) to PIC18FXXXX 100 — — ns 18A Port Input Invalid PIC18LFXXXX 200 — — ns VDD = 2.0V (I/O in hold time) 19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time) 0 — — ns 20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB7:RB4 Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. © 2009 Microchip Technology Inc. DS39636D-page 335

PIC18F2X1X/4X1X FIGURE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure25-5 for load conditions. FIGURE 25-9: BROWN-OUT RESET TIMING VDD BVDD 35 VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 25-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.4 4.0 4.6 ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 55.6 65.5 75 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIVRST Time for Internal Reference — 20 50 μs Voltage to become Stable 37 TLVD High/Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD 38 TCSD CPU Start-up Time — 10 — μs 39 TIOBST Time for INTOSC to Stabilize — 1 — μs DS39636D-page 336 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 25-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure25-5 for load conditions. TABLE 25-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 Tt0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 Tt1H T13CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 Tt1L T13CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 Tt1P T13CKI Synchronous Greater of: — ns N = prescale Input 20ns or value (1, 2, 4, 8) Period (TCY + 40)/N Asynchronous 60 — ns Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 Tcke2tmrI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment © 2009 Microchip Technology Inc. DS39636D-page 337

PIC18F2X1X/4X1X FIGURE 25-11: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure25-5 for load conditions. TABLE 25-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TccL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 51 TccH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 52 TccP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TccF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V DS39636D-page 338 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 25-12: PARALLEL SLAVE PORT TIMING (PIC18F4410/4415/4510/4515/4610) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure25-5 for load conditions. TABLE 25-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4410/4415/4510/4515/4610) Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In PIC18FXXXX 20 — ns Invalid (hold time) PIC18LFXXXX 35 — ns VDD = 2.0V 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from — 3 TCY WR ↑ or CS ↑ © 2009 Microchip Technology Inc. DS39636D-page 339

PIC18F2X1X/4X1X FIGURE 25-13: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure25-5 for load conditions. TABLE 25-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after PIC18FXXXX — 50 ns TscL2doV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39636D-page 340 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 25-14: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure25-5 for load conditions. TABLE 25-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after PIC18FXXXX — 50 ns TscL2doV SCK Edge PIC18LFXXXX 100 ns VDD = 2.0V 81 TdoV2scH, SDO Data Output Setup to SCK Edge TCY — ns TdoV2scL Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39636D-page 341

PIC18F2X1X/4X1X FIGURE 25-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure25-5 for load conditions. TABLE 25-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns (Slave mode) 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns TscL2doV PIC18LFXXXX 100 ns VDD = 2.0V 83 TscH2ssH, SS ↑ after SCK edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39636D-page 342 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X FIGURE 25-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure25-5 for load conditions. TABLE 25-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns TssL2scL 71 TscH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TscL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX 45 ns VDD = 2.0V 76 TdoF SDO Data Output Fall Time — 25 ns 77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns 78 TscR SCK Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TscF SCK Output Fall Time (Master mode) — 25 ns 80 TscH2doV, SDO Data Output Valid after SCK PIC18FXXXX — 50 ns TscL2doV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 82 TssL2doV SDO Data Output Valid after SS ↓ PIC18FXXXX — 50 ns Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TscH2ssH, SS ↑ after SCK Edge 1.5 TCY + 40 — ns TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39636D-page 343

PIC18F2X1X/4X1X FIGURE 25-17: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure25-5 for load conditions. TABLE 25-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 25-18: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure25-5 for load conditions. DS39636D-page 344 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 25-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs SSP module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs SSP module 1.5 TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 106 THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs 109 TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCL line is released. © 2009 Microchip Technology Inc. DS39636D-page 345

PIC18F2X1X/4X1X FIGURE 25-19: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure25-5 for load conditions. TABLE 25-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 25-20: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure25-5 for load conditions. DS39636D-page 346 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 25-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission 400 kHz mode 1.3 — ms can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter 107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107=1000+250=1250ns (for 100 kHz mode), before the SCL line is released. © 2009 Microchip Technology Inc. DS39636D-page 347

PIC18F2X1X/4X1X FIGURE 25-21: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure25-5 for load conditions. TABLE 25-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 Tckrf Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns (Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V 122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V FIGURE 25-22: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure25-5 for load conditions. TABLE 25-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TdtV2ckl SYNC RCV (MASTER & SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TckL2dtl Data Hold after CK ↓ (DT hold time) 15 — ns DS39636D-page 348 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X TABLE 25-24: A/D CONVERTER CHARACTERISTICS: PIC18F2X1X/4X1X (INDUSTRIAL) PIC18LF2X1X/4X1X (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 1.8 — — V VDD < 3.0V (VREFH – VREFL) 3 — — V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS — VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. © 2009 Microchip Technology Inc. DS39636D-page 349

PIC18F2X1X/4X1X FIGURE 25-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 25-25: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX TBD 1 μs A/D RC mode PIC18LFXXXX TBD 3 μs VDD = 2.0V; A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — μs -40°C to +85°C TBD — μs 0°C ≤ to ≤ +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) TBD TDIS Discharge Time 0.2 — μs Legend: TBD = To Be Determined Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. DS39636D-page 350 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 26.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. © 2009 Microchip Technology Inc. DS39636D-page 351

PIC18F2X1X/4X1X NOTES: DS39636D-page 352 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F2610-I/SPe3 XXXXXXXXXXXXXXXXX 0710017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F2610-E/SOe3 XXXXXXXXXXXXXXXXXXXX 0710017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN Example XXXXXXXX 18F2510 XXXXXXXX -I/MLe3 YYWWNNN 0710017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39636D-page 353

PIC18F2X1X/4X1X 27.1 Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F4610-I/Pe3 XXXXXXXXXXXXXXXXXX 0710017 XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead QFN Example XXXXXXXXXX PIC18F4610 XXXXXXXXXX -I/MLe3 XXXXXXXXXX 0710017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX PIC18F4610 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0710017 YYWWNNN DS39636D-page 354 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 27.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-070B © 2009 Microchip Technology Inc. DS39636D-page 355

PIC18F2X1X/4X1X 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α h φ c A A2 L A1 L1 β Units MILLMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 1.27 BSC Overall Height A – – 2.65 Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E 10.30 BSC Molded Package Width E1 7.50 BSC Overall Length D 17.90 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle Top φ 0° – 8° Lead Thickness c 0.18 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-052B DS39636D-page 356 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE 1 L TOP VIEW BOTTOM VIEW A A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 6.00 BSC Exposed Pad Width E2 3.65 3.70 4.20 Overall Length D 6.00 BSC Exposed Pad Length D2 3.65 3.70 4.20 Contact Width b 0.23 0.30 0.35 Contact Length L 0.50 0.55 0.70 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-105B © 2009 Microchip Technology Inc. DS39636D-page 357

PIC18F2X1X/4X1X 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c b1 A1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 40 Pitch e .100 BSC Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .590 – .625 Molded Package Width E1 .485 – .580 Overall Length D 1.980 – 2.095 Tip to Seating Plane L .115 – .200 Lead Thickness c .008 – .015 Upper Lead Width b1 .030 – .070 Lower Lead Width b .014 – .023 Overall Row Spacing § eB – – .700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-016B DS39636D-page 358 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE 1 N L K TOP VIEW BOTTOM VIEW A A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 44 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 8.00 BSC Exposed Pad Width E2 6.30 6.45 6.80 Overall Length D 8.00 BSC Exposed Pad Length D2 6.30 6.45 6.80 Contact Width b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-103B © 2009 Microchip Technology Inc. DS39636D-page 359

PIC18F2X1X/4X1X 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β A1 A2 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-076B DS39636D-page 360 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (June 2004) The differences between the devices listed in this data Original data sheet for PIC18F2X1X/4X1X devices. sheet are shown in TableB-1 and TableB-2. Revision B (October 2006) Changes to Register 22-13: Device ID Register 2 and packaging diagrams updated. Revision C (January 2007) Packaging diagrams updated. Revision D (October 2009) Updated to remove Preliminary status. TABLE B-1: DEVICE DIFFERENCES (PIC18F2410/2415/2510/2515/2610) Features PIC18F2410 PIC18F2510 PIC18F2515 PIC18F2610 Program Memory (Bytes) 16384 32768 49152 65536 Program Memory (Instructions) 8192 16384 24576 32768 Interrupt Sources 18 18 18 18 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, (E) Capture/Compare/PWM Modules 2 2 2 2 Enhanced 0 0 0 0 Capture/Compare/PWM Modules Parallel No No No No Communications (PSP) 10-bit Analog-to-Digital Module 10 input channels 10 input channels 10 input channels 10 input channels Packages 28-pin SPDIP 28-pin SPDIP 28-pin SPDIP 28-pin SPDIP 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin QFN 28-pin QFN TABLE B-2: DEVICE DIFFERENCES (PIC18F4410/4415/4510/4515/4610) Features PIC18F4410 PIC18F4510 PIC18F4515 PIC18F4610 Program Memory (Bytes) 16384 32768 49152 65536 Program Memory (Instructions) 8192 16384 24576 32768 Interrupt Sources 19 19 19 19 I/O Ports Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 2 2 Enhanced 0 0 0 0 Capture/Compare/PWM Modules Parallel Yes Yes Yes Yes Communications (PSP) 10-bit Analog-to-Digital Module 13 input channels 13 input channels 13 input channels 13 input channels Packages 40-pin PDIP 40-pin PDIP 40-pin PDIP 40-pin PDIP 44-pin QFN 44-pin QFN 44-pin QFN 44-pin QFN 44-pin TQFP 44-pin TQFP 44-pin TQFP 44-pin TQFP © 2009 Microchip Technology Inc. DS39636D-page 361

PIC18F2X1X/4X1X APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39636D-page 362 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442.” The changes discussed, while device PIC18CXXX Migration.” This Application Note is specific, are generally applicable to all mid-range to available as Literature Number DS00726. enhanced device migrations. This Application Note is available as Literature Number DS00716. © 2009 Microchip Technology Inc. DS39636D-page 363

PIC18F2X1X/4X1X NOTES: DS39636D-page 364 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X INDEX A Block Diagrams A/D ...........................................................................216 A/D ...................................................................................213 Analog Input Model ..................................................217 A/D Converter Interrupt, Configuring .......................217 Baud Rate Generator ..............................................179 Acquisition Requirements ........................................218 Capture Mode Operation .........................................133 ADCON0 Register ....................................................213 Comparator Analog Input Model ..............................227 ADCON1 Register ....................................................213 Comparator I/O Operating Modes (Diagram) ..........224 ADCON2 Register ....................................................213 Comparator Output ..................................................226 ADRESH Register ............................................213, 216 Comparator Voltage Reference ...............................230 ADRESL Register ....................................................213 Comparator Voltage Reference Output Buffer Example Analog Port Pins, Configuring ..................................220 231 Associated Registers ...............................................222 Compare Mode Operation .......................................134 Calculating the Minimum Required Acquisition Time ..... Device Clock ..............................................................30 218 Enhanced PWM .......................................................141 Configuring the Module ............................................217 EUSART Receive ....................................................204 Conversion Clock (TAD) ...........................................219 EUSART Transmit ...................................................202 Conversion Status (GO/DONE Bit) ..........................216 Conversions .............................................................221 External Power-on Reset Circuit (Slow VDD Power-up) 45 Converter Characteristics ........................................349 Fail-Safe Clock Monitor ...........................................251 Operation in Power Managed Modes ......................220 Generic I/O Port .........................................................97 Selecting and Configuring Acquisition Time ............219 High/Low-Voltage Detect with External Input ..........234 Special Event Trigger (CCP) ....................................222 Interrupt Logic ............................................................84 Special Event Trigger (ECCP) .................................140 MSSP (I2C Master Mode) ........................................177 Use of the CCP2 Trigger ..........................................222 MSSP (I2C Mode) ....................................................162 Absolute Maximum Ratings .............................................313 MSSP (SPI Mode) ...................................................153 AC (Timing) Characteristics .............................................331 On-Chip Reset Circuit ................................................43 Load Conditions for Device Timing Specifications ...332 PIC18F2410/2510/2515/2610 ...................................13 Parameter Symbology .............................................331 PIC18F4410/4510/4515/4610 ...................................14 Temperature and Voltage Specifications .................332 PLL (HS Mode) ..........................................................27 Timing Conditions ....................................................332 PORTD and PORTE (Parallel Slave Port) ...............112 AC Characteristics PWM Operation (Simplified) ....................................136 Internal RC Accuracy ...............................................334 Reads from Flash Program Memory .........................78 Access Bank Single Comparator ...................................................225 Mapping with Indexed Literal Offset Addressing Mode .. Table Read Operation ...............................................77 75 Timer0 in 16-Bit Mode .............................................116 ACKSTAT ........................................................................183 Timer0 in 8-Bit Mode ...............................................116 ACKSTAT Status Flag .....................................................183 Timer1 .....................................................................120 ADCON0 Register ............................................................213 Timer1 (16-Bit Read/Write Mode) ............................120 GO/DONE Bit ...........................................................216 Timer2 .....................................................................126 ADCON1 Register ............................................................213 Timer3 .....................................................................128 ADCON2 Register ............................................................213 Timer3 (16-Bit Read/Write Mode) ............................128 ADDFSR ..........................................................................302 Watchdog Timer ......................................................248 ADDLW ............................................................................265 BN ....................................................................................268 ADDULNK ........................................................................302 BNC .................................................................................269 ADDWF ............................................................................265 BNN .................................................................................269 ADDWFC .........................................................................266 BNOV ..............................................................................270 ADRESH Register ............................................................213 BNZ .................................................................................270 ADRESL Register ....................................................213, 216 BOR. See Brown-out Reset. Analog-to-Digital Converter. See A/D. BOV .................................................................................273 ANDLW ............................................................................266 BRA .................................................................................271 ANDWF ............................................................................267 Break Character (12-Bit) Transmit and Receive ..............207 Assembler BRG. See Baud Rate Generator. MPASM Assembler ..................................................310 Brown-out Reset (BOR) .....................................................46 Auto-Wake-up on Sync Break Character .........................206 Detecting ...................................................................46 B Disabling in Sleep Mode ............................................46 Bank Select Register (BSR) ...............................................61 Software Enabled ......................................................46 Baud Rate Generator .......................................................179 BSF ..................................................................................271 BC ....................................................................................267 BTFSC .............................................................................272 BCF ..................................................................................268 BTFSS .............................................................................272 BF ....................................................................................183 BTG .................................................................................273 BF Status Flag .................................................................183 BZ ....................................................................................274 © 2009 Microchip Technology Inc. DS39636D-page 365

PIC18F2X1X/4X1X C Configuring ..............................................................229 Connection Considerations ......................................230 C Compilers Effects of a Reset ....................................................230 MPLAB C18 .............................................................310 Operation During Sleep ...........................................230 CALL ................................................................................274 Compare (CCP Module) ..................................................134 CALLW .............................................................................303 Associated Registers ...............................................135 Capture (CCP Module) .....................................................133 CCPRx Register ......................................................134 Associated Registers ...............................................135 Pin Configuration .....................................................134 CCP Pin Configuration .............................................133 Software Interrupt ....................................................134 CCPRxH:CCPRxL Registers ...................................133 Special Event Trigger ..............................129, 134, 222 Prescaler ..................................................................133 Timer1/Timer3 Mode Selection ................................134 Software Interrupt ....................................................133 Compare (ECCP Module) ................................................140 Timer1/Timer3 Mode Selection ................................133 Special Event Trigger ..............................................140 Capture (ECCP Module) ..................................................140 Computed GOTO ...............................................................58 Capture/Compare/PWM (CCP) ........................................131 Configuration Bits ............................................................239 Capture Mode. See Capture. Configuration Register Protection ....................................257 CCP Mode and Timer Resources ............................132 Context Saving During Interrupts .......................................95 CCPRxH Register ....................................................132 Conversion Considerations ..............................................362 CCPRxL Register .....................................................132 CPFSEQ ..........................................................................276 Compare Mode. See Compare. CPFSGT ..........................................................................277 Interaction of Two CCP Modules .............................132 CPFSLT ...........................................................................277 Module Configuration ...............................................132 Crystal Oscillator/Ceramic Resonator ................................25 Clock Sources ....................................................................30 Customer Change Notification Service ............................375 Selecting the 31 kHz Source ......................................31 Customer Notification Service .........................................375 Selection Using OSCCON Register ...........................31 Customer Support ............................................................375 CLRF ................................................................................275 CLRWDT ..........................................................................275 D Code Examples Data Addressing Modes ....................................................71 16 x 16 Signed Multiply Routine ................................82 Comparing Addressing Modes with the Extended In- 16 x 16 Unsigned Multiply Routine ............................82 struction Set Enabled ........................................74 8 x 8 Signed Multiply Routine ....................................81 Direct .........................................................................71 8 x 8 Unsigned Multiply Routine ................................81 Indexed Literal Offset ................................................73 Changing Between Capture Prescalers ...................133 Indirect .......................................................................71 Computed GOTO Using an Offset Value ...................58 Inherent and Literal ....................................................71 Fast Register Stack ....................................................58 Data Memory .....................................................................61 How to Clear RAM (Bank 1) Using Indirect Addressing . Access Bank ..............................................................65 71 and the Extended Instruction Set ..............................73 Implementing a Real-Time Clock Using a Timer1 Inter- Bank Select Register (BSR) ......................................61 rupt Service ......................................................123 General Purpose Registers .......................................65 Initializing PORTA ......................................................97 Map for PIC18F2410/4410 ........................................62 Initializing PORTB ....................................................100 Map for PIC18F2510/4510 ........................................63 Initializing PORTC ....................................................103 Map for PIC18F2515/2610/4515/4610 ......................64 Initializing PORTD ....................................................106 Special Function Registers ........................................66 Initializing PORTE ....................................................109 DAW ................................................................................278 Loading the SSPBUF (SSPSR) Register .................156 DC and AC Characteristics Reading a Flash Program Memory Word ..................79 Graphs and Tables ..................................................351 Saving Status, WREG and BSR Registers in RAM ...95 DC Characteristics ...........................................................326 Code Protection ...............................................................239 Power-Down and Supply Current ............................317 COMF ...............................................................................276 Supply Voltage ........................................................316 Comparator ......................................................................223 DCFSNZ ..........................................................................279 Analog Input Connection Considerations .................227 DECF ...............................................................................278 Associated Registers ...............................................227 DECFSZ ..........................................................................279 Configuration ............................................................224 Development Support ......................................................309 Effects of a Reset .....................................................226 Device Differences ...........................................................361 Interrupts ..................................................................226 Device Overview ..................................................................9 Operation .................................................................225 Details on Individual Family Members .......................10 Operation During Sleep ...........................................226 New Core Features ......................................................9 Outputs ....................................................................225 Other Special Features ..............................................10 Reference ................................................................225 Device Overview (PIC18F2410/2510/2515/2610) External Signal .................................................225 Features (table) .........................................................11 Internal Signal ..................................................225 Device Overview (PIC18F4410/4510/4515/4610) Response Time ........................................................225 Features (table) .........................................................12 Comparator Specifications ...............................................329 Device Reset Timers .........................................................47 Comparator Voltage Reference .......................................229 Oscillator Start-up Timer (OST) .................................47 Accuracy and Error ..................................................230 PLL Lock Time-out .....................................................47 Associated Registers ...............................................231 Power-up Timer (PWRT) ...........................................47 DS39636D-page 366 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X Direct Addressing ...............................................................72 F E Fail-Safe Clock Monitor ...........................................239, 251 Interrupts in Power Managed Modes .......................252 Effect on Standard PIC Instructions ...........................73, 306 POR or Wake from Sleep ........................................252 Effects of Power Managed Modes on Various Clock Sources WDT During Oscillator Failure .................................251 33 Fast Register Stack ...........................................................58 Electrical Characteristics ..................................................313 Flash Program Memory .....................................................77 Enhanced Capture/Compare/PWM (ECCP) ....................139 Associated Registers .................................................79 Capture and Compare Modes ..................................140 Control Registers .......................................................78 Capture Mode. See Capture (ECCP Module). Reading .....................................................................78 Outputs and Configuration .......................................140 TABLAT (Table Latch) Register ................................78 Pin Configurations for ECCP1 .................................140 Table Reads and Table Writes ..................................77 PWM Mode. See PWM (ECCP Module). TBLPTR (Table Pointer) Register ..............................78 Standard PWM Mode ...............................................140 FSCM. See Fail-Safe Clock Monitor. Timer Resources ......................................................140 Enhanced PWM Mode. See PWM (ECCP Module). ........141 G Enhanced Universal Synchronous Asynchronous Receiver General Call Address Support .........................................176 Transmitter (EUSART). See EUSART. GOTO ..............................................................................280 Equations A/D Acquisition Time ................................................218 H A/D Minimum Charging Time ...................................218 Hardware Multiplier ............................................................81 Errata ...................................................................................8 Introduction ................................................................81 EUSART Operation ...................................................................81 Asynchronous Mode ................................................202 Performance Comparison ..........................................81 12-Bit Break Transmit and Receive .................207 High/Low-Voltage Detect .................................................233 Associated Registers, Receive ........................205 Applications .............................................................236 Associated Registers, Transmit .......................203 Associated Registers ...............................................237 Auto-Wake-up on Sync Break .........................206 Characteristics .........................................................330 Receiver ...........................................................204 Current Consumption ..............................................235 Setting up 9-bit Mode with Address Detect ......204 Effects of a Reset ....................................................237 Transmitter .......................................................202 Operation .................................................................234 Baud Rate Generator During Sleep ....................................................237 Operation in Power Managed Mode ................197 Setup .......................................................................235 Baud Rate Generator (BRG) ....................................197 Start-up Time ...........................................................235 Associated Registers .......................................197 Typical Application ...................................................236 Auto-Baud Rate Detect ....................................200 HLVD. See High/Low-Voltage Detect. .............................233 Baud Rate Error, Calculating ...........................197 Baud Rates, Asynchronous Modes .................198 I High Baud Rate Select (BRGH Bit) .................197 I/O Ports ............................................................................97 Sampling ..........................................................197 I2C Mode (MSSP) Synchronous Master Mode ......................................208 Acknowledge Sequence Timing ..............................186 Associated Registers, Receive ........................210 Baud Rate Generator ..............................................179 Associated Registers, Transmit .......................209 Bus Collision Reception .........................................................210 During a Repeated Start Condition ..................190 Transmission ...................................................208 During a Stop Condition ..................................191 Synchronous Slave Mode ........................................211 Clock Arbitration ......................................................180 Associated Registers, Receive ........................212 Clock Stretching ......................................................172 Associated Registers, Transmit .......................211 10-Bit Slave Receive Mode (SEN = 1) ............172 Reception .........................................................212 10-Bit Slave Transmit Mode ............................172 Transmission ...................................................211 7-Bit Slave Receive Mode (SEN = 1) ..............172 Extended Instruction Set ..................................................301 7-Bit Slave Transmit Mode ..............................172 ADDFSR ..................................................................302 Clock Synchronization and the CKP bit (SEN = 1) ..173 ADDULNK ................................................................302 Effects of a Reset ....................................................187 and Using MPLAB Tools ..........................................308 General Call Address Support .................................176 CALLW .....................................................................303 I2C Clock Rate w/BRG ............................................179 Considerations for Use ............................................306 Master Mode ............................................................177 MOVSF ....................................................................303 Operation .........................................................178 MOVSS ....................................................................304 Reception ........................................................183 PUSHL .....................................................................304 Repeated Start Timing .....................................182 SUBFSR ..................................................................305 Start Condition Timing .....................................181 SUBULNK ................................................................305 Transmission ...................................................183 Syntax ......................................................................301 Multi-Master Communication, Bus Collision and External Clock Input ...........................................................26 Arbitration ........................................................187 Multi-Master Mode ...................................................187 Operation .................................................................166 © 2009 Microchip Technology Inc. DS39636D-page 367

PIC18F2X1X/4X1X Read/Write Bit Information (R/W Bit) ...............166, 167 MOVF ......................................................................283 Registers ..................................................................162 MOVFF ....................................................................284 Serial Clock (RC3/SCK/SCL) ...................................167 MOVLB ....................................................................284 Slave Mode ..............................................................166 MOVLW ...................................................................285 Addressing .......................................................166 MOVWF ...................................................................285 Reception .........................................................167 MULLW ....................................................................286 Transmission ....................................................167 MULWF ....................................................................286 Sleep Operation .......................................................187 NEGF .......................................................................287 Stop Condition Timing ..............................................186 NOP .........................................................................287 ID Locations .............................................................239, 257 Opcode Field Descriptions .......................................260 INCF .................................................................................280 POP .........................................................................288 INCFSZ ............................................................................281 PUSH .......................................................................288 In-Circuit Debugger ..........................................................257 RCALL .....................................................................289 In-Circuit Serial Programming (ICSP) ......................239, 257 RESET .....................................................................289 Indexed Literal Offset Addressing RETFIE ....................................................................290 and Standard PIC18 Instructions .............................306 RETLW ....................................................................290 Indexed Literal Offset Mode .......................................73, 306 RETURN ..................................................................291 Indirect Addressing ............................................................72 RLCF .......................................................................291 INFSNZ ............................................................................281 RLNCF .....................................................................292 Initialization Conditions for all Registers ......................51–54 RRCF .......................................................................292 Instruction Cycle .................................................................59 RRNCF ....................................................................293 Clocking Scheme .......................................................59 SETF .......................................................................293 Instruction Flow/Pipelining .................................................59 SETF (Indexed Literal Offset mode) ........................307 Instruction Set SLEEP .....................................................................294 ADDLW ....................................................................265 Standard Instructions ...............................................259 ADDWF ....................................................................265 SUBFWB .................................................................294 ADDWF (Indexed Literal Offset mode) ....................307 SUBLW ....................................................................295 ADDWFC .................................................................266 SUBWF ....................................................................295 ANDLW ....................................................................266 SUBWFB .................................................................296 ANDWF ....................................................................267 SWAPF ....................................................................296 BC ............................................................................267 TBLRD .....................................................................297 BCF ..........................................................................268 TBLWT ....................................................................298 BN ............................................................................268 TSTFSZ ...................................................................299 BNC .........................................................................269 XORLW ...................................................................299 BNN .........................................................................269 XORWF ...................................................................300 BNOV .......................................................................270 INTCON Registers .......................................................85–87 BNZ ..........................................................................270 Inter-Integrated Circuit. See I2C. BOV .........................................................................273 Internal Oscillator Block .....................................................28 BRA ..........................................................................271 Adjustment .................................................................28 BSF ..........................................................................271 INTIO Modes .............................................................28 BSF (Indexed Literal Offset mode) ..........................307 INTOSC Frequency Drift ............................................28 BTFSC .....................................................................272 INTOSC Output Frequency .......................................28 BTFSS .....................................................................272 OSCTUNE Register ...................................................28 BTG ..........................................................................273 PLL in INTOSC Modes ..............................................28 BZ ............................................................................274 Internal RC Oscillator CALL ........................................................................274 Use with WDT ..........................................................248 CLRF ........................................................................275 Internet Address ..............................................................375 CLRWDT ..................................................................275 Interrupt Sources .............................................................239 COMF ......................................................................276 A/D Conversion Complete .......................................217 CPFSEQ ..................................................................276 Capture Complete (CCP) .........................................133 CPFSGT ..................................................................277 Compare Complete (CCP) .......................................134 CPFSLT ...................................................................277 Interrupt-on-Change (RB7:RB4) ..............................100 DAW .........................................................................278 INTn Pin .....................................................................95 DCFSNZ ..................................................................279 PORTB, Interrupt-on-Change ....................................95 DECF .......................................................................278 TMR0 .........................................................................95 DECFSZ ...................................................................279 TMR0 Overflow ........................................................117 Firmware Instructions ...............................................259 TMR1 Overflow ........................................................119 General Format ........................................................261 TMR2 to PR2 Match (PWM) ............................136, 141 GOTO ......................................................................280 TMR3 Overflow ................................................127, 129 INCF .........................................................................280 Interrupts ............................................................................83 INCFSZ ....................................................................281 Interrupts, Flag Bits INFSNZ ....................................................................281 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .....100 IORLW .....................................................................282 INTOSC, INTRC. See Internal Oscillator Block. IORWF .....................................................................282 IORLW .............................................................................282 LFSR ........................................................................283 IORWF .............................................................................282 DS39636D-page 368 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X IPR Registers .....................................................................92 Oscillator Switching ...........................................................30 Oscillator Transitions .........................................................31 L Oscillator, Timer1 .....................................................119, 129 LFSR ................................................................................283 Oscillator, Timer3 .............................................................127 Low-Voltage ICSP Programming. See Single-Supply ICSP P Programming Packaging Information .....................................................353 M Details (Diagrams) ...................................................355 Master Clear (MCLR) .........................................................45 Marking ....................................................................353 Master Synchronous Serial Port (MSSP). See MSSP. Parallel Slave Port (PSP) .........................................106, 112 Memory Organization .........................................................55 Associated Registers ...............................................113 Data Memory .............................................................61 CS (Chip Select) ......................................................112 Program Memory .......................................................55 PORTD ....................................................................112 Memory Programming Requirements ..............................328 RD (Read Input) ......................................................112 Microchip Internet Web Site .............................................375 Select (PSPMODE Bit) ....................................106, 112 Migration from Baseline to Enhanced Devices ................362 WR (Write Input) ......................................................112 Migration from High-End to Enhanced Devices ...............363 PIE Registers .....................................................................90 Migration from Mid-Range to Enhanced Devices ............363 Pin Functions MOVF ...............................................................................283 MCLR/VPP/RE3 ...................................................15, 19 MOVFF ............................................................................284 OSC1/CLKI/RA7 ..................................................15, 19 MOVLB ............................................................................284 OSC2/CLKO/RA6 ................................................15, 19 MOVLW ...........................................................................285 RA0/AN0 ..............................................................16, 20 MOVSF ............................................................................303 RA1/AN1 ..............................................................16, 20 MOVSS ............................................................................304 RA2/AN2/VREF-/CVREF .......................................16, 20 MOVWF ...........................................................................285 RA3/AN3/VREF+ ..................................................16, 20 MPLAB ASM30 Assembler, Linker, Librarian ..................310 RA4/T0CKI/C1OUT .............................................16, 20 MPLAB Integrated Development Environment Software .309 RA5/AN4/SS/HLVDIN/C2OUT ............................16, 20 MPLAB PM3 Device Programmer ...................................312 RB0/INT0/FLT0/AN12 .........................................17, 21 MPLAB REAL ICE In-Circuit Emulator System ................311 RB1/INT1/AN10 ...................................................17, 21 MPLINK Object Linker/MPLIB Object Librarian ...............310 RB2/INT2/AN8 .....................................................17, 21 MSSP RB3/AN9/CCP2 ...................................................17, 21 ACK Pulse ........................................................166, 167 RB4/KBI0/AN11 ...................................................17, 21 Control Registers (general) ......................................153 RB5/KBI1/PGM ....................................................17, 21 I2C Mode. See I2C Mode. RB6/KBI2/PGC ....................................................17, 21 Module Overview .....................................................153 RB7/KBI3/PGD ....................................................17, 21 SPI Master/Slave Connection ..................................157 RC0/T1OSO/T13CKI ...........................................18, 22 SPI Mode. See SPI Mode. RC1/T1OSI/CCP2 ...............................................18, 22 SSPBUF ...................................................................158 RC2/CCP1 .................................................................18 SSPSR .....................................................................158 RC2/CCP1/P1A .........................................................22 MULLW ............................................................................286 RC3/SCK/SCL .....................................................18, 22 MULWF ............................................................................286 RC4/SDI/SDA ......................................................18, 22 RC5/SDO .............................................................18, 22 N RC6/TX/CK ..........................................................18, 22 NEGF ...............................................................................287 RC7/RX/DT ..........................................................18, 22 NOP .................................................................................287 RD0/PSP0 .................................................................23 O RD1/PSP1 .................................................................23 RD2/PSP2 .................................................................23 OPTION_REG Register RD3/PSP3 .................................................................23 PSA Bit .....................................................................117 RD4/PSP4 .................................................................23 T0CS Bit ...................................................................116 RD5/PSP5/P1B .........................................................23 T0PS2:T0PS0 Bits ...................................................117 RD6/PSP6/P1C .........................................................23 T0SE Bit ...................................................................116 RD7/PSP7/P1D .........................................................23 Oscillator Configuration ......................................................25 RE0/RD/AN5 .............................................................24 EC ..............................................................................25 RE1/WR/AN6 .............................................................24 ECIO ..........................................................................25 RE2/CS/AN7 ..............................................................24 HS ..............................................................................25 VDD ......................................................................18, 24 HSPLL ........................................................................25 VSS ......................................................................18, 24 Internal Oscillator Block .............................................28 Pinout I/O Descriptions INTIO1 .......................................................................25 PIC18F2410/2510/2515/2610 ...................................15 INTIO2 .......................................................................25 PIC18F4410/4510/4515/4610 ...................................19 LP ...............................................................................25 PIR Registers .....................................................................88 RC ..............................................................................25 PLL Frequency Multiplier ...................................................27 RCIO ..........................................................................25 HSPLL Oscillator Mode .............................................27 XT ..............................................................................25 Use with INTOSC ......................................................27 Oscillator Selection ..........................................................239 POP .................................................................................288 Oscillator Start-up Timer (OST) ...................................33, 47 POR. See Power-on Reset. © 2009 Microchip Technology Inc. DS39636D-page 369

PIC18F2X1X/4X1X PORTA Timer2 .....................................................................142 Associated Registers .................................................99 Prescaler, Timer0 ............................................................117 LATA Register ............................................................97 Assignment (PSA Bit) ..............................................117 PORTA Register ........................................................97 Rate Select (T0PS2:T0PS0 Bits) .............................117 TRISA Register ..........................................................97 Switching Between Timer0 and WDT ......................117 PORTB Prescaler, Timer2 ............................................................137 Associated Registers ...............................................102 PRI_IDLE Mode .................................................................40 LATB Register ..........................................................100 PRI_RUN Mode .................................................................36 PORTB Register ......................................................100 Program Counter ...............................................................56 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........100 PCL, PCH and PCU Registers ..................................56 TRISB Register ........................................................100 PCLATH and PCLATU Registers ..............................56 PORTC Program Memory Associated Registers ...............................................105 and Extended Instruction Set ....................................75 LATC Register .........................................................103 Code Protection .......................................................255 PORTC Register ......................................................103 Instructions ................................................................60 RC3/SCK/SCL Pin ...................................................167 Two-Word ..........................................................60 TRISC Register ........................................................103 Interrupt Vector ..........................................................55 PORTD Look-up Tables ..........................................................58 Associated Registers ...............................................108 Map and Stack (diagram) ..........................................55 LATD Register .........................................................106 Reset Vector ..............................................................55 Parallel Slave Port (PSP) Function ..........................106 Program Verification and Code Protection ......................253 PORTD Register ......................................................106 Associated Registers ...............................................254 TRISD Register ........................................................106 Programming, Device Instructions ...................................259 PORTE PSP. See Parallel Slave Port. Associated Registers ...............................................111 Pulse-Width Modulation. See PWM (CCP Module) and LATE Register ..........................................................109 PWM (ECCP Module). PORTE Register ......................................................109 PUSH ...............................................................................288 PSP Mode Select (PSPMODE Bit) ..........................106 PUSH and POP Instructions ..............................................57 TRISE Register ........................................................109 PUSHL .............................................................................304 Postscaler, WDT PWM (CCP Module) Assignment (PSA Bit) ..............................................117 Associated Registers ...............................................138 Rate Select (T0PS2:T0PS0 Bits) .............................117 Auto-Shutdown (CCP1 only) ....................................137 Switching Between Timer0 and WDT ......................117 CCPR1H:CCPR1L Registers ...................................141 Power Managed Modes .....................................................35 Duty Cycle .......................................................136, 142 and A/D Operation ...................................................220 Example Frequencies/Resolutions ..................137, 142 and EUSART Operation ...........................................197 Period ..............................................................136, 141 and Multiple Sleep Commands ..................................36 Setup for PWM Operation ........................................137 and PWM Operation ................................................151 TMR2 to PR2 Match ........................................136, 141 and SPI Operation ...................................................161 PWM (ECCP Module) ......................................................141 Clock Sources ............................................................35 Associated Registers ...............................................152 Clock Transitions and Status Indicators .....................36 Direction Change in Full-Bridge Output Mode .........146 Effects on Clock Sources ...........................................33 Effects of a Reset ....................................................151 Entering ......................................................................35 Enhanced PWM Auto-Shutdown .............................148 Exiting Idle and Sleep Modes ....................................41 Full-Bridge Application Example ..............................146 by Interrupt .........................................................41 Full-Bridge Mode .....................................................145 by Reset .............................................................41 Half-Bridge Mode .....................................................144 by WDT Time-out ...............................................41 Half-Bridge Output Mode Applications Example ......144 Without a Start-up Delay ....................................42 Operation in Power Managed Modes ......................151 Idle Modes .................................................................39 Operation with Fail-Safe Clock Monitor ...................151 PRI_IDLE ...........................................................40 Output Configurations ..............................................142 RC_IDLE ............................................................41 Output Relationships (Active-High) ..........................143 SEC_IDLE ..........................................................40 Output Relationships (Active-Low) ..........................143 Run Modes .................................................................36 Programmable Dead-Band Delay ............................148 PRI_RUN ...........................................................36 Setup for PWM Operation ........................................151 RC_RUN ............................................................37 Start-up Considerations ...........................................150 SEC_RUN ..........................................................36 Q Selecting ....................................................................35 Sleep Mode ................................................................39 Q Clock ....................................................................137, 142 Summary (table) ........................................................35 R Power-on Reset (POR) ......................................................45 Power-up Timer (PWRT) ...........................................47 RAM. See Data Memory. Time-out Sequence ....................................................47 RBIF Bit ...........................................................................100 Power-up Delays ................................................................33 RC Oscillator ......................................................................27 Power-up Timer (PWRT) ....................................................33 RCIO Oscillator Mode ................................................27 Prescaler RC_IDLE Mode ..................................................................41 RC_RUN Mode ..................................................................37 DS39636D-page 370 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X RCALL .............................................................................289 Power-up Timer (PWRT) .........................................239 RCON Register RETFIE ............................................................................290 Bit Status During Initialization ....................................50 RETLW ............................................................................290 Reader Response ............................................................376 RETURN ..........................................................................291 Register File .......................................................................65 Return Address Stack ........................................................56 Registers Return Stack Pointer (STKPTR) ........................................57 ADCON0 (A/D Control 0) .........................................213 Revision History ...............................................................361 ADCON1 (A/D Control 1) .........................................214 RLCF ...............................................................................291 ADCON2 (A/D Control 2) .........................................215 RLNCF .............................................................................292 BAUDCON (Baud Rate Control) ..............................196 RRCF ...............................................................................292 CCP1CON (Enhanced Capture/Compare/PWM RRNCF ............................................................................293 Control 1) .........................................................139 S CCPxCON (Standard Capture/Compare/PWM Control) ..........................................................................131 SCK .................................................................................153 CMCON (Comparator Control) ................................223 SDI ...................................................................................153 CONFIG1H (Configuration 1 High) ..........................240 SDO .................................................................................153 CONFIG2H (Configuration 2 High) ..........................242 SEC_IDLE Mode ...............................................................40 CONFIG2L (Configuration 2 Low) ............................241 SEC_RUN Mode ................................................................36 CONFIG3H (Configuration 3 High) ..........................243 Serial Clock, SCK ............................................................153 CONFIG4L (Configuration 4 Low) ............................243 Serial Data In (SDI) ..........................................................153 CONFIG5H (Configuration 5 High) ..........................244 Serial Data Out (SDO) .....................................................153 CONFIG5L (Configuration 5 Low) ............................244 Serial Peripheral Interface. See SPI Mode. CONFIG6H (Configuration 6 High) ..........................245 SETF ...............................................................................293 CONFIG6L (Configuration 6 Low) ............................245 Single-Supply ICSP Programming. CONFIG7H (Configuration 7 High) ..........................246 Slave Select (SS) .............................................................153 CONFIG7L (Configuration 7 Low) ............................246 SLEEP .............................................................................294 CVRCON (Comparator Voltage Reference Control) 229 Sleep Device ID Register 1 ................................................247 OSC1 and OSC2 Pin States ......................................33 Device ID Register 2 ................................................247 Software Simulator (MPLAB SIM) ...................................311 ECCP1AS (ECCP Auto-Shutdown Control) .............149 Special Event Trigger. See Compare (ECCP Mode). HLVDCON (HLVD Control) ......................................233 Special Event Trigger. See Compare (ECCP Module). INTCON (Interrupt Control) ........................................85 Special Features of the CPU ...........................................239 INTCON2 (Interrupt Control 2) ...................................86 Special Function Registers ................................................66 INTCON3 (Interrupt Control 3) ...................................87 Map ............................................................................66 IPR1 (Peripheral Interrupt Priority 1) ..........................92 SPI Mode (MSSP) IPR2 (Peripheral Interrupt Priority 2) ..........................93 Associated Registers ...............................................161 OSCCON (Oscillator Control) ....................................32 Bus Mode Compatibility ...........................................161 OSCTUNE (Oscillator Tuning) ...................................29 Effects of a Reset ....................................................161 PIE1 (Peripheral Interrupt Enable 1) ..........................90 Enabling SPI I/O ......................................................157 PIE2 (Peripheral Interrupt Enable 2) ..........................91 Master Mode ............................................................158 PIR1 (Peripheral Interrupt Request (Flag) 1) .............88 Master/Slave Connection ........................................157 PIR2 (Peripheral Interrupt Request (Flag) 2) .............89 Operation .................................................................156 PWM1CON (PWM Configuration) ............................148 Operation in Power Managed Modes ......................161 RCON (Reset Control) .........................................44, 94 Serial Clock .............................................................153 RCSTA (Receive Status and Control) ......................195 Serial Data In ...........................................................153 SSPCON1 (MSSP Control 1, I2C Mode) .................164 Serial Data Out ........................................................153 SSPCON1 (MSSP Control 1, SPI Mode) .................155 Slave Mode ..............................................................159 SSPCON2 (MSSP Control 2, I2C Mode) .................165 Slave Select .............................................................153 SSPSTAT (MSSP Status, I2C Mode) .......................163 Slave Select Synchronization ..................................159 SSPSTAT (MSSP Status, SPI Mode) ......................154 SPI Clock .................................................................158 Status .........................................................................70 Typical Connection ..................................................157 STKPTR (Stack Pointer) ............................................57 SS ....................................................................................153 T0CON (Timer0 Control) ..........................................115 SSPOV ............................................................................183 T1CON (Timer1 Control) ..........................................119 SSPOV Status Flag .........................................................183 T2CON (Timer 2 Control) .........................................125 SSPSTAT Register T3CON (Timer3 Control) ..........................................127 R/W Bit ............................................................166, 167 TRISE (PORTE/PSP Control) ..................................110 Stack Full/Underflow Resets ..............................................58 TXSTA (Transmit Status and Control) .....................194 SUBFSR ..........................................................................305 WDTCON (Watchdog Timer Control) ......................249 SUBFWB .........................................................................294 RESET .............................................................................289 SUBLW ............................................................................295 Reset State of Registers ....................................................50 SUBULNK ........................................................................305 Resets ........................................................................43, 239 SUBWF ............................................................................295 Brown-out Reset (BOR) ...........................................239 SUBWFB .........................................................................296 Oscillator Start-up Timer (OST) ...............................239 SWAPF ............................................................................296 Power-on Reset (POR) ............................................239 © 2009 Microchip Technology Inc. DS39636D-page 371

PIC18F2X1X/4X1X T Bus Collision During a Stop Condition (Case 2) ......191 Bus Collision for Transmit and Acknowledge ..........187 Table Pointer Operations (table) ........................................78 Capture/Compare/PWM (CCP) ...............................338 Table Reads/Table Writes ..................................................58 CLKO and I/O ..........................................................335 TBLRD .............................................................................297 Clock Synchronization .............................................173 TBLWT .............................................................................298 Clock/Instruction Cycle ..............................................59 Time-out in Various Situations (table) ................................47 Example SPI Master Mode (CKE = 0) .....................340 Timer0 ..............................................................................115 Example SPI Master Mode (CKE = 1) .....................341 16-Bit Mode Timer Reads and Writes ......................116 Example SPI Slave Mode (CKE = 0) .......................342 Associated Registers ...............................................117 Example SPI Slave Mode (CKE = 1) .......................343 Clock Source Edge Select (T0SE Bit) ......................116 External Clock (All Modes except PLL) ...................333 Clock Source Select (T0CS Bit) ...............................116 Fail-Safe Clock Monitor ...........................................252 Operation .................................................................116 First Start Bit Timing ................................................181 Overflow Interrupt ....................................................117 Full-Bridge PWM Output ..........................................145 Prescaler ..................................................................117 Half-Bridge PWM Output .........................................144 Prescaler. See Prescaler, Timer0. High/Low-Voltage Detect Characteristics ................330 Timer1 ..............................................................................119 High-Voltage Detect (VDIRMAG = 1) ......................236 16-Bit Read/Write Mode ...........................................121 I2C Bus Data ............................................................344 Associated Registers ...............................................123 I2C Bus Start/Stop Bits ............................................344 Interrupt ....................................................................122 I2C Master Mode (7 or 10-Bit Transmission) ...........184 Operation .................................................................120 I2C Master Mode (7-Bit Reception) ..........................185 Oscillator ..........................................................119, 121 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........170 Oscillator Layout Considerations .............................122 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........175 Overflow Interrupt ....................................................119 I2C Slave Mode (10-Bit Transmission) ....................171 Resetting, Using the CCP Special Event Trigger .....122 I2C Slave Mode (7-Bit Reception, SEN = 0) ............168 Special Event Trigger (ECCP) .................................140 I2C Slave Mode (7-Bit Reception, SEN = 1) ............174 TMR1H Register ......................................................119 I2C Slave Mode (7-Bit Transmission) ......................169 TMR1L Register .......................................................119 I2C Slave Mode General Call Address Sequence (7 or Use as a Real-Time Clock .......................................122 10-Bit Address Mode) ......................................176 Timer2 ..............................................................................125 I2C Stop Condition Receive or Transmit Mode ........186 Associated Registers ...............................................126 Low-Voltage Detect (VDIRMAG = 0) .......................235 Interrupt ....................................................................126 Master SSP I2C Bus Data ........................................346 Operation .................................................................125 Master SSP I2C Bus Start/Stop Bits ........................346 Output ......................................................................126 Parallel Slave Port (PIC18F4410/4510/4515/4610) .339 PR2 Register ....................................................136, 141 Parallel Slave Port (PSP) Read ...............................113 TMR2 to PR2 Match Interrupt ..........................136, 141 Parallel Slave Port (PSP) Write ...............................113 Timer3 ..............................................................................127 PWM Auto-Shutdown (PRSEN = 0, 16-Bit Read/Write Mode ...........................................129 Auto-Restart Disabled) ....................................150 Associated Registers ...............................................129 PWM Auto-Shutdown (PRSEN = 1, Operation .................................................................128 Auto-Restart Enabled) .....................................150 Oscillator ..........................................................127, 129 PWM Direction Change ...........................................147 Overflow Interrupt ............................................127, 129 PWM Direction Change at Near 100% Duty Cycle ..147 Special Event Trigger (CCP) ....................................129 PWM Output ............................................................136 TMR3H Register ......................................................127 Repeat Start Condition ............................................182 TMR3L Register .......................................................127 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer Timing Diagrams (OST), Power-up Timer (PWRT) .....................336 A/D Conversion ........................................................350 Send Break Character Sequence ............................207 Acknowledge Sequence ..........................................186 Slave Synchronization .............................................159 Asynchronous Reception .........................................205 Asynchronous Transmission ....................................203 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................................................49 Asynchronous Transmission (Back to Back) ...........203 SPI Mode (Master Mode) .........................................158 Automatic Baud Rate Calculation ............................201 SPI Mode (Slave Mode, CKE = 0) ...........................160 Auto-Wake-up Bit (WUE) During Normal Operation 206 SPI Mode (Slave Mode, CKE = 1) ...........................160 Auto-Wake-up Bit (WUE) During Sleep ...................206 Synchronous Reception (Master Mode, SREN) ......210 Baud Rate Generator with Clock Arbitration ............180 Synchronous Transmission .....................................208 BRG Overflow Sequence .........................................201 Synchronous Transmission (Through TXEN) ..........209 BRG Reset Due to SDA Arbitration During Start Condi- Time-out Sequence on POR w/PLL Enabled (MCLR Tied tion ...................................................................189 Brown-out Reset (BOR) ...........................................336 to VDD) ...............................................................49 Time-out Sequence on Power-up (MCLR Not Tied Bus Collision During a Repeated Start Condition (Case 1) ......................................................................190 to VDD, Case 1) .................................................48 Time-out Sequence on Power-up (MCLR Not Tied Bus Collision During a Repeated Start Condition (Case 2) ......................................................................190 to VDD, Case 2) .................................................48 Bus Collision During a Start Condition (SCL = 0) ....189 Time-out Sequence on Power-up (MCLR Tied to VDD, Bus Collision During a Start Condition (SDA only) ..188 VDD Rise < TPWRT) ............................................48 Timer0 and Timer1 External Clock ..........................337 Bus Collision During a Stop Condition (Case 1) ......191 DS39636D-page 372 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X Transition for Entry to Idle Mode ................................40 Transition for Entry to SEC_RUN Mode ....................37 Transition for Entry to Sleep Mode ............................39 Transition for Two-Speed Start-up (INTOSC to HSPLL) 250 Transition for Wake from Idle to Run Mode ...............40 Transition for Wake from Sleep (HSPLL) ...................39 Transition from RC_RUN Mode to PRI_RUN Mode ..38 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) .............................................................37 Transition to RC_RUN Mode .....................................38 USART Synchronous Receive (Master/Slave) ........348 USART Synchronous Transmission (Master/Slave) 348 Timing Diagrams and Specifications ................................333 A/D Conversion Requirements ................................350 Capture/Compare/PWM (CCP) Requirements ........338 CLKO and I/O Requirements ...................................335 Example SPI Mode Requirements (Master Mode, CKE = 0) ..........................................................340 Example SPI Mode Requirements (Master Mode, CKE = 1) ..........................................................341 Example SPI Mode Requirements (Slave Mode, CKE = 0) ..........................................................342 Example SPI Mode Requirements (Slave Mode, CKE = 1) ..........................................................343 External Clock Requirements ..................................333 I2C Bus Data Requirements (Slave Mode) ..............345 Master SSP I2C Bus Data Requirements ................347 Master SSP I2C Bus Start/Stop Bits Requirements .346 Parallel Slave Port Requirements (PIC18F4410/4510/ 4515/4610) .......................................................339 PLL Clock .................................................................334 Reset, Watchdog Timer, Oscillator Start-up Timer, Pow- er-up Timer and Brown-out Reset Requirements .. 336 Timer0 and Timer1 External Clock Requirements ...337 USART Synchronous Receive Requirements .........348 USART Synchronous Transmission Requirements .348 Top-of-Stack Access ..........................................................56 TRISE Register PSPMODE Bit ..........................................................106 TSTFSZ ...........................................................................299 Two-Speed Start-up .................................................239, 250 Two-Word Instructions Example Cases ..........................................................60 TXSTA Register BRGH Bit .................................................................197 V Voltage Reference Specifications ....................................329 W Watchdog Timer (WDT) ...........................................239, 248 Associated Registers ...............................................249 Control Register .......................................................248 During Oscillator Failure ..........................................251 Programming Considerations ..................................248 WCOL ......................................................181, 182, 183, 186 WCOL Status Flag ...................................181, 182, 183, 186 WWW Address .................................................................375 WWW, On-Line Support ......................................................8 X XORLW ............................................................................299 XORWF ............................................................................300 © 2009 Microchip Technology Inc. DS39636D-page 373

PIC18F2X1X/4X1X DS39636D-page 374 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39636D-page 375

PIC18F2X1X/4X1X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2X1X/4X1X Literature Number: DS39636D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39636D-page 376 © 2009 Microchip Technology Inc.

PIC18F2X1X/4X1X PIC18F2X1X/4X1X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF4510-I/P 301 = Industrial temp., PDIP Range package, Extended VDD limits, QTP pattern #301. b) PIC18LF2410-I/SO = Industrial temp., SOIC package, Extended VDD limits. Device PIC18F2410/2415/2510/2515/2610(1), c) PIC18F4410-I/P = Industrial temp., PDIP PPIICC1188FF42441100//42441155//24551100//24551155//42661100T(1()2, ), package, normal VDD limits. PIC18F4410/4415/4510/4515/4610 T(2); VDD range 4.2V to 5.5V PIC18LF2410/2510/2515/2610(1), PIC18LF4410/4510/4515/4610(1), PIC18LF2410/2510/2515/2610T(2), PIC18LF4410/4510/4515/4610T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Note1: F = Standard Voltage Range LF = Wide Voltage Range 2: T = in tape and reel TQFP Package PT = TQFP (Thin Quad Flatpack) packages only. SO = SOIC SP = Skinny Plastic DIP P = PDIP ML = QFN Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39636D-page 377

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F4515-E/P PIC18F2610T-I/SO PIC18F2410T-I/ML PIC18F2410T-I/SO PIC18F4510-E/ML PIC18F4410-E/ML PIC18F4610-E/ML PIC18F2510T-I/SO PIC18F2515T-I/SO PIC18LF4510-I/P PIC18LF4610-I/P PIC18F4515-E/PT PIC18F4410T-I/ML PIC18LF2515T-I/SO PIC18LF2510T-I/SO PIC18F2515-I/SO PIC18LF2410T-I/SO PIC18F2515- I/SP PIC18LF4510-I/PT PIC18F4410-I/P PIC18F4510-I/P PIC18F4610-I/P PIC18F4515-I/P PIC18F4610-E/P PIC18F4410-E/P PIC18F4510-E/P PIC18F2515-E/SO PIC18F4510T-I/ML PIC18F2515-E/SP PIC18F4515T-I/PT PIC18F4515T-I/ML PIC18F4510T-I/PT PIC18F2610-E/SP PIC18F2410-E/ML PIC18F2610-E/SO PIC18LF4410-I/ML PIC18F2510-E/ML PIC18LF4610-I/ML PIC18F2410-E/SP PIC18F2410-E/SO PIC18LF4510-I/ML PIC18LF2510T- I/ML PIC18LF2410T-I/ML PIC18LF4610T-I/ML PIC18LF2515-I/SO PIC18LF4610T-I/PT PIC18F4610-I/ML PIC18F4410-I/PT PIC18F4610-I/PT PIC18F4410-I/ML PIC18LF2515-I/SP PIC18F4510-I/ML PIC18F4510-I/PT PIC18LF4515-I/P PIC18LF4515-I/ML PIC18F2410-I/ML PIC18F2510-I/SO PIC18F2510-I/ML PIC18F2610-I/SO PIC18F2610-I/SP PIC18F2410-I/SP PIC18F2410-I/SO PIC18LF4515-I/PT PIC18F2510-I/SP PIC18LF4410T-I/ML PIC18LF4410T-I/PT PIC18LF4410-I/P PIC18F4515-I/PT PIC18LF2610T-I/SO PIC18F4610T-I/PT PIC18F4610T-I/ML PIC18LF2510-I/ML PIC18F4510-E/PT PIC18LF2410-I/ML PIC18F4410-E/PT PIC18LF2610-I/SP PIC18LF2510- I/SO PIC18LF2410-I/SP PIC18F4610-E/PT PIC18LF2510-I/SP PIC18LF2610-I/SO PIC18LF2410-I/SO PIC18F2510T-I/ML PIC18LF4515T-I/PT PIC18LF4510T-I/PT PIC18LF4510T-I/ML PIC18LF4515T-I/ML PIC18F4515- I/ML PIC18F4515-E/ML PIC18F4410T-I/PT PIC18F2510-E/SP PIC18F2510-E/SO PIC18LF4410-I/PT PIC18LF4610-I/PT