PIC16F872 Data Sheet 28-Pin, 8-Bit CMOS Flash Microcontroller with 10-Bit A/D © 2006 Microchip Technology Inc. DS30221C

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PROMATE, PowerSmart, rfPIC and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR registered trademarks of Microchip Technology Incorporated WARRANTIES OF ANY KIND WHETHER EXPRESS OR in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, hold harmless Microchip from any and all damages, claims, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active suits, or expenses resulting from such use. No licenses are Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS30221C-page ii © 2006 Microchip Technology Inc.

PIC16F872 28-Pin, 8-Bit CMOS FLASH Microcontroller with 10-bit A/D High Performance RISC CPU: Pin Diagram (cid:129) Only 35 single word instructions to learn DIP, SOIC, SSOP (cid:129) All single cycle instructions except for program branches, which are two-cycle MCLR/VPP 1 28 RB7/PGD (cid:129) Operating speed: DC - 20 MHz clock input RA0/AN0 2 27 RB6/PGC DC - 200 ns instruction cycle RA1/AN1 3 26 RB5 (cid:129) 2K x 14 words of FLASH Program Memory RA2/AN2/VREF- 4 25 RB4 RA3/AN3/VREF+ 5 24 RB3/PGM (cid:129) 128 bytes of Data Memory (RAM) RA4/T0CKI 6 72 23 RB2 (cid:129) 64 bytes of EEPROM Data Memory RA5/AN4/SS 7 F8 22 RB1 (cid:129) Pinout compatible to the PIC16C72A OSC1/CLVKSINS 89 PIC16 2201 RVDBD0/INT (cid:129) Interrupt capability (up to 10 sources) OSC2/CLKOUT 10 19 VSS (cid:129) Eight level deep hardware stack RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK (cid:129) Direct, Indirect and Relative Addressing modes RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA Peripheral Features: (cid:129) High Sink/Source Current: 25mA (cid:129) Timer0: 8-bit timer/counter with 8-bit prescaler Special Microcontroller Features: (cid:129) Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external (cid:129) Power-on Reset (POR), Power-up Timer (PWRT) crystal/clock and Oscillator Start-up Timer (OST) (cid:129) Timer2: 8-bit timer/counter with 8-bit period (cid:129) Watchdog Timer (WDT) with its own on-chip RC register, prescaler and postscaler oscillator for reliable operation (cid:129) One Capture, Compare, PWM module (cid:129) Programmable code protection - Capture is 16-bit, max. resolution is 12.5 ns (cid:129) Power saving SLEEP mode - Compare is 16-bit, max. resolution is 200 ns (cid:129) Selectable oscillator options - PWM max. resolution is 10-bit (cid:129) In-Circuit Serial Programming™ (ICSP™) via two (cid:129) 10-bit, 5-channel Analog-to-Digital converter (A/D) pins (cid:129) Synchronous Serial Port (SSP) with SPI™ (Master (cid:129) Single 5V In-Circuit Serial Programming capability mode) and I2C™ (Master/Slave) (cid:129) In-Circuit Debugging via two pins (cid:129) Brown-out detection circuitry for (cid:129) Processor read/write access to program memory Brown-out Reset (BOR) CMOS Technology: (cid:129) Low power, high speed CMOS FLASH/EEPROM technology (cid:129) Wide operating voltage range: 2.0V to 5.5V (cid:129) Fully static design (cid:129) Commercial, Industrial and Extended temperature ranges (cid:129) Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 20 μA typical @ 3V, 32 kHz - < 1 μA typical standby current © 2006 Microchip Technology Inc. DS30221C-page 1

PIC16F872 Table of Contents 1.0 Device Overview......................................................................................................................................................................... 3 2.0 Memory Organization.................................................................................................................................................................. 7 3.0 Data EEPROM and FLASH Program Memory......................................................................................................................... 23 4.0 I/O Ports.................................................................................................................................................................................... 29 5.0 Timer0 Module.......................................................................................................................................................................... 35 6.0 Timer1 Module.......................................................................................................................................................................... 39 7.0 Timer2 Module.......................................................................................................................................................................... 43 8.0 Capture/Compare/PWM Module............................................................................................................................................... 45 9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 51 10.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................ 79 11.0 Special Features of the CPU.................................................................................................................................................... 87 12.0 Instruction Set Summary......................................................................................................................................................... 103 13.0 Development Support............................................................................................................................................................. 111 14.0 Electrical Characteristics......................................................................................................................................................... 117 15.0 DC and AC Characteristics Graphs and Tables..................................................................................................................... 139 16.0 Packaging Information............................................................................................................................................................ 151 Appendix A:Revision History ........................................................................................................................................................... 155 Appendix B:Conversion Considerations........................................................................................................................................... 155 Index................................................................................................................................................................................................. 157 On-Line Support................................................................................................................................................................................ 163 Reader Response............................................................................................................................................................................. 164 PIC16F872 Product Identification System........................................................................................................................................ 165 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:129) Microchip’s Worldwide Web site; http://www.microchip.com (cid:129) Your local Microchip sales office (see last page) (cid:129) The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30221C-page 2 © 2006 Microchip Technology Inc.

PIC16F872 1.0 DEVICE OVERVIEW document to this data sheet, and is highly recom- mended reading for a better understanding of the This document contains device specific information device architecture and operation of the peripheral about the PIC16F872 microcontroller. Additional infor- modules. mation may be found in the PICmicro™ Mid-Range The block diagram of the PIC16F872 architecture is Reference Manual (DS33023), which may be obtained shown in Figure1-1. A pinout description is provided in from your local Microchip Sales Representative or Table1-2. downloaded from the Microchip website. The Refer- ence Manual should be considered a complementary TABLE 1-1: KEY FEATURES OF THE PIC16F872 Operating Frequency DC - 20 MHz RESETS (and Delays) POR, BOR (PWRT, OST) FLASH Program Memory (14-bit words) 2K Data Memory (bytes) 128 EEPROM Data Memory (bytes) 64 Interrupts 10 I/O Ports Ports A, B, C Timers 3 Capture/Compare/PWM module 1 Serial Communications MSSP 10-bit Analog-to-Digital Module 5 input channels Instruction Set 35 Instructions Packaging 28-lead PDIP 28-lead SOIC 28-lead SSOP © 2006 Microchip Technology Inc. DS30221C-page 3

PIC16F872 FIGURE 1-1: PIC16F872 BLOCK DIAGRAM 13 Data Bus 8 PORTA Program Counter RA0/AN0 FLASH RA1/AN1 Program RA2/AN2/VREF- Memory 8 Level Stack RAM RA3/AN3/VREF+ (13-bit) File RA4/T0CKI Registers RA5/AN4/SS Program 14 Bus RAM Addr (1) 9 Addr MUX PORTB Instruction reg RB0/INT Direct Addr 7 Indirect RB1 8 Addr RB2 RB3/PGM FSR reg RB4 RB5 STATUS reg RB6/PGC 8 RB7/PGD Power-up 3 MUX Timer PORTC RC0/T1OSO/T1CKI Instruction Oscillator RC1/T1OSI/CCP2 Decode & Start-up Timer ALU RC2/CCP1 Control Power-on RC3/SCK/SCL Reset 8 RC4/SDI/SDA Timing Watchdog RC5/SDO Generation Timer W reg RC6 OSC1/CLKIN Brown-out RC7 OSC2/CLKOUT Reset In-Circuit Debugger Low Voltage Programming MCLR VDD, VSS Timer0 Timer1 Timer2 Synchronous Data EEPROM CCP Serial Port 10-bit A/D Note 1: Higher order bits are from the STATUS register. DS30221C-page 4 © 2006 Microchip Technology Inc.

PIC16F872 TABLE 1-2: PIC16F872 PINOUT DESCRIPTION I/O/P Buffer Pin Name Pin# Description Type Type OSC1/CLKI 9 I ST/CMOS Oscillator crystal or external clock input. OSC1 Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. CLKI External clock source input. Always associated with pin function OSC1 (see OSC2/CLKO pin). OSC2/CLKO 10 O — Oscillator crystal or clock output. OSC2 Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. MCLR/VPP 1 I/P ST Master Clear (input) or programming voltage (output). MCLR Master Clear (Reset) input. This pin is an active low RESET to the device. VPP Programming voltage input. PORTA is a bi-directional I/O port. RA0/AN0 2 I/O TTL RA0 Digital I/O. AN0 Analog input 0. RA1/AN1 3 I/O TTL RA1 Digital I/O. AN1 Analog input 1. RA2/AN2/VREF- 4 I/O TTL RA2 Digital I/O. AN2 Analog input 2. VREF- Negative analog reference voltage. RA3/AN3/VREF+ 5 I/O TTL RA3 Digital I/O. AN3 Analog input 3. VREF+ Positive analog reference voltage. RA4/T0CKI 6 I/O ST RA4 Digital I/O; open drain when configured as output. T0CKI Timer0 clock input. RA5/SS/AN4 7 I/O TTL RA5 Digital I/O. SS Slave Select for the Synchronous Serial Port. AN4 Analog input 4. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. © 2006 Microchip Technology Inc. DS30221C-page 5

PIC16F872 TABLE 1-2: PIC16F872 PINOUT DESCRIPTION (CONTINUED) I/O/P Buffer Pin Name Pin# Description Type Type PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 I/O TTL/ST(1) RB0 Digital I/O. INT External interrupt pin. RB1 22 I/O TTL Digital I/O. RB2 23 I/O TTL Digital I/O. RB3/PGM 24 I/O TTL RB3 Digital I/O. PGM Low voltage ICSP programming enable pin. RB4 25 I/O TTL Digital I/O. RB5 26 I/O TTL Digital I/O. RB6/PGC 27 I/O TTL/ST(2) RB6 Digital I/O. PGC In-Circuit Debugger and ICSP programming clock. RB7/PGD 28 I/O TTL/ST(2) RB7 Digital I/O. PGD In-Circuit Debugger and ICSP programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 I/O ST RC0 Digital I/O. T1OSO Timer1 oscillator output. T1CKI Timer1 clock input. RC1/T1OSI 12 I/O ST RC1 Digital I/O. T1OSI Timer1 oscillator input. RC2/CCP1 13 I/O ST RC2 Digital I/O. CCP1 Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 14 I/O ST RC3 Digital I/O. SCK Synchronous serial clock input/output for SPI mode. SCL Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 15 I/O ST RC4 Digital I/O. SDI SPI Data In pin (SPI mode). SDA SPI Data I/O pin (I2C mode). RC5/SDO 16 I/O ST RC5 Digital I/O. SDO SPI Data Out pin (SPI mode). RC6 17 I/O ST Digital I/O. RC7 18 I/O ST Digital I/O. VSS 8, 19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. DS30221C-page 6 © 2006 Microchip Technology Inc.

PIC16F872 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization There are three memory blocks in the PIC16F872. The The data memory is partitioned into multiple banks Program Memory and Data Memory have separate which contain the General Purpose Registers and the buses so that concurrent access can occur. Data mem- Special Function Registers. Bits RP1 (STATUS<6>) ory is covered in this section; the EEPROM data mem- and RP0 (STATUS<5>) are the bank select bits. ory and FLASH program memory blocks are detailed in Section3.0. RP1:RP0 Bank Additional information on device memory may be found 00 0 in the PICmicro™ Mid-Range Reference Manual 01 1 (DS33023). 10 2 2.1 Program Memory Organization 11 3 The PIC16F872 has a 13-bit program counter capable Each bank extends up to 7Fh (128 bytes). The lower of addressing an 8K word x 14 bit program memory locations of each bank are reserved for the Special space. The PIC16F872 device actually has 2K words of Function Registers. Above the Special Function Regis- FLASH program memory. Accessing a location above ters are General Purpose Registers, implemented as the physically implemented address will cause a wrap- static RAM. All implemented banks contain Special around. Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in The RESET vector is at 0000h and the interrupt vector another bank for code reduction and quicker access. is at 0004h. Note: EEPROM Data Memory description can be FIGURE 2-1: PIC16F872 PROGRAM found in Section 4.0 of this data sheet. MEMORY MAP AND 2.2.1 GENERAL PURPOSE REGISTER STACK FILE PC<12:0> The register file can be accessed either directly, or indi- rectly through the File Select Register (FSR). CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-Chip Page 0 Program Memory 07FFh 1FFFh © 2006 Microchip Technology Inc. DS30221C-page 7

PIC16F872 FIGURE 2-2: PIC16F872 REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(1) 18Eh TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(1) 18Fh T1CON 10h 90h 110h 190h TMR2 11h SSPCON2 91h T2CON 12h PR2 92h SSPBUF 13h SSPADD 93h SSPCON 14h SSPSTAT 94h CCPR1L 15h 95h CCPR1H 16h 96h CCP1CON 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ADCON1 9Fh 120h 1A0h 20h General A0h Purpose accesses accesses Register 20h-7Fh A0h - BFh General Purpose 32 Bytes BFh 1BFh Register C0h 1C0h 96 Bytes 16Fh 1EFh EFh accesses F0h accesses 170h accesses 1F0h 70h-7Fh 70h-7Fh 70h-7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are reserved; maintain these registers clear. DS30221C-page 8 © 2006 Microchip Technology Inc.

PIC16F872 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in the implemented as static RAM. A list of these registers is peripheral feature section. given in Table2-1. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on BOR page: Bank 0 00h(2) INDF Addressing this location uses contents of FSR to address data memory 0000 0000 21, 93 (not a physical register) 01h TMR0 Timer0 Module Register xxxx xxxx 35, 93 02h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93 03h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 12, 93 04h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 29, 93 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31, 93 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 33, 93 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93 0Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93 0Ch PIR1 (3) ADIF (3) (3) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 16, 93 0Dh PIR2 — (3) — EEIF BCLIF — — (3) -r-0 0--r 18, 93 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 40, 94 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 40, 94 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 39, 94 11h TMR2 Timer2 Module Register 0000 0000 43, 94 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 43, 94 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 55, 94 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 53, 94 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx 45, 94 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx 45, 94 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 45, 94 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH A/D Result Register High Byte xxxx xxxx 84, 94 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/ — ADON 0000 00-0 79, 94 DONE Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear. © 2006 Microchip Technology Inc. DS30221C-page 9

PIC16F872 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on BOR page: Bank 1 80h(2) INDF Addressing this location uses contents of FSR to address data memory 0000 0000 21, 93 (not a physical register) 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13, 94 82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93 83h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 12, 93 84h(2) FSR Indirect data memory address pointer xxxx xxxx 21, 93 85h TRISA — — PORTA Data Direction Register --11 1111 29, 94 86h TRISB PORTB Data Direction Register 1111 1111 31, 94 87h TRISC PORTC Data Direction Register 1111 1111 33, 94 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93 8Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93 8Ch PIE1 (3) ADIE (3) (3) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 15, 94 8Dh PIE2 — (3) — EEIE BCLIE — — (3) -r-0 0--r 17, 94 8Eh PCON — — — — — — POR BOR ---- --qq 19, 94 8Fh — Unimplemented — — 90h — Unimplemented — — 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 54, 94 92h PR2 Timer2 Period Register 1111 1111 43, 94 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 58, 94 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 52, 94 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 95h — Unimplemented — — 95h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 84, 94 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 80, 94 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear. DS30221C-page 10 © 2006 Microchip Technology Inc.

PIC16F872 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on BOR page: Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory 0000 0000 21, 93 (not a physical register) 101h TMR0 Timer0 Module Register xxxx xxxx 35, 93 102h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93 103h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 12, 93 104h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31, 93 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93 10Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93 10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 23, 94 10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 23, 94 10Eh EEDATH — — EEPROM Data Register High Byte xxxx xxxx 23, 94 10Fh EEADRH — — — EEPROM Address Register High Byte xxxx xxxx 23, 94 Bank 3 180h(2) INDF Addressing this location uses contents of FSR to address data memory 0000 0000 21, 93 (not a physical register) 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 13, 94 182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 20, 93 183h(2) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 12, 93 184h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 21, 93 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 31, 94 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93 18Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 14, 93 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 24, 94 18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 23, 94 18Eh — Reserved; maintain clear 0000 0000 — 18Fh — Reserved; maintain clear 0000 0000 — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: These bits are reserved; always maintain these bits clear. © 2006 Microchip Technology Inc. DS30221C-page 11

PIC16F872 2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register contains the arithmetic status of as 000u u1uu (where u = unchanged). the ALU, the RESET status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, as with any other register. If the STATUS affect the Z, C or DC bits from the STATUS register. For register is the destination for an instruction that affects other instructions not affecting any status bits, see the the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary." disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not Note: The C and DC bits operate as a borrow writable, therefore, the result of an instruction with the and digit borrow bit, respectively, in sub- STATUS register as destination may be different than traction. See the SUBLW and SUBWF intended. instructions for examples. REGISTER 2-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6:5 RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 12 © 2006 Microchip Technology Inc.

PIC16F872 2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for The OPTION_REG Register is a readable and writable the TMR0 register, assign the prescaler to register, which contains various control bits to configure the Watchdog Timer. the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper- ation of the device © 2006 Microchip Technology Inc. DS30221C-page 13

PIC16F872 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON Register is a readable and writable regis- condition occurs, regardless of the state of ter, which contains various enable and flag bits for the its corresponding enable bit or the global TMR0 register overflow, RB Port change and External enable bit, GIE (INTCON<7>). User soft- RB0/INT pin interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 14 © 2006 Microchip Technology Inc.

PIC16F872 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to The PIE1 register contains the individual enable bits for enable any peripheral interrupt. the peripheral interrupts. REGISTER 2-4: PIE1 REGISTER (ADDRESS: 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 reserved ADIE reserved reserved SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 Reserved: Always maintain these bits clear bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5-4 Reserved: Always maintain these bits clear bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 15

PIC16F872 2.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt The PIR1 register contains the individual flag bits for condition occurs, regardless of the state of the peripheral interrupts. its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1 REGISTER (ADDRESS: 0Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 reserved ADIF reserved reserved SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 Reserved: Always maintain these bits clear bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete bit 5-4 Reserved: Always maintain these bits clear bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: (cid:129) SPI - A transmission/reception has taken place (cid:129) I2C Slave - A transmission/reception has taken place (cid:129) I2C Master - A transmission/reception has taken place - The initiated START condition was completed by the SSP module - The initiated STOP condition was completed by the SSP module - The initiated Restart condition was completed by the SSP module - The initiated Acknowledge condition was completed by the SSP module - A START condition occurred while the SSP module was idle (multi-master system) - A STOP condition occurred while the SSP module was idle (multi-master system) 0 = No SSP interrupt condition has occurred bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 16 © 2006 Microchip Technology Inc.

PIC16F872 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS: 8Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — reserved — EEIE BCLIE — — reserved bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 Reserved: Always maintain this bit clear bit 5 Unimplemented: Read as '0' bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt bit 2-1 Unimplemented: Read as '0' bit 0 Reserved: Always maintain this bit clear Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 17

PIC16F872 2.2.2.7 PIR2 Register Note: Interrupt flag bits are set when an interrupt The PIR2 register contains the flag bits for the CCP2 condition occurs, regardless of the state of interrupt, the SSP bus collision interrupt and the its corresponding enable bit or the global EEPROM write operation interrupt. enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- . rupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2 REGISTER (ADDRESS: 0Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — reserved — EEIF BCLIF — — reserved bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 Reserved: Always maintain this bit clear bit 5 Unimplemented: Read as '0' bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP, when configured for I2C Master mode 0 = No bus collision has occurred bit 2-1 Unimplemented: Read as '0' bit 0 Reserved: Always maintain this bit clear Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 18 © 2006 Microchip Technology Inc.

PIC16F872 2.2.2.8 PCON Register Note: BOR is unknown on POR. It must be set by The Power Control (PCON) Register contains flag bits the user and checked on subsequent to allow differentiation between a Power-on Reset RESETS to see if BOR is clear, indicating (POR), a Brown-out Reset (BOR), a Watchdog Reset a brown-out has occurred. The BOR status (WDT) and an external MCLR Reset. bit is a don’t care and is not predictable if the brown-out circuit is disabled (by clear- ing the BODEN bit in the Configuration Word). REGISTER 2-8: PCON REGISTER (ADDRESS: 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as '0' bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 19

PIC16F872 2.3 PCL and PCLATH 2.3.2 STACK The program counter (PC) is 13-bits wide. The low byte The PIC16FXXX family has an 8-level deep x 13-bit comes from the PCL register, which is a readable and wide hardware stack. The stack space is not part of writable register. The upper bits (PC<12:8>) are not either program or data space and the stack pointer is readable, but are indirectly writable through the not readable or writable. The PC is PUSHed onto the PCLATH register. On any RESET, the upper bits of the stack when a CALL instruction is executed or an inter- PC will be cleared. Figure2-3 shows the two situations rupt causes a branch. The stack is POPed in the event for the loading of the PC. The upper example in the fig- of a RETURN, RETLW or a RETFIE instruction execu- ure shows how the PC is loaded on a write to PCL tion. PCLATH is not affected by a PUSH or POP oper- (PCLATH<4:0> → PCH). The lower example in the fig- ation. ure shows how the PC is loaded during a CALL or GOTO The stack operates as a circular buffer. This means that instruction (PCLATH<4:3> → PCH). after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first FIGURE 2-3: LOADING OF PC IN push. The tenth push overwrites the second push (and DIFFERENT SITUATIONS so on). Note 1: There are no status bits to indicate stack PCH PCL overflow or stack underflow conditions. 12 8 7 0 Instruction with 2: There are no instructions/mnemonics PC PCL as Destination called PUSH or POP. These are actions 5 PCLATH<4:0> 8 ALU that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an inter- PCLATH rupt address. PCH PCL 2.4 Program Memory Paging 12 11 10 8 7 0 PC GOTO,CALL All PIC16FXXX devices are capable of addressing a continuous 8K word block of program memory. The PCLATH<4:3> 11 2 Opcode <10:0> CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program PCLATH memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. Since the PIC16F872 has only 2K 2.3.1 COMPUTED GOTO words of program memory or one page, additional code is not required to ensure that the correct page is A computed GOTO is accomplished by adding an offset selected before a CALL or GOTO instruction is exe- to the program counter (ADDWF PCL). When doing a cuted. The PCLATH<4:3> bits should always be main- table read using a computed GOTO method, care tained as zeros. If a return from a CALL instruction (or should be exercised if the table location crosses a PCL interrupt) is executed, the entire 13-bit PC is popped off memory boundary (each 256 byte block). Refer to the the stack. Therefore, manipulation of the Application Note, “Implementing a Table Read" PCLATH<4:3> bits are not required for the return (AN556). instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH regis- ter for any subsequent subroutine calls or GOTO instructions. DS30221C-page 20 © 2006 Microchip Technology Inc.

PIC16F872 2.5 Indirect Addressing, INDF and A simple program to clear RAM locations 20h-2Fh FSR Registers using indirect addressing is shown in Example2-1. The INDF register is not a physical register. Addressing EXAMPLE 2-1: INDIRECT ADDRESSING the INDF register will cause indirect addressing. MOVLW 0x20 ;initialize pointer Indirect addressing is possible by using the INDF reg- MOVWF FSR ;to RAM ister. Any instruction using the INDF register actually NEXT CLRF INDF ;clear INDF register accesses the register pointed to by the File Select Reg- INCF FSR,F ;inc pointer BTFSS FSR,4 ;all done? ister, FSR. Reading the INDF register itself indirectly GOTO NEXT ;no clear next (FSR = '0'), will read 00h. Writing to the INDF register CONTINUE indirectly results in a no operation (although status bits : ;yes continue may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 From Opcode 0 IRP 7 FSR Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 80h 100h 180h Data Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail, see Figure2-2. © 2006 Microchip Technology Inc. DS30221C-page 21

PIC16F872 NOTES: DS30221C-page 22 © 2006 Microchip Technology Inc.

PIC16F872 3.0 DATA EEPROM AND FLASH The EEPROM Data memory allows byte read and write PROGRAM MEMORY operations without interfering with the normal operation of the microcontroller. When interfacing to EEPROM The Data EEPROM and FLASH Program Memory are Data memory, the EEADR register holds the address to readable and writable during normal operation over the be accessed. Depending on the operation, the EEDATA entire VDD range. These operations take place on a sin- register holds the data to be written or the data read at gle byte for Data EEPROM memory and a single word the address in EEADR. The PIC16F872 has 64 bytes of for Program memory. A write operation causes an EEPROM Data memory and therefore, requires that the erase-then-write operation to take place on the speci- two Most Significant bits of EEADR remain clear. fied byte or word. A bulk erase operation may not be EEPROM Data memory on these devices wraps around issued from user code (which includes removing code to 0 (i.e., 40h in the EEADR maps to 00h). protection). The FLASH Program memory allows non-intrusive Access to program memory allows for checksum calcu- read access, but write operations cause the device to lation. The values written to Program memory do not stop executing instructions until the write completes. need to be valid instructions. Therefore, numbers of up When interfacing to the Program memory, the to 14 bits can be stored in memory for use as calibra- EEADRH:EEADR registers pair forms a two-byte word tion parameters, serial numbers, packed 7-bit ASCII, which holds the 13-bit address of the memory location etc. Executing a program memory location, containing being accessed. The EEDATH:EEDATA register pair data that forms an invalid instruction, results in the exe- holds the 14-bit data for writes or reflects the value of cution of a NOP instruction. program memory after a read operation. Just as in EEPROM Data memory accesses, the value of the The EEPROM Data memory is rated for high erase/ EEADRH:EEADR registers must be within the valid write cycles (specification #D120). The FLASH Pro- range of program memory, depending on the device gram memory is rated much lower (specification (0000h to 07FFh). Addresses outside of this range #D130) because EEPROM Data memory can be used wrap around to 0000h (i.e., 0800h maps to 0000h). to store frequently updated values. An on-chip timer controls the write time and it will vary with voltage and 3.1 EECON1 and EECON2 Registers temperature, as well as from chip to chip. Please refer to the specifications for exact limits (specifications The EECON1 register is the control register for config- #D122 and #D133). uring and initiating the access. The EECON2 register is not a physically implemented register, but is used A byte or word write automatically erases the location exclusively in the memory write sequence to prevent and writes the new value (erase before write). Writing inadvertent writes. to EEPROM Data memory does not impact the opera- tion of the device. Writing to Program memory will There are many bits used to control the read and write cease the execution of instructions until the write is operations to EEPROM Data and FLASH Program complete. The program memory cannot be accessed memory. The EEPGD bit determines if the access will during the write. During the write operation, the oscilla- be a program or data memory access. When clear, any tor continues to run, the peripherals continue to func- subsequent operations will work on the EEPROM Data tion and interrupt events will be detected and memory. When set, all subsequent operations will essentially “queued” until the write is complete. When operate in the Program memory. the write completes, the next instruction in the pipeline Read operations only use one additional bit, RD, which is executed and the branch to the interrupt vector will initiates the read operation from the desired memory take place if the interrupt is enabled and occurred dur- location. Once this bit is set, the value of the desired ing the write. memory location will be available in the data registers. Read and write access to both memories take place This bit cannot be cleared by firmware. It is automati- indirectly through a set of Special Function Registers cally cleared at the end of the read operation. For (SFR). The six SFRs used are: EEPROM Data memory reads, the data will be avail- able in the EEDATA register in the very next instruction (cid:129) EEDATA cycle after the RD bit is set. For program memory (cid:129) EEDATH reads, the data will be loaded into the (cid:129) EEADR EEDATH:EEDATA registers, following the second (cid:129) EEADRH instruction after the RD bit is set. (cid:129) EECON1 (cid:129) EECON2 © 2006 Microchip Technology Inc. DS30221C-page 23

PIC16F872 Write operations have two control bits, WR and WREN, desired memory location pointed to by and two status bits, WRERR and EEIF. The WREN bit EEADRH:EEADR will be erased. Then the data value is used to enable or disable the write operation. When in EEDATH:EEDATA will be programmed. When com- WREN is clear, the write operation will be disabled. plete, the EEIF flag bit will be set and the microcontrol- Therefore, the WREN bit must be set before executing ler will continue to execute code. a write operation. The WR bit is used to initiate the write The WRERR bit is used to indicate when the device operation. It also is automatically cleared at the end of has been RESET during a write operation. WRERR the write operation. The interrupt flag EEIF (located in should be cleared after Power-on Reset. Thereafter, it register PIR2) is used to determine when the memory should be checked on any other RESET. The WRERR write completes. This flag must be cleared in software bit is set when a write operation is interrupted by a before setting the WR bit. For EEPROM Data memory, MCLR Reset or a WDT Time-out Reset during normal once the WREN bit and the WR bit have been set, the operation. In these situations, following a RESET, the desired memory address in EEADR will be erased fol- user should check the WRERR bit and rewrite the lowed by a write of the data in EEDATA. This operation memory location if set. The contents of the data regis- takes place in parallel with the microcontroller continu- ters, address registers and EEPGD bit are not affected ing to execute normally. When the write is complete, by either MCLR Reset or WDT Time-out Reset during the EEIF flag bit will be set. For program memory, once normal operation. the WREN bit and the WR bit have been set, the micro- controller will cease to execute instructions. The REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch) R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses Program memory 0 = Accesses data memory (This bit cannot be changed while a read or write operation is in progress.) bit 6-4 Unimplemented: Read as '0' bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during normal operation) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 24 © 2006 Microchip Technology Inc.

PIC16F872 3.2 Reading the EEPROM Data should be kept clear at all times, except when writing to Memory the EEPROM Data. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they Reading EEPROM Data memory only requires that the both cannot be set in the same operation. The WREN desired address to access be written to the EEADR bit should then be cleared by firmware after the write. register and clear the EEPGD bit. After the RD bit is set, Clearing the WREN bit before the write actually com- data will be available in the EEDATA register on the pletes will not terminate the write in progress. very next instruction cycle. EEDATA will hold this value Writes to EEPROM Data memory must also be pref- until another read operation is initiated or until it is writ- aced with a special sequence of instructions that pre- ten by firmware. vent inadvertent write operations. This is a sequence of The steps to reading the EEPROM Data Memory are: five instructions that must be executed without interrup- 1. Write the address to EEDATA. Make sure that tion for each byte written. the address is not larger than the memory size The steps to write to program memory are: of the device. 1. Write the address to EEADR. Make sure that the 2. Clear the EEPGD bit to point to EEPROM Data address is not larger than the memory size of memory. the device. 3. Set the RD bit to start the read operation. 2. Write the 8-bit data value to be programmed in 4. Read the data from the EEDATA register. the EEDATA registers. 3. Clear the EEPGD bit to point to EEPROM Data EXAMPLE 3-1: EEPROM DATA READ memory. BSF STATUS, RP1 ; 4. Set the WREN bit to enable program operations. BCF STATUS, RP0 ;Bank 2 5. Disable interrupts (if enabled). MOVF ADDR, W ;Write address MOVWF EEADR ;to read from 6. Execute the special five instruction sequence: BSF STATUS, RP0 ;Bank 3 (cid:129) Write 55h to EECON2 in two steps (first to W, BCF EECON1, EEPGD ;Point to Data memory then to EECON2) BSF EECON1, RD ;Start read operation (cid:129) Write AAh to EECON2 in two steps (first to BCF STATUS, RP0 ;Bank 2 W, then to EECON2) MOVF EEDATA, W ;W = EEDATA (cid:129) Set the WR bit 7. Enable interrupts (if using interrupts). 3.3 Writing to the EEPROM Data 8. Clear the WREN bit to disable program operations. Memory 9. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. There are many steps in writing to the EEPROM Data (EEIF must be cleared by firmware). Firmware memory. Both address and data values must be written may check for EEIF to be set or WR to clear to to the SFRs. The EEPGD bit must be cleared and the indicate end of program cycle. WREN bit must be set to enable writes. The WREN bit EXAMPLE 3-2: EEPROM DATA WRITE BSF STATUS, RP1 ; BCF STATUS, RP0 ;Bank 2 MOVF ADDR, W ;Address to MOVWF EEADR ;write to MOVF VALUE, W ;Data to MOVWF EEDATA ;write BSF STATUS, RP0 ;Bank 3 BCF EECON1, EEPGD ;Point to Data memory BSF EECON1, WREN ;Enable writes ;Only disable interrupts BCF INTCON, GIE ;if already enabled, ;otherwise discard MOVLW 0x55 ;Write 55h to de MOVWF EECON2 ;EECON2 RequireSequenc MMOOVVLWWF 0ExEACAO N 2 ;;WErEiCtOeN 2AAh to BSF EECON1, WR ;Start write operation ;Only enable interrupts BSF INTCON, GIE ;if using interrupts, ;otherwise discard BCF EECON1, WREN ;Disable writes © 2006 Microchip Technology Inc. DS30221C-page 25

PIC16F872 3.4 Reading the FLASH Program The steps to reading the FLASH Program Memory are: Memory 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the mem- Reading FLASH Program memory is much like that of ory size of the device. EEPROM Data memory, only two NOP instructions 2. Set the EEPGD bit to point to FLASH Program must be inserted after the RD bit is set. These two memory. instruction cycles that the NOP instructions execute will be used by the microcontroller to read the data out of 3. Set the RD bit to start the read operation. program memory and insert the value into the 4. Execute two NOP instructions to allow the micro- EEDATH:EEDATA registers. Data will be available fol- controller to read out of program memory. lowing the second NOP instruction. EEDATH and 5. Read the data from the EEDATH:EEDATA EEDATA will hold their value until another read opera- registers. tion is initiated, or until they are written by firmware. EXAMPLE 3-3: FLASH PROGRAM READ BSF STATUS, RP1 ; BCF STATUS, RP0 ;Bank 2 MOVF ADDRL, W ;Write the MOVWF EEADR ;address bytes MOVF ADDRH,W ;for the desired MOVWF EEADRH ;address to read BSF STATUS, RP0 ;Bank 3 BSF EECON1, EEPGD ;Point to Program memory RequiredSequence BNNSOOFPP E E C O N 1 , R D ;;;SRteaqruti rreeda dt woop eNrOaPtsion BCF STATUS, RP0 ;Bank 2 MOVF EEDATA, W ;DATAL = EEDATA MOVWF DATAL ; MOVF EEDATH,W ;DATAH = EEDATH MOVWF DATAH ; 3.5 Writing to the FLASH Program clear at all times, except when writing to the FLASH Memory Program memory. The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they Writing to FLASH Program memory is unique in that the both cannot be set in the same operation. The WREN microcontroller does not execute instructions while pro- bit should then be cleared by firmware after the write. gramming is taking place. The oscillator continues to Clearing the WREN bit before the write actually com- run and all peripherals continue to operate and queue pletes will not terminate the write in progress. interrupts, if enabled. Once the write operation com- Writes to program memory must also be prefaced with pletes (specification #D133), the processor begins exe- a special sequence of instructions that prevent inad- cuting code from where it left off. The other important vertent write operations. This is a sequence of five difference when writing to FLASH Program memory is instructions that must be executed without interruption that the WRT configuration bit, when clear, prevents for each byte written. These instructions must then be any writes to program memory (see Table3-1). followed by two NOP instructions to allow the microcon- Just like EEPROM Data memory, there are many steps troller to setup for the write operation. Once the write is in writing to the FLASH Program memory. Both complete, the execution of instructions starts with the address and data values must be written to the SFRs. instruction after the second NOP. The EEPGD bit must be set and the WREN bit must be set to enable writes. The WREN bit should be kept DS30221C-page 26 © 2006 Microchip Technology Inc.

PIC16F872 The steps to write to program memory are: (cid:129) Write AAh to EECON2 in two steps (first to W, then to EECON2) 1. Write the address to EEADRH:EEADR. Make sure that the address is not larger than the mem- (cid:129) Set the WR bit ory size of the device. 7. Execute two NOP instructions to allow the micro- 2. Write the 14-bit data value to be programmed in controller to setup for write operation. the EEDATH:EEDATA registers. 8. Enable interrupts (if using interrupts). 3. Set the EEPGD bit to point to FLASH Program 9. Clear the WREN bit to disable program memory. operations. 4. Set the WREN bit to enable program operations. At the completion of the write cycle, the WR bit is 5. Disable interrupts (if enabled). cleared and the EEIF interrupt flag bit is set. (EEIF 6. Execute the special five instruction sequence: must be cleared by firmware). Since the microcontroller does not execute instructions during the write cycle, the (cid:129) Write 55h to EECON2 in two steps (first to W, firmware does not necessarily have to check either then to EECON2) EEIF or WR to determine if the write had finished. EXAMPLE 3-4: FLASH PROGRAM WRITE BSF STATUS, RP1 ; BCF STATUS, RP0 ;Bank 2 MOVF ADDRL, W ;Write address MOVWF EEADR ;of desired MOVF ADDRH, W ;program memory MOVWF EEADRH ;location MOVF VALUEL, W ;Write value to MOVWF EEDATA ;program at MOVF VALUEH, W ;desired memory MOVWF EEDATH ;location BSF STATUS, RP0 ;Bank 3 BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, WREN ;Enable writes ;Only disable interrupts BCF INTCON, GIE ;if already enabled, ;otherwise discard MOVLW 0x55 ;Write 55h to MOVWF EECON2 ;EECON2 de MOVLW 0xAA ;Write AAh to RequireSequenc MBOSVFW F EEEECCOONN21 , W R ;;ESEtCaOrNt2 write operation NOP ;Two NOPs to allow micro NOP ;to setup for write ;Only enable interrupts BSF INTCON, GIE ;if using interrupts, ;otherwise discard BCF EECON1, WREN ;Disable writes 3.6 Write Verify 3.7 Protection Against Spurious Writes The PIC16F87X devices do not automatically verify the There are conditions when the device may not want to value written during a write operation. Depending on write to the EEPROM Data memory or FLASH program the application, good programming practice may dic- memory. To protect against these spurious write condi- tate that the value written to memory be verified against tions various mechanisms have been built into the the original value. This should be used in applications device. On power-up, the WREN bit is cleared and the where excessive writes can stress bits near the speci- Power-up Timer (if enabled) prevents writes. fied endurance limits. The write initiate sequence and the WREN bit together help prevent any accidental writes during brown-out, power glitches or firmware malfunction. © 2006 Microchip Technology Inc. DS30221C-page 27

PIC16F872 3.8 Operation While Code Protected ent effects on writing to program memory. Table 4-1 shows the effect of the code protect bits and the WRT The PIC16F872 has two code protect mechanisms, bit on program memory. one bit for EEPROM Data memory and two bits for Once code protection has been enabled for either FLASH Program memory. Data can be read and written EEPROM Data memory or FLASH Program memory, to the EEPROM Data memory regardless of the state only a full erase of the entire device will disable code of the code protection bit, CPD. When code protection protection. is enabled, CPD cleared, external access via ICSP is disabled regardless of the state of the program memory 3.9 FLASH Program Memory Write code protect bits. This prevents the contents of Protection EEPROM Data memory from being read out of the device. The configuration word contains a bit that write protects The state of the program memory code protect bits, the FLASH Program memory called WRT. This bit can CP0 and CP1, do not affect the execution of instruc- only be accessed when programming the device via tions out of program memory. The PIC16F872 can ICSP. Once write protection is enabled, only an erase always read the values in program memory, regardless of the entire device will disable it. When enabled, write of the state of the code protect bits. However, the state protection prevents any writes to FLASH Program of the code protect bits and the WRT bit will have differ- memory. Write protection does not affect program memory reads. TABLE 3-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY Configuration Bits Internal Internal Memory Location ICSP Read ICSP Write Read Write CP1 CP0 WRT 0 0 0 All program memory Yes No No No 0 0 1 All program memory Yes Yes No No 1 1 0 All program memory Yes No Yes Yes 1 1 1 All program memory Yes Yes Yes Yes TABLE 3-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 10Dh EEADR EEPROM Address Register, Low Byte xxxx xxxx uuuu uuuu 10Fh EEADRH — — — EEPROM Address, High Byte xxxx xxxx uuuu uuuu 10Ch EEDATA EEPROM Data Register, Low Byte xxxx xxxx uuuu uuuu 10Eh EEDATH — — EEPROM Data Register, High Byte xxxx xxxx uuuu uuuu 18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000 18Dh EECON2 EEPROM Control Register2 (not a physical register) — — 8Dh PIE2 — (1) — EEIE BCLIE — — (1) -r-0 0--r -r-0 0--r 0Dh PIR2 — (1) — EEIF BCLIF — — (1) -r-0 0--r -r-0 0--r Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access. Note 1: These bits are reserved; always maintain these bits clear. DS30221C-page 28 © 2006 Microchip Technology Inc.

PIC16F872 4.0 I/O PORTS FIGURE 4-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS The PIC16F872 provides three general purpose I/O ports. Some pins for these ports are multiplexed with an Data Data Latch alternate function for the peripheral features on the Bus D Q device. In general, when a peripheral is enabled, that VDD WR pin may not be used as a general purpose I/O pin. Port CK Q P Additional information on I/O ports may be found in the I/O pin(1) PICmicro™ Mid-Range Reference Manual (DS33023). TRIS Latch 4.1 PORTA and the TRISA Register D Q N WR PORTA is a 6-bit wide, bi-directional port. The corre- TRIS CK Q sponding data direction register is TRISA. Setting a VSS TRISA bit (= ‘1’) will make the corresponding PORTA Analog pin an input (i.e., put the corresponding output driver in Input Mode a Hi-Impedance mode). Clearing a TRISA bit (= ‘0’) will make the corresponding PORTA pin an output (i.e., put RD the contents of the output latch on the selected pin). TRIS TTL Reading the PORTA register reads the status of the Input Buffer pins, whereas writing to it will write to the port latch. All Q D write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are ENEN read, the value is modified and then written to the port data latch. RD PORT Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI To A/D Converter pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full Note 1: I/O pins have protection diodes to VDD and VSS. CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is FIGURE 4-2: BLOCK DIAGRAM OF selected by clearing/setting the control bits in the RA4/T0CKI PIN ADCON1 register (A/D Control Register1). Data Data Latch Note: On a Power-on Reset, these pins are con- Bus D Q figured as analog inputs and read as '0'. WR PORT The TRISA register controls the direction of the RA CK Q I/O pin(1) N pins, even when they are being used as analog inputs. TRIS Latch The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. D Q VSS WR TRIS EXAMPLE 4-1: INITIALIZING PORTA CK Q Schmitt Trigger BCF STATUS, RP0 ; Input BCF STATUS, RP1 ; Bank0 Buffer CLRF PORTA ; Initialize PORTA by RD TRIS ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 Q D MOVLW 0x06 ; Configure all pins MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ENEN ; initialize data RD PORT ; direction MOVWF TRISA ; Set RA<3:0> as inputs TMR0 clock input ; RA<5:4> as outputs ; TRISA<7:6>are always ; read as '0'. Note 1: I/O pin has protection diodes to VSS only. © 2006 Microchip Technology Inc. DS30221C-page 29

PIC16F872 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR RESETS 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111. DS30221C-page 30 © 2006 Microchip Technology Inc.

PIC16F872 4.2 PORTB and the TRISB Register This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the PORTB is an 8-bit wide, bi-directional port. The corre- interrupt in the following manner: sponding data direction register is TRISB. Setting a a) Any read or write of PORTB. This will end the TRISB bit (= ‘1’) will make the corresponding PORTB mismatch condition. pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will b) Clear flag bit RBIF. make the corresponding PORTB pin an output (i.e., put A mismatch condition will continue to set flag bit RBIF. the contents of the output latch on the selected pin). Reading PORTB will end the mismatch condition and Three pins of PORTB are multiplexed with the Low allow flag bit RBIF to be cleared. Voltage Programming function; RB3/PGM, RB6/PGC The interrupt-on-change feature is recommended for and RB7/PGD. The alternate functions of these pins wake-up on key depression operation and operations are described in the Special Features Section. where PORTB is only used for the interrupt-on-change Each of the PORTB pins has a weak internal pull-up. A feature. Polling of PORTB is not recommended while single control bit can turn on all the pull-ups. This is per- using the interrupt-on-change feature. formed by clearing bit RBPU (OPTION_REG<7>). The This interrupt on mismatch feature, together with soft- weak pull-up is automatically turned off when the port ware configurable pull-ups on these four pins, allow pin is configured as an output. The pull-ups are dis- easy interface to a keypad and make it possible for abled on a Power-on Reset. wake-up on key depression. Refer to the Embedded Control Handbook, “Implementing Wake-Up on Key FIGURE 4-3: BLOCK DIAGRAM OF Stroke” (AN552). RB3:RB0 PINS RB0/INT is an external interrupt input pin and is config- VDD ured using the INTEDG bit (OPTION_REG<6>). RBPU(2) Weak RB0/INT is discussed in detail in Section11.10.1. P Pull-up Data Latch Data Bus D Q FIGURE 4-4: BLOCK DIAGRAM OF I/O pin(1) RB7:RB4 PINS WR Port CK VDD TRIS Latch RBPU(2) Weak D Q P Pull-up TTL Data Latch WR TRIS CK IBnupfufetr Data Bus D Q WR Port I/O pin(1) CK RD TRIS TRIS Latch D Q Q D RD Port WR TRIS CK TInTpLut EN Buffer ST Buffer RB0/INT RB3/PGM RD TRIS Latch Schmitt Trigger RD Port Q D Buffer RD Port Note 1: I/O pins have diode protection to VDD and VSS. EN Q1 2: To enable weak pull-ups, set the appropriate TRIS Set RBIF bit(s) and clear the RBPU bit (OPTION_REG<7>). Q D Four of the PORTB pins, RB7:RB4, have an interrupt- From other RD Port on-change feature. Only pins configured as inputs can RB7:RB4 pins EN cause this interrupt to occur (i.e., any RB7:RB4 pin Q3 configured as an output is excluded from the interrupt- RB7:RB6 on-change comparison). The input pins (of RB7:RB4) In Serial Programming Mode are compared with the old value latched on the last Note 1: I/O pins have diode protection to VDD and VSS. read of PORTB. The “mismatch” outputs of RB7:RB4 2: To enable weak pull-ups, set the appropriate TRIS are OR’ed together to generate the RB Port Change bit(s) and clear the RBPU bit (OPTION_REG<7>). Interrupt with flag bit RBIF (INTCON<0>). © 2006 Microchip Technology Inc. DS30221C-page 31

PIC16F872 TABLE 4-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3/PGM bit3 TTL Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming clock. RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30221C-page 32 © 2006 Microchip Technology Inc.

PIC16F872 4.3 PORTC and the TRISC Register FIGURE 4-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT PORTC is an 8-bit wide, bi-directional port. The corre- OVERRIDE) RC<4:3> sponding data direction register is TRISC. Setting a TRISC bit (= ‘1’) will make the corresponding PORTC Port/Peripheral Select(2) pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= ‘0’) will DPeartaip hBeursal Data Out 0 VDD make the corresponding PORTC pin an output (i.e., put D Q the contents of the output latch on the selected pin). WPORRT CK Q 1 P pIi/nO(1) PORTC is multiplexed with several peripheral functions Data Latch (Table4-5). PORTC pins have Schmitt Trigger input buffers. D Q WR When the I2C module is enabled, the PORTC (4:3) pins TRIS CK Q N can be configured with normal I2C levels or with SMBus TRIS Latch levels by using the CKE bit (SSPSTAT<6>). Vss RD When enabling peripheral functions, care should be TRIS Schmitt taken in defining TRIS bits for each PORTC pin. Some Trigger peripherals override the TRIS bit to make a pin an out- Peripheral put, while other peripherals override the TRIS bit to OE(3) Q D Schmitt make a pin an input. Since the TRIS bit override is in Trigger EN with effect while the peripheral is enabled, read-modify- RD SMBus write instructions (BSF, BCF, XORWF) with TRISC as PORT 0 Levels SSPl Input the destination should be avoided. The user should 1 refer to the corresponding peripheral section for the correct TRIS bit settings. CKE SSPSTAT<6> FIGURE 4-5: PORTC BLOCK DIAGRAM Note 1: I/O pins have diode protection to VDD and VSS. (PERIPHERAL OUTPUT 2: Port/Peripheral select signal selects between port data and peripheral output. OVERRIDE) RC<2:0> 3: Peripheral OE (output enable) is only activated if RC<7:5> peripheral select is active. Port/Peripheral Select(2) Peripheral Data Out 0 VDD Data Bus D Q P WR 1 PORT CK Q Data Latch I/O pin(1) D Q WR TRIS CK Q N TRIS Latch VSS RD TRIS Schmitt Trigger Peripheral OE(3) Q D EN RD PORT Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. © 2006 Microchip Technology Inc. DS30221C-page 33

PIC16F872 TABLE 4-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM output. RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output (SPI mode). RC6 bit6 ST Input/output port pin. RC7 bit7 ST Input/output port pin. Legend: ST = Schmitt Trigger input TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged DS30221C-page 34 © 2006 Microchip Technology Inc.

PIC16F872 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will The Timer0 module timer/counter has the following increment either on every rising or falling edge of pin features: RA4/T0CKI. The incrementing edge is determined by (cid:129) 8-bit timer/counter the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the ris- (cid:129) Readable and writable ing edge. Restrictions on the external clock input are (cid:129) 8-bit software programmable prescaler discussed in detail in Section5.2. (cid:129) Internal or external clock select The prescaler is mutually exclusively shared between (cid:129) Interrupt on overflow from FFh to 00h the Timer0 module and the Watchdog Timer. The pres- (cid:129) Edge select for external clock caler is not readable or writable. Section5.3 details the Figure5-1 is a block diagram of the Timer0 module and operation of the prescaler. the prescaler shared with the WDT. 5.1 Timer0 Interrupt Additional information on the Timer0 module is avail- able in the PICmicro™ Mid-Range MCU Family Refer- The TMR0 interrupt is generated when the TMR0 reg- ence Manual (DS33023). ister overflows from FFh to 00h. This overflow sets bit Timer mode is selected by clearing bit T0CS TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF (OPTION_REG<5>). In Timer mode, the Timer0 mod- ule will increment every instruction cycle (without pres- must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this inter- caler). If the TMR0 register is written, the increment is rupt. The TMR0 interrupt cannot awaken the processor inhibited for the following two instruction cycles. The from SLEEP, since the timer is shut-off during SLEEP. user can work around this by writing an adjusted value to the TMR0 register. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (= FOSC/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC Pin 1 X 0 U 2 TMR0 reg X Cycles T0SE T0CS PSA Set Flag Bit TMR0IF on Overflow PRESCALER 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). © 2006 Microchip Technology Inc. DS30221C-page 35

PIC16F872 5.2 Using Timer0 with an External Timer0 module means that there is no prescaler for the Clock Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure5-1). When no prescaler is used, the external clock input is The PSA and PS2:PS0 bits (OPTION_REG<3:0>) the same as the prescaler output. The synchronization determine the prescaler assignment and prescale ratio. of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and When assigned to the Timer0 module, all instructions Q4 cycles of the internal phase clocks. Therefore, it is writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, necessary for T0CKI to be high for at least 2TOSC (and BSF 1,x....etc.) will clear the prescaler. When assigned a small RC delay of 20 ns) and low for at least 2TOSC to WDT, a CLRWDT instruction will clear the prescaler (and a small RC delay of 20 ns). Refer to the electrical along with the Watchdog Timer. The prescaler is not specification of the desired device. readable or writable. Note: Writing to TMR0, when the prescaler is 5.3 Prescaler assigned to Timer0, will clear the prescaler There is only one prescaler available, which is mutually count, but will not change the prescaler exclusively shared between the Timer0 module and the assignment. Watchdog Timer. A prescaler assignment for the REGISTER 5-1: OPTION_REG REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU bit 6 INTEDG bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS30221C-page 36 © 2006 Microchip Technology Inc.

PIC16F872 TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. © 2006 Microchip Technology Inc. DS30221C-page 37

PIC16F872 NOTES: DS30221C-page 38 © 2006 Microchip Technology Inc.

PIC16F872 6.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input. of two 8-bit registers (TMR1H and TMR1L), which are Timer1 can be enabled/disabled by setting/clearing readable and writable. The TMR1 Register pair control bit TMR1ON (T1CON<0>). (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, Timer1 also has an internal “RESET input”. This is generated on overflow, which is latched in interrupt RESET can be generated by either of the two CCP flag bit TMR1IF (PIR1<0>). This interrupt can be modules (Section8.0). Register6-1 shows the Timer1 enabled/disabled by setting/clearing TMR1 interrupt control register. enable bit TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is Timer1 can operate in one of two modes: set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is (cid:129) As a Timer ignored, and these pins read as ‘0’. (cid:129) As a Counter Additional information on timer modules is available in The operating mode is determined by the clock select the PICmicro™ Mid-range MCU Family Reference bit, TMR1CS (T1CON<1>). Manual (DS33023). REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 39

PIC16F872 6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation Timer mode is selected by clearing the TMR1CS Timer1 may operate in either a Synchronous or an (T1CON<1>) bit. In this mode, the input clock to the Asynchronous mode, depending on the setting of the timer is FOSC/4. The synchronize control bit T1SYNC TMR1CS bit. (T1CON<2>) has no effect since the internal clock is When Timer1 is being incremented via an external always in sync. source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 6-1: TIMER1 INCREMENTING EDGE T1CKI (Default High) T1CKI (Default Low) Note: Arrows indicate counter increments. 6.3 Timer1 Operation in Synchronized If T1SYNC is cleared, then the external clock input is Counter Mode synchronized with internal phase clocks. The synchro- nization is done after the prescaler stage. The pres- Counter mode is selected by setting bit TMR1CS. In caler stage is an asynchronous ripple counter. this mode, the timer increments on every rising edge of In this configuration, during SLEEP mode, Timer1 will clock input on pin RC1/T1OSI/CCP2, when bit not increment even if the external clock is present, T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when since the synchronization circuit is shut-off. The pres- bit T1OSCEN is cleared. caler, however, will continue to increment. FIGURE 6-2: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow Synchronized TMR1 0 Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC RC0/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI/CCP2(2) Oscillator(1) Clock 2 Q Clock T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. DS30221C-page 40 © 2006 Microchip Technology Inc.

PIC16F872 6.4 Timer1 Operation in TABLE 6-1: CAPACITOR SELECTION FOR Asynchronous Counter Mode THE TIMER1 OSCILLATOR If control bit T1SYNC (T1CON<2>) is set, the external Osc Type Freq C1 C2 clock input is not synchronized. The timer continues to LP 32 kHz 33 pF 33 pF increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can 100 kHz 15 pF 15 pF generate an interrupt on overflow, which will wake-up 200 kHz 15 pF 15 pF the processor. However, special precautions in soft- These values are for design guidance only. ware are needed to read/write the timer (Section6.4.1). Crystals Tested: In Asynchronous Counter mode, Timer1 cannot be 32.768 kHz Epson C-001R32.768K-A ± 20 PPM used as a time-base for capture or compare opera- 100 kHz Epson C-2 100.00 KC-P ± 20 PPM tions. 200 kHz STD XTL 200.000 kHz ± 20 PPM 6.4.1 READING AND WRITING TIMER1 IN Note 1: Higher capacitance increases the stability ASYNCHRONOUS COUNTER of oscillator, but also increases the start-up MODE time. 2: Since each resonator/crystal has its own Reading TMR1H or TMR1L while the timer is running characteristics, the user should consult the from an external asynchronous clock will guarantee a resonator/crystal manufacturer for appro- valid read (taken care of in hardware). However, the priate values of external components. user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since 6.6 Resetting Timer1 using a CCP the timer may overflow between the reads. Trigger Output For writes, it is recommended that the user simply stop If the CCP1 or CCP2 module is configured in Compare the timer and write the desired values. A write conten- mode to generate a “special event trigger” tion may occur by writing to the timer registers while the (CCP1M3:CCP1M0 = 1011), this signal will reset register is incrementing. This may produce an unpre- Timer1. dictable value in the timer register. Reading the 16-bit value requires some care. Exam- Note: The special event triggers from the CCP1 ples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU and CCP2 modules will not set interrupt Family Reference Manual (DS33023) show how to flag bit TMR1IF (PIR1<0>). read and write Timer1 when it is running in Asynchro- Timer1 must be configured for either Timer or Synchro- nous mode. nized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, 6.5 Timer1 Oscillator this RESET operation may not work. A crystal oscillator circuit is built-in between pins T1OSI In the event that a write to Timer1 coincides with a spe- (input) and T1OSO (amplifier output). It is enabled by cial event trigger from CCP1 or CCP2, the write will setting control bit T1OSCEN (T1CON<3>). The oscilla- take precedence. tor is a low power oscillator, rated up to 200 kHz. It will In this mode of operation, the CCPRxH:CCPRxL regis- continue to run during SLEEP. It is primarily intended ter pair effectively becomes the period register for for use with a 32 kHz crystal. Table6-1 shows the Timer1. capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. 6.7 Resetting of Timer1 Register Pair The user must provide a software time delay to ensure (TMR1H, TMR1L) proper oscillator start-up. TMR1H and TMR1L registers are not reset to 00h on a POR or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected. 6.8 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. © 2006 Microchip Technology Inc. DS30221C-page 41

PIC16F872 TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 (3) ADIF (3) (3) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 8Ch PIE1 (3) ADIE (3) (3) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. DS30221C-page 42 © 2006 Microchip Technology Inc.

PIC16F872 7.0 TIMER2 MODULE Register7-1 shows the Timer2 Control register. Additional information on timer modules is available in Timer2 is an 8-bit timer with a prescaler and a the PICmicro™ Mid-Range MCU Family Reference postscaler. It can be used as the PWM time-base for Manual (DS33023). the PWM mode of the CCP module(s). The TMR2 reg- ister is readable and writable, and is cleared on any FIGURE 7-1: TIMER2 BLOCK DIAGRAM device RESET. The input clock (FOSC/4) has a prescale option of 1:1, Sets Flag TMR2 1:4 or 1:16, selected by control bits bit TMR2IF Output(1) T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Reset TMR2 reg Prescaler FOSC/4 1:1, 1:4, 1:16 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is Postscaler Comparator 2 a readable and writable register. The PR2 register is 1:1 to 1:16 EQ T2CKPS1: initialized to FFh upon RESET. 4 PR2 reg T2CKPS0 The match output of TMR2 goes through a 4-bit T2OUTPS3: postscaler (which gives a 1:1 to 1:16 scaling inclusive) T2OUTPS0 to generate a TMR2 interrupt (latched in flag bit, Note 1: TMR2 register output can be software selected by the TMR2IF (PIR1<1>)). SSP module as a baud clock. Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale (cid:129) (cid:129) (cid:129) 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 43

PIC16F872 7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2 The prescaler and postscaler counters are cleared The output of TMR2 (before the postscaler) is fed to the when any of the following occurs: SSP module, which optionally uses it to generate shift clock. (cid:129) a write to the TMR2 register (cid:129) a write to the T2CON register (cid:129) any device RESET (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written. TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 (3) ADIF (3) (3) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 8Ch PIE1 (3) ADIE (3) (3) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. DS30221C-page 44 © 2006 Microchip Technology Inc.

PIC16F872 8.0 CAPTURE/COMPARE/PWM Additional information on CCP modules is available in MODULE the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) and in Application Note (AN594), The Capture/Compare/PWM (CCP) module contains a “Using the CCP Modules” (DS00594). 16-bit register, which can operate as a: TABLE 8-1: CCP MODE - TIMER (cid:129) 16-bit Capture register RESOURCES REQUIRED (cid:129) 16-bit Compare register (cid:129) PWM Master/Slave Duty Cycle register CCP Mode Timer Resource The timer resources used by the module are shown in Capture Timer1 Table8-1. Compare Timer1 Capture/Compare/PWM Register 1 (CCPR1) is com- PWM Timer2 prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1. REGISTER 8-1: CCP1CON REGISTER (ADDRESS: 17h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCP module) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 45

PIC16F872 8.1 Capture Mode 8.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchro- 16-bit value of the TMR1 register when an event occurs nized Counter mode for the CCP module to use the on pin RC2/CCP1. An event is defined as one of the capture feature. In Asynchronous Counter mode, the following: capture operation may not work. (cid:129) Every falling edge 8.1.3 SOFTWARE INTERRUPT (cid:129) Every rising edge When the Capture mode is changed, a false capture (cid:129) Every 4th rising edge interrupt may be generated. The user should keep bit (cid:129) Every 16th rising edge CCP1IE (PIE1<2>) clear to avoid false interrupts and The type of event is configured by control bits should clear the flag bit, CCP1IF, following any such CCP1M3:CCP1M0 (CCP1CON<3:0>). When a cap- change in operating mode. ture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in 8.1.4 CCP PRESCALER software. If another capture occurs before the value in There are four prescaler settings, specified by bits register CCPR1 is read, the old captured value is over- CCP1M3:CCP1M0. Whenever the CCP module is written by the new value. turned off, or the CCP module is not in Capture mode, 8.1.1 CCP PIN CONFIGURATION the prescaler counter is cleared. Any RESET will clear the prescaler counter. In Capture mode, the RC2/CCP1 pin should be config- Switching from one capture prescaler to another may ured as an input by setting the TRISC<2> bit. generate an interrupt. Also, the prescaler counter will Note: If the RC2/CCP1 pin is configured as an not be cleared, therefore, the first capture may be from output, a write to the port can cause a cap- a non-zero prescaler. Example8-1 shows the recom- ture condition. mended method for switching between capture pres- calers. This example also clears the prescaler counter FIGURE 8-1: CAPTURE MODE and will not generate the “false” interrupt. OPERATION BLOCK DIAGRAM EXAMPLE 8-1: CHANGING BETWEEN CAPTURE PRESCALERS RC2/CCP1 Set Flag bit CCP1IF Pin Prescaler (PIR1<2>) CLRF CCP1CON ; Turn CCP module off ÷ 1, 4, 16 MOVLW NEW_CAPT_PS ; Load the W reg with ; the new prescaler CCPR1H CCPR1L ; move value and CCP ON MOVWF CCP1CON ; Load CCP1CON with this and Capture ; value Edge Detect Enable TMR1H TMR1L CCP1CON<3:0> Qs DS30221C-page 46 © 2006 Microchip Technology Inc.

PIC16F872 8.2 Compare Mode 8.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is The user must configure the RC2/CCP1 pin as an out- constantly compared against the TMR1 register pair put by clearing the TRISC<2> bit. value. When a match occurs, the RC2/CCP1 pin is: Note: Clearing the CCP1CON register will force (cid:129) Driven high the RC2/CCP1 compare output latch to the (cid:129) Driven low default low level. This is not the PORTC I/O data latch. (cid:129) Remains unchanged The action on the pin is based on the value of control 8.2.2 TIMER1 MODE SELECTION bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. Timer1 must be running in Timer mode or Synchro- nized Counter mode if the CCP module is using the FIGURE 8-2: COMPARE MODE compare feature. In Asynchronous Counter mode, the compare operation may not work. OPERATION BLOCK DIAGRAM 8.2.3 SOFTWARE INTERRUPT MODE Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), When Generate Software Interrupt mode is chosen, the and set bit GO/DONE (ADCON0<2>). CCP1 pin is not affected. The CCPIF bit is set, causing a CCP interrupt (if enabled). Special Event Trigger 8.2.4 SPECIAL EVENT TRIGGER Set Flag bit CCP1IF (PIR1<2>) RC2/CCP1 In this mode, an internal hardware trigger is generated, Pin CCPR1H CCPR1L which may be used to initiate an action. Q S Output Comparator The special event trigger output of CCP1 resets the R Logic Match TMR1 register pair and starts an A/D conversion (if the TRISC<2> TMR1H TMR1L A/D module is enabled). This allows the CCPR1 regis- Output Enable CCP1CON<3:0> ter to effectively be a 16-bit programmable period Mode Select register for Timer1. Note: The special event trigger from the CCP module will not set interrupt flag bit TMR1IF (PIR1<0>). TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits are reserved; always maintain clear. © 2006 Microchip Technology Inc. DS30221C-page 47

PIC16F872 8.3 PWM Mode (PWM) 8.3.1 PWM PERIOD In Pulse Width Modulation mode, the CCP1 pin pro- The PWM period is specified by writing to the PR2 reg- duces up to a 10-bit resolution PWM output. Since the ister. The PWM period can be calculated using the fol- CCP1 pin is multiplexed with the PORTC data latch, the lowing formula: TRISC<2> bit must be cleared to make the CCP1 pin PWM period = [(PR2) + 1] • 4 (cid:129)TOSC (cid:129) an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. (cid:129) TMR2 is cleared Figure8-3 shows a simplified block diagram of the (cid:129) The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step-by-step procedure on how to set up the CCP (cid:129) The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section8.3.3. CCPR1H FIGURE 8-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscaler (see Section7.1) is DIAGRAM not used in the determination of the PWM frequency. The postscaler could be used CCP1CON<5:4> Duty Cycle Registers to have a servo update rate at a different CCPR1L frequency than the PWM output. 8.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1H (Slave) CCPR1L register and to the CCP1CON<5:4> bits. Up RC2/CCP1 to 10-bit resolution is available. The CCPR1L contains Comparator R Q the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) S used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) (cid:129) Comparator TRISC<2> TOSC (cid:129)(TMR2 prescale value) Clear Timer, CCP1 pin and CCPR1L and CCP1CON<5:4> can be written to at any latch D.C. PR2 time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 Note1: The 8-bit timer is concatenated with 2-bit internal Q occurs (i.e., the period is complete). In PWM mode, clock, or 2 bits of the prescaler to create 10-bit time-base. CCPR1H is a read only register. A PWM output (Figure8-4) has a time-base (period) The CCPR1H register and a 2-bit internal latch are and a time that the output stays high (duty cycle). The used to double buffer the PWM duty cycle. This double frequency of the PWM is the inverse of the period buffering is essential for glitch-free PWM operation. (1/period). When the CCPR1H and 2-bit latch match TMR2, con- catenated with an internal 2-bit Q clock or 2 bits of the FIGURE 8-4: PWM OUTPUT TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM Period frequency is given by the formula: (FOSC ) log Resolution = FPWM bits Duty Cycle log(2) TMR2 = PR2 Note: If the PWM duty cycle value is longer than TMR2 = Duty Cycle the PWM period, the CCP1 pin will not be cleared. TMR2 = PR2 DS30221C-page 48 © 2006 Microchip Technology Inc.

PIC16F872 8.3.3 SETUP FOR PWM OPERATION 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. The following steps should be taken when configuring 4. Set the TMR2 prescale value and enable Timer2 the CCP module for PWM operation: by writing to T2CON. 1. Set the PWM period by writing to the PR2 5. Configure the CCP1 module for PWM operation. register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 8-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 Modules Register 0000 0000 0000 0000 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: These bits are reserved; always maintain clear. © 2006 Microchip Technology Inc. DS30221C-page 49

PIC16F872 NOTES: DS30221C-page 50 © 2006 Microchip Technology Inc.

PIC16F872 9.0 MASTER SYNCHRONOUS The MSSP module is controlled by three special func- SERIAL PORT (MSSP) tion registers: MODULE (cid:129) SSPSTAT (cid:129) SSPCON The Master Synchronous Serial Port (MSSP) module is (cid:129) SSPCON2 a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral The SSPSTAT and SSPCON registers are used in both devices may be serial EEPROMs, shift registers, dis- SPI and I2C modes; their individual bits take on differ- play drivers, A/D converters, etc. The MSSP module ent functions depending on the mode selected. The can operate in one of two modes: SSPCON2 register, on the other hand, is associated only with I2C operations. The registers are detailed in (cid:129) Serial Peripheral Interface (SPI) Registers9-1 through9-3 on the following pages. (cid:129) Inter-Integrated Circuit (I2C) The operation of the module in SPI mode is discussed in greater detail in Section9.1. The operations of the module in the the various I2C modes are covered in Section9.2, while special considerations for connect- ing the I2C bus are discussed in Section9.3. © 2006 Microchip Technology Inc. DS30221C-page 51

PIC16F872 REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for High Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (Figure9-2, Figure9-3 and Figure9-4) SPI mode: For CKP = 0 1 = Transmit happens on transition from active clock state to idle clock state 0 = Transmit happens on transition from idle clock state to active clock state For CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK In I 2 C Master or Slave mode: 1 = Input levels conform to SMBus spec 0 = Input levels conform to I2C specs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: STOP bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET) 0 = STOP bit was not detected last bit 3 S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a START bit has been detected last (this bit is '0' on RESET) 0 = START bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress. Logical OR of this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 52 © 2006 Microchip Technology Inc.

PIC16F872 REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS: 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to SSPBUF was attempted while the I2C conditions were not valid 0 = No collision Slave mode: 1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 =A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid over- flows. In Master mode, the overflow bit is not set since each operation is initiated by writing to the SSPBUF register. (Must be cleared in software.) 0 =No overflow In I 2 C mode: 1 =A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in Transmit mode. (Must be cleared in software.) 0 =No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In SPI mode: When enabled, these pins must be properly configured as input or output. 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: When enabled, these pins must be properly configured as input or output. 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = IDLE state for clock is a high level 0 = IDLE state for clock is a low level In I 2 C slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C master mode: Unused in this mode bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 =SPI Master mode, clock = FOSC/4 0001 =SPI Master mode, clock = FOSC/16 0010 =SPI Master mode, clock = FOSC/64 0011 =SPI Master mode, clock = TMR2 output/2 0100 =SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 =SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 =I2C Slave mode, 7-bit address 0111 =I2C Slave mode, 10-bit address 1000 =I2C Master mode, clock = FOSC / (4 * (SSPADD+1) 1011 =I2C Firmware Controlled Master mode (slave idle) 1110 =I2C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled 1111 =I2C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled 1001, 1010, 1100, 1101 = reserved Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 53

PIC16F872 REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS: 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only) In Master Receive mode: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Auto- matically cleared by hardware. 0 = Acknowledge sequence IDLE bit 3 RCEN: Receive Enable bit (In I2C Master mode only). 1 = Enables Receive mode for I2C 0 = Receive IDLE bit 2 PEN: STOP Condition Enable bit (In I2C Master mode only) SCK Release Control: 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition IDLE bit 1 RSEN: Repeated START Condition Enabled bit (In I2C Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition IDLE bit 0 SEN: START Condition Enabled bit (In I2C Master mode only) 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition IDLE Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 54 © 2006 Microchip Technology Inc.

PIC16F872 9.1 SPI Mode FIGURE 9-1: MSSP BLOCK DIAGRAM (SPIMODE) The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four Internal Data Bus modes of SPI are supported. To accomplish communi- cation, typically three pins are used: Read Write (cid:129) Serial Data Out (SDO) SSPBUF reg (cid:129) Serial Data In (SDI) (cid:129) Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: SSPSR reg (cid:129) Slave Select (SS) SDI bit0 Shift Clock When initializing the SPI, several options need to be specified. This is done by programming the appropriate SDO control bits (SSPCON<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: SS Control (cid:129) Master mode (SCK is the clock output) Enable (cid:129) Slave mode (SCK is the clock input) SS Edge (cid:129) Clock Polarity (IDLE state of SCK) Select (cid:129) Data input sample phase (middle or end of data output time) 2 Clock Select (cid:129) Clock edge (output data on rising/falling edge of SCK) SSPM3:SSPM0 (cid:129) Clock Rate (Master mode only) SMP:CKE 4 TMR2 Output (cid:129) Slave Select mode (Slave mode only) 2 2 Edge Figure9-4 shows the block diagram of the MSSP mod- Select Prescaler TOSC ule when in SPI mode. SCK 4, 16, 64 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI Data to TX/RX in SSPSR Data Direction bit mode, clear bit SSPEN, re-initialize the SSPCON reg- isters, and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must 9.1.1 MASTER MODE have their data direction bits (in the TRIS register) appropriately programmed. That is: The master can initiate the data transfer at any time (cid:129) SDI is automatically controlled by the SPI module because it controls the SCK. The master determines (cid:129) SDO must have TRISC<5> cleared when the slave (Processor 2, Figure9-5) is to broad- cast data by the software protocol. (cid:129) SCK (Master mode) must have TRISC<3> cleared In Master mode, the data is transmitted/received as (cid:129) SCK (Slave mode) must have TRISC<3> set soon as the SSPBUF register is written to. If the SPI module is only going to receive, the SDO output could (cid:129) SS must have TRISA<5> set, and be disabled (programmed as an input). The SSPSR (cid:129) Register ADCON1 must be set in a way that pin register will continue to shift in the signal present on the RA5 is configured as a digital I/O SDI pin at the programmed clock rate. As each byte is Any serial port function that is not desired may be over- received, it will be loaded into the SSPBUF register as ridden by programming the corresponding data direc- if a normal received byte (interrupts and status bits tion (TRIS) register to the opposite value. appropriately set). This could be useful in receiver applications as a “line activity monitor”. © 2006 Microchip Technology Inc. DS30221C-page 55

PIC16F872 The clock polarity is selected by appropriately program- This allows a maximum bit clock frequency (at 20 MHz) ming bit CKP (SSPCON<4>). This, then, would give of 5.0 MHz. waveforms for SPI communication as shown in Figure9-6 shows the waveforms for Master mode. Figure9-6, Figure9-8 and Figure9-9, where the MSb is When CKE=1, the SDO data is valid before there is a transmitted first. In Master mode, the SPI clock rate (bit clock edge on SCK. The change of the input sample is rate) is user programmable to be one of the following: shown based on the state of the SMP bit. The time (cid:129) FOSC/4 (or TCY) when the SSPBUF is loaded with the received data is (cid:129) FOSC/16 (or 4 (cid:129) TCY) shown. (cid:129) FOSC/64 (or 16 (cid:129) TCY) (cid:129) Timer2 Output/2 FIGURE 9-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF 9.1.2 SLAVE MODE While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up In Slave mode, the data is transmitted and received as from SLEEP. the external clock pulses appear on SCK. When the last bit is latched, the interrupt flag bit SSPIF (PIR1<3>) Note 1: When the SPI module is in Slave mode is set. with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module While in Slave mode, the external clock is supplied by will reset if the SS pin is set to VDD. the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as 2: If the SPI is used in Slave mode with specified in the electrical specifications. CKE='1', then SS pin control must be enabled. DS30221C-page 56 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE=0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE=1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are reserved; always maintain these bits clear. © 2006 Microchip Technology Inc. DS30221C-page 57

PIC16F872 9.2 MSSP I2C Operation The SSPCON register allows control of the I2C opera- tion. Four mode selection bits (SSPCON<3:0>) allow The MSSP module in I2C mode, fully implements all one of the following I2C modes to be selected: master and slave functions (including general call sup- (cid:129) I2C Slave mode (7-bit address) port) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master func- (cid:129) I2C Slave mode (10-bit address) tion). The MSSP module implements the standard (cid:129) I2C Master mode, clock = OSC/4 (SSPADD +1) mode specifications, as well as 7-bit and 10-bit Before selecting any I2C mode, the SCL and SDA pins addressing. must be programmed to inputs by setting the appropri- Refer to Application Note (AN578), "Use of the SSP ate TRIS bits. Selecting an I2C mode by setting the Module in the I2C Multi-Master Environment." SSPEN bit, enables the SCL and SDA pins to be used as the clock and data lines in I2C mode. Pull-up resis- A "glitch" filter is on the SCL and SDA pins when the pin tors must be provided externally to the SCL and SDA is an input. This filter operates in both the 100 kHz and pins for the proper operation of the I2C module. 400 kHz modes. In the 100 kHz mode, when these pins are an output, there is a slew rate control of the pin that The CKE bit (SSPSTAT<6:7>) sets the levels of the is independent of device frequency. SDA and SCL pins in either Master or Slave mode. When CKE = 1, the levels will conform to the SMBus FIGURE 9-5: I2C SLAVE MODE BLOCK specification. When CKE = 0, the levels will conform to DIAGRAM the I2C specification. The SSPSTAT register gives the status of the data Internal Data Bus transfer. This information includes detection of a START (S) or STOP (P) bit, specifies if the received Read Write byte was data or address, if the next byte is the com- pletion of 10-bit address, and if this will be a read or SSPBUF reg SCL write data transfer. Shift SSPBUF is the register to which the transfer data is Clock written to or read from. The SSPSR register shifts the SSPSR reg data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered SDA MSb LSb receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the Match Detect Addr Match complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register SSPADD reg is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the START and Set, Reset SSPSR is lost. STOP bit Detect S, P bits (SSPSTAT reg) The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte Two pins are used for data transfer. These are the SCL address match, the low byte of the address needs to be pin, which is the clock, and the SDA pin, which is the loaded (A7:A0). data. The SDA and SCL pins are automatically config- ured when the I2C mode is enabled. The SSP module 9.2.1 SLAVE MODE functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). In Slave mode, the SCL and SDA pins must be config- The MSSP module has six registers for I2C operation. ured as inputs. The MSSP module will override the They are the: input state with the output data when required (slave- transmitter). (cid:129) SSP Control Register (SSPCON) When an address is matched, or the data transfer after (cid:129) SSP Control Register2 (SSPCON2) an address match is received, the hardware automati- (cid:129) SSP Status Register (SSPSTAT) cally will generate the Acknowledge (ACK) pulse, and (cid:129) Serial Receive/Transmit Buffer (SSPBUF) then load the SSPBUF register with the received value (cid:129) SSP Shift Register (SSPSR) - Not directly currently in the SSPSR register. accessible (cid:129) SSP Address Register (SSPADD) DS30221C-page 58 © 2006 Microchip Technology Inc.

PIC16F872 There are certain conditions that will cause the MSSP 1. Receive first (high) byte of Address (bits SSPIF, module not to give this ACK pulse. These are if either BF and UA (SSPSTAT<1>) are set). (or both): 2. Update the SSPADD register with the second a) The buffer full bit BF (SSPSTAT<0>) was set (low) byte of Address (clears bit UA and before the transfer was received. releases the SCL line). b) The overflow bit SSPOV (SSPCON<6>) was set 3. Read the SSPBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPIF. 4. Receive second (low) byte of Address (bits If the BF bit is set, the SSPSR register value is not SSPIF, BF and UA are set). loaded into the SSPBUF, but bit SSPIF and SSPOV are set. Table9-2 shows what happens when a data trans- 5. Update the SSPADD register with the first (high) fer byte is received, given the status of bits BF and byte of Address. This will clear bit UA and SSPOV. The shaded cells show the condition where release the SCL line. user software did not properly clear the overflow condi- 6. Read the SSPBUF register (clears bit BF) and tion. Flag bit BF is cleared by reading the SSPBUF reg- clear flag bit SSPIF. ister, while bit SSPOV is cleared through software. 7. Receive Repeated START condition. The SCL clock input must have a minimum high and 8. Receive first (high) byte of Address (bits SSPIF low time for proper operation. The high and low times and BF are set). of the I2C specification, as well as the requirement of 9. Read the SSPBUF register (clears bit BF) and the MSSP module, is shown in timing parameter #100 clear flag bit SSPIF. and parameter #101 of the electrical specifications. Note: Following the Repeated START condition 9.2.1.1 Addressing (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. The Once the MSSP module has been enabled, it waits for user does not update the SSPADD for the a START condition to occur. Following the START con- second half of the address. dition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the 9.2.1.2 Slave Reception clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The When the R/W bit of the address byte is clear and an address is compared on the falling edge of the eighth address match occurs, the R/W bit of the SSPSTAT clock (SCL) pulse. If the addresses match, and the BF register is cleared. The received address is loaded into and SSPOV bits are clear, the following events occur: the SSPBUF register. a) The SSPSR register value is loaded into the When the address byte overflow condition exists, then SSPBUF register on the falling edge of the 8th no Acknowledge (ACK) pulse is given. An overflow SCL pulse. condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error b) The buffer full bit, BF, is set on the falling edge condition due to user firmware. of the 8th SCL pulse. c) An ACK pulse is generated. An SSP interrupt is generated for each data transfer d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- (interrupt is generated if enabled) on the falling ware. The SSPSTAT register is used to determine the edge of the 9th SCL pulse. status of the received byte. In 10-bit Address mode, two address bytes need to be Note: The SSPBUF will be loaded if the SSPOV received by the slave. The five Most Significant bits bit is set and the BF flag is cleared. If a (MSbs) of the first address byte specify if this is a 10-bit read of the SSPBUF was performed, but address. Bit R/W (SSPSTAT<2>) must specify a write, the user did not clear the state of the so the slave device will receive the second address SSPOV bit before the next receive byte. For a 10-bit address the first byte would equal occurred, the ACK is not sent and the ‘1111 0 A9 A8 0’, where A9 and A8 are the two SSPBUF is updated. MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7-9 for slave transmitter: © 2006 Microchip Technology Inc. DS30221C-page 59

PIC16F872 TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF Generate ACK (SSP Interrupt occurs BF SSPOV SSPSR → SSPBUF Pulse if enabled) 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 Yes No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 9.2.1.3 Slave Transmission An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in software When the R/W bit of the incoming address byte is set and the SSPSTAT register is used to determine the sta- and an address match occurs, the R/W bit of the tus of the byte transfer. The SSPIF flag bit is set on the SSPSTAT register is set. The received address is falling edge of the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and the SCL pin is held low. As a slave-transmitter, the ACK pulse from the master The transmit data must be loaded into the SSPBUF receiver is latched on the rising edge of the ninth SCL register, which also loads the SSPSR register. Then the input pulse. If the SDA line is high (Not ACK), then the SCL pin should be enabled by setting bit CKP data transfer is complete. When the Not ACK is latched (SSPCON<4>). The master must monitor the SCL pin by the slave, the slave logic is reset and the slave then prior to asserting another clock pulse. The slave monitors for another occurrence of the START bit. If the devices may be holding off the master by stretching the SDA line was low (ACK), the transmit data must be clock. The eight data bits are shifted out on the falling loaded into the SSPBUF register, which also loads the edge of the SCL input. This ensures that the SDA sig- SSPSR register. Then, the SCL pin should be enabled nal is valid during the SCL high time (Figure9-7). by setting the CKP bit. FIGURE 9-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R/W=0 Not Receiving Address ACK Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF Bus Master terminates transfer BF (SSPSTAT<0>) Cleared in software SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full ACK is not sent DS30221C-page 60 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 9-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 1 R/W = 0 Receiving Address ACK Transmitting Data Not ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF BF (SSPSTAT<0>) Cleared in software From SSP Interrupt SSPBUF is written in software Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) 9.2.2 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), The addressing procedure for the I2C bus is such that the SSPIF flag is set. the first byte after the START condition usually deter- When the interrupt is serviced, the source for the inter- mines which device will be the slave addressed by the rupt can be checked by reading the contents of the master. The exception is the general call address, SSPBUF, to determine if the address was device spe- which can address all devices. When this address is cific or a general call address. used, all devices should, in theory, respond with an Acknowledge. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is sampled when GCEN is set while the slave is config- consists of all 0’s with R/W = 0. ured in 10-bit Address mode, then the second half of The general call address is recognized when the Gen- the address is not necessary, the UA bit will not be set, eral Call Enable bit (GCEN) is enabled (SSPCON2<7> and the slave will begin receiving data after the is set). Following a START bit detect, 8-bits are shifted Acknowledge (Figure9-8). into SSPSR and the address is compared against SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 9-8: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE) Address is compared to General Call Address after ACK, set interrupt flag R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV '0' (SSPCON<6>) GCEN '1' (SSPCON2<7>) © 2006 Microchip Technology Inc. DS30221C-page 61

PIC16F872 9.2.3 SLEEP OPERATION 9.2.4 EFFECTS OF A RESET While in SLEEP mode, the I2C module can receive A RESET disables the SSP module and terminates the addresses or data. When an address match or com- current transfer. plete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 0Dh PIR2 — (1) — EEIF BCLIF — (1) CCP2IF -r-0 0--0 -r-0 0--0 8Dh PIE2 — (1) — EEIE BCLIE — (1) CCP2IE -r-0 0--r -r-0 0--r 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I2C mode. Note 1: These bits are reserved; always maintain these bits clear. DS30221C-page 62 © 2006 Microchip Technology Inc.

PIC16F872 9.2.5 MASTER MODE The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (an SSP Interrupt will occur if Master mode of operation is supported by interrupt enabled): generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are (cid:129) START condition cleared from a RESET or when the MSSP module is (cid:129) STOP condition disabled. Control of the I2C bus may be taken when the (cid:129) Data transfer byte transmitted/received P bit is set, or the bus is IDLE, with both the S and P (cid:129) Acknowledge transmit bits clear. (cid:129) Repeated START In Master mode, the SCL and SDA lines are manipu- lated by the MSSP hardware. 2 FIGURE 9-9: SSP BLOCK DIAGRAM (I C MASTER MODE) Internal SSPM3:SSPM0, Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock ct e SSPSR Detce) MSb LSb L ur e Oo SCL Receive Enabl STAARcTGk enbnoitew, rSlaeTtdeOgeP bit, clock cntl k Arbitrate/WChold off clock s c( o Cl START bit Detect, STOP bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT) Bus Collision Clock Arbitration Set SSPIF, BCLIF State Counter for Reset ACKSTAT, PEN (SSPCON2) End of XMIT/RCV 9.2.6 MULTI-MASTER MODE The states where arbitration can be lost are: In Multi-Master mode, the interrupt generation on the (cid:129) Address Transfer detection of the START and STOP conditions allows (cid:129) Data Transfer the determination of when the bus is free. The STOP (cid:129) A START Condition (P) and START (S) bits are cleared from a RESET or (cid:129) A Repeated START Condition when the MSSP module is disabled. Control of the I2C (cid:129) An Acknowledge Condition bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is IDLE with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will gener- ate the interrupt when the STOP condition occurs. In Multi-Master operation, the SDA line must be moni- tored for arbitration to see if the signal level is the expected output level. This check is performed in hard- ware, with the result placed in the BCLIF bit. © 2006 Microchip Technology Inc. DS30221C-page 63

PIC16F872 9.2.7 I2C MASTER MODE SUPPORT will automatically begin counting on a write to the SSPBUF. Once the given operation is complete (i.e., Master mode is enabled by setting and clearing the transmission of the last data bit is followed by ACK) the appropriate SSPM bits in SSPCON and by setting the internal clock will automatically stop counting and the SSPEN bit. Once Master mode is enabled, the user SCL pin will remain in its last state has six options. A typical transmit sequence would go as follows: (cid:129) Assert a START condition on SDA and SCL. a) The user generates a Start Condition by setting (cid:129) Assert a Repeated START condition on SDA and the START enable bit (SEN) in SSPCON2. SCL. b) SSPIF is set. The module will wait the required (cid:129) Write to the SSPBUF register, initiating transmis- start time before any other operation takes place. sion of data/address. c) The user loads the SSPBUF with address to (cid:129) Generate a STOP condition on SDA and SCL. transmit. (cid:129) Configure the I2C port to receive data. d) Address is shifted out the SDA pin until all 8 bits (cid:129) Generate an Acknowledge condition at the end of are transmitted. a received byte of data. e) The MSSP module shifts in the ACK bit from the Note: The MSSP module, when configured in I2C slave device and writes its value into the Master mode, does not allow queueing of SSPCON2 register (SSPCON2<6>). events. For instance, the user is not f) The module generates an interrupt at the end of allowed to initiate a START condition and the ninth clock cycle by setting SSPIF. immediately write the SSPBUF register to g) The user loads the SSPBUF with eight bits of data. initiate transmission, before the START h) DATA is shifted out the SDA pin until all 8 bits are condition is complete. In this case, the transmitted. SSPBUF will not be written to and the WCOL bit will be set, indicating that a write i) The MSSP module shifts in the ACK bit from the to the SSPBUF did not occur. slave device, and writes its value into the SSPCON2 register (SSPCON2<6>). 9.2.7.1 I2C Master Mode Operation j) The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The master device generates all of the serial clock pulses and the START and STOP conditions. A trans- k) The user generates a STOP condition by setting fer is ended with a STOP condition or with a Repeated the STOP enable bit PEN in SSPCON2. START condition. Since the Repeated START condi- l) Interrupt is generated once the STOP condition tion is also the beginning of the next serial transfer, the is complete. I2C bus will not be released. 9.2.8 BAUD RATE GENERATOR In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The In I2C Master mode, the reload value for the BRG is first byte transmitted contains the slave address of the located in the lower 7 bits of the SSPADD register receiving device (7 bits) and the Read/Write (R/W) bit. (Figure9-10). When the BRG is loaded with this value, In this case, the R/W bit will be logic '0'. Serial data is the BRG counts down to 0 and stops until another reload transmitted 8 bits at a time. After each byte is transmit- has taken place. The BRG count is decremented twice ted, an Acknowledge bit is received. START and STOP per instruction cycle (TCY), on the Q2 and Q4 clock. conditions are output to indicate the beginning and the In I2C Master mode, the BRG is reloaded automatically. end of a serial transfer. If Clock Arbitration is taking place, for instance, the In Master Receive mode, the first byte transmitted con- BRG will be reloaded when the SCL pin is sampled tains the slave address of the transmitting device high (Figure9-11). (7bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave FIGURE 9-10: BAUD RATE GENERATOR address followed by a '1' to indicate receive bit. Serial BLOCK DIAGRAM data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each SSPM3:SSPM0 SSPADD<6:0> byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. SSPM3:SSPM0 Reload Reload The baud rate generator used for SPI mode operation SCL Control is now used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. The baud FOSC/4 rate generator reload value is contained in the lower 7 CLKOUT BRG Down Counter bits of the SSPADD register. The baud rate generator DS30221C-page 64 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL de-asserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements (on Q2 and Q4 cycles) BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place, and BRG starts its count. BRG Reload 9.2.9 I2C MASTER MODE START Note: If, at the beginning of START condition, the CONDITION TIMING SDA and SCL pins are already sampled low, or if during the START condition, the To initiate a START condition, the user sets the START SCL line is sampled low before the SDA condition enable bit, SEN (SSPCON2<0>). If the SDA line is driven low, a bus collision occurs, and SCL pins are sampled high, the baud rate genera- the Bus Collision Interrupt Flag (BCLIF) is tor is reloaded with the contents of SSPADD<6:0> and set, the START condition is aborted, and starts its count. If SCL and SDA are both sampled high the I2C module is reset into its IDLE state. when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being 9.2.9.1 WCOL Status Flag driven low while SCL is high is the START condition, and causes the S bit (SSPSTAT<3>) to be set. Follow- If the user writes the SSPBUF when a START ing this, the baud rate generator is reloaded with the sequence is in progress, then WCOL is set and the contents of SSPADD<6:0> and resumes its count. contents of the buffer are unchanged (the write doesn’t When the baud rate generator times out (TBRG), the occur). SEN bit (SSPCON2<0>) will be automatically cleared Note: Because queueing of events is not by hardware. The baud rate generator is suspended, allowed, writing to the lower 5 bits of leaving the SDA line held low, and the START condition SSPCON2 is disabled until the START is complete. condition is complete. FIGURE 9-12: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of START bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st Bit 2nd Bit SDA TBRG SCL TBRG S © 2006 Microchip Technology Inc. DS30221C-page 65

PIC16F872 9.2.10 I2C MASTER MODE REPEATED Immediately following the SSPIF bit getting set, the START CONDITION TIMING user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. A Repeated START condition occurs when the RSEN After the first eight bits are transmitted and an ACK is bit (SSPCON2<1>) is programmed high and the I2C received, the user may then transmit an additional eight module is in the IDLE state. When the RSEN bit is set, bits of address (10-bit mode), or eight bits of data (7-bit the SCL pin is asserted low. When the SCL pin is sam- mode). pled low, the baud rate generator is loaded with the contents of SSPADD<6:0> and begins counting. The 9.2.10.1 WCOL Status Flag SDA pin is released (brought high) for one baud rate If the user writes the SSPBUF when a Repeated generator count (TBRG). When the baud rate generator START sequence is in progress, then WCOL is set and times out if SDA is sampled high, the SCL pin will be the contents of the buffer are unchanged (the write de-asserted (brought high). When SCL is sampled doesn’t occur). high, the baud rate generator is reloaded with the con- tents of SSPADD<6:0> and begins counting. SDA and Note: Because queueing of events is not SCL must be sampled high for one TBRG. This action is allowed, writing of the lower 5 bits of then followed by assertion of the SDA pin (SDA is low) SSPCON2 is disabled until the Repeated for one TBRG, while SCL is high. Following this, the START condition is complete. RSEN bit in the SSPCON2 register will be automati- cally cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: (cid:129) SDA is sampled low when SCL goes from low to high. (cid:129) SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". FIGURE 9-13: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, At completion of START bit, SDA = 1, SCL = 1 hardware clear RSEN bit SCL(no change). and set SSPIF TBRG TBRG TBRG 1st Bit SDA Falling edge of ninth clock Write to SSPBUF occurs here End of Xmit TBRG SCL TBRG Sr = Repeated START DS30221C-page 66 © 2006 Microchip Technology Inc.

PIC16F872 9.2.11 I2C MASTER MODE 9.2.11.1 BF Status Flag TRANSMISSION In Transmit mode, the BF bit (SSPSTAT<0>) is set Transmission of a data byte, a 7-bit address, or either when the CPU writes to SSPBUF and is cleared when half of a 10-bit address, is accomplished by simply writ- all 8 bits are shifted out. ing a value to SSPBUF register. This action will set the 9.2.11.2 WCOL Status Flag buffer full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit If the user writes the SSPBUF when a transmit is of address/data will be shifted out onto the SDA pin already in progress (i.e., SSPSR is still shifting out a after the falling edge of SCL is asserted (see data hold data byte), then WCOL is set and the contents of the time spec). SCL is held low for one baud rate gener- buffer are unchanged (the write doesn’t occur). ator rollover count (TBRG). Data should be valid before WCOL must be cleared in software. SCL is released high (see data setup time spec). When the SCL pin is released high, it is held that way for 9.2.11.3 ACKSTAT Status Flag TBRG. The data on the SDA pin must remain stable for In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is that duration and some hold time after the next falling cleared when the slave has sent an Acknowledge edge of SCL. After the eighth bit is shifted out (the fall- (ACK= 0), and is set when the slave does Not ing edge of the eighth clock), the BF flag is cleared and Acknowledge (ACK = 1). A slave sends an Acknowl- the master releases SDA, allowing the slave device edge when it has recognized its address (including a being addressed to respond with an ACK bit during the general call), or when the slave has properly received ninth bit time, if an address match occurs or if data was its data. received properly. The status of ACK is read into the ACKDT on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge status bit (ACKSTAT) is cleared. If not, the bit is set. After the ninth clock, the SSPIF is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure9-14). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL, until all seven address bits and the R/W bit are completed. On the fall- ing edge of the eighth clock, the master will de-assert the SDA pin allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmis- sion of the address, the SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. © 2006 Microchip Technology Inc. DS30221C-page 67

PIC16F872 FIGURE 9-14: I2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting data or second halfof 10-bit address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom SSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re R/W = 0 A d R/W, 89 hardware PCON2<0> SEN = 1,ondition begins SEN = 0 Transmit Address to Slave A7A6A5A4A3A2A1 SSPBUF written with 7-bit address anstart transmit 1234567 Cleared in software SSPBUF written After START condition SEN cleared by Sc ST Write STAR S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS30221C-page 68 © 2006 Microchip Technology Inc.

PIC16F872 9.2.12 I2C MASTER MODE RECEPTION 9.2.12.1 BF Status Flag Master mode reception is enabled by programming the In receive operation, BF is set when an address or data receive enable bit, RCEN (SSPCON2<3>). byte is loaded into SSPBUF from SSPSR. It is cleared when SSPBUF is read. Note: The SSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit 9.2.12.2 SSPOV Status Flag will be disregarded. In receive operation, SSPOV is set when 8 bits are The baud rate generator begins counting, and on each received into the SSPSR, and the BF flag is already set rollover, the state of the SCL pin changes (high to low/ from a previous reception. low to high), and data is shifted into the SSPSR. After 9.2.12.3 WCOL Status Flag the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the If the user writes the SSPBUF when a receive is SSPSR are loaded into the SSPBUF, the BF flag is set, already in progress (i.e., SSPSR is still shifting in a data the SSPIF is set, and the baud rate generator is sus- byte), then WCOL is set and the contents of the buffer pended from counting, holding SCL low. The SSP is are unchanged (the write doesn’t occur). now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag is automati- cally cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). © 2006 Microchip Technology Inc. DS30221C-page 69

PIC16F872 FIGURE 9-15: I2C MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from masterster configured as a receiverSDA = ACKDT = 1 SDA = ACKDT = 0 programming SSPCON2<3> (RCEN = 1)PEN bit = 1RCEN = 1, startRCEN clearedRCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer967898756512343124PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Maby ve CK CK from sla R/W = 1 A 98 A A1 7 Write to SSPCON2<0>(SEN = 1),begin START Condition SEN = 0Write to SSPBUF occurs hereStart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSPIF Cleared in softwareSDA = 0, SCL = 1,while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN DS30221C-page 70 © 2006 Microchip Technology Inc.

PIC16F872 9.2.13 ACKNOWLEDGE SEQUENCE sampled high (clock arbitration), the baud rate genera- TIMING tor counts for TBRG. The SCL pin is then pulled low. Fol- lowing this, the ACKEN bit is automatically cleared, the An Acknowledge sequence is enabled by setting the baud rate generator is turned off, and the SSP module Acknowledge sequence enable bit, ACKEN then goes into IDLE mode (Figure9-16). (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit 9.2.13.1 WCOL Status Flag are presented on the SDA pin. If the user wishes to gen- If the user writes the SSPBUF when an acknowledge erate an Acknowledge, the ACKDT bit should be sequence is in progress, the WCOL is set and the con- cleared. If not, the user should set the ACKDT bit before tents of the buffer are unchanged (the write doesn’t starting an Acknowledge sequence. The baud rate gen- occur). erator then counts for one rollover period (TBRG), and the SCL pin is de-asserted high). When the SCL pin is FIGURE 9-16: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here. Write to SSPCON2, ACKEN automatically cleared ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Set SSPIF at the end Cleared in Cleared in of receive software software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one baud rate generator period. 9.2.14 STOP CONDITION TIMING Whenever the firmware decides to take control of the bus, it will first determine if the bus is busy by checking A STOP bit is asserted on the SDA pin at the end of a the S and P bits in the SSPSTAT register. If the bus is receive/transmit, by setting the Stop Sequence Enable busy, then the CPU can be interrupted (notified) when bit PEN (SSPCON2<2>). At the end of a receive/ a STOP bit is detected (i.e., bus is free). transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master 9.2.14.1 WCOL Status Flag will assert the SDA line low. When the SDA line is sam- If the user writes the SSPBUF when a STOP sequence pled low, the baud rate generator is reloaded and is in progress, then WCOL is set and the contents of the counts down to 0. When the baud rate generator times buffer are unchanged (the write doesn’t occur). out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure9-17). © 2006 Microchip Technology Inc. DS30221C-page 71

PIC16F872 FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG Write to SSPCON2, after SDA sampled high. P bit (SSPSTAT<4>) is set. set PEN Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition. Note: TBRG = one baud rate generator period. 9.2.15 CLOCK ARBITRATION 9.2.16 SLEEP OPERATION Clock arbitration occurs when the master, during any While in SLEEP mode, the I2C module can receive receive, transmit, or Repeated START/STOP condi- addresses or data, and when an address match or tion, de-asserts the SCL pin (SCL allowed to float high). complete byte transfer occurs, wake the processor When the SCL pin is allowed to float high, the baud rate from SLEEP (if the SSP interrupt is enabled). generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is 9.2.17 EFFECTS OF A RESET sampled high, the baud rate generator is reloaded with A RESET disables the SSP module and terminates the the contents of SSPADD<6:0> and begins counting. current transfer. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure9-18). FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, release SCL. If SCL = 1, load BRG with SSPADD<6:0> and start count BRG overflow occurs, to measure high time interval. release SCL. Slave device holds SCL low. SCL = 1, BRG starts counting clock high interval SCL SCL line sampled once every machine cycle (TOSC • 4). Hold off BRG until SCL is sampled high. SDA TBRG TBRG TBRG DS30221C-page 72 © 2006 Microchip Technology Inc.

PIC16F872 9.2.18 MULTI -MASTER If a START, Repeated START, STOP or Acknowledge COMMUNICATION, condition was in progress when the bus collision BUS COLLISION, AND occurred, the condition is aborted, the SDA and SCL BUS ARBITRATION lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- Multi-Master mode support is achieved by bus arbitra- vices the bus collision Interrupt Service Routine, and if tion. When the master outputs address/data bits onto the I2C bus is free, the user can resume communication the SDA pin, arbitration takes place when the master by asserting a START condition. outputs a '1' on SDA, by letting SDA float high and The master will continue to monitor the SDA and SCL another master asserts a '0'. When the SCL pin floats pins, and if a STOP condition occurs, the SSPIF bit will high, data should be stable. If the expected data on be set. SDA is a '1' and the data sampled on the SDA pin = '0', a bus collision has taken place. The master will set the A write to the SSPBUF will start the transmission of Bus Collision Interrupt Flag, BCLIF and reset the I2C data at the first data bit, regardless of where the trans- port to its IDLE state. (Figure9-19). mitter left off when the bus collision occurred. If a transmit was in progress when the bus collision In Multi-Master mode, the interrupt generation on the occurred, the transmission is halted, the BF flag is detection of START and STOP conditions allows the cleared, the SDA and SCL lines are de-asserted, and determination of when the bus is free. Control of the I2C the SSPBUF can be written to. When the user services bus can be taken when the P bit is set in the SSPSTAT the bus collision Interrupt Service Routine, and if the register, or the bus is IDLE and the S and P bits are I2C bus is free, the user can resume communication by cleared. asserting a START condition. FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDA line pulled low Sample SDA. While SCL is high, Data changes by another source data doesn’t match what is driven while SCL = 0 by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt BCLIF © 2006 Microchip Technology Inc. DS30221C-page 73

PIC16F872 9.2.18.1 Bus Collision During a START If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure9-22). If, however, a '1' is sampled on the SDA During a START condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The baud rate generator is then reloaded and the START condition (Figure9-20). counts down to 0. During this time, if the SCL pins are b) SCL is sampled low before SDA is asserted low. sampled as '0', a bus collision does not occur. At the (Figure9-21). end of the BRG count, the SCL pin is asserted low. During a START condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. If either the SDA pin or the SCL pin during a START condition, is that no two is already low, then these events all occur: bus masters can assert a START condition (cid:129) the START condition is aborted, at the exact same time. Therefore, one master will always assert SDA before the (cid:129) and the BCLIF flag is set other. This condition does not cause a bus (cid:129) and the SSP module is reset to its IDLE state collision, because the two masters must be (Figure9-20). allowed to arbitrate the first address follow- The START condition begins with the SDA and SCL ing the START condition. If the address is pins de-asserted. When the SDA pin is sampled high, the same, arbitration must be allowed to the baud rate generator is loaded from SSPADD<6:0> continue into the data portion, Repeated and counts down to 0. If the SCL pin is sampled low START or STOP conditions. while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. FIGURE 9-20: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START SEN cleared automatically because of bus collision. condition if SDA = 1, SCL=1 SSP module reset into IDLE state. SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS30221C-page 74 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, Bus collision occurs. Set BCLIF. BCLIF Interrupts cleared in software S '0' '0' SSPIF '0' '0' FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL s SCL pulled low after BRG Time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF '0' S SSPIF SDA = 0, SCL = 1 Interrupts cleared Set SSPIF in software. © 2006 Microchip Technology Inc. DS30221C-page 75

PIC16F872 9.2.18.2 Bus Collision During a Repeated SDA is sampled high, the BRG is reloaded and begins START Condition counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two During a Repeated START condition, a bus collision masters can assert SDA at exactly the same time. occurs if: If, however, SCL goes from high to low before the BRG a) A low level is sampled on SDA when SCL goes times out and SDA has not already been asserted, a from low level to high level. bus collision occurs. In this case, another master is b) SCL goes low before SDA is asserted low, indi- attempting to transmit a data’1’ during the Repeated cating that another master is attempting to trans- START condition. mit a data ’1’. If, at the end of the BRG time-out, both SCL and SDA When the user de-asserts SDA and the pin is allowed are still high, the SDA pin is driven low, the BRG is to float high, the BRG is loaded with SSPADD<6:0> reloaded and begins counting. At the end of the count, and counts down to 0. The SCL pin is then de-asserted, regardless of the status of the SCL pin, the SCL pin is and when sampled high, the SDA pin is sampled. If driven low and the Repeated START condition is com- SDA is low, a bus collision has occurred (i.e., another plete (Figure9-23). master is attempting to transmit a data’0’). If, however, FIGURE 9-23: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S '0' '0' SSPIF '0' '0' FIGURE 9-24: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S '0' '0' '0' '0' SSPIF DS30221C-page 76 © 2006 Microchip Technology Inc.

PIC16F872 9.2.18.3 Bus Collision During a STOP The STOP condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a STOP condition if: the baud rate generator is loaded with SSPADD<6:0> a) After the SDA pin has been de-asserted and and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is de-asserted, SCL is sam- drive a data '0'. If the SCL pin is sampled low before pled low before SDA goes high. SDA is allowed to float high, a bus collision occurs. This is a case of another master attempting to drive a data '0' (Figure9-25). FIGURE 9-25: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P '0' '0' SSPIF '0' '0' FIGURE 9-26: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P '0' SSPIF '0' © 2006 Microchip Technology Inc. DS30221C-page 77

PIC16F872 9.3 Connection Considerations for I2C VOL max = 0.4V at 3mA, Rp min = (5.5-0.4)/0.003 = Bus 1.7kΩ. VDD, as a function of Rp, is shown in Figure9-27. The desired noise margin of 0.1 VDD for For standard mode I2C bus devices, the values of the low level limits the maximum value of R. Series s resistors Rp and Rs in Figure9-27 depend on the fol- resistors are optional and used to improve ESD lowing parameters: susceptibility. (cid:129) Supply voltage The bus capacitance is the total capacitance of wire, (cid:129) Bus capacitance connections, and pins. This capacitance limits the max- (cid:129) Number of connected devices imum value of Rp, due to the specified rise time (Figure9-27). (input current + leakage current). The supply voltage limits the minimum value of resistor The SMP bit is the slew rate control enabled bit. This bit R, due to the specified minimum sink current of 3mA is in the SSPSTAT register, and controls the slew rate atp VOL max = 0.4V, for the specified output stages. For of the I/O pins when in I2C mode (master or slave). example, with a supply voltage of VDD = 5V+10% and FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I2C BUS VDD + 10% DEVICE Rp Rp Rs Rs SDA SCL C =10 - 400 pF b Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected. DS30221C-page 78 © 2006 Microchip Technology Inc.

PIC16F872 10.0 ANALOG-TO-DIGITAL The A/D module has four registers. These registers CONVERTER (A/D) MODULE are: (cid:129) A/D Result High Register (ADRESH) The Analog-to-Digital (A/D) Converter module has five (cid:129) A/D Result Low Register (ADRESL) input channels. The analog input charges a sample and (cid:129) A/D Control Register0 (ADCON0) hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter (cid:129) A/D Control Register1 (ADCON1) then generates a digital result of this analog level via The ADCON0 register, shown in Register10-1, con- successive approximation. The A/D conversion of the trols the operation of the A/D module. The ADCON1 analog input signal results in a corresponding 10-bit register, shown in Register10-2, configures the func- digital number. The A/D module has high and low volt- tions of the port pins. The port pins can be configured age reference input that is software selectable to some as analog inputs (RA3 can also be the voltage refer- combination of VDD, VSS, RA2 or RA3. ence), or as digital I/O. The A/D converter has a unique feature of being able Additional information on using the A/D module can be to operate while the device is in SLEEP mode. To oper- found in the PICmicro™ Mid-Range MCU Family Ref- ate in SLEEP, the A/D clock must be derived from the erence Manual (DS33023). A/D’s internal RC oscillator. REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (RA0/AN0) 001 = Channel 1 (RA1/AN1) 010 = Channel 2 (RA2/AN2) 011 = Channel 3 (RA3/AN3) 100 = Channel 4 (RA5/AN4) bit 2 GO/DONE: A/D Conversion Status bit If ADON = 1: 1 =A/D conversion in progress (setting this bit starts the A/D conversion) 0 =A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown © 2006 Microchip Technology Inc. DS30221C-page 79

PIC16F872 REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh) U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’. bit 6-4 Unimplemented: Read as '0' bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: AN4 AN3 AN2 AN1 AN0 CHAN/ PCFG0 RA5 RA3 RA2 RA1 RA0 VREF+ VREF- Refs(1) 0000 A A A A A VDD VSS 8/0 0001 A VREF+ A A A RA3 VSS 7/1 0010 A A A A A VDD VSS 5/0 0011 A VREF+ A A A RA3 VSS 4/1 0100 D A D A A VDD VSS 3/0 0101 D VREF+ D A A RA3 VSS 2/1 011x D D D D D VDD VSS 0/0 1000 A VREF+ VREF- A A RA3 RA2 6/2 1001 A A A A A VDD VSS 6/0 1010 A VREF+ A A A RA3 VSS 5/1 1011 A VREF+ VREF- A A RA3 RA2 4/2 1100 A VREF+ VREF- A A RA3 RA2 3/2 1101 D VREF+ VREF- A A RA3 RA2 2/2 1110 D D D D A VDD VSS 1/0 1111 D VREF+ VREF- D A RA3 RA2 1/2 A = Analog input D = Digital I/O Note 1: This column indicates the number of analog channels available as A/D inputs and the number of analog channels used as voltage reference inputs. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30221C-page 80 © 2006 Microchip Technology Inc.

PIC16F872 The ADRESH:ADRESL registers contain the 10-bit 2. Configure A/D interrupt (if desired): result of the A/D conversion. When the A/D conversion (cid:129) Clear ADIF bit is complete, the result is loaded into this A/D result reg- (cid:129) Set ADIE bit ister pair, the GO/DONE bit (ADCON0<2>) is cleared (cid:129) Set PEIE bit and the A/D interrupt flag bit ADIF is set. The block dia- gram of the A/D module is shown in Figure10-1. (cid:129) Set GIE bit 3. Wait the required acquisition time. After the A/D module has been configured as desired, the selected channel must be acquired before the con- 4. Start conversion: version is started. The analog input channels must (cid:129) Set GO/DONE bit (ADCON0) have their corresponding TRIS bits selected as inputs. 5. Wait for A/D conversion to complete, by either: To determine sample time, see Section10.1. After this (cid:129) Polling for the GO/DONE bit to be cleared acquisition time has elapsed, the A/D conversion can (with interrupts enabled); OR be started. (cid:129) Waiting for the A/D interrupt These steps should be followed for doing an A/D 6. Read A/D Result register pair conversion: (ADRESH:ADRESL), clear bit ADIF if required. 7. For the next conversion, go to step 1 or step 2, 1. Configure the A/D module: as required. The A/D conversion time per bit is (cid:129) Configure analog pins/voltage reference and defined as TAD. digital I/O (ADCON1) (cid:129) Select A/D input channel (ADCON0) (cid:129) Select A/D conversion clock (ADCON0) (cid:129) Turn on A/D module (ADCON0) FIGURE 10-1: A/D BLOCK DIAGRAM CHS2:CHS0 100 RA5/AN4 011 RA3/AN3/VREF+ VAIN 010 RA2/AN2/VREF- (Input Voltage) 001 RA1/AN1 000 RA0/AN0 VDD A/D Converter VREF+ (Reference Voltage) PCFG3:PCFG0 VREF- (Reference Voltage) VSS PCFG3:PCFG0 © 2006 Microchip Technology Inc. DS30221C-page 81

PIC16F872 10.1 A/D Acquisition Requirements decreased. After the analog input channel is selected (changed), this acquisition must be done before the For the A/D converter to meet its specified accuracy, conversion can be started. the charge holding capacitor (CHOLD) must be allowed Equation10-1 may be used to calculate the minimum to fully charge to the input channel voltage level. The acquisition time. This equation assumes that 1/2 LSb analog input model is shown in Figure10-2. The error is used (1024 steps for the A/D). The 1/2 LSb source impedance (RS) and the internal sampling error is the maximum error allowed for the A/D to meet switch (RSS) impedance directly affect the time its specified resolution. required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage To calculate the minimum acquisition time, TACQ, see (VDD), Figure10-2. The maximum recommended the PICmicro™ Mid-Range Reference Manual impedance for analog sources is 10 kΩ. As the (DS33023). impedance is decreased, the acquisition time may be EQUATION 10-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2 μs + TC + [(Temperature -25°C)(0.05 μs/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) - 120 pF (1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885) = 16.47 μs TACQ = 2 μs + 16.47 μs + [(50°C -25°C)(0.05 μs/°C) = 19.72 μs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. FIGURE 10-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC ≤ 1k SS RSS CHOLD VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE == 1D2A0C p cFapacitance VSS Legend CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (kΩ) DS30221C-page 82 © 2006 Microchip Technology Inc.

PIC16F872 10.2 Selecting the A/D Conversion 10.3 Configuring Analog Port Pins Clock The ADCON1, and TRIS registers control the operation The A/D conversion time per bit is defined as TAD. The of the A/D port pins. The port pins that are desired as A/D conversion requires a minimum 12TAD per 10-bit analog inputs must have their corresponding TRIS bits conversion. The source of the A/D conversion clock is set (input). If the TRIS bit is cleared (output), the digital software selected. The four possible options for TAD output level (VOH or VOL) will be converted. are: The A/D operation is independent of the state of the (cid:129) 2TOSC CHS2:CHS0 bits and the TRIS bits. (cid:129) 8TOSC Note 1: When reading the port register, any pin (cid:129) 32TOSC configured as an analog input channel will (cid:129) Internal A/D module RC oscillator (2-6 μs) read as cleared (a low level). Pins config- ured as digital inputs will convert an ana- For correct A/D conversions, the A/D conversion clock log input. Analog levels on a digitally (TAD) must be selected to ensure a minimum TAD time configured input will not affect the conver- of 1.6 μs. sion accuracy. Table10-1shows the resultant TAD times derived from 2: Analog levels on any pin that is defined as the device operating frequencies and the A/D clock a digital input (including the AN7:AN0 source selected. pins), may cause the input buffer to con- sume current that is out of the device specifications. TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C)) AD Clock Source (TAD) Maximum Device Frequency Operation ADCS1:ADCS0 2TOSC 00 1.25 MHz 8TOSC 01 5 MHz 32TOSC 10 20 MHz RC(1, 2, 3) 11 (Note 1) Note 1: The RC source has a typical TAD time of 4 μs, but can vary between 2-6 μs. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom- mended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 14.1 and 14.2). © 2006 Microchip Technology Inc. DS30221C-page 83

PIC16F872 10.4 A/D Conversions In Figure10-3, after the GO bit is set, the first time seg- ment has a minimum of TCY and a maximum of TAD. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register Note: The GO/DONE bit should NOT be set in pair will NOT be updated with the partially completed the same instruction that turns on the A/D. A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. FIGURE 10-3: A/D CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input 10.4.1 A/D RESULT REGISTERS Format Select bit (ADFM) controls this justification. Figure10-4 shows the operation of the A/D result justi- The ADRESH:ADRESL register pair is the location fication. The extra bits are loaded with ’0’s’. When an where the 10-bit A/D result is loaded at the completion A/D result will not overwrite these locations (A/D of the A/D conversion. This register pair is 16-bits wide. disable), these registers may be used as two general The A/D module gives the flexibility to left or right justify purpose 8-bit registers. the 10-bit result in the 16-bit result register. The A/D FIGURE 10-4: A/D RESULT JUSTIFICATION 10-Bit Result ADFM = 1 ADFM = 0 7 2 1 0 7 0 7 0 7 6 5 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified DS30221C-page 84 © 2006 Microchip Technology Inc.

PIC16F872 10.5 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC Note: For the A/D module to operate in SLEEP, (ADCS1:ADCS0 = 11). When the RC clock source is the A/D clock source must be set to RC selected, the A/D module waits one instruction cycle (ADCS1:ADCS0 = 11). To allow the con- before starting the conversion. This allows the SLEEP version to occur during SLEEP, ensure the instruction to be executed, which eliminates all digital SLEEP instruction immediately follows the switching noise from the conversion. When the conver- instruction that sets the GO/DONE bit. sion is completed, the GO/DONE bit will be cleared and 10.6 Effects of a RESET the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from A device RESET forces all registers to their RESET SLEEP. If the A/D interrupt is not enabled, the A/D mod- state. This forces the A/D module to be turned off, and ule will then be turned off, although the ADON bit will any conversion is aborted. All A/D input pins are con- remain set. figured as analog inputs. When the A/D clock source is another clock option (not The value that is in the ADRESH:ADRESL registers is RC), a SLEEP instruction will cause the present conver- not modified for a Power-on Reset. The sion to be aborted and the A/D module to be turned off, ADRESH:ADRESL registers will contain unknown data though the ADON bit will remain set. after a Power-on Reset. TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D POR, MCLR, Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOR WDT 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These bits are reserved; always maintain clear. © 2006 Microchip Technology Inc. DS30221C-page 85

PIC16F872 NOTES: DS30221C-page 86 © 2006 Microchip Technology Inc.

PIC16F872 11.0 SPECIAL FEATURES OF THE 11.1 Configuration Bits CPU The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various The PIC16F872 microcontroller has a host of features device configurations. The erased, or unprogrammed, intended to maximize system reliability, minimize cost value of the configuration word is 3FFFh. These bits through elimination of external components, provide are mapped in program memory location 2007h. power saving operating modes and offer code protec- tion. These are: It is important to note that address 2007h is beyond the user program memory space, which can be accessed (cid:129) Oscillator Selection only during programming. (cid:129) RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) (cid:129) Interrupts (cid:129) Watchdog Timer (WDT) (cid:129) SLEEP (cid:129) Code Protection (cid:129) ID Locations (cid:129) In-Circuit Serial Programming (cid:129) Low Voltage In-Circuit Serial Programming (cid:129) In-Circuit Debugger The microcontrollers have a Watchdog Timer, which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options. Additional information on special features is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). © 2006 Microchip Technology Inc. DS30221C-page 87

PIC16F872 REGISTER 11-1: CONFIGURATION WORD (ADDRESS: 2007h)(1) R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP1 CP0 DEBUG — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 bit 13-12 CP1:CP0: FLASH Program Memory Code Protection bits(2) bit 5-4 11 = Code protection off 10 = Not supported 01 = Not supported 00 = All memory code protected bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger bit 10 Unimplemented: Read as ‘1’ bit 9 WRT: FLASH Program Memory Write Enable bit 1 = Unprotected program memory may be written to by EECON control 0 = Unprotected program memory may not be written to by EECON control bit 8 CPD: Data EEPROM Memory Code Protection bit 1 = Code protection off 0 = Data EEPROM memory code protected bit 7 LVP: Low Voltage In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6 BODEN: Brown-out Reset Enable bit(3) 1 = BOR enabled 0 = BOR disabled bit 3 PWRTE: Power-up Timer Enable bit(3) 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ - n = Value when device is unprogrammed u = Unchanged from programmed state DS30221C-page 88 © 2006 Microchip Technology Inc.

PIC16F872 11.2 Oscillator Configurations FIGURE 11-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR 11.2.1 OSCILLATOR TYPES LP OSC CONFIGURATION) The PIC16F872 can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: Clock from OSC1 (cid:129) LP Low Power Crystal Ext. System PIC16F87X (cid:129) XT Crystal/Resonator Open OSC2 (cid:129) HS High Speed Crystal/Resonator (cid:129) RC Resistor/Capacitor 11.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator TABLE 11-1: CERAMIC RESONATORS is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure11-1). The Ranges Tested: PIC16F872 oscillator design requires the use of a par- Mode Freq OSC1 OSC2 allel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- XT 455 kHz 68 - 100 pF 68 - 100 pF tions. When in XT, LP or HS modes, the device can 2.0 MHz 15 - 68 pF 15 - 68 pF have an external clock source to drive the OSC1/ 4.0 MHz 15 - 68 pF 15 - 68 pF CLKIN pin (Figure11-2). HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF FIGURE 11-1: CRYSTAL/CERAMIC These values are for design guidance only. RESONATOR OPERATION See notes following Table11-2. (HS, XT OR LP OSC CONFIGURATION) Resonators Used: 455 kHz Panasonic EFO-A455K04B ± 0.3% C1(1) OSC1 2.0 MHz Murata Erie CSA2.00MG ± 0.5% To 4.0 MHz Murata Erie CSA4.00MG ± 0.5% Internal XTAL RF(3) Logic 8.0 MHz Murata Erie CSA8.00MT ± 0.5% OSC2 16.0 MHz Murata Erie CSA16.00MX ± 0.5% SLEEP RS(2) All resonators used did not have built-in capacitors. C2(1) PIC16F87X Note 1: See Table11-1 and Table11-2 for recom- mended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen. © 2006 Microchip Technology Inc. DS30221C-page 89

PIC16F872 TABLE 11-2: CAPACITOR SELECTION FOR 11.2.3 RC OSCILLATOR CRYSTAL OSCILLATOR For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator Cap. Crystal Cap. Range frequency is a function of the supply voltage, the resis- Osc Type Range Freq C1 C2 tor (REXT) and capacitor (CEXT) values, and the operat- ing temperature. In addition to this, the oscillator LP 32 kHz 33 pF 33 pF frequency will vary from unit to unit due to normal pro- 200 kHz 15 pF 15 pF cess parameter variation. Furthermore, the difference in lead frame capacitance between package types will XT 200 kHz 47-68 pF 47-68 pF also affect the oscillation frequency, especially for low 1 MHz 15 pF 15 pF CEXT values. The user also needs to take into account 4 MHz 15 pF 15 pF variation due to tolerance of external R and C compo- HS 4 MHz 15 pF 15 pF nents used. Figure11-3 shows how the R/C combina- tion is connected to the PIC16F872. 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF FIGURE 11-3: RC OSCILLATOR MODE These values are for design guidance only. See notes following this table. VDD Crystals Used REXT 32 kHz Epson C-001R32.768K-A ± 20 PPM Internal OSC1 Clock 200 kHz STD XTL 200.000KHz ± 20 PPM 1 MHz ECS ECS-10-13-1 ± 50 PPM CEXT PIC16F87X 4 MHz ECS ECS-40-20-1 ± 50 PPM VSS OSC2/CLKOUT 8 MHz EPSON CA-301 8.000M-C ± 30 PPM FOSC/4 20 MHz EPSON CA-301 20.000M-C ± 30 PPM Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20pF Note 1: Higher capacitance increases the stability of oscillator, but also increases the start- up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PICmicro® devices, oscillator performance should be verified. DS30221C-page 90 © 2006 Microchip Technology Inc.

PIC16F872 11.3 Reset SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the The PIC16F872 differentiates between various kinds of resumption of normal operation. The TO and PD bits RESET: are set or cleared differently in different RESET situa- (cid:129) Power-on Reset (POR) tions, as indicated in Table11-4. These bits are used in (cid:129) MCLR Reset during normal operation software to determine the nature of the RESET. See Table11-6 for a full description of RESET states of all (cid:129) MCLR Reset during SLEEP registers. (cid:129) WDT Reset (during normal operation) A simplified block diagram of the On-Chip Reset circuit (cid:129) WDT Wake-up (during SLEEP) is shown in Figure11-4. (cid:129) Brown-out Reset (BOR) These devices have a MCLR noise filter in the MCLR Some registers are not affected in any RESET condi- Reset path. The filter will detect and ignore small tion. Their status is unknown on POR and unchanged pulses. in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset (POR), on the It should be noted that a WDT Reset does not drive MCLR and WDT Reset, on MCLR Reset during MCLR pin low. FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External RESET MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect VDD Power-on Reset Brown-out Reset S BODEN OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 (1) PWRT On-Chip 10-bit Ripple Counter RC OSC Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. © 2006 Microchip Technology Inc. DS30221C-page 91

PIC16F872 11.4 Power-on Reset (POR) 11.7 Brown-out Reset (BOR) A Power-on Reset pulse is generated on-chip when The configuration bit, BODEN, can enable or disable VDD rise is detected (in the range of 1.2V - 1.7V). To the Brown-out Reset circuit. If VDD falls below VBOR take advantage of the POR, tie the MCLR pin directly (parameter #D005, about 4V) for longer than TBOR (or through a resistor) to VDD. This will eliminate exter- (parameter #35, about 100 μS), the brown-out situation nal RC components usually needed to create a Power- will reset the device. If VDD falls below VBOR for less on Reset. A maximum rise time for VDD is specified. than TBOR, a RESET may not occur. See Electrical Specifications for details. Once the brown-out occurs, the device will remain in When the device starts normal operation (exits the Brown-out Reset until VDD rises above VBOR. The RESET condition), device operating parameters (volt- Power-up Timer then keeps the device in RESET for age, frequency, temperature,...) must be met to ensure TPWRT (parameter #33, about 72 mS). If VDD should fall operation. If these conditions are not met, the device below VBOR during TPWRT, the Brown-out Reset pro- must be held in RESET until the operating conditions cess will restart when VDD rises above VBOR with the are met. Brown-out Reset may be used to meet the Power-up Timer Reset. The Power-up Timer is always start-up conditions. For additional information, refer to enabled when the Brown-out Reset circuit is enabled, Application Note (AN007), “Power-up Trouble regardless of the state of the PWRT configuration bit. Shooting”, (DS00007). 11.8 Time-out Sequence 11.5 Power-up Timer (PWRT) On power-up, the time-out sequence is as follows: the The Power-up Timer provides a fixed 72 ms nominal PWRT delay starts (if enabled) when a POR Reset time-out on power-up only from the POR. The Power- occurs. Then, OST starts counting 1024 oscillator up Timer operates on an internal RC oscillator. The cycles when PWRT ends (LP, XT, HS). When the OST chip is kept in RESET as long as the PWRT is active. ends, the device comes out of RESET. The PWRT’s time delay allows VDD to rise to an accept- If MCLR is kept low long enough, the time-outs will able level. A configuration bit is provided to enable/dis- expire. Bringing MCLR high will begin execution imme- able the PWRT. diately. This is useful for testing purposes or to synchro- The power-up time delay will vary from chip to chip due nize more than one PIC16F872 device operating in to VDD, temperature and process variation. See DC parallel. parameters for details (TPWRT, parameter #33). Table11-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table11-6 11.6 Oscillator Start-up Timer (OST) shows the RESET conditions for all the registers. The Oscillator Start-up Timer (OST) provides a delay of 11.9 Power Control/Status Register 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). This helps to (PCON) ensure that the crystal oscillator or resonator has The Power Control/Status Register, PCON, has two bits. started and stabilized. Bit 0 is the Brown-out Reset Status bit (BOR). Bit BOR The OST time-out is invoked only for XT, LP and HS is unknown on a Power-on Reset. It must then be set modes and only on Power-on Reset or wake-up from by the user and checked on subsequent RESETS to SLEEP. see if bit BOR cleared, indicating a BOR occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. Bit 1 is the Power-on Reset Status bit (POR). It is cleared on a Power-on Reset and unaffected other- wise. The user must set this bit following a Power-on Reset. TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up from Oscillator Configuration Brown-out SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — DS30221C-page 92 © 2006 Microchip Technology Inc.

PIC16F872 TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, MCLR Resets Wake-up via WDT or Register Brown-out Reset WDT Reset Interrupt W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA --0x 0000 --0u 0000 --uu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PORTC xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) PIR1 r0rr 0000 r0rr 0000 rurr uuuu(1) PIR2 -r-0 0--r -r-0 0--r -r-u u--r(1) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table11-5 for RESET value for specific condition. © 2006 Microchip Technology Inc. DS30221C-page 93

PIC16F872 TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, MCLR Resets Wake-up via WDT or Register Brown-out Reset WDT Reset Interrupt TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON --00 0000 --uu uuuu --uu uuuu TMR2 0000 0000 0000 0000 uuuu uuuu T2CON -000 0000 -000 0000 -uuu uuuu SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 0000 0000 0000 0000 uuuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON --00 0000 --00 0000 --uu uuuu ADRESH xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 1111 1111 1111 1111 uuuu uuuu TRISA --11 1111 --11 1111 --uu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu TRISC 1111 1111 1111 1111 uuuu uuuu PIE1 r0rr 0000 r0rr 0000 rurr uuuu PIE2 -r-0 0--r -r-0 0--r -r-u u--r PCON ---- --qq ---- --uu ---- --uu SSPCON2 0000 0000 0000 0000 uuuu uuuu PR2 1111 1111 1111 1111 1111 1111 SSPADD 0000 0000 0000 0000 uuuu uuuu SSPSTAT --00 0000 --00 0000 --uu uuuu ADRESL xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 0--- 0000 0--- 0000 u--- uuuu EEDATA 0--- 0000 0--- 0000 u--- uuuu EEADR xxxx xxxx uuuu uuuu uuuu uuuu EEDATH xxxx xxxx uuuu uuuu uuuu uuuu EEADRH xxxx xxxx uuuu uuuu uuuu uuuu EECON1 x--- x000 u--- u000 u--- uuuu EECON2 ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table11-5 for RESET value for specific condition. DS30221C-page 94 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET © 2006 Microchip Technology Inc. DS30221C-page 95

PIC16F872 FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-8: SLOW RISETIME (MCLR TIED TO VDD VIA RC NETWORK) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30221C-page 96 © 2006 Microchip Technology Inc.

PIC16F872 11.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in The PIC16F872 has 10 sources of interrupt. The inter- the INTCON register. rupt control register (INTCON) records individual inter- The peripheral interrupt flags are contained in the spe- rupt requests in flag bits. It also has individual and cial function registers, PIR1 and PIR2. The correspond- global interrupt enable bits. ing interrupt enable bits are contained in special Note: Individual interrupt flag bits are set, regard- function registers, PIE1 and PIE2, and the peripheral less of the status of their corresponding interrupt enable bit is contained in special function mask bit or the GIE bit. register, INTCON. A global interrupt enable bit, GIE (INTCON<7>), When an interrupt is responded to, the GIE bit is enables (if set) all unmasked interrupts or disables (if cleared to disable any further interrupt, the return cleared) all interrupts. When bit GIE is enabled, and an address is pushed onto the stack and the PC is loaded interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the Interrupt Service Routine, the vector immediately. Individual interrupts can be dis- source(s) of the interrupt can be determined by polling abled through their corresponding enable bits in vari- the interrupt flag bits. The interrupt flag bit(s) must be ous registers. Individual interrupt bits are set, cleared in software before re-enabling interrupts to regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts. cleared on RESET. For external interrupt events, such as the INT pin or The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be the interrupt routine, as well as sets the GIE bit, which three or four instruction cycles. The exact latency re-enables interrupts. depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit FIGURE 11-9: INTERRUPT LOGIC EEIF EEIE ADIF Wake-up (If in SLEEP mode) TMR0IF ADIE TMR0IE INTF SSPIF INTE Interrupt to CPU SSPIE RBIF RBIE CCP1IF CCP1IE PEIE GIE TMR2IF TMR2IE TMR1IF TMR1IE BCLIF BCLIE © 2006 Microchip Technology Inc. DS30221C-page 97

PIC16F872 11.10.1 INT INTERRUPT 11.10.3 PORTB INTCON CHANGE External interrupt on the RB0/INT pin is edge triggered, An input change on PORTB<7:4> sets flag bit RBIF either rising if bit INTEDG (OPTION_REG<6>) is set, (INTCON<0>). The interrupt can be enabled/disabled or falling if the INTEDG bit is clear. When a valid edge by setting/clearing enable bit RBIE (INTCON<4>), see appears on the RB0/INT pin, flag bit INTF Section4.2. (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF 11.11 Context Saving During Interrupts must be cleared in software in the Interrupt Service During an interrupt, only the return PC value is saved Routine before re-enabling this interrupt. The INT inter- on the stack. Typically, users may wish to save key reg- rupt can wake-up the processor from SLEEP, if bit INTE isters during an interrupt, (i.e., W register and STATUS was set prior to going into SLEEP. The status of global register). This will have to be implemented in software. interrupt enable bit GIE, decides whether or not the processor branches to the interrupt vector following Since the upper 16 bytes of each bank are common in wake-up. See Section11.13 for details on SLEEP PIC16F872 devices, temporary holding registers, mode. W_TEMP, STATUS_TEMP and PCLATH_TEMP, should be placed in here. These 16 locations don’t 11.10.2 TMR0 INTERRUPT require banking and therefore, make it easier for con- text save and restore. The same code shown in An overflow (FFh → 00h) in the TMR0 register will set Example11-1 can be used. flag bit TMR0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>), see Section5.0. EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page : :(ISR) ;(Insert user code here) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS30221C-page 98 © 2006 Microchip Technology Inc.

PIC16F872 11.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- The Watchdog Timer is a free running on-chip RC oscil- ues for the WDT prescaler (actually a postscaler, but lator, which does not require any external components. shared with the Timer0 prescaler) may be assigned This RC oscillator is separate from the RC oscillator of using the OPTION_REG register. the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO Note 1: The CLRWDT and SLEEP instructions pins of the device has been stopped, for example, by clear the WDT and the postscaler, if execution of a SLEEP instruction. assigned to the WDT, and prevent it from timing out and generating a device During normal operation, a WDT time-out generates a RESET condition. device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to 2: When a CLRWDT instruction is executed wake-up and continue with normal operation (Watch- and the prescaler is assigned to the WDT, dog Timer Wake-up). The TO bit in the STATUS regis- the prescaler count will be cleared, but ter will be cleared upon a Watchdog Timer time-out. the prescaler assignment is not changed. The WDT can be permanently disabled by clearing configuration bit WDTE (Section11.1). FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure5-1) 0 M Postscaler 1 WDT Timer U X 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure5-1) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. TABLE 11-7: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register11-1 for operation of these bits. © 2006 Microchip Technology Inc. DS30221C-page 99

PIC16F872 11.13 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. Power-down mode is entered by executing a SLEEP When the SLEEP instruction is being executed, the next instruction. instruction (PC + 1) is pre-fetched. For the device to If enabled, the Watchdog Timer will be cleared but wake-up through an interrupt event, the corresponding keeps running, the PD bit (STATUS<3>) is cleared, the interrupt enable bit must be set (enabled). Wake-up is TO (STATUS<4>) bit is set, and the oscillator driver is regardless of the state of the GIE bit. If the GIE bit is turned off. The I/O ports maintain the status they had clear (disabled), the device continues execution at the before the SLEEP instruction was executed (driving instruction after the SLEEP instruction. If the GIE bit is high, low, or hi-impedance). set (enabled), the device executes the instruction after For lowest current consumption in this mode, place all the SLEEP instruction and then branches to the inter- I/O pins at either VDD or VSS, ensure no external cir- rupt address (0004h). In cases where the execution of cuitry is drawing current from the I/O pin, power-down the instruction following SLEEP is not desirable, the the A/D and disable external clocks. Pull all I/O pins user should have a NOP after the SLEEP instruction. that are hi-impedance inputs, high or low externally, to 11.13.2 WAKE-UP USING INTERRUPTS avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest When global interrupts are disabled (GIE cleared) and current consumption. The contribution from on-chip any interrupt source has both its interrupt enable bit pull-ups on PORTB should also be considered. and interrupt flag bit set, one of the following will occur: The MCLR pin must be at a logic high level (VIHMC). (cid:129) If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will com- 11.13.1 WAKE-UP FROM SLEEP plete as a NOP. Therefore, the WDT and WDT The device can wake-up from SLEEP through one of postscaler will not be cleared, the TO bit will not the following events: be set and PD bits will not be cleared. 1. External RESET input on MCLR pin. (cid:129) If the interrupt occurs during or after the execu- tion of a SLEEP instruction, the device will imme- 2. Watchdog Timer wake-up (if WDT was diately wake-up from SLEEP. The SLEEP enabled). instruction will be completely executed before the 3. Interrupt from INT pin, RB port change or wake-up. Therefore, the WDT and WDT Peripheral Interrupt. postscaler will be cleared, the TO bit will be set External MCLR Reset will cause a device RESET. All and the PD bit will be cleared. other events are considered a continuation of program Even if the flag bits were checked before executing a execution and cause a “wake-up”. The TO and PD bits SLEEP instruction, it may be possible for flag bits to in the STATUS register can be used to determine the become set before the SLEEP instruction completes. To cause of device RESET. The PD bit, which is set on determine whether a SLEEP instruction executed, test power-up, is cleared when SLEEP is invoked. The TO the PD bit. If the PD bit is set, the SLEEP instruction bit is cleared if a WDT time-out occurred and caused was executed as a NOP. wake-up. To ensure that the WDT is cleared, a CLRWDT instruc- The following peripheral interrupts can wake the device tion should be executed before a SLEEP instruction. from SLEEP: 1. PSP read or write. 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. CCP Capture mode interrupt. 4. Special event trigger (Timer1 in Asynchronous mode using an external clock). 5. SSP (START/STOP) bit detect interrupt. 6. SSP transmit or receive in Slave mode (SPI/I2C). 7. USART RX or TX (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation completion. DS30221C-page 100 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 11-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Instruction Executed Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 11.14 In-Circuit Debugger 11.15 Program Verification/Code Protection When the DEBUG bit in the configuration word is programmed to a '0', the In-Circuit Debugger function- If the code protection bit(s) have not been pro- ality is enabled. This function allows simple debugging grammed, the on-chip program memory can be read functions when used with MPLAB® IDE. When the out for verification purposes. microcontroller has this feature enabled, some of the resources are not available for general use. Table11-8 11.16 ID Locations shows which features are consumed by the back- ground debugger. Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are TABLE 11-8: DEBUGGER RESOURCES not accessible during normal execution, but are read- I/O pins RB6, RB7 able and writable during program/verify. It is recom- mended that only the 4 Least Significant bits of the ID Stack 1 level location are used. Program Memory Address 0000h must be NOP Last 100h words Data Memory 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB - 0x1EF To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. © 2006 Microchip Technology Inc. DS30221C-page 101

PIC16F872 11.17 In-Circuit Serial Programming If Low Voltage Programming mode is not used, the LVP bit can be programmed to a '0' and RB3/PGM becomes PIC16F872 microcontrollers can be serially pro- a digital I/O pin. However, the LVP bit may only be pro- grammed while in the end application circuit. This is grammed when programming is entered with VIHH on simply done with two lines for clock and data and three MCLR. The LVP bit can only be charged when using other lines for power, ground, and the programming high voltage on MCLR. voltage. This allows customers to manufacture boards It should be noted that once the LVP bit is programmed with unprogrammed devices, and then program the to 0, only the High Voltage Programming mode is avail- microcontroller just before shipping the product. This able and only High Voltage Programming mode can be also allows the most recent firmware or a custom firm- used to program the device. ware to be programmed. When using low voltage ICSP, the part must be sup- When using ICSP, the part must be supplied 4.5V to plied 4.5V to 5.5V if a bulk erase will be executed. This 5.5V if a bulk erase will be executed. This includes includes reprogramming of the code protect bits from reprogramming of the code protect, both from an on- an on-state to off-state. For all other cases of low volt- state to off-state. For all other cases of ICSP, the part age ICSP, the part may be programmed at the normal may be programmed at the normal operating voltages. operating voltage. This means calibration values, This means calibration values, unique user IDs or user unique user IDs, or user code can be reprogrammed or code can be reprogrammed or added. added. For complete details of serial programming, please refer to the EEPROM Memory Programming Specifica- tion for the PIC16F87X (DS39025). 11.18 Low Voltage ICSP Programming The LVP bit of the configuration word enables low volt- age ICSP programming. This mode allows the micro- controller to be programmed via ICSP, using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB3/PGM pin is dedicated to the program- ming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the MCLR pin. To enter Programming mode, VDD must be applied to the RB3/PGM pin, provided the LVP bit is set. The LVP bit defaults to on (‘1’) from the factory. Note 1: The High Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in low voltage ICSP mode, the RB3 pin can no longer be used as a general purpose I/O pin. 3: When using low voltage ICSP program- ming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. DS30221C-page 102 © 2006 Microchip Technology Inc.

PIC16F872 12.0 INSTRUCTION SET SUMMARY For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result The PIC16 instruction set is highly orthogonal and is back to PORTB. This example would have the unin- comprised of three basic categories: tended result that the condition that sets the RBIF flag (cid:129) Byte-oriented operations would be cleared. (cid:129) Bit-oriented operations TABLE 12-1: OPCODE FIELD (cid:129) Literal and control operations DESCRIPTIONS Each PIC16 instruction is a 14-bit word divided into an opcode which specifies the instruction type, and one or Field Description more operands which further specify the operation of f Register file address (0x00 to 0x7F) the instruction. The formats for each of the categories W Working register (accumulator) is presented in Figure12-1, while the various opcode fields are summarized in Table12-1. b Bit address within an 8-bit file register Table13-2 lists the instructions recognized by the k Literal field, constant data or label MPASMTM Assembler. A complete description of each x Don't care location (= 0 or 1). instruction is also available in the PICmicro™ Mid- The assembler will generate code with x = 0. Range Reference Manual (DS33023). It is the recommended form of use for For byte-oriented instructions, ‘f’ represents a file reg- compatibility with all Microchip software tools. ister designator and ‘d’ represents a destination desig- d Destination select; d = 0: store result in W, nator. The file register designator specifies which file d = 1: store result in file register f. register is to be used by the instruction. Default is d = 1. The destination designator specifies where the result of PC Program Counter the operation is to be placed. If ‘d’ is zero, the result is TO Time-out bit placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field FIGURE 12-1: GENERAL FORMAT FOR designator, which selects the bit affected by the opera- INSTRUCTIONS tion, while ‘f’ represents the address of the file in which the bit is located. Byte-oriented file register operations For literal and control operations, ‘k’ represents an 13 8 7 6 0 eight- or eleven-bit constant or literal value OPCODE d f (FILE #) One instruction cycle consists of four oscillator periods; d = 0 for destination W for an oscillator frequency of 4 MHz, this gives a normal d = 1 for destination f f = 7-bit file register address instruction execution time of 1 µs. All instructions are executed within a single instruction cycle, unless a con- ditional test is true or the program counter is changed Bit-oriented file register operations 13 10 9 7 6 0 as a result of an instruction. When this occurs, the exe- cution takes two instruction cycles with the second OPCODE b (BIT #) f (FILE #) cycle executed as a NOP. b = 3-bit bit address f = 7-bit file register address Note: To maintain upward compatibility with future PIC16F872 products, do not use the OPTION and TRIS instructions. Literal and control operations General All instruction examples use the format ‘0xhh’ to repre- sent a hexadecimal number, where ‘h’ signifies a hexa- 13 8 7 0 decimal digit. OPCODE k (literal) k = 8-bit immediate value 12.1 READ-MODIFY-WRITE OPERATIONS CALL and GOTO instructions only Any instruction that specifies a file register as part of 13 11 10 0 the instruction performs a Read-Modify-Write (R-M-W) OPCODE k (literal) operation. The register is read, the data is modified, k = 11-bit immediate value and the result is stored according to either the instruc- tion or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. © 2006 Microchip Technology Inc. DS30221C-page 103

PIC16F872 TABLE 12-2: PIC16F872 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). DS30221C-page 104 © 2006 Microchip Technology Inc.

PIC16F872 12.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 Operation: (W) + k → (W) 0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal 'k' Description: Bit 'b' in register 'f' is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + (f) → (destination) Operation: 1 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit 'b' in register 'f' is set. with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSS f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0 ≤ b < 7 Operation: (W) .AND. (k) → (W) Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit 'b' in register 'f' is '0', the next 'k'. The result is placed in the W instruction is executed. register. If bit 'b' is '1', then the next instruc- tion is discarded and a NOP is executed instead, making this a 2TCY instruction. ANDWF AND W with f BTFSC Bit Test, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) .AND. (f) → (destination) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: AND the W register with register Description: If bit 'b' in register 'f' is '1', the next 'f'. If 'd' is 0, the result is stored in instruction is executed. the W register. If 'd' is 1, the result If bit 'b', in register 'f', is '0', the is stored back in register 'f'. next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction. © 2006 Microchip Technology Inc. DS30221C-page 105

PIC16F872 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, Operation: 00h → WDT k → PC<10:0>, 0 → WDT prescaler, (PCLATH<4:3>) → PC<12:11> 1 → TO 1 → PD Status Affected: None Status Affected: TO, PD Description: Call Subroutine. First, return address (PC+1) is pushed onto Description: CLRWDT instruction resets the the stack. The eleven-bit immedi- Watchdog Timer. It also resets ate address is loaded into PC bits the prescaler of the WDT. Status <10:0>. The upper bits of the PC bits TO and PD are set. are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) d ∈ [0,1] 1 → Z Operation: (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register 'f' are Description: The contents of register 'f' are cleared and the Z bit is set. complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. CLRW Clear W DECF Decrement f Syntax: [ label ] CLRW Syntax: [ label ] DECF f,d Operands: None Operands: 0 ≤ f ≤ 127 Operation: 00h → (W) d ∈ [0,1] 1 → Z Operation: (f) - 1 → (destination) Status Affected: Z Status Affected: Z Description: W register is cleared. Zero bit (Z) Description: Decrement register 'f'. If 'd' is 0, is set. the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. DS30221C-page 106 © 2006 Microchip Technology Inc.

PIC16F872 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are Description: The contents of register 'f' are decremented. If 'd' is 0, the result incremented. If 'd' is 0, the result is is placed in the W register. If 'd' is placed in the W register. If 'd' is 1, 1, the result is placed back in the result is placed back in register 'f'. register 'f'. If the result is 1, the next instruc- If the result is 1, the next instruc- tion is executed. If the result is 0, tion is executed. If the result is 0, then a NOP is executed instead, a NOP is executed instead, making making it a 2TCY instruction. it a 2TCY instruction. GOTO Unconditional Branch IORLW Inclusive OR Literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255 Operation: k → PC<10:0> Operation: (W) .OR. k → (W) PCLATH<4:3> → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal 'k'. The eleven-bit immediate value is The result is placed in the W loaded into PC bits <10:0>. The register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two- cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register 'f' are Description: Inclusive OR the W register with incremented. If 'd' is 0, the result register 'f'. If 'd' is 0, the result is is placed in the W register. If 'd' is placed in the W register. If 'd' is 1, 1, the result is placed back in the result is placed back in register 'f'. register 'f'. © 2006 Microchip Technology Inc. DS30221C-page 107

PIC16F872 MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0 ≤ f ≤ 127 Operands: None d ∈ [0,1] Operation: No operation Operation: (f) → (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. MOVLW Move Literal to W RETFIE Return from Interrupt Syntax: [ label ] MOVLW k Syntax: [ label ] RETFIE Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: TOS → PC, 1 → GIE Status Affected: None Status Affected: None Description: The eight-bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s. MOVWF Move W to f RETLW Return with Literal in W Syntax: [ label ] MOVWF f Syntax: [ label ] RETLW k Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: (W) → (f) Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Move data from W register to register 'f'. Description: The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. DS30221C-page 108 © 2006 Microchip Technology Inc.

PIC16F872 RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 Operands: None d ∈ [0,1] Operation: 00h → WDT, Operation: See description below 0 → WDT prescaler, 1 → TO, Status Affected: C 0 → PD Description: The contents of register 'f' are rotated Status Affected: TO, PD one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in Description: The power-down status bit, PD is the W register. If 'd' is 1, the result is cleared. Time-out status bit, TO stored back in register 'f'. is set. Watchdog Timer and its prescaler are cleared. C Register f The processor is put into SLEEP mode with the oscillator stopped. RETURN Return from Subroutine SUBLW Subtract W from Literal Syntax: [ label ] RETURN Syntax: [ label ] SUBLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC Operation: k - (W) → (W) Status Affected: None Status Affected: C, DC, Z Description: Return from subroutine. The stack Description: The W register is subtracted (2’s is POPed and the top of the stack complement method) from the (TOS) is loaded into the program eight-bit literal 'k'. The result is counter. This is a two-cycle placed in the W register. instruction. RRF Rotate Right f through Carry SUBWF Subtract W from f Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: (f) - (W) → (destination) Status Affected: C Status C, DC, Z Affected: Description: The contents of register 'f' are rotated one bit to the right through Description: Subtract (2’s complement method) the Carry Flag. If 'd' is 0, the result W register from register 'f'. If 'd' is 0, is placed in the W register. If 'd' is the result is stored in the W 1, the result is placed back in register. If 'd' is 1, the result is register 'f'. stored back in register 'f'. C Register f © 2006 Microchip Technology Inc. DS30221C-page 109

PIC16F872 SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), Operation: (W) .XOR. (f) → (destination) (f<7:4>) → (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register 'f'. If 'd' is register 'f' are exchanged. If 'd' is 0, the result is stored in the W 0, the result is placed in the W register. If 'd' is 1, the result is register. If 'd' is 1, the result is stored back in register 'f'. placed in register 'f'. XORLW Exclusive OR Literal with W Syntax: [label] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit lit- eral 'k'. The result is placed in the W register. DS30221C-page 110 © 2006 Microchip Technology Inc.

PIC16F872 13.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: (cid:129) Edit your source files (either assembly or ‘C’) The PICmicro® microcontrollers are supported with a full range of hardware and software development tools: (cid:129) One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- (cid:129) Integrated Development Environment matically updates all project information) - MPLAB® IDE Software (cid:129) Debug using: (cid:129) Assemblers/Compilers/Linkers - source files - MPASMTM Assembler - absolute listing file - MPLAB C17 and MPLAB C18 C Compilers - machine code - MPLINKTM Object Linker/ The ability to use MPLAB IDE with multiple debugging MPLIBTM Object Librarian tools allows users to easily switch from the cost- (cid:129) Simulators effective simulator to a full-featured emulator with - MPLAB SIM Software Simulator minimal retraining. (cid:129) Emulators 13.2 MPASM Assembler - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC™ In-Circuit Emulator The MPASM assembler is a full-featured universal (cid:129) In-Circuit Debugger macro assembler for all PICmicro MCU’s. - MPLAB ICD The MPASM assembler has a command line interface (cid:129) Device Programmers and a Windows shell. It can be used as a stand-alone - PRO MATE® II Universal Device Programmer application on a Windows 3.x or greater system, or it - PICSTART® Plus Entry-Level Development can be used through MPLAB IDE. The MPASM assem- bler generates relocatable object files for the MPLINK Programmer object linker, Intel® standard HEX files, MAP files to (cid:129) Low Cost Demonstration Boards detail memory usage and symbol reference, an abso- - PICDEMTM 1 Demonstration Board lute LST file that contains source lines and generated - PICDEM 2 Demonstration Board machine code, and a COD file for debugging. - PICDEM 3 Demonstration Board The MPASM assembler features include: - PICDEM 17 Demonstration Board (cid:129) Integration into MPLAB IDE projects. - KEELOQ® Demonstration Board (cid:129) User-defined macros to streamline assembly code. 13.1 MPLAB Integrated Development (cid:129) Conditional assembly for multi-purpose source Environment Software files. The MPLAB IDE software brings an ease of software (cid:129) Directives that allow complete control over the development previously unseen in the 8-bit microcon- assembly process. troller market. The MPLAB IDE is a Windows®-based application that contains: 13.3 MPLAB C17 and MPLAB C18 C Compilers (cid:129) An interface to debugging tools - simulator The MPLAB C17 and MPLAB C18 Code Development - programmer (sold separately) Systems are complete ANSI ‘C’ compilers for - emulator (sold separately) Microchip’s PIC17CXXX and PIC18CXXX family of - in-circuit debugger (sold separately) microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not (cid:129) A full-featured editor found with other compilers. (cid:129) A project manager For easier source level debugging, the compilers pro- (cid:129) Customizable toolbar and key mapping vide symbol information that is compatible with the (cid:129) A status bar MPLAB IDE memory display. (cid:129) On-line help © 2006 Microchip Technology Inc. DS30221C-page 111

PIC16F872 13.4 MPLINK Object Linker/ 13.6 MPLAB ICE High Performance MPLIB Object Librarian Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the The MPLAB ICE universal in-circuit emulator is intended MPLAB C17 and MPLAB C18 C compilers. It can also to provide the product development engineer with a link relocatable objects from pre-compiled libraries, complete microcontroller design tool set for PICmicro using directives from a linker script. microcontrollers (MCUs). Software control of the The MPLIB object librarian is a librarian for pre- MPLAB ICE in-circuit emulator is provided by the compiled code to be used with the MPLINK object MPLAB Integrated Development Environment (IDE), linker. When a routine from a library is called from which allows editing, building, downloading and source another source file, only the modules that contain that debugging from a single environment. routine will be linked in with the application. This allows The MPLAB ICE 2000 is a full-featured emulator sys- large libraries to be used efficiently in many different tem with enhanced trace, trigger and data monitoring applications. The MPLIB object librarian manages the features. Interchangeable processor modules allow the creation and modification of library files. system to be easily reconfigured for emulation of differ- The MPLINK object linker features include: ent processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to (cid:129) Integration with MPASM assembler and MPLAB support new PICmicro microcontrollers. C17 and MPLAB C18 C compilers. The MPLAB ICE in-circuit emulator system has been (cid:129) Allows all memory areas to be defined as sections designed as a real-time emulation system, with to provide link-time flexibility. advanced features that are generally found on more The MPLIB object librarian features include: expensive development tools. The PC platform and (cid:129) Easier linking because single libraries can be Microsoft® Windows environment were chosen to best included instead of many smaller files. make these features available to you, the end user. (cid:129) Helps keep code maintainable by grouping 13.7 ICEPIC In-Circuit Emulator related modules together. (cid:129) Allows libraries to be created and modules to be The ICEPIC low cost, in-circuit emulator is a solution added, listed, replaced, deleted or extracted. for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- 13.5 MPLAB SIM Software Simulator Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X The MPLAB SIM software simulator allows code devel- or PIC16CXXX products through the use of inter- opment in a PC-hosted environment by simulating the changeable personality modules, or daughter boards. PICmicro series microcontrollers on an instruction The emulator is capable of emulating without target level. On any given instruction, the data areas can be application circuitry being present. examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debug- ging using the MPLAB C17 and the MPLAB C18 C com- pilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. DS30221C-page 112 © 2006 Microchip Technology Inc.

PIC16F872 13.8 MPLAB ICD In-Circuit Debugger 13.11 PICDEM 1 Low Cost PICmicro Demonstration Board Microchip's In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board based on the FLASH PICmicro MCUs and can be used which demonstrates the capabilities of several of to develop for this and other PICmicro microcontrollers. Microchip’s microcontrollers. The microcontrollers sup- The MPLAB ICD utilizes the in-circuit debugging capa- ported are: PIC16C5X (PIC16C54 to PIC16C58A), bility built into the FLASH devices. This feature, along PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, with Microchip's In-Circuit Serial ProgrammingTM proto- PIC17C42, PIC17C43 and PIC17C44. All necessary col, offers cost-effective in-circuit FLASH debugging hardware and software is included to run basic demo from the graphical user interface of the MPLAB programs. The user can program the sample microcon- Integrated Development Environment. This enables a trollers provided with the PICDEM 1 demonstration designer to develop and debug source code by watch- board on a PROMATE II device programmer, or a ing variables, single-stepping and setting break points. PICSTART Plus development programmer, and easily Running at full speed enables testing hardware in real- test firmware. The user can also connect the time. PICDEM1 demonstration board to the MPLAB ICE in- circuit emulator and download the firmware to the emu- 13.9 PRO MATE II Universal Device lator for testing. A prototype area is available for the Programmer user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features The PRO MATE II universal device programmer is a include an RS-232 interface, a potentiometer for simu- full-featured programmer, capable of operating in lated analog input, push button switches and eight stand-alone mode, as well as PC-hosted mode. The LEDs connected to PORTB. PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has program- 13.12 PICDEM 2 Low Cost PIC16CXX mable VDD and VPP supplies, which allow it to verify Demonstration Board programmed memory at VDD min and VDD max for max- imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem- and error messages, keys to enter commands and a onstration board that supports the PIC16C62, modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74 package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft- device programmer can read, verify, or program ware is included to run the basic demonstration pro- PICmicro devices. It can also set code protection in this grams. The user can program the sample mode. microcontrollers provided with the PICDEM2 demon- stration board on a PRO MATE II device programmer, 13.10 PICSTART Plus Entry Level or a PICSTART Plus development programmer, and Development Programmer easily test firmware. The MPLAB ICE in-circuit emula- tor may also be used with the PICDEM 2 demonstration The PICSTART Plus development programmer is an board to test firmware. A prototype area has been pro- easy-to-use, low cost, prototype programmer. It con- vided to the user for adding additional hardware and nects to the PC via a COM (RS-232) port. MPLAB connecting it to the microcontroller socket(s). Some of Integrated Development Environment software makes the features include a RS-232 interface, push button using the programmer simple and efficient. switches, a potentiometer for simulated analog input, a The PICSTART Plus development programmer sup- serial EEPROM to demonstrate usage of the I2CTM bus ports all PICmicro devices with up to 40 pins. Larger pin and separate headers for connection to an LCD count devices, such as the PIC16C92X and module and a keypad. PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. © 2006 Microchip Technology Inc. DS30221C-page 113

PIC16F872 13.13 PICDEM 3 Low Cost PIC16CXXX 13.14 PICDEM 17 Demonstration Board Demonstration Board The PICDEM 17 demonstration board is an evaluation The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752, PIC16C924 in the PLCC package. It will also support PIC17C756A, PIC17C762 and PIC17C766. All neces- future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs, ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed included to run the basic demonstration programs. The sample is included and the user may erase it and user can program the sample microcontrollers pro- program it with the other sample programs using the vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and development programmer with an adapter socket, and test the sample code. In addition, the PICDEM17 dem- easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports downloading of programs to tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board. board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs include a RS-232 interface, push button switches, a can be run and modified using either emulator. Addition- potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user and separate headers for connection to an external hardware. LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 13.15 KEELOQ Evaluation and commons and 12 segments, that is capable of display- Programming Tools ing time, temperature and day of the week. The KEELOQ evaluation and programming tools support PICDEM 3 demonstration board provides an additional Microchip’s HCS Secure Data Products. The HCS eval- RS-232 interface and Windows software for showing uation kit includes a LCD display to show changing the demultiplexed LCD signals on a PC. A simple serial codes, a decoder to decode transmissions and a pro- interface allows the user to construct a hardware gramming interface to program test transmitters. demultiplexer for the LCD signals. DS30221C-page 114 © 2006 Microchip Technology Inc.

PIC16F872 TABLE 13-1: DEVELOPMENT TOOLS FROM MICROCHIP 7. 0152PCM ! 6, 7 7 4, 7 XXXFRCM ! ! ! ! 73, 2, 7 5, XXXSCH ! ! ! ! 4, 6 6 XXC39 63, //XXXXCC4522 ! ! C62, 6 1 C XXXF81CIP ! ! ! ! ! ! ! ! h PI wit 1) 2XXC81CIP ! ! ! ! ! ! ! 00 4 6 1 V D XX7C71CIP ! ! ! ! ! ! ! er ( g g u X4C71CIP ! ! ! ! ! ! ! eb D uit XX9C61CIP ! ! ! ! ! ! ! Circ n- D I XX8F61CIP ! ! ! ! ! ! C ® I B A L X8C61CIP ! ! ! ! ! ! ! MP e h e t XX7C61CIP ! ! ! ! ! ! us o w t o X7C61CIP ! ! ! ! *! ! ! †! †! n h o n o X26F61CIP ! ! **! **! **! mati or nf XXXC61CIP ! ! ! ! ! ! ! m for i o c p. X6C61CIP ! ! ! ! *! ! ! †! hi c o cr mi XX0X50XC0C462111CCCIIPPIP ®MPLAB Integrated!!!Development Environment ®MPLAB C17 C Compiler ®MPLAB C18 C Compiler TMMPASM Assembler/!!! TMMPLINKObject Linker ®MPLAB ICE In-Circuit Emulator!!! TMICEPIC In-Circuit Emulator!! ®MPLAB ICD In-Circuit Debugger ®PICSTART Plus Entry Level!!!Development Programmer ®PRO MATE II !!!Universal Device Programmer TMPICDEM 1 Demonstration !Board TMPICDEM 2 Demonstration Board TMPICDEM 3 Demonstration Board TMPICDEM 14A Demonstration !Board TMPICDEM 17 Demonstration Board ® KLEvaluation KitEEOQ ®KL Transponder KitEEOQ TMmicroID Programmer’s Kit TM125 kHz microID Developer’s Kit TM125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision TM Developer’s KitmicroID MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at www.Contact Microchip Technology Inc. for availability date.Development tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***† © 2006 Microchip Technology Inc. DS30221C-page 115

PIC16F872 NOTES: DS30221C-page 116 © 2006 Microchip Technology Inc.

PIC16F872 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by PORTA and PORTB....................................................................................................200mA Maximum current sourced by PORTA and PORTB..............................................................................................200mA Maximum current sunk by PORTC.......................................................................................................................200mA Maximum current sourced by PORTC..................................................................................................................200mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. DS30221C-page 117

PIC16F872 FIGURE 14-1: PIC16F872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V e g a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 20 MHz Frequency FIGURE 14-2: PIC16LF872 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V e g 4.0 V a t l o 3.5 V V 3.0 V Equation 2 2.5 V 2.2 V 2.0 V Equation 1 4 MHz 10 MHz 20 MHz Frequency Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz; VDDAPPMIN = 2.2V - 3.0V Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN - 3.0V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz. DS30221C-page 118 © 2006 Microchip Technology Inc.

PIC16F872 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial PIC16F872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device VDD Supply Voltage D001 PIC16LF872 2.2 — 5.5 V LP,XT,RC osc configuration (DC to 4 MHz) D001 PIC16F872 4.0 — 5.5 V LP, XT, RC osc configuration D001A PIC16LF872 4.5 5.5 V HS osc configuration D001A PIC16F872 VBOR 5.5 V BOR enabled, FMAX = 14 MHz(7) D002 VDR RAM Data Retention — 1.5 — V Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See section on Power-on Reset for details ensure internal Power-on Reset signal D004 SVDD VDD Rise Rate to ensure 0.05 — — V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 VBOR Brown-out Reset 3.7 4.0 4.35 V BODEN bit in configuration word enabled Voltage IDD Supply Current(2,5) D010 PIC16LF872 — 0.6 2.0 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V D010 PIC16F872 — 1.6 4 mA RC osc configurations FOSC = 4 MHz, VDD = 5.5V D010A PIC16LF872 — 20 35 μA LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D013 PIC16F872 — 7 15 mA HS osc configuration, FOSC = 20MHz, VDD = 5.5V Legend: Rows with standard voltage device data only are shaded for improved readability. † Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 μA to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The Δ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. © 2006 Microchip Technology Inc. DS30221C-page 119

PIC16F872 14.1 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) PIC16LF872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial PIC16F872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device D015 ΔIBOR Brown-out — 85 200 μA BOR enabled, VDD = 5.0V Reset Current(6) IPD Power-down Current(3,5) D020 PIC16LF872 — 7.5 30 μA VDD = 3.0V, WDT enabled, -40°C to +85°C D020 PIC16F872 — 10.5 42 μA VDD = 4.0V, WDT enabled, -40°C to +85°C D021 PIC16LF872 — 0.9 5 μA VDD = 3.0V, WDT disabled, 0°C to +70°C D021 PIC16F872 — 1.5 16 μA VDD = 4.0V, WDT disabled, -40°C to +85°C D021A PIC16LF872 0.9 5 μA VDD = 3.0V, WDT disabled, -40°C to +85°C D021A PIC16F872 1.5 19 μA VDD = 4.0V, WDT disabled, -40°C to +85°C D023 ΔIBOR Brown-out — 85 200 μA BOR enabled, VDD = 5.0V Reset Current(6) Legend: Rows with standard voltage device data only are shaded for improved readability. † Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 μA to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The Δ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30221C-page 120 © 2006 Microchip Technology Inc.

PIC16F872 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section14.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP modes) VSS - 0.3VDD V (Note 1) Ports RC3 and RC4: D034 with Schmitt Trigger buffer VSS - 0.3VDD V For entire VDD range D034A with SMBus -0.5 - 0.6 V for VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports: - D040 with TTL buffer 2.0 - VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP modes) 0.7VDD - VDD V (Note 1) D043 OSC1 (in RC mode) 0.9VDD - VDD V Ports RC3 and RC4: D044 with Schmitt Trigger buffer 0.7VDD - VDD V For entire VDD range D044A with SMBus 1.4 - 5.5 V for VDD = 4.5 to 5.5V D070 IPURB PORTB Weak Pull-up Current 50 250 400 μA VDD = 5V, VPIN = VSS, -40°C TO +85°C IIL Input Leakage Current(2, 3) D060 I/O ports - - ±1 μA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI - - ±5 μA Vss ≤ VPIN ≤ VDD D063 OSC1 - - ±5 μA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2006 Microchip Technology Inc. DS30221C-page 121

PIC16F872 14.2 DC Characteristics: PIC16F872 (Commercial, Industrial) PIC16LF872 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section14.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080 I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C VOH Output High Voltage D090 I/O ports(3) VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C D150* VOD Open Drain High Voltage - - 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (RC - - 50 pF D102 CB mode) SCL, SDA (I2C mode) - - 400 pF Data EEPROM Memory D120 ED Endurance 100K - - E/W 25°C at 5V D121 VDRW VDD for read/write VMIN - 5.5 V Using EECON to read/write VMIN = min. operating voltage D122 TDEW Erase/write cycle time - 4 8 ms Program FLASH Memory D130 EP Endurance 1000 - - E/W 25°C at 5V D131 VPR VDD for read VMIN - 5.5 V Vmin = min operating voltage D132A VDD for erase/write VMIN - 5.5 V Using EECON to read/write, VMIN = min. operating voltage D133 TPEW Erase/Write cycle time - 4 8 ms * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30221C-page 122 © 2006 Microchip Technology Inc.

PIC16F872 14.3 DC Characteristics: PIC16F872 (Extended) PIC16F872 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Symbol Characteristic/ Min Typ† Max Units Conditions No. Device VDD Supply Voltage D001 4.0 — 5.5 V LP, XT, RC osc configuration D001A 4.5 5.5 V HS osc configuration D001A VBOR 5.5 V BOR enabled, FMAX = 14 MHz(7) D002 VDR RAM Data Retention — 1.5 — V Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See section on Power-on Reset for ensure internal Power-on details Reset signal D004 SVDD VDD Rise Rate to ensure 0.05 — — V/ms See section on Power-on Reset for internal Power-on Reset details signal D005 VBOR Brown-out Reset 3.7 4.0 4.35 V BODEN bit in configuration word Voltage enabled IDD Supply Current(2,5) D010 — 1.6 4 mA RC osc configurations FOSC = 4 MHz, VDD = 5.5V D013 — 7 15 mA HS osc configuration, FOSC = 20MHZ, VDD = 5.5V D015 ΔIBOR Brown-out — 85 200 μA BOR enabled, VDD = 5.0V Reset Current(6) IPD Power-down Current(3,5) D020A 10.5 60 μA VDD = 4.0V, WDT enabled D021B 1.5 30 μA VDD = 4.0V, WDT disabled D023 ΔIBOR Brown-out — 85 200 μA BOR enabled, VDD = 5.0V Reset Current(6) † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 μA to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The Δ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. © 2006 Microchip Technology Inc. DS30221C-page 123

PIC16F872 14.4 DC Characteristics: PIC16F872 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C DC CHARACTERISTICS Operating voltage VDD range as described in DC specification (Section14.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer Vss - 0.15VDD V For entire VDD range D030A Vss - 0.8V V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer Vss - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP modes) VSS - 0.3VDD V (Note1) Ports RC3 and RC4: D034 with Schmitt Trigger buffer Vss - 0.3VDD V For entire VDD range D034A with SMBus -0.5 - 0.6 V for VDD = 4.5 to 5.5V VIH Input High Voltage I/O ports: - D040 with TTL buffer 2.0 - VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP modes) 0.7VDD - VDD V (Note1) D043 OSC1 (in RC mode) 0.9VDD - VDD V Ports RC3 and RC4: D044 with Schmitt Trigger buffer 0.7VDD - VDD V For entire VDD range D044A with SMBus 1.4 - 5.5 V for VDD = 4.5 to 5.5V D070A IPURB PORTB Weak Pull-up Current 50 300 500 μA VDD = 5V, VPIN = VSS, IIL Input Leakage Current(2, 3) D060 I/O ports - - ±1 μA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI - - ±5 μA Vss ≤ VPIN ≤ VDD D063 OSC1 - - ±5 μA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30221C-page 124 © 2006 Microchip Technology Inc.

PIC16F872 14.4 DC Characteristics: PIC16F872 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C DC CHARACTERISTICS Operating voltage VDD range as described in DC specification (Section14.1) Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080A I/O Ports 0.6 V IOL =2.5 mA, VDD = 4.5V D083A OSC2/CLKOUT (RC osc config) 0.6 V IOL = 1.2 mA, VDD = 4.5V VOH Output High Voltage D090A I/O ports(3) VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V D092A OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V D150* VOD Open Drain High Voltage - - 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 - - 50 pF (RC mode) D102 CB SCL, SDA (I2C mode) - - 400 pF Data EEPROM Memory D120 ED Endurance 100K - - E/W 25°C at 5V D121 VDRW VDD for read/write VMIN - 5.5 V Using EECON to read/write VMIN = min. operating voltage D122 TDEW Erase/write cycle time - 4 8 ms Program FLASH Memory D130 EP Endurance 1000 - - E/W 25°C at 5V D131 VPR VDD for read VMIN - 5.5 V VMIN = min. operating voltage D132A VDD for erase/write VMIN - 5.5 V Using EECON to read/write, VMIN = min. operating voltage D133 TPEW Erase/Write cycle time - 4 8 ms * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F872 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2006 Microchip Technology Inc. DS30221C-page 125

PIC16F872 14.5 Timing Parameter Symbology The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 14-3: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464Ω CL = 50pF for all pins except OSC2, but including PORTD and PORTE outputs as ports 15pF for OSC2 output DS30221C-page 126 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 TOSC External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — μs LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 50 — 250 ns HS osc mode (-20) 5 — — μs LP osc mode 2 TCY Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC (Note 1) 3 TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — μs LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. © 2006 Microchip Technology Inc. DS30221C-page 127

PIC16F872 FIGURE 14-5: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure14-3 for load conditions. TABLE 14-2: CLKOUT AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns (Note 1) 11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns (Note 1) 12* TckR CLKOUT rise time — 35 100 ns (Note 1) 13* TckF CLKOUT fall time — 35 100 ns (Note 1) 14* TckL2ioV CLKOUT↓ to Port out valid — — 0.5TCY + 20 ns (Note 1) 15* TioV2ckH Port in valid before CLKOUT↑ TOSC + 200 — — ns (Note 1) 16* TckH2ioI Port in hold after CLKOUT↑ 0 — — ns (Note 1) 17* TosH2ioV OSC1↑ (Q1 cycle) to — 100 255 ns Port out valid 18* TosH2ioI OSC1↑ (Q2 cycle) to Port Standard (F) 100 — — ns input invalid (I/O in hold time) Extended (LF) 200 — — ns 19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20* TIOR Port output rise time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 21* TIOF Port output fall time Standard (F) — 10 40 ns Extended (LF) — — 145 ns 22††* TINP INT pin high or low time TCY — — ns 23††* TRBP RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC. DS30221C-page 128 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure14-3 for load conditions. FIGURE 14-7: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Symbol Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (Low) 2 — — μs VDD = 5V, -40°C to +85°C 31* TWDT Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C (No Prescaler) 32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* TPWRT Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O Hi-Impedance from MCLR Low — — 2.1 μs or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 100 — — μs VDD ≤ VBOR (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. DS30221C-page 129

PIC16F872 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure14-3 for load conditions. TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale 20 or TCY + 40 value (2, 4,..., N 256) 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2,4,8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard(F) 15 — — ns parameter 47 Prescaler = 2,4,8 Extended(LF) 25 — — ns Asynchronous Standard(F) 30 — — ns Extended(LF) 50 — — ns 47* Tt1P T1CKI Input Synchronous Standard(F) Greater of: — — ns N = prescale Period 30 OR TCY + 40 value (1, 2, 4, 8) N Extended(LF) Greater of: N = prescale 50 OR TCY + 40 value (1, 2, 4, 8) N Asynchronous Standard(F) 60 — — ns Extended(LF) 100 — — ns Ft1 Timer1 Oscillator Input Frequency Range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from External Clock Edge to Timer Increment 2TOSC — 7TOSC — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30221C-page 130 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure14-3 for load conditions. TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 51* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns Standard(F) 10 — — ns With Prescaler Extended(LF) 20 — — ns 52* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale N value (1,4 or 16) 53* TccR CCP1 Output Rise Time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 54* TccF CCP1 Output Fall Time Standard(F) — 10 25 ns Extended(LF) — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. DS30221C-page 131

PIC16F872 FIGURE 14-10: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure14-3 for load conditions. FIGURE 14-11: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure14-3 for load conditions. DS30221C-page 132 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 14-12: SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure14-3 for load conditions. FIGURE 14-13: SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure14-3 for load conditions. © 2006 Microchip Technology Inc. DS30221C-page 133

PIC16F872 TABLE 14-6: SPI MODE REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SS↓ to SCK↓ or SCK↑ Input TCY — — ns TssL2scL 71* TscH SCK Input High Time (Slave mode) TCY + 20 — — ns 72* TscL SCK Input Low Time (Slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup Time of SDI Data Input to SCK Edge 100 — — ns TdiV2scL 74* TscH2diL, Hold Time of SDI Data Input to SCK Edge 100 — — ns TscL2diL 75* TdoR SDO Data Output Rise Time Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 76* TdoF SDO Data Output Fall Time — 10 25 ns 77* TssH2doZ SS↑ to SDO Output Hi-Impedance 10 — 50 ns 78* TscR SCK Output Rise Time (Master mode) Standard(F) — 10 25 ns Extended(LF) — 25 50 ns 79* TscF SCK Output Fall Time (Master mode) — 10 25 ns 80* TscH2doV, SDO Data Output Valid after SCK Standard(F) — — 50 ns TscL2doV Edge Extended(LF) — — 145 81* TdoV2scH, SDO Data Output Setup to SCK Edge TCY — — ns TdoV2scL 82* TssL2doV SDO Data Output Valid after SS↓ Edge — — 50 ns 83* TscH2ssH, SS↑ after SCK Edge 1.5TCY + 40 — — ns TscL2ssH * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 14-14: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure14-3 for load conditions. TABLE 14-7: I2C BUS START/STOP BITS REQUIREMENTS Parameter Symbol Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — START condition 91 THD:STA START condition 100 kHz mode 4000 — — ns After this period, the first clock Hold time 400 kHz mode 600 — — pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — DS30221C-page 134 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 14-15: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure14-3 for load conditions. TABLE 14-8: I2C BUS DATA REQUIREMENTS Param Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA START Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs START condition 91 THD:STA START Condition Hold 100 kHz mode 4.0 — μs After this period, the first clock Time 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO STOP Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs 109 TAA Output Valid From 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free before 400 kHz mode 1.3 — μs a new transmission can start CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that TSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line: TR max.+ TSU:DAT=1000+250=1250ns (according to the standard mode I2C bus specification) before the SCL line is released. © 2006 Microchip Technology Inc. DS30221C-page 135

PIC16F872 TABLE 14-9: A/D CONVERTER CHARACTERISTICS: PIC16F872 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LF872 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A06 EOFF Offset Error — — < ± 2 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A07 EGN Gain Error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A10 — Monotonicity — guaranteed(3) — — VSS ≤ VAIN ≤ VREF A20 VREF Reference Voltage (VREF+ - VREF-) 2.0 — VDD + 0.3 V Absolute minimum electrical spec. to ensure 10-bit accuracy. A21 VREF+ Reference Voltage High AVDD - 2.5V AVDD + 0.3V V A22 VREF- Reference Voltage Low AVSS - 0.3V VREF+ - 2.0V V A25 VAIN Analog Input Voltage VSS - 0.3V — VREF + 0.3V V A30 ZAIN Recommended Impedance of — — 10.0 kΩ Analog Voltage Source A40 IAD A/D Conversion Standard — 220 — μA Average current consumption Current (VDD) Extended — 90 — μA when A/D is on (Note 1). A50 IREF VREF Input Current (Note 2) 10 — 1000 μA During VAIN acquisition, based on differential of VHOLD to VAIN to charge CHOLD, see Section10.1. — — 10 μA During A/D conversion cycle. * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS30221C-page 136 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 14-16: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 14-10: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D Clock Period Standard(F) 1.6 — — μs TOSC based, VREF ≥ 3.0V Extended(LF) 3.0 — — μs TOSC based, VREF ≥ 2.0V Standard(F) 2.0 4.0 6.0 μs A/D RC mode Extended(LF) 3.0 6.0 9.0 μs A/D RC mode 131 TCNV Conversion Time (not including S/H time) — 12 TAD (Note 1) 132 TACQ Acquisition Time (Note 2) 40 — μs 10* — — μs The minimum time is the amplifier settling time. This may be used if the "new" input volt- age has not changed by more than 1 LSb (i.e., 20.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D Clock Start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section10.1 for min. conditions. © 2006 Microchip Technology Inc. DS30221C-page 137

PIC16F872 NOTES: DS30221C-page 138 © 2006 Microchip Technology Inc.

PIC16F872 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified oper- ating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean+3σ) or (mean-3σ) respectively, where σ is a standard deviation, over the whole temperature range. FIGURE 15-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 7 Typical: statistical mean @ 25°C 6 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5 5.5V 4 5.0V A) m (D 4.5V D I 3 4.0V 2 3.5V 3.0V 1 2.5V 2.2V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 15-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 8 Typical: statistical mean @ 25°C 7 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 6 5.5V 5 5.0V A) (mD 4 4.5V D I 4.0V 3 3.5V 2 3.0V 1 2.5V 2.2V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) © 2006 Microchip Technology Inc. DS30221C-page 139

PIC16F872 FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.5V 1.2 5.0V 1.0 4.5V A) (mD 0.8 4.0V D I 3.5V 0.6 3.0V 2.5V 0.4 2.2V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.0 Typical: statistical mean @ 25°C 1.8 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.6 5.5V 1.4 5.0V 1.2 4.5V A) m (D 1.0 4.0V D I 0.8 3.5V 3.0V 0.6 2.5V 0.4 2.2V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) DS30221C-page 140 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 15-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 80 5.5V Typical: statistical mean @ 25°C 70 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0V 60 4.5V 50 4.0V A)A) μ (D (uDD 40 3.5V DI I 3.0V 30 2.5V 2.2V 20 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 15-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 110 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3σ (-40°C to 125°C) 100 Minimum: mean – 3σ (-40°C to 125°C) 5.0V 90 80 4.5V 70 A)A) 4.0V μ (D (uDD 60 DI 3.5V I 50 3.0V 40 2.5V 30 2.2V 20 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) © 2006 Microchip Technology Inc. DS30221C-page 141

PIC16F872 FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20pF, 25°C) 4.0 3.3kΩ 3.5 3.0 5.1kΩ 2.5 z) H M q ( 2.0 Fre 10kΩ 1.5 1.0 0.5 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100pF, 25°C) 2.0 1.8 3.3kΩ 1.6 1.4 5.1kΩ 1.2 z) H M q ( 1.0 e Fr 0.8 10kΩ 0.6 0.4 0.2 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30221C-page 142 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 15-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300pF, 25°C) 1.0 0.9 3.3kΩ 0.8 0.7 0.6 5.1kΩ z) H M q ( 0.5 e Fr 0.4 10kΩ 0.3 0.2 0.1 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) MMaaxx ((112255C°C)) 10 MMaaxx ((8855C°C)) A) μ (D 1 P I 0.1 TTyypp ((2255°CC)) 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2006 Microchip Technology Inc. DS30221C-page 143

PIC16F872 FIGURE 15-11: ΔIBOR vs. VDD OVER TEMPERATURE 1.2 Typical: statistical mean @ 25°C Note:Device current in RESET 1.0 Maximum: mean + 3σ (-40°C to 125°C) depends on oscillator mode, Minimum: mean – 3σ (-40°C to 125°C) frequency and circuit. MMaaxx R REeSseEtT 0.8 A) m (R 0.6 O B ΔI TTyypp RREeSseEtT Indeterminate ((2255°CC)) State 0.4 DDeevviiccee iinn SSLleEeEpP DDeevvicicee inin RREeSseEtT 0.2 MMaaxx S SLleEeEpP TTypyp S SLlEeEepP ((2255C°C)) 0.0 2.0 2.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-12: TYPICAL AND MAXIMUM ΔITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2=50pF) 90 80 Typical: statistical mean @ 25°C 70 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 60 A) 50 μ (1 R M ΔIT 40 MMaaxx ( -(1-100°CC)) 30 20 TTyypp ((2255°CC)) 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30221C-page 144 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 15-13: TYPICAL AND MAXIMUM ΔIWDT vs. VDD OVER TEMPERATURE 14 Typical: statistical mean @ 25°C 12 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 10 MMaaxx ( 1(12255°CC)) 8 A) μ (T TTyypp ((2255°CC)) D W ΔI 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD(V) FIGURE 15-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 40 35 ms) 30 MMaaxx ((8855°CC)) d ( o eri 25 P T D W 20 TTyypp ((2255°CC)) 15 MMinin ( (--4400°CC)) 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2006 Microchip Technology Inc. DS30221C-page 145

PIC16F872 FIGURE 15-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C) 50 45 Typical: statistical mean @ 25°C 40 112255°CC Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 35 8855°CC s) 30 m od ( 2255°CC eri 25 P T D W 20 --4400°CC 15 10 5 0 2.0 2.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=5V, -40°C TO +125°C) 5.0 MMaaxx ((--4400C°C)) 4.5 TTyypp ((2255°CC)) 4.0 V) (H 3.5 O V MMiinn ((112255°CC)) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.0 0 5 10 15 20 25 IOH (-mA) DS30221C-page 146 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 15-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=3V, -40°C TO +125°C) 3.0 MMaaxx ((--4400°CC)) Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) TTyypp ((2255°CC)) 2.0 MMinin ( (112255°CC)) V) (H 1.5 O V 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 15-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=5V, -40°C TO 125°C) 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.4 1.2 V) (L 1.0 VO MMaaxx ((112255C°C)) 0.8 0.6 TTyypp ((2255°CC)) 0.4 MMiinn ((--4400°CC)) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) © 2006 Microchip Technology Inc. DS30221C-page 147

PIC16F872 FIGURE 15-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=3V, -40°C TO +125°C) 3.0 Typical: statistical mean @ 25°C 2.5 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 2.0 V) (L 1.5 MMaaxx ((112255°CC)) O V 1.0 TTyypp ((2255C°C)) 0.5 MMiinn ((--4400°CC)) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 15-20: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO +125°C) 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 1.4 Max 1.2 Min 1.0 V) (N VI 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30221C-page 148 © 2006 Microchip Technology Inc.

PIC16F872 FIGURE 15-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.5 4.0 Typical: statistical mean @ 25°C 3.5 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max High 3.0 Min High 2.5 V) (N VI 2.0 Max Low 1.5 Min Low 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C) 3.5 Typical: statistical mean @ 25°C Max High 3.0 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Min High 2.5 2.0 V) (N VI 1.5 Max Low Min Low 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2006 Microchip Technology Inc. DS30221C-page 149

PIC16F872 NOTES: DS30221C-page 150 © 2006 Microchip Technology Inc.

PIC16F872 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC16F872/SPe3 XXXXXXXXXXXXXXXXX 0610017 YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC16F872-I/SOe3 XXXXXXXXXXXXXXXXXXXX 0610017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX PIC16LF872 XXXXXXXXXXXX -I/SSe3 YYWWNNN 0610017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. DS30221C-page 151

PIC16F872 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A2 A L c β A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 DS30221C-page 152 © 2006 Microchip Technology Inc.

PIC16F872 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top φ 0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 © 2006 Microchip Technology Inc. DS30221C-page 153

PIC16F872 28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 A c A2 φ A1 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .026 0.65 Overall Height A - - .079 - - 2.00 Molded Package Thickness A2 .065 .069 .073 1.65 1.75 1.85 Standoff A1 .002 - - 0.05 - - Overall Width E .295 .307 .323 7.49 7.80 8.20 Molded Package Width E1 .197 .209 .220 5.00 5.30 5.60 Overall Length D .390 .402 .413 9.90 10.20 10.50 Foot Length L .022 .030 .037 0.55 0.75 0.95 Lead Thickness c .004 - .010 0.09 - 0.25 Foot Angle φ 0° 4° 8° 0° 4° 8° Lead Width B .009 - .015 0.22 - 0.38 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-073 Revised 1-12-06 DS30221C-page 154 © 2006 Microchip Technology Inc.

PIC16F872 APPENDIX A: REVISION HISTORY APPENDIX B: CONVERSION CONSIDERATIONS Version Date Revision Description Considerations for converting from previous versions A 11/99 This is a new data sheet (Pre- of devices to the ones listed in this data sheet are listed liminary). However, these in TableB-1. devices are similar to the PIC16C72A devices found in TABLE B-1: CONVERSION the PIC16C62B/72A Data CONSIDERATIONS Sheet (DS35008). B 12/01 Final version of data sheet. Characteristic PIC16C72A PIC16F872 Includes DC and AC charac- teristics graphs and updated Pins 28 28 electrical specifications. C 9/06 Packaging diagrams updated. Timers 3 3 Interrupts 7 10 Communication Basic SSP SSP (SPI, I2C (SPI, I2C Master/Slave) Slave) Frequency 20 MHz 20 MHz A/D 8-bit, 10-bit 5 channels 5 channels CCP 1 1 Program 2K EPROM 2K FLASH Memory RAM 128 bytes 128 bytes EEPROM Data None 64 bytes Other ⎯ In-Circuit Debugger, Low Voltage Programming © 2006 Microchip Technology Inc. DS30221C-page 155

PIC16F872 NOTES: DS30221C-page 156 © 2006 Microchip Technology Inc.

PIC16F872 INDEX A PWM Mode ...............................................................48 RA3:RA0 and RA5 Pins ............................................29 A/D .....................................................................................79 RA4/T0CKI Pin ..........................................................29 Acquisition Requirements ..........................................82 RB3:RB0 Pins ...........................................................31 ADCON0 Register .....................................................79 RB7:RB4 Pins ...........................................................31 ADCON1 Register .....................................................79 RC Oscillator Mode ...................................................90 ADIF Bit .............. .......................................................81 SSP (I2C Master Mode) ............................................63 ADRESH Register .....................................................79 Timer0/WDT Prescaler ..............................................35 ADRESL Register ......................................................79 Timer1 .......................................................................40 Associated Registers and Bits ...................................85 Timer2 .......................................................................43 Configuring Analog Port Pins ....................................83 Watchdog Timer ........................................................99 Configuring the Interrupt ............................................81 BOR. See Brown-out Reset Configuring the Module .............................................81 , , , Brown-out Reset (BOR) ................................87 91 92 93 Conversion Clock ......................................................83 Bus Arbitration ...................................................................73 Conversions ...............................................................84 Bus Collision Effects of a RESET ....................................................85 Section ......................................................................73 GO/DONE Bit ............................................................81 Bus Collision During a Repeated START Condition .........76 Internal Sampling Switch (Rss) Impedance ...............82 Bus Collision During a START Condition ..........................74 Operation During SLEEP ...........................................85 Bus Collision During a STOP Condition ............................77 Result Registers ........................................................84 Bus Collision Interrupt Flag (BCLIF) ..................................18 Source Impedance ....................................................82 TAD ............................................................................83 C Absolute Maximum Ratings .............................................117 Capture Mode ACK pulse ..........................................................................59 CCP Pin Configuration ..............................................46 ACKDT Bit Software Interrupt ......................................................46 Acknowledge Data Bit (ACKDT) ................................54 Timer1 Mode Selection .............................................46 ACKEN Bit Capture/Compare/PWM (CCP) .........................................45 Acknowledge Sequence Enable Bit (ACKEN) ...........54 Associated Registers ................................................47 Acknowledge Pulse (ACK) .................................................59 PWM and Timer2 ..............................................49 ACKSTAT Bit Capture Mode ...........................................................46 Acknowledge Status Bit (ACKSTAT) .........................54 CCP1IF .............................................................46 ACKSTAT Status Flag .......................................................67 Prescaler ...........................................................46 ADCON0 Register ...............................................................9 CCP Timer Resources ..............................................45 ADCON1 Register .............................................................10 Compare Mode .........................................................47 ADRESH Register ...............................................................9 Software Interrupt Mode ....................................47 ADRESL Register ..............................................................10 Special Event Trigger ........................................47 Analog-to-Digital Converter. See A/D PWM Mode ...............................................................48 Application Notes Duty Cycle .........................................................48 AN552 (Implementing Wake-up on Key Stroke) ........31 Example Frequencies/ AN556 (Implementing a Table Read) ........................20 Resolutions (Table) ...........................49 AN578 (Use of the SSP Module in the I2C PWM Period ......................................................48 Multi-Master Environment) ........................58 Special Event Trigger and A/D Conversions .............47 Assembler CCP. See Capture/Compare/PWM MPASM Assembler .................................................111 CCP1CON Register ............................................................9 B CCP1M3:CCP1M0 bits ......................................................45 CCP1X bit ..........................................................................45 Banking, Data Memory ........................................................7 CCP1Y bit ..........................................................................45 BCLIF Bit ...........................................................................18 , CCPR1H Register .........................................................9 45 BF Bit , CCPR1L Register ..........................................................9 45 Buffer Full Status Bit (BF) ..........................................52 , CKE Bit ..............................................................................52 BF Status Flag ............................................................67 69 CKP Bit ..............................................................................53 Block Diagrams Clock Polarity Select Bit (CKP) .........................................53 A/D Converter ............................................................81 Code Examples Analog Input Model ....................................................82 Changing Between Capture Prescalers ....................46 Baud Rate Generator ................................................64 EEPROM Data Read ................................................25 Capture Mode ............................................................46 EEPROM Data Write .................................................25 Compare Mode ..........................................................47 I2C Slave Mode .........................................................58 FLASH Program Read ..............................................26 FLASH Program Write ..............................................27 Interrupt Logic ............................................................97 Indirect Addressing ...................................................21 MSSP (SPI Mode) .....................................................55 Initializing PORTA .....................................................29 On-Chip Reset Circuit ................................................91 Saving STATUS, W and PCLATH Registers ............98 Peripheral Output Override (RC 2:0, 7:5) ..................33 Code Protected Operation Peripheral Output Override (RC 4:3) .........................33 Data EEPROM and FLASH Program Memory ..........28 PIC16F872 ..................................................................4 © 2006 Microchip Technology Inc. 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PIC16F872 Code Protection ........................................................87, 101 I Compare Mode I/O Ports ............................................................................29 CCP Pin Configuration ...............................................47 I2C Bus Timer1 Mode Selection ..............................................47 Connection Considerations .......................................78 Computed GOTO ...............................................................20 Sample Device Configuration ....................................78 Configuration Bits . .............................................................87 I2C Mode Configuration Word ............................................................88 Acknowledge Sequence Timing ................................71 Conversion Considerations ..............................................155 Addressing ................................................................59 D Associated Registers .................................................62 Baud Rate Generator (BRG) .....................................64 D/A Bit ................................................................................52 Bus Arbitration ...........................................................73 Data EEPROM ...................................................................23 Bus Collision ..............................................................73 Associated Registers .................................................28 Repeated START Condition ..............................76 Code Protection .........................................................28 START Condition ..............................................74 Reading .....................................................................25 STOP Condition ................................................77 Special Functions Registers ......................................23 Clock Arbitration ........................................................72 Spurious Write Protection ..........................................27 Conditions to not give ACK Pulse .............................59 Write Verify ................................................................27 , Effects of a RESET .............................................62 72 Writing to ....................................................................25 General Call Address Support ...................................61 Data Memory .......................................................................7 Master Mode .............................................................63 Bank Select (RP1:RP0 Bits) ........................................7 Master Mode Operation .............................................64 General Purpose Register File ....................................7 Master Mode Reception ............................................69 Register File Map .........................................................8 Master Mode Repeated START Condition ................66 Special Function Registers ..........................................9 Master Mode START Condition ................................65 Data/Address Bit (D/A) ......................................................52 Master Mode Transmission .......................................67 DC and AC Characteristics Graphs and Tables ..............139 Master Mode Transmit Sequence .............................64 DC Characteristics Multi-Master Communication .....................................73 Commercial and Industrial ...............................119–122 Multi-Master Mode .....................................................63 Extended ............................................................123–52 Operation ...................................................................58 Development Support ......................................................111 Slave Mode ...............................................................58 Device Overview ..................................................................3 Slave Reception ........................................................59 Direct Addressing ..............................................................21 Slave Transmission ...................................................60 E SLEEP Operation ................................................62, 72 SSPADD Address Register .......................................58 EECON1 and EECON2 Registers .....................................23 SSPBUF Register ......................................................58 EECON1 Register ..............................................................11 STOP Condition Timing .............................................71 EECON2 Register ..............................................................11 ICEPIC In-Circuit Emulator ..............................................112 Electrical Characteristics .................................................117 , ID Locations ..............................................................87 101 Equations , In-Circuit Debugger ...................................................87 101 A/D , In-Circuit Serial Programming (ICSP) .......................87 102 Calculating Acquisition Time .............................82 INDF Register ......................................................................9 Errata ...................................................................................2 Indirect Addressing ............................................................21 External Clock Timing Requirements ..............................127 , FSR Register .........................................................7 21 F Instruction Format ...........................................................103 Firmware Instructions ......................................................103 Instruction Set .................................................................103 FLASH Program Memory ..................................................23 ADDLW ...................................................................105 Associated Registers .................................................28 ADDWF ...................................................................105 Code Protection .........................................................28 ANDLW ...................................................................105 Configuration Bits and Read/Write State ...................28 ANDWF ...................................................................105 Reading .....................................................................26 BCF .........................................................................105 Special Function Registers ........................................23 BSF .........................................................................105 Spurious Write Protection ..........................................27 BTFSC .....................................................................105 Write Protection .........................................................28 BTFSS .....................................................................105 CALL .......................................................................106 Write Verify ................................................................27 Writing to ....................................................................26 CLRF .......................................................................106 FSR Register ................................................................9, 21 CLRW ......................................................................106 CLRWDT .................................................................106 G COMF ......................................................................106 GCEN Bit DECF .......................................................................106 General Call Enable Bit (GCEN) ................................54 DECFSZ ..................................................................107 General Call Address Support ...........................................61 GOTO ......................................................................107 INCF ........................................................................107 INCFSZ ...................................................................107 IORLW .....................................................................107 IORWF ....................................................................107 DS30221C-page 158 © 2006 Microchip Technology Inc.

PIC16F872 MOVF ......................................................................108 M MOVLW ...................................................................108 Master Clear (MCLR) MOVWF ...................................................................108 , MCLR Reset, Normal Operation .........................91 93 NOP .........................................................................108 , MCLR Reset, SLEEP ..........................................91 93 RETFIE ....................................................................108 Master Synchronous Serial Port. See MSSP RETLW ....................................................................108 MCLR/VPP Pin .....................................................................5 RETURN ..................................................................109 Memory Organization ..........................................................7 RLF ..........................................................................109 Data Memory ...............................................................7 RRF .........................................................................109 Program Memory ........................................................7 SLEEP .....................................................................109 MPLAB C17 and MPLAB C18 C Compilers ....................111 SUBLW ....................................................................109 MPLAB ICD In-Circuit Debugger .....................................113 SUBWF ....................................................................109 MPLAB ICE High Performance Universal In-Circuit SWAPF ....................................................................110 Emulator with MPLAB IDE ......................................112 XORLW ...................................................................110 MPLAB Integrated Development XORWF ...................................................................110 Environment Software .............................................111 Summary Table .......................................................104 MPLINK Object Linker/MPLIB Object Librarian ...............112 INT Interrupt (RB0/INT). See Interrupt Sources , MSSP ................................................................................51 INTCON Reg ister ..........................................................9 14 I2C Operation ............................................................58 GIE Bit .......................................................................14 Overflow Detect Bit (SSPOV) ....................................59 INTE Bit .....................................................................14 Special Function Registers INTF Bit .....................................................................14 SSPCON ...........................................................51 PEIE Bit .....................................................................14 SSPCON2 .........................................................51 RBIE Bit .....................................................................14 , SSPSTAT ..........................................................51 RBIF Bit ..............................................................14 31 SPI Master Mode ......................................................55 TMR0IE Bit ................................................................14 SPI Mode ..................................................................55 TMR0IF Bit ................................................................14 Inter-Integrated Circuit (I2C) ..............................................51 SPI Slave Mode ........................................................56 SSPADD ...................................................................59 Internal Sampling Switch (Rss) Impedance .......................82 , SSPADD Register .....................................................58 Interrupt Sources ........................................................87 97 SSPBUF ....................................................................55 Interrupt-on-Change (RB7:RB4 ) ...............................31 SSPBUF Register .....................................................58 RB0/INT Pin, External ...............................................98 , SSPSR ................................................................55 59 TMR0 Overflow ..........................................................98 SSPSTAT Register ...................................................58 Interrupts Multi-Master Communication .............................................73 Bus Collision Interrupt ...............................................18 Synchronous Serial Port Interrupt .............................16 O Interrupts, Context Saving During ......................................98 OPCODE Field Descriptions ...........................................103 Interrupts, Enable Bits OPTION_REG Register ..............................................10, 13 Global Interrupt Enable (GIE Bit) ...............................97 INTEDG Bit ...............................................................13 Interrupt-on-Change (RB7:RB4) Enable PS2:PS0 Bits .............................................................13 (RBIE Bit) ..................................................98 PSA Bit ......................................................................13 Interrupts, Flag Bits RBPU Bit ...................................................................13 Interrupt-on-Change (RB7:RB4) Flag T0CS Bit ....................................................................13 (RBIF Bit) ............................................31, 98 T0SE Bit ....................................................................13 TMR0 Overflow Flag (TMR0IF Bit) ............................98 OSC1/CLKI Pin ...................................................................5 K OSC2/CLKO Pin ..................................................................5 Oscillator Configuration KEELOQ Evaluation and Programming Tools ...................114 HS .......................................................................89, 92 , L LP ........................................................................89 92 , , RC ................................................................89 90 92 Load Conditions ...............................................................126 , XT ........................................................................89 92 Loading of PC ....................................................................20 Oscillator Selection ............................................................87 Low Voltage ICSP Programming .....................................102 Oscillator, WDT .................................................................99 Low Voltage In-Circuit Serial Programming .......................87 Oscillators Capacitor Selection ...................................................90 Crystal and Ceramic Resonators ..............................89 RC .............................................................................90 © 2006 Microchip Technology Inc. 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PIC16F872 P Program Memory Interrupt Vector ............................................................7 P Bit Paging .......................................................................20 STOP Bit (P) ..............................................................52 – Program Memory Map and Stack ................................7 Packaging ...............................................................151 154 , , RESET Vector .............................................................7 PCL Register ..........................................................9 10 20 , Program Verification ........................................................101 PCLATH Register .........................................................9 20 , , Programming, Device Instructions ..................................103 PCON Register .....................................................10 19 92 Pulse Width Modulation.See Capture/Compare/PWM, BOR Bit ......................................................................19 PWM Mode. POR Bit ......................................................................19 PUSH ................................................................................20 PEN Bit PWM Mode STOP Condition Enable Bit (PEN) .............................54 Setup .........................................................................49 PICDEM 1 Low Cost PICmicro Demonstration Board ...............................................113 R PICDEM 17 Demonstration Board ...................................114 R/W Bit ..............................................................................59 PICDEM 2 Low Cost PIC16CXX Read/Write Bit Information (R/W) ..............................52 Demonstration Board ...............................................113 R/W Bit ..............................................................................59 PICDEM 3 Low Cost PIC16CXXX RA0/AN0 Pin .......................................................................5 Demonstration Board ...............................................114 RA1/AN1 Pin .......................................................................5 PICSTART Plus Entry Level Development RA2/AN2/VREF- Pin .............................................................5 Programmer .............................................................113 , RA3/AN3/VREF+ Pin ............................................................5 PIE1 Register ..............................................................10 15 , RA4/T0CKI Pin ....................................................................5 PIE2 Register ..............................................................10 17 – RA5/SS/AN4 Pin .................................................................5 Pinout Descriptions .........................................................5 6 , RAM. See Data Memory PIR1 Register ...............................................................9 16 , RB0/INT Pin ........................................................................6 PIR2 Register ...............................................................9 18 RB1 Pin ...............................................................................6 POP ...................................................................................20 RB2 Pin ...............................................................................6 POR. See Power-on Reset RB3/PGM Pin ......................................................................6 PORTA ................................................................................5 RB4 Pin ...............................................................................6 Associated Registers .................................................30 RB5 Pin ...............................................................................6 Functions ...................................................................30 , RB6/PGC Pin ......................................................................6 PORTA Register ...................................................9 29 RB7/PGD Pin ......................................................................6 RA3 RC0/T1OSO/T1CKI Pin .......................................................6 RA0 and RA5 Port Pins .....................................29 RC1/T1OSI Pin ....................................................................6 TRISA Register ..........................................................29 RC2/CCP1 Pin ....................................................................6 PORTB ................................................................................6 RC3/SCK/SCL Pin ...............................................................6 Associated Registers .................................................32 RC4/SDI/SDA Pin ................................................................6 Functions ...................................................................32 , RC5/SDO Pin ......................................................................6 PORTB Register ...................................................9 31 RC6 Pin ...............................................................................6 RB0/INT Pin, External ................................................98 RC7 Pin ...............................................................................6 RB7:RB4 Interrupt-on-Change ..................................98 RCEN Bit RB7:RB4 Interrupt-on-Change Enable Receive Enable Bit (RCEN) ......................................54 (RBIE Bit) ...................................................98 Receive Overflow Indicator Bit (SSPOV) ..........................53 RB7:RB4 Interrupt-on-Change Flag , Registers (RBIF Bit) ............................................31 98 , ADCON0 (A/D Control 0) Register ............................79 TRISB Register ...................................................11 31 ADCON1 (A/D Control 1) Register ............................80 PORTC ................................................................................6 CCP1CON (CCP Control 1) Register ........................45 Associated Registers .................................................34 EECON1 (EEPROM Control) Register ......................24 Functions ...................................................................34 , INTCON Register ......................................................14 PORTC Register ...................................................9 33 , OPTION_REG Register ......................................13 36 TRISC Register ..........................................................33 PCON (Power Control) Register ...............................19 Power-down Mode. See SLEEP , , , PIE1 (Peripheral Interrupt Enable 1) Register ...........15 Power-on Reset (POR) ..................................87 91 92 93 , PIE2 (Peripheral Interrupt Enable 2) Register ...........17 Oscillator Start-up Timer (OST) ..........................87 92 PIR1 (Peripheral Interrupt Request 1) Register ........16 Power Control (PCON) Register ................................92 PIR2 (Peripheral Interrupt Request 2) Register ........18 Power-down (PD Bit) .................................................91 , Special Function, Summary ........................................9 Power-up Timer (PWRT) ....................................87 92 SSPCON (Sync Serial Port Control) Register ...........53 Time-out (TO Bit) .......................................................91 SSPCON2 (Sync Serial Port Control 2) Register ......54 Time-out Sequence on Power-up ..............................96 , SSPSTAT (Sync Serial Port Status) Register ...........52 PR2 Register ..............................................................10 43 STATUS Register ......................................................12 PRO MATE II Universal Device Programmer ..................113 T1CON (Timer1 Control) Register .............................39 Program Counter T2CON (Timer 2 Control) Register ............................43 RESET Conditions .....................................................93 DS30221C-page 160 © 2006 Microchip Technology Inc.

PIC16F872 , , RESET ........................................................................87 91 STATUS Register ..........................................................9 12 RESET Conditions for All Registers ..........................93 C Bit ..........................................................................12 RESET Conditions for PCON Register ......................93 DC Bit ........................................................................12 RESET Conditions for Program Counter ...................93 IRP Bit .......................................................................12 , RESET Conditions for Special Registers ..................93 PD Bit ..................................................................12 91 RESET Conditions for STATUS Register ..................93 RP1:RP0 Bits ............................................................12 , RESET TO Bit ..................................................................12 91 Brown-out Reset (BOR). See Brown-out Reset (BOR) Z Bit ...........................................................................12 MCLR Reset. See MCLR Synchronous Serial Port Enable Bit (SSPEN) ...................53 Power-on Reset (POR). See Power-on Reset (POR) Synchronous Serial Port Interrupt .....................................16 WDT Reset. See Watchdog Timer (WDT) Synchronous Serial Port Mode Select Bits Revision History ...............................................................155 (SSPM3:SSPM0) ......................................................53 RSEN Bit T Repeated START Condition Enabled Bit (RSEN) .....54 T1CKPS0 bit ......................................................................39 S T1CKPS1 bit ......................................................................39 S Bit T1CON Register ..................................................................9 START Bit (S) ............................................................52 T1OSCEN bit .....................................................................39 Sample Bit (SMP) ..............................................................52 T1SYNC bit .......................................................................39 SCK Pin .............................................................................55 T2CON Register ..................................................................9 SCL Pin ..............................................................................58 Time-out Sequence ...........................................................92 SDA Pin .............................................................................58 Timer0 ...............................................................................35 SDI Pin ...............................................................................55 Associated Registers ................................................37 SDO Pin .............................................................................55 External Clock ...........................................................36 SEN Bit Interrupt .....................................................................35 START Condition Enabled Bit (SEN) ........................54 Overflow Flag (TMR0IF Bit) ......................................98 Serial Clock (SCK) .............................................................55 Overflow Interrupt ......................................................98 Serial Clock (SCL) .............................................................58 Prescaler ...................................................................36 Serial Data Address (SDA) ................................................58 T0CKI ........................................................................36 Serial Data In (SDI) ............................................................55 Timer1 ...............................................................................39 Serial Data Out (SDO) .......................................................55 Associated Registers ................................................42 Slave Select (SS) ...............................................................55 Asynchronous Counter Mode ....................................41 , , SLEEP ................................................................87 91 100 Counter Operation .....................................................40 SMP Bit ..............................................................................52 Operation in Timer Mode ..........................................40 Software Simulator (MPLAB SIM) ...................................112 Oscillator ...................................................................41 Special Features of the CPU .............................................87 Capacitor Selection ...........................................41 Special Function Registers (SFRs) ......................................9 Prescaler ...................................................................41 Data EEPROM and FLASH Program Memory ..........23 Reading and Writing in Asynchronous Speed, Operating .................................................................1 Counter Mode ...........................................41 SPI Clock Edge Select Bit (CKE) .......................................52 Resetting of Timer1 Registers ...................................41 SPI Mode Resetting Timer1 using a CCP Trigger Output .........41 Associated Registers .................................................57 Synchronized Counter Mode .....................................40 Master Mode ..............................................................56 Timer2 ...............................................................................43 Serial Clock ...............................................................55 Associated Registers ................................................44 Serial Data In .............................................................55 Output .......................................................................44 Serial Data Out ..........................................................55 Postscaler .................................................................43 Slave Select ...............................................................55 Prescaler ...................................................................43 SPI Clock ...................................................................56 Prescaler and Postscaler ..........................................44 SS Pin ................................................................................55 Timing Diagrams SSBUF Register ..................................................................9 A/D Conversion .......................................................137 MSSP Acknowledge Sequence ............................................71 See also I2C Mode and SPI Mode. Baud Rate Generator with Clock Arbitration .............65 SSPADD Register ..............................................................10 BRG Reset Due to SDA Collision During SSPBUF register ...............................................................58 START Condition ......................................75 SSPCON Register ...............................................................9 Brown-out Reset .....................................................129 SSPCON2 Register ...........................................................10 Bus Collision SSPEN Bit .........................................................................53 Transmit and Acknowledge ...............................73 , SSPIF .........................................................................16 59 Bus Collision During a Repeated START SSPM3:SSPM0 Bits ..........................................................53 Condition (Case 1) ....................................76 , SSPOV Bit ..................................................................53 59 Bus Collision During a Repeated START SSPOV Status Flag ...........................................................69 Condition (Case2) .....................................76 , SSPSTAT Register .....................................................10 58 Bus Collision During a STOP Condition Stack ..................................................................................20 (Case 1) ....................................................77 Overflows ...................................................................20 Bus Collision During a STOP Condition Underflow ..................................................................20 (Case 2) ....................................................77 © 2006 Microchip Technology Inc. DS30221C-page 161

PIC16F872 Bus Collision During START Condition U (SCL = 0) ...................................................75 UA Bit Bus Collision During START Condition Update Address Bit (UA) ...........................................52 (SDA Only) ................................................74 Capture/Compare/PWM ..........................................131 W CLKOUT and I/O .....................................................128 Wake-up from SLEEP ...............................................87, 100 External Clock ..........................................................127 Interrupts ...................................................................93 First START Bit Timing ..............................................65 MCLR Reset ..............................................................93 I2C Bus Data ............................................................135 WDT Reset ................................................................93 I2C Bus START/STOP Bits ......................................134 Wake-Up Using Interrupts ...............................................100 I2C Master Mode Transmission .................................68 Watchdog Timer (WDT) ..............................................87, 99 I2C Mode (7-bit Reception) .................................60, 70 Enable (WDTE Bit) ....................................................99 I2C Mode (7-bit Transmission) ...................................61 Postscaler. See Postscaler, WDT Master Mode Transmit Clock Arbitration ...................72 Programming Considerations ....................................99 Power-up Timer .......................................................129 RC Oscillator .............................................................99 Repeat START Condition ..........................................66 Time-out Period .........................................................99 RESET .....................................................................129 WDT Reset, Normal Operation ...........................91, 93 Slave Mode General Call Address Sequence WDT Reset, SLEEP ............................................91, 93 (7 or 10-bit Mode) ......................................61 WDT Reset, Wake-up ...............................................93 Slow Rise Time (MCLR Tied to VDD WCOL ................................................................................65 Via RC Network) ........................................96 WCOL Bit ..........................................................................53 SPI Master Mode .......................................................56 WCOL Status Flag ........................................65, 67, 69, 71 SPI Master Mode (CKE = 0, SMP = 0) ....................132 Write Collision Detect Bit (WCOL) .....................................53 SPI Master Mode (CKE = 1, SMP = 1) ....................132 Write Verify SPI Slave Mode (CKE = 0) ...............................57, 133 Data EEPROM and FLASH Program Memory ..........27 SPI Slave Mode (CKE = 1) ...............................57, 133 WWW, On-Line Support ......................................................2 Start-up Timer ..........................................................129 STOP Condition Receive or Transmit Mode ..............72 Time-out Sequence on Power-up ..............................96 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 1 ...............................................................95 Case 2 ...............................................................96 Time-out Sequence on Power-up (MCLR Tied to VDD Via RC Network) ........95 Timer0 ......................................................................130 Timer1 ......................................................................130 Wake-up from SLEEP via Interrupt ..........................101 Watchdog Timer ......................................................129 Timing Parameter Symbology .........................................126 , TMR0 Register ..............................................................9 11 TMR1CS bit .......................................................................39 TMR1H Register ..................................................................9 TMR1L Register ...................................................................9 TMR1ON bit .......................................................................39 TMR2 Register .....................................................................9 TOUTPS3:TOUTPS0 bits ..................................................43 TRISA Register ..................................................................10 TRISB Register ..................................................................10 TRISC Register ..................................................................10 DS30221C-page 162 © 2006 Microchip Technology Inc.

PIC16F872 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following (cid:129) Field Application Engineer (FAE) information: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, (cid:129) Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help (cid:129) General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. DS30221C-page 163

PIC16F872 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F872 Literature Number: DS30221C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Advance Information DS30221C-page 164 © 2006 Microchip Technology Inc.

PIC16F872 PIC16F872 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F872 - I/P 301 = Industrial temp., skinny Range PDIP package, normal VDD limits, QTP pattern #301. b) PIC16F872 - E/SO = Extended temp., SOIC Device PPIICC1166LFF887X7X(1()1, ),P PICIC1166FL8F78X7TX(2T);(V2 D);DV DraDn rgaen g4e.0 2V. 0toV 5to.5 5V.5V c) pPpaaICcckk1aa6ggLeeF,,8 en7xo2tr em- n/aSdle SVd D= VD CD loDimm liitmms.ietsrc.ial temp., SSOP Temperature Range blank = 0°C to +70°C (Commercial) I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package SO = SOIC SP = Skinny Plastic DIP SS = SSOP Note 1: F = CMOS FLASH LF = Low Power CMOS FLASH 2: T = in tape and reel - SOIC, PLCC, MQFP, TQFP packages only. © 2006 Microchip Technology Inc. DS30221C-page 165

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F872-I/SSG PIC16F872-I/SOG PIC16F872T-E/SO PIC16F872T-E/SS PIC16LF872-I/SS PIC16LF872-I/SP PIC16LF872-I/SO PIC16LF872T-I/SS PIC16F872-E/SO PIC16F872-E/SS PIC16F872-E/SP PIC16LF872T-I/SO PIC16F872T-I/SO PIC16F872T-I/SS PIC16F872-I/SS PIC16F872-I/SO PIC16F872-I/SP