PIC16F818/819 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology Low-Power Features: Pin Diagram • Power-Managed modes: 18-Pin PDIP, SOIC - Primary Run: XT, RC oscillator, 87A, 1MHz, 2V RA2/AN2/VREF- 1 18 RA1/AN1 RA3/AN3/VREF+ 2 17 RA0/AN0 - INTRC: 7A, 31.25kHz, 2V RA4/AN4/T0CKI 3 19 16 RA7/OSC1/CLKI 8 - Sleep: 0.2A, 2V RA5/MCLR/VPP 4 8/ 15 RA6/OSC2/CLKO 1 • Timer1 oscillator: 1.8A, 32kHz, 2V VSS 5 F8 14 VDD RB0/INT 6 6 13 RB7/T1OSI/PGD 1 • Watchdog Timer: 0.7A, 2V RB1/SDI/SDA 7 C 12 RB6/T1OSO/T1CKI/PGC RB2/SDO/CCP1 8 PI 11 RB5/SS • Wide operating voltage range: RB3/CCP1/PGM 9 10 RB4/SCK/SCL - Industrial: 2.0V to 5.5V Oscillators: Special Microcontroller Features: • Three Crystal modes: - LP, XT, HS: up to 20MHz • 100,000 erase/write cycles Enhanced Flash program memory typical • Two External RC modes • 1,000,000 typical erase/write cycles EEPROM • One External Clock mode: data memory typical - ECIO: up to 20MHz • EEPROM Data Retention: > 40 years • Internal oscillator block: • In-Circuit Serial ProgrammingTM (ICSPTM) via two pins - 8 user selectable frequencies: 31kHz, 125kHz, • Processor read/write access to program memory 250kHz, 500kHz, 1MHz, 2MHz, 4MHz, 8MHz • Low-Voltage Programming Peripheral Features: • In-Circuit Debugging via two pins • 16 I/O pins with individual direction control • High sink/source current: 25 mA • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture, Compare, PWM (CCP) module: - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit • 10-bit, 5-channel Analog-to-Digital converter • Synchronous Serial Port (SSP) with SPI (Master/Slave) and I2C™ (Slave) Program Memory Data Memory SSP 10-bit CCP Timers Device I/O Pins Flash # Single-Word SRAM EEPROM A/D (ch) (PWM) Slave 8/16-bit SPI (Bytes) Instructions (Bytes) (Bytes) I2C™ PIC16F818 1792 1024 128 128 16 5 1 Y Y 2/1 PIC16F819 3584 2048 256 256 16 5 1 Y Y 2/1  2001-2013 Microchip Technology Inc. DS39598F-page 1

PIC16F818/819 Pin Diagrams 18-Pin PDIP, SOIC 20-Pin SSOP RA2/AN2/VREF- 1 18 RA1/AN1 RA2/AN2/VREF- 1 20 RA1/AN1 RA3/AN3/VREF+ 2 9 17 RA0/AN0 RA3/AN3/VREF+ 2 9 19 RA0/AN0 RA4/AN4/T0CKI 3 81 16 RA7/OSC1/CLKI RA4/AN4/T0CKI 3 81 18 RA7/OSC1/CLKI RA5/MCLR/VPP 4 8/ 15 RA6/OSC2/CLKO RA5/MCLR/VPP 4 8/ 17 RA6/OSC2/CLKO VSS 5 81 14 VDD VSS 5 81 16 VDD RB1/SRDBI0/S/IDNAT 67 16F 1132 RRBB67//TT11OOSSOI/P/TG1CDKI/PGC RB0/VINSTS 67 16F 1154 RVDBD7/T1OSI/PGD C RB1/SDI/SDA 8 C 13 RB6/T1OSO/T1CKI/PGC RB2/SDO/CCP1 8 PI 11 RB5/SS RB2/SDO/CCP1 9 PI 12 RB5/SS RB3/CCP1/PGM 9 10 RB4/SCK/SCL RB3/CCP1/PGM 10 11 RB4/SCK/SCL 28-Pin QFN(1) T0CKI V+REF V-REF N4/ N3/ N2/ N1 N0 A A A A A A4/ A3/ A2/ C A1/ A0/ C R R R N R R N 8 7 6 5 4 3 2 2 2 2 2 2 2 2 RA5/MCLR/VPP 1 21 RA7/OSC1/CLKI NC 2 20 RA6/OSC2/CLKO VSS 3 19 VDD NC 4 PIC16F818/819 18 NC VSS 5 17 VDD NC 6 16 RB7/T1OSI/PGD RB0/INT 7 15 RB6/T1OSO/T1CKI/PGC 0 1 2 3 4 8 9 1 1 1 1 1 A 1 M C L S C RB1/SDI/SD B2/SDO/CCP B3/CCP1/PG N RB4/SCK/SC RB5/S N R R Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS39598F-page 2  2001-2013 Microchip Technology Inc.

PIC16F818/819 Table of Contents 1.0 Device Overview..........................................................................................................................................................................5 2.0 Memory Organization...................................................................................................................................................................9 3.0 Data EEPROM and Flash Program Memory..............................................................................................................................25 4.0 Oscillator Configurations............................................................................................................................................................33 5.0 I/O Ports.....................................................................................................................................................................................39 6.0 Timer0 Module...........................................................................................................................................................................53 7.0 Timer1 Module...........................................................................................................................................................................57 8.0 Timer2 Module...........................................................................................................................................................................63 9.0 Capture/Compare/PWM (CCP) Module.....................................................................................................................................65 10.0 Synchronous Serial Port (SSP) Module.....................................................................................................................................71 11.0 Analog-to-Digital Converter (A/D) Module..................................................................................................................................81 12.0 Special Features of the CPU......................................................................................................................................................89 13.0 Instruction Set Summary..........................................................................................................................................................103 14.0 Development Support...............................................................................................................................................................111 15.0 Electrical Characteristics..........................................................................................................................................................115 16.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................141 17.0 Packaging Information..............................................................................................................................................................155 Appendix A: Revision History.............................................................................................................................................................165 Appendix B: Device Differences........................................................................................................................................................165 INDEX................................................................................................................................................................................................167 The Microchip Web Site.....................................................................................................................................................................173 Customer Change Notification Service..............................................................................................................................................173 Customer Support..............................................................................................................................................................................173 Reader Response..............................................................................................................................................................................174 PIC16F818/819 Product Identification System..................................................................................................................................175 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2001-2013 Microchip Technology Inc. DS39598F-page 3

PIC16F818/819 NOTES: DS39598F-page 4  2001-2013 Microchip Technology Inc.

PIC16F818/819 1.0 DEVICE OVERVIEW Program Data Data Device This document contains device specific information for Flash Memory EEPROM the operation of the PIC16F818/819 devices. Additional PIC16F819 2K x14 256 x 8 256 x 8 information may be found in the “PIC® Mid-Range MCU There are 16 I/O pins that are user configurable on a Family Reference Manual” (DS33023) which may be pin-to-pin basis. Some pins are multiplexed with other downloaded from the Microchip web site. The Reference device functions. These functions include: Manual should be considered a complementary docu- ment to this data sheet and is highly recommended • External Interrupt reading for a better understanding of the device architec- • Change on PORTB Interrupt ture and operation of the peripheral modules. • Timer0 Clock Input The PIC16F818/819 belongs to the Mid-Range family • Low-Power Timer1 Clock/Oscillator of the PIC® devices. The devices differ from each other • Capture/Compare/PWM in the amount of Flash program memory, data memory • 10-bit, 5-channel Analog-to-Digital Converter and data EEPROM (see Table1-1). A block diagram of the devices is shown in Figure1-1. These devices con- • SPI/I2C tain features that are new to the PIC16 product line: • MCLR (RA5) can be configured as an Input • Internal RC oscillator with eight selectable Table1-2 details the pinout of the devices with frequencies, including 31.25kHz, 125kHz, descriptions and details for each pin. 250kHz, 500kHz, 1MHz, 2MHz, 4MHz and 8MHz. The INTRC can be configured as the system clock via the configuration bits. Refer to Section4.5 “Internal Oscillator Block” and Section12.1 “Configuration Bits” for further details. • The Timer1 module current consumption has been greatly reduced from 20A (previous PIC16 devices) to 1.8A typical (32kHz at 2V), which is ideal for real-time clock applications. Refer to Section6.0 “Timer0 Module” for further details. • The amount of oscillator selections has increased. The RC and INTRC modes can be selected with an I/O pin configured as an I/O or a clock output (FOSC/4). An external clock can be configured with an I/O pin. Refer to Section4.0 “Oscillator Configurations” for further details. TABLE 1-1: AVAILABLE MEMORY IN PIC16F818/819 DEVICES Program Data Data Device Flash Memory EEPROM PIC16F818 1K x 14 128 x 8 128 x 8  2001-2013 Microchip Technology Inc. DS39598F-page 5

PIC16F818/819 FIGURE 1-1: PIC16F818/819 BLOCK DIAGRAM 13 Data Bus 8 PORTA Program Counter RA0/AN0 Flash RA1/AN1 Program RA2/AN2/VREF- Memory RAM RA3/AN3/VREF+ 1K/2K x 14 8-Level Stack File RA4/AN4/T0CKI (13-bit) Registers RA5/MCLR/VPP RA6/OSC2/CLKO 128/256 x 8 Program RA7/OSC1/CLKI Bus 14 RAM Addr(1) 9 PORTB Addr MUX RB0/INT Instruction reg RB1/SDI/SDA Direct Addr 7 8 InAddirderct RRBB23//SCDCOP1/C/PCGPM1 RB4/SCK/SCL FSR reg RB5/SS RB6/T1OSO/T1CKI/PGC Status reg 8 RB7/T1OSI/PGD 3 Power-up MUX Timer Instruction Oscillator Decode & Start-up Timer ALU Control Power-on Reset 8 Timing Watchdog Generation Timer W reg RA7/OSC1/CLKI Brown-out RA6/OSC2/CLKO Reset MCLR VDD, VSS Data EE Timer0 Timer1 Timer2 128/256 Bytes 10-bit, 5-channel Synchronous CCP1 A/D Serial Port Note1: Higher order bits are from the Status register. DS39598F-page 6  2001-2013 Microchip Technology Inc.

PIC16F818/819 TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS PDIP/ SSOP QFN I/O/P Buffer Pin Name SOIC Description Pin# Pin# Type Type Pin# PORTA is a bidirectional I/O port. RA0/AN0 17 19 23 RA0 I/O TTL Bidirectional I/O pin. AN0 I Analog Analog input channel 0. RA1/AN1 18 20 24 RA1 I/O TTL Bidirectional I/O pin. AN1 I Analog Analog input channel 1. RA2/AN2/VREF- 1 1 26 RA2 I/O TTL Bidirectional I/O pin. AN2 I Analog Analog input channel 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 2 2 27 RA3 I/O TTL Bidirectional I/O pin. AN3 I Analog Analog input channel 3. VREF+ I Analog A/D reference voltage (high) input. RA4/AN4/T0CKI 3 3 28 RA4 I/O ST Bidirectional I/O pin. AN4 I Analog Analog input channel 4. T0CKI I ST Clock input to the TMR0 timer/counter. RA5/MCLR/VPP 4 4 1 RA5 I ST Input pin. MCLR I ST Master Clear (Reset). Input/programming voltage input. This pin is an active-low Reset to the device. VPP P – Programming threshold voltage. RA6/OSC2/CLKO 15 17 20 RA6 I/O ST Bidirectional I/O pin. OSC2 O – Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O – In RC mode, this pin outputs CLKO signal which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA7/OSC1/CLKI 16 18 21 RA7 I/O ST Bidirectional I/O pin. OSC1 I ST/CMOS(3) Oscillator crystal input. CLKI I – External clock source input. Legend: I = Input O = Output I/O = Input/Output P = Power – = Not used TTL = TTL Input ST = Schmitt Trigger Input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2001-2013 Microchip Technology Inc. DS39598F-page 7

PIC16F818/819 TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS (CONTINUED) PDIP/ SSOP QFN I/O/P Buffer Pin Name SOIC Description Pin# Pin# Type Type Pin# PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 6 7 7 RB0 I/O TTL Bidirectional I/O pin. INT I ST(1) External interrupt pin. RB1/SDI/SDA 7 8 8 RB1 I/O TTL Bidirectional I/O pin. SDI I ST SPI data in. SDA I/O ST I2C™ data. RB2/SDO/CCP1 8 9 9 RB2 I/O TTL Bidirectional I/O pin. SDO O ST SPI data out. CCP1 I/O ST Capture input, Compare output, PWM output. RB3/CCP1/PGM 9 10 10 RB3 I/O TTL Bidirectional I/O pin. CCP1 I/O ST Capture input, Compare output, PWM output. PGM I ST Low-Voltage ICSP™ Programming enable pin. RB4/SCK/SCL 10 11 12 RB4 I/O TTL Bidirectional I/O pin. Interrupt-on-change pin. SCK I/O ST Synchronous serial clock input/output for SPI. SCL I ST Synchronous serial clock input for I2C. RB5/SS 11 12 13 RB5 I/O TTL Bidirectional I/O pin. Interrupt-on-change pin. SS I TTL Slave select for SPI in Slave mode. RB6/T1OSO/T1CKI/PGC 12 13 15 RB6 I/O TTL Interrupt-on-change pin. T1OSO O ST Timer1 Oscillator output. T1CKI I ST Timer1 clock input. PGC I ST(2) In-circuit debugger and ICSP programming clock pin. RB7/T1OSI/PGD 13 14 16 RB7 I/O TTL Interrupt-on-change pin. T1OSI I ST Timer1 oscillator input. PGD I ST(2) In-circuit debugger and ICSP programming data pin. VSS 5 5, 6 3, 5 P – Ground reference for logic and I/O pins. VDD 14 15, 16 17, 19 P – Positive supply for logic and I/O pins. Legend: I = Input O = Output I/O = Input/Output P = Power – = Not used TTL = TTL Input ST = Schmitt Trigger Input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39598F-page 8  2001-2013 Microchip Technology Inc.

PIC16F818/819 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization There are two memory blocks in the PIC16F818/819. The PIC16F818/819 devices have a 13-bit program These are the program memory and the data memory. counter capable of addressing an 8K x 14 program Each block has its own bus, so access to each block memory space. For the PIC16F818, the first 1K x 14 can occur during the same oscillator cycle. (0000h-03FFh) is physically implemented (see Figure2-1). For the PIC16F819, the first 2K x 14 is The data memory can be further broken down into the located at 0000h-07FFh (see Figure2-2). Accessing a general purpose RAM and the Special Function location above the physically implemented address will Registers (SFRs). The operation of the SFRs that cause a wraparound. For example, the same instruc- control the “core” are described here. The SFRs used tion will be accessed at locations 020h, 420h, 820h, to control the peripheral modules are described in the C20h, 1020h, 1420h, 1820h and 1C20h. section discussing each individual peripheral module. The Reset vector is at 0000h and the interrupt vector is The data memory area also contains the data at 0004h. EEPROM memory. This memory is not directly mapped into the data memory but is indirectly mapped. That is, an indirect address pointer specifies the address of the data EEPROM memory to read/write. The PIC16F818 device’s 128 bytes of data EEPROM memory have the address range of 00h-7Fh and the PIC16F819 device’s 256 bytes of data EEPROM memory have the address range of 00h-FFh. More details on the EEPROM memory can be found in Section3.0 “Data EEPROM and Flash Program Memory”. Additional information on device memory may be found in the “PIC® Mid-Range Reference Manual” (DS33023). FIGURE 2-1: PROGRAM MEMORY MAP FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC16F818 PIC16F819 PC<12:0> PC<12:0> CALL, RETURN 13 CALL, RETURN 13 RETFIE, RETLW RETFIE, RETLW Stack Level 1 Stack Level 1 Stack Level 2 Stack Level 2 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h Interrupt Vector 0004h On-Chip 0005h On-Chip 0005h Program Page 0 Program Memory 03FFh Memory Page 0 0400h 07FFh 0800h Wraps to 0000h-03FFh Wraps to 0000h-07FFh 1FFFh 1FFFh  2001-2013 Microchip Technology Inc. DS39598F-page 9

PIC16F818/819 2.2 Data Memory Organization Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special The data memory is partitioned into multiple banks that Function Registers. Above the Special Function Regis- contain the General Purpose Registers and the Special ters are the General Purpose Registers, implemented Function Registers. Bits RP1 (Status<6>) and RP0 as static RAM. All implemented banks contain SFRs. (Status<5>) are the bank select bits. Some “high use” SFRs from one bank may be mirrored in another bank for code reduction and quicker access RP1:RP0 Bank (e.g., the Status register is in Banks 0-3). 00 0 Note: EEPROM data memory description can be 01 1 found in Section3.0 “Data EEPROM and 10 2 Flash Program Memory” of this data sheet. 11 3 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indirectly through the File Select Register, FSR. DS39598F-page 10  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 2-3: PIC16F818 REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h 07h 87h 107h 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(1) 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved(1) 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h 91h T2CON 12h PR2 92h SSPBUF 13h SSPADD 93h SSPCON 14h SSPSTAT 94h CCPR1L 15h 95h CCPR1H 16h 96h CCP1CON 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h General A0h 120h 1A0h Purpose Register General 32 Bytes BFh Purpose C0h Accesses Accesses Register 20h-7Fh 20h-7Fh Accesses 96 Bytes 40h-7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. *Not a physical register. Note 1: These registers are reserved; maintain these registers clear.  2001-2013 Microchip Technology Inc. DS39598F-page 11

PIC16F818/819 FIGURE 2-4: PIC16F819 REGISTER FILE MAP File File File File Address Address Address Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h 07h 87h 107h 187h 08h 88h 108h 188h 09h 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(1) 18Eh TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved(1) 18Fh T1CON 10h OSCTUNE 90h 110h 190h TMR2 11h 91h T2CON 12h PR2 92h SSPBUF 13h SSPADD 93h SSPCON 14h SSPSTAT 94h CCPR1L 15h 95h CCPR1H 16h 96h CCP1CON 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh 20h 120h 1A0h A0h General General General Purpose Purpose Purpose Register Register Accesses Register 80 Bytes 80 Bytes 20h-7Fh 96 Bytes EFh 16Fh Accesses F0h Accesses 170h 70h-7Fh 70h-7Fh 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as ‘0’. *Not a physical register. Note 1: These registers are reserved; maintain these registers clear. DS39598F-page 12  2001-2013 Microchip Technology Inc.

PIC16F818/819 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in the implemented as static RAM. A list of these registers is peripheral feature section. given in Table2-1. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on Details on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR page: Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 01h TMR0 Timer0 Module Register xxxx xxxx 53, 17 02h(1) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23 03h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 16 04h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 23 05h PORTA PORTA Data Latch when written; PORTA pins when read xxx0 0000 39 06h PORTB PORTB Data Latch when written; PORTB pins when read xxxx xxxx 43 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23 0Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 20 0Dh PIR2 — — — EEIF — — — — ---0 ---- 21 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57 11h TMR2 Timer2 Module Register 0000 0000 63 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 64 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 71, 76 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 66, 67, 68 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 66, 67, 68 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 65 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH A/D Result Register High Byte xxxx xxxx 81 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 81 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note1: These registers can be addressed from any bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.  2001-2013 Microchip Technology Inc. DS39598F-page 13

PIC16F818/819 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Details on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR page: Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17, 54 82h(1) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23 83h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 16 84h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 23 85h TRISA TRISA7 TRISA6 TRISA5(3) PORTA Data Direction Register (TRISA<4:0> 1111 1111 39 86h TRISB PORTB Data Direction Register 1111 1111 43 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 23 8Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 19 8Dh PIE2 — — — EEIE — — — — ---0 ---- 21 8Eh PCON — — — — — — POR BOR ---- --qq 22 8Fh OSCCON — IRCF2 IRCF1 IRCF0 — IOFS — — -000 -0-- 38 90h(1) OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 36 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 68 93h SSPADD Synchronous Serial Port (I2C™ mode) Address Register 0000 0000 71, 76 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 72 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 81 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 82 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note1: These registers can be addressed from any bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’. DS39598F-page 14  2001-2013 Microchip Technology Inc.

PIC16F818/819 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Details on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR page: Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 101h TMR0 Timer0 Module Register xxxx xxxx 53 102h(1 PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23 103h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 16 104h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 23 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written; PORTB pins when read xxxx xxxx 43 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23 10Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18 10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx 25 10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx 25 10Eh EEDATH — — EEPROM/Flash Data Register High Byte --xx xxxx 25 10Fh EEADRH — — — — — EEPROM/Flash Address Register ---- -xxx 25 High Byte Bank 3 180h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17, 54 182h(1) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 23 183h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 16 184h(1) FSR Indirect Data Memory Address Pointer xxxx xxxx 23 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 43 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23 18Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 18 18Ch EECON1 EEPGD — — FREE WRERR WREN WR RD x--x x000 26 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 25 18Eh — Reserved; maintain clear 0000 0000 — 18Fh — Reserved; maintain clear 0000 0000 — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note1: These registers can be addressed from any bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 3: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.  2001-2013 Microchip Technology Inc. DS39598F-page 15

PIC16F818/819 2.2.2.1 Status Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the Status register as The Status register, shown in Register2-1, contains the ‘000u u1uu’ (where u = unchanged). arithmetic status of the ALU, the Reset status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The Status register can be the destination for any Status register because these instructions do not affect instruction, as with any other register. If the Status the Z, C or DC bits from the Status register. For other register is the destination for an instruction that affects instructions not affecting any status bits, see the Z, DC or C bits, then the write to these three bits is Section13.0 “Instruction Set Summary”. disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not Note: The C and DC bits operate as a borrow writable. Therefore, the result of an instruction with the and digit borrow bit, respectively, in Status register as destination may be different than subtraction. See the SUBLW and SUBWF intended. instructions for examples. REGISTER 2-1: STATUS: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1,2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. 2: For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 16  2001-2013 Microchip Technology Inc.

PIC16F818/819 2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for The OPTION_REG register is a readable and writable the TMR0 register, assign the prescaler to register that contains various control bits to configure the Watchdog Timer. the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 17

PIC16F818/819 2.2.2.3 INTCON Register Note: Interrupt flag bits get set when an interrupt The INTCON register is a readable and writable regis- condition occurs regardless of the state of ter that contains various enable and flag bits for the its corresponding enable bit or the Global TMR0 register overflow, RB port change and external Interrupt Enable bit, GIE (INTCON<7>). RB0/INT pin interrupts. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 18  2001-2013 Microchip Technology Inc.

PIC16F818/819 2.2.2.4 PIE1 Register This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5-4 Unimplemented: Read as ‘0’ bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 19

PIC16F818/819 2.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt This register contains the individual flag bits for the condition occurs regardless of the state of peripheral interrupts. its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete bit 5-4 Unimplemented: Read as ‘0’ bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The SSP interrupt condition has occurred and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are a transmission/ reception has taken place. 0 = No SSP interrupt condition has occurred bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 20  2001-2013 Microchip Technology Inc.

PIC16F818/819 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt. REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — EEIE — — — — bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EE write interrupt 0 = Disable EE write interrupt bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2.2.2.7 PIR2 Register . The PIR2 register contains the flag bit for the EEPROM Note: Interrupt flag bits are set when an interrupt write operation interrupt. condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh) U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — EEIF — — — — bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIF: EEPROM Write Operation Interrupt Enable bit 1 = Enable EE write interrupt 0 = Disable EE write interrupt bit 3-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 21

PIC16F818/819 2.2.2.8 PCON Register Note: BOR is unknown on Power-on Reset. It Note: Interrupt flag bits get set when an interrupt must then be set by the user and checked condition occurs regardless of the state of on subsequent Resets to see if BOR is its corresponding enable bit or the Global clear, indicating a brown-out has occurred. Interrupt Enable bit, GIE (INTCON<7>). The BOR status bit is a ‘don’t care’ and is User software should ensure the appropri- not necessarily predictable if the brown- ate interrupt flag bits are clear prior to out circuit is disabled (by clearing the enabling an interrupt. BOREN bit in the Configuration word). The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), a Brown-out Reset, an external MCLR Reset and WDT Reset. REGISTER 2-8: PCON: POWER CONTROL REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 22  2001-2013 Microchip Technology Inc.

PIC16F818/819 2.3 PCL and PCLATH The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth The Program Counter (PC) is 13 bits wide. The low push overwrites the value that was stored from the first byte comes from the PCL register, which is a readable push. The tenth push overwrites the second push (and and writable register. The upper bits (PC<12:8>) are so on). not readable but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the Note1: There are no status bits to indicate stack PC will be cleared. Figure2-5 shows the two situations overflow or stack underflow conditions. for the loading of the PC. The upper example in the 2: There are no instructions/mnemonics figure shows how the PC is loaded on a write to PCL called PUSH or POP. These are actions (PCLATH<4:0>  PCH). The lower example in the that occur from the execution of the figure shows how the PC is loaded during a CALL or CALL, RETURN, RETLW and RETFIE GOTO instruction (PCLATH<4:3>  PCH). instructions or the vectoring to an interrupt address. FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS 2.4 Indirect Addressing: INDF and FSR Registers PCH PCL The INDF register is not a physical register. Addressing 12 8 7 0 Instruction with INDF actually addresses the register whose address is PC PCL as Destination contained in the FSR register (FSR is a pointer). This is PCLATH<4:0> 8 indirect addressing. 5 ALU EXAMPLE 2-1: INDIRECT ADDRESSING PCLATH • Register file 05 contains the value 10h PCH PCL • Register file 06 contains the value 0Ah 12 11 10 8 7 0 • Load the value 05 into the FSR register PC GOTO,CALL • A read of the INDF register will return the value PCLATH<4:3> 11 of 10h 2 Opcode <10:0> • Increment the value of the FSR register by one (FSR = 06) PCLATH • A read of the INDF register now will return the value of 0Ah 2.3.1 COMPUTED GOTO Reading INDF itself indirectly (FSR=0) will produce A computed GOTO is accomplished by adding an offset 00h. Writing to the INDF register indirectly results in a to the program counter (ADDWF PCL). When doing a no operation (although status bits may be affected). table read using a computed GOTO method, care A simple program to clear RAM locations, 20h-2Fh, should be exercised if the table location crosses a PCL using indirect addressing is shown in Example2-2. memory boundary (each 256-byte block). Refer to the application note AN556, “Implementing a Table Read” EXAMPLE 2-2: HOW TO CLEAR RAM (DS00556). USING INDIRECT 2.3.2 STACK ADDRESSING MOVLW 0x20 ;initialize pointer The PIC16F818/819 family has an 8-level deep x 13-bit MOVWF FSR ;to RAM wide hardware stack. The stack space is not part of NEXT CLRF INDF ;clear INDF register either program or data space and the Stack Pointer is INCF FSR ;inc pointer not readable or writable. The PC is PUSHed onto the BTFSS FSR, 4 ;all done? stack when a CALL instruction is executed or an GOTO NEXT ;NO, clear next interrupt causes a branch. The stack is POPed in the CONTINUE event of a RETURN, RETLW or a RETFIE instruction : ;YES, continue execution. PCLATH is not affected by a PUSH or POP operation. An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (Status<7>) as shown in Figure2-6.  2001-2013 Microchip Technology Inc. DS39598F-page 23

PIC16F818/819 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 From Opcode 0 IRP 7 FSR Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 80h 100h 180h Data Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail, see Figure2-3 or Figure2-4. DS39598F-page 24  2001-2013 Microchip Technology Inc.

PIC16F818/819 3.0 DATA EEPROM AND FLASH When the device is code-protected, the CPU may PROGRAM MEMORY continue to read and write the data EEPROM memory. Depending on the settings of the write-protect bits, the The data EEPROM and Flash program memory are device may or may not be able to write certain blocks readable and writable during normal operation (over of the program memory; however, reads of the program the full VDD range). This memory is not directly mapped memory are allowed. When code-protected, the device in the register file space. Instead, it is indirectly programmer can no longer access data or program addressed through the Special Function Registers. memory; this does NOT inhibit internal reads or writes. There are six SFRs used to read and write this memory: 3.1 EEADR and EEADRH • EECON1 The EEADRH:EEADR register pair can address up to • EECON2 a maximum of 256 bytes of data EEPROM or up to a • EEDATA maximum of 8K words of program EEPROM. When • EEDATH selecting a data address value, only the LSB of the address is written to the EEADR register. When select- • EEADR ing a program address value, the MSB of the address • EEADRH is written to the EEADRH register and the LSB is This section focuses on reading and writing data written to the EEADR register. EEPROM and Flash program memory during normal If the device contains less memory than the full address operation. Refer to the appropriate device program- reach of the address register pair, the Most Significant ming specification document for serial programming bits of the registers are not implemented. For example, information. if the device has 128 bytes of data EEPROM, the Most When interfacing the data memory block, EEDATA Significant bit of EEADR is not implemented on access holds the 8-bit data for read/write and EEADR holds the to data EEPROM. address of the EEPROM location being accessed. These devices have 128 or 256 bytes of data 3.2 EECON1 and EECON2 Registers EEPROM, with an address range from 00h to 0FFh. Addresses from 80h to FFh are unimplemented on the EECON1 is the control register for memory accesses. PIC16F818 device and will read 00h. When writing to Control bit, EEPGD, determines if the access will be a unimplemented locations, the charge pump will be program or data memory access. When clear, as it is turned off. when Reset, any subsequent operations will operate When interfacing the program memory block, the on the data memory. When set, any subsequent EEDATA and EEDATH registers form a two-byte word operations will operate on the program memory. that holds the 14-bit data for read/write and the EEADR Control bits, RD and WR, initiate read and write, and EEADRH registers form a two-byte word that holds respectively. These bits cannot be cleared, only set in the 13-bit address of the EEPROM location being software. They are cleared in hardware at completion accessed. These devices have 1K or 2K words of of the read or write operation. The inability to clear the program Flash, with an address range from 0000h to WR bit in software prevents the accidental, premature 03FFh for the PIC16F818 and 0000h to 07FFh for the termination of a write operation. PIC16F819. Addresses above the range of the respec- The WREN bit, when set, will allow a write or erase tive device will wraparound to the beginning of program operation. On power-up, the WREN bit is clear. The memory. WRERR bit is set when a write (or erase) operation is The EEPROM data memory allows single byte read interrupted by a MCLR or a WDT Time-out Reset and write. The Flash program memory allows single- during normal operation. In these situations, following word reads and four-word block writes. Program Reset, the user can check the WRERR bit and rewrite memory writes must first start with a 32-word block the location. The data and address will be unchanged erase, then write in 4-word blocks. A byte write in data in the EEDATA and EEADRregisters. EEPROM memory automatically erases the location Interrupt flag bit, EEIF in the PIR2 register, is set when and writes the new data (erase before write). the write is complete. It must be cleared in software. The write time is controlled by an on-chip timer. The EECON2 is not a physical register. Reading EECON2 write/erase voltages are generated by an on-chip will read all ‘0’s. The EECON2 register is used charge pump, rated to operate over the voltage range exclusively in the EEPROM write sequence. of the device for byte or word operations.  2001-2013 Microchip Technology Inc. DS39598F-page 25

PIC16F818/819 REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch) R/W-x U-0 U-0 R/W-x R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress. bit 6-5 Unimplemented: Read as ‘0’ bit 4 FREE: EEPROM Forced Row Erase bit 1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command 0 = Perform write-only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal operation) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Set only U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 26  2001-2013 Microchip Technology Inc.

PIC16F818/819 3.3 Reading Data EEPROM Memory The steps to write to EEPROM data memory are: 1. If step 10 is not implemented, check the WR bit To read a data memory location, the user must write the to see if a write is in progress. address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD 2. Write the address to EEADR. Make sure that the (EECON1<0>). The data is available in the very next address is not larger than the memory size of cycle in the EEDATA register; therefore, it can be read the device. in the next instruction (see Example3-1). EEDATA will 3. Write the 8-bit data value to be programmed in hold this value until another read or until it is written to the EEDATA register. by the user (during a write operation). 4. Clear the EEPGD bit to point to EEPROM data The steps to reading the EEPROM data memory are: memory. 5. Set the WREN bit to enable program operations. 1. Write the address to EEADR. Make sure that the address is not larger than the memory size of 6. Disable interrupts (if enabled). the device. 7. Execute the special five instruction sequence: 2. Clear the EEPGD bit to point to EEPROM data • Write 55h to EECON2 in two steps (first to W, memory. then to EECON2) 3. Set the RD bit to start the read operation. • Write AAh to EECON2 in two steps (first to W, 4. Read the data from the EEDATA register. then to EECON2) • Set the WR bit EXAMPLE 3-1: DATA EEPROM READ 8. Enable interrupts (if using interrupts). BANKSEL EEADR ; Select Bank of EEADR 9. Clear the WREN bit to disable program MOVF ADDR, W ; operations. MOVWF EEADR ; Data Memory Address 10. At the completion of the write cycle, the WR bit ; to read is cleared and the EEIF interrupt flag bit is set BANKSEL EECON1 ; Select Bank of EECON1 (EEIF must be cleared by firmware). If step 1 is BCF EECON1, EEPGD ; Point to Data memory not implemented, then firmware should check BSF EECON1, RD ; EE Read BANKSEL EEDATA ; Select Bank of EEDATA for EEIF to be set, or WR to be clear, to indicate MOVF EEDATA, W ; W = EEDATA the end of the program cycle. EXAMPLE 3-2: DATA EEPROM WRITE 3.4 Writing to Data EEPROM Memory BANKSELEECON1 ; Select Bank of To write an EEPROM data location, the user must first ; EECON1 write the address to the EEADR register and the data BTFSC EECON1, WR ; Wait for write GOTO $-1 ; to complete to the EEDATA register. Then, the user must follow a BANKSELEEADR ; Select Bank of specific write sequence to initiate the write for each ; EEADR byte. MOVF ADDR, W ; The write will not initiate if the write sequence is not MOVWF EEADR ; Data Memory exactly followed (write 55h to EECON2, write AAh to ; Address to write EECON2, then set WR bit) for each byte. We strongly MOVF VALUE, W ; MOVWF EEDATA ; Data Memory Value recommend that interrupts be disabled during this ; to write codesegment (see Example3-2). BANKSELEECON1 ; Select Bank of Additionally, the WREN bit in EECON1 must be set to ; EECON1 enable write. This mechanism prevents accidental BCF EECON1, EEPGD ; Point to DATA writes to data EEPROM due to errant (unexpected) ; memory code execution (i.e., lost programs). The user should BSF EECON1, WREN ; Enable writes keep the WREN bit clear at all times except when BCF INTCON, GIE ; Disable INTs. updating EEPROM. The WREN bit is not cleared MOVLW 55h ; byhardware AWbefRt einEr hNaib wbitierti dtwe if lrslo enmqout baeenffiencecgt hstheaitss u bwnerleeitsens ci ntyhicteilae Wt.e TdRh,E ecN lWe baRirti nbisgit swtehitel.l RequiredSequence MMMBOOOSVVVFWLWFWF EAEEEAEEChCCOOONNN221, WR ;;;; WWSrreiittt eeW R5A 5Abhhit to ; begin write At the completion of the write cycle, the WR bit is BSF INTCON, GIE ; Enable INTs. cleared in hardware and the EE Write Complete BCF EECON1, WREN ; Disable writes Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.  2001-2013 Microchip Technology Inc. DS39598F-page 27

PIC16F818/819 3.5 Reading Flash Program Memory 3.6 Erasing Flash Program Memory To read a program memory location, the user must The minimum erase block is 32 words. Only through write two bytes of the address to the EEADR and the use of an external programmer, or through ICSP EEADRH registers, set the EEPGD control bit control, can larger blocks of program memory be bulk (EECON1<7>) and then set control bit, RD erased. Word erase in the Flash array is not supported. (EECON1<0>). Once the read control bit is set, the When initiating an erase sequence from the micro- program memory Flash controller will use the second controller itself, a block of 32 words of program memory instruction cycle to read the data. This causes the is erased. The Most Significant 11 bits of the second instruction immediately following the EEADRH:EEADR point to the block being erased. “BSF EECON1, RD” instruction to be ignored. The data EEADR< 4:0> are ignored. is available in the very next cycle in the EEDATA and EEDATH registers; therefore, it can be read as two The EECON1 register commands the erase operation. bytes in the following instructions. EEDATA and The EEPGD bit must be set to point to the Flash EEDATH registers will hold this value until another read program memory. The WREN bit must be set to enable or until it is written to by the user (during a write write operations. The FREE bit is set to select an erase operation). operation. For protection, the write initiate sequence for EECON2 EXAMPLE 3-3: FLASH PROGRAM READ must be used. BANKSEL EEADRH ; Select Bank of EEADRH After the “BSF EECON1, WR” instruction, the processor MOVF ADDRH, W ; requires two cycles to set up the erase operation. The MOVWF EEADRH ; MS Byte of Program user must place two NOP instructions after the WR bit is ; Address to read set. The processor will halt internal operations for the MOVF ADDRL, W ; typical 2ms, only during the cycle in which the erase MOVWF EEADR ; LS Byte of Program takes place. This is not Sleep mode, as the clocks and ; Address to read BANKSEL EECON1 ; Select Bank of EECON1 peripherals will continue to run. After the erase cycle, BSF EECON1, EEPGD; Point to PROGRAM the processor will resume operation with the third ; memory instruction after the EECON1 write instruction. BSF EECON1, RD ; EE Read ; 3.6.1 FLASH PROGRAM MEMORY NOP ; Any instructions ERASE SEQUENCE ; here are ignored as NOP ; program memory is The sequence of events for erasing a block of internal ; read in second cycle program memory location is: ; after BSF EECON1,RD 1. Load EEADRH:EEADR with address of row BANKSEL EEDATA ; Select Bank of EEDATA being erased. MOVF EEDATA, W ; DATAL = EEDATA MOVWF DATAL ; 2. Set EEPGD bit to point to program memory; set MOVF EEDATH, W ; DATAH = EEDATH WREN bit to enable writes and set FREE bit to MOVWF DATAH ; enable the erase. 3. Disable interrupts. 4. Write 55h to EECON2. 5. Write AAh to EECON2. 6. Set the WR bit. This will begin the row erase cycle. 7. The CPU will stall for duration of the erase. DS39598F-page 28  2001-2013 Microchip Technology Inc.

PIC16F818/819 EXAMPLE 3-4: ERASING A FLASH PROGRAM MEMORY ROW BANKSEL EEADRH ; Select Bank of EEADRH MOVF ADDRH, W ; MOVWF EEADRH ; MS Byte of Program Address to Erase MOVF ADDRL, W ; MOVWF EEADR ; LS Byte of Program Address to Erase ERASE_ROW BANKSEL EECON1 ; Select Bank of EECON1 BSF EECON1, EEPGD ; Point to PROGRAM memory BSF EECON1, WREN ; Enable Write to memory BSF EECON1, FREE ; Enable Row Erase operation ; BCF INTCON, GIE ; Disable interrupts (if using) MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Start Erase (CPU stall) NOP ; Any instructions here are ignored as processor ; halts to begin Erase sequence NOP ; processor will stop here and wait for Erase complete ; after Erase processor continues with 3rd instruction BCF EECON1, FREE ; Disable Row Erase operation BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts (if using)  2001-2013 Microchip Technology Inc. DS39598F-page 29

PIC16F818/819 3.7 Writing to Flash Program Memory The user must follow the same specific sequence to initiate the write for each word in the program block by Flash program memory may only be written to if the writing each program word in sequence (00, 01, 10, destination address is in a segment of memory that is 11). not write-protected, as defined in bits WRT1:WRT0 of the device Configuration Word (Register12-1). Flash There are 4 buffer register words and all four locations program memory must be written in four-word blocks. MUST be written to with correct data. A block consists of four words with sequential After the “BSF EECON1, WR” instruction, if addresses, with a lower boundary defined by an EEADRxxxxxx11, then a short write will occur. address, where EEADR<1:0> = 00. At the same time, This short write-only transfers the data to the buffer all block writes to program memory are done as write- register. The WR bit will be cleared in hardware after only operations. The program memory must first be onecycle. erased. The write operation is edge-aligned and cannot After the “BSF EECON1, WR” instruction, if occur across boundaries. EEADR=xxxxxx11, then a long write will occur. This To write to the program memory, the data must first be will simultaneously transfer the data from loaded into the buffer registers. There are four 14-bit EEDATH:EEDATA to the buffer registers and begin the buffer registers and they are addressed by the low write of all four words. The processor will execute the 2bits of EEADR. next instruction and then ignore the subsequent The following sequence of events illustrate how to instruction. The user should place NOP instructions into perform a write to program memory: the second words. The processor will then halt internal operations for typically 2msec in which the write takes • Set the EEPGD and WREN bits in the EECON1 place. This is not a Sleep mode, as the clocks and register peripherals will continue to run. After the write cycle, • Clear the FREE bit in EECON1 the processor will resume operation with the 3rd • Write address to EEADRH:EEADR instruction after the EECON1 write instruction. • Write data to EEDATH:EEDATA After each long write, the 4 buffer registers will be reset • Write 55 to EECON2 to 3FFF. • Write AA to EECON2 • Set WR bit in EECON 1 FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY 7 5 0 7 0 EEDATH EEDATA All buffers are 6 8 transferred to Flash automatically First word of block after this word to be written is written 14 14 14 14 EEADR<1:0> = 00 EEADR<1:0> = 01 EEADR<1:0> = 10 EEADR<1:0> = 11 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory DS39598F-page 30  2001-2013 Microchip Technology Inc.

PIC16F818/819 An example of the complete four-word write sequence is shown in Example3-5. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing, assuming that a row erase sequence has already been performed. EXAMPLE 3-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. The 32 words in the erase block have already been erased. ; 2. A valid starting address (the least significant bits = '00') is loaded into EEADRH:EEADR ; 3. This example is starting at 0x100, this is an application dependent setting. ; 4. The 8 bytes (4 words) of data are loaded, starting at an address in RAM called ARRAY. ; 5. This is an example only, location of data to program is application dependent. ; 6. word_block is located in data memory. BANKSEL EECON1 ;prepare for WRITE procedure BSF EECON1, EEPGD ;point to program memory BSF EECON1, WREN ;allow write cycles BCF EECON1, FREE ;perform write only BANKSEL word_block MOVLW .4 MOVWF word_block ;prepare for 4 words to be written BANKSEL EEADRH ;Start writing at 0x100 MOVLW 0x01 MOVWF EEADRH ;load HIGH address MOVLW 0x00 MOVWF EEADR ;load LOW address BANKSEL ARRAY MOVLW ARRAY ;initialize FSR to start of data MOVWF FSR LOOP BANKSEL EEDATA MOVF INDF, W ;indirectly load EEDATA MOVWF EEDATA INCF FSR, F ;increment data pointer MOVF INDF, W ;indirectly load EEDATH MOVWF EEDATH INCF FSR, F ;increment data pointer BANKSEL EECON1 MOVLW 0x55 ;required sequence MOVWF EECON2 RequiredSequence MMBNOOSOVVFPLWWF 0EExEEACCAOONN21, WR ;;isnestt rWuRc tbiiotn st oh ebreeg ianr ew riigtneored as processor NOP BANKSEL EEADR INCF EEADR, f ;load next word address BANKSEL word_block DECFSZ word_block, f ;have 4 words been written? GOTO loop ;NO, continue with writing BANKSEL EECON1 BCF EECON1, WREN ;YES, 4 words complete, disable writes BSF INTCON, GIE ;enable interrupts  2001-2013 Microchip Technology Inc. DS39598F-page 31

PIC16F818/819 3.8 Protection Against Spurious Write 3.9 Operation During Code-Protect There are conditions when the device should not write When the data EEPROM is code-protected, the micro- to the data EEPROM memory. To protect against controller can read and write to the EEPROM normally. spurious EEPROM writes, various mechanisms have However, all external access to the EEPROM is been built-in. On power-up, WREN is cleared. Also, the disabled. External write access to the program memory Power-up Timer (72ms duration) prevents an is also disabled. EEPROM write. When program memory is code-protected, the micro- The write initiate sequence and the WREN bit together controller can read and write to program memory help prevent an accidental write during brown-out, normally as well as execute instructions. Writes by the power glitch or software malfunction. device may be selectively inhibited to regions of thememory depending on the setting of bits, WRT1:WRT0, of the Configuration Word (see Section12.1 “Configuration Bits” for additional information). External access to the memory is also disabled. TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND FLASH PROGRAM MEMORIES Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on all other Reset Resets 10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx uuuu uuuu 10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx uuuu uuuu 10Eh EEDATH — — EEPROM/Flash Data Register High Byte --xx xxxx --uu uuuu 10Fh EEADRH — — — — — EEPROM/Flash Address ---- -xxx ---- -uuu Register High Byte 18Ch EECON1 EEPGD — — FREE WRERR WREN WR RD x--x x000 x--x q000 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ---- 0Dh PIR2 — — — EEIF — — — — ---0 ---- ---0 ---- 8Dh PIE2 — — — EEIE — — — — ---0 ---- ---0 ---- Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM or Flash program memory. DS39598F-page 32  2001-2013 Microchip Technology Inc.

PIC16F818/819 4.0 OSCILLATOR TABLE 4-1: CAPACITOR SELECTION FOR CONFIGURATIONS CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY) 4.1 Oscillator Types Typical Capacitor Values Crystal Tested: Osc Type The PIC16F818/819 can be operated in eight different Freq oscillator modes. The user can program three configu- C1 C2 ration bits (FOSC2:FOSC0) to select one of these eight LP 32 kHz 33 pF 33 pF modes (modes 5-8 are new PIC16 oscillator configurations): 200 kHz 15 pF 15 pF XT 200 kHz 56 pF 56 pF 1. LP Low-Power Crystal 2. XT Crystal/Resonator 1 MHz 15 pF 15 pF 3. HS High-Speed Crystal/Resonator 4 MHz 15 pF 15 pF 4. RC External Resistor/Capacitor with HS 4 MHz 15 pF 15 pF FOSC/4 output on RA6 8 MHz 15 pF 15 pF 5. RCIO External Resistor/Capacitor with 20 MHz 15 pF 15 pF I/O on RA6 Capacitor values are for design guidance only. 6. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 These capacitors were tested with the crystals listed below for basic start-up and operation. These values 7. INTIO2 Internal Oscillator with I/O on RA6 were not optimized. and RA7 8. ECIO External Clock with I/O on RA6 Different capacitor values may be required to produce acceptable oscillator operation. The user should test 4.2 Crystal Oscillator/Ceramic the performance of the oscillator over the expected VDD and temperature range for the application. Resonators See the notes following this table for additional In XT, LP or HS modes, a crystal or ceramic resonator information. is connected to the OSC1/CLKI and OSC2/CLKO pins to establish oscillation (see Figure4-1 and Figure4-2). Note 1: Higher capacitance increases the stability The PIC16F818/819 oscillator design requires the use of the oscillator but also increases the of a parallel cut crystal. Use of a series cut crystal may start-up time. give a frequency out of the crystal manufacturer’s specifications. 2: Since each crystal has its own character- istics, the user should consult the crystal manufacturer for appropriate values of FIGURE 4-1: CRYSTAL OPERATION external components. (HS, XT OR LP OSC CONFIGURATION) 3: RS may be required in HS mode, as well as XT mode, to avoid overdriving crystals OSC1 PIC16F818/819 with low drive level specification. C1(1) 4: Always verify oscillator performance over the VDD and temperature range that is XTAL RF(3) Sleep expected for the application. OSC2 RS(2) C2(1) To Internal Logic Note 1: See Table4-1 for typical values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen (typically between 2M to 10M.  2001-2013 Microchip Technology Inc. DS39598F-page 33

PIC16F818/819 FIGURE 4-2: CERAMIC RESONATOR 4.3 External Clock Input OPERATION (HS OR XT The ECIO Oscillator mode requires an external clock OSC CONFIGURATION) source to be connected to the OSC1 pin. There is no OSC1 PIC16F818/819 oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. C1(1) In the ECIO Oscillator mode, the OSC2 pin becomes RES RF(3) Sleep an additional general purpose I/O pin. The I/O pin OSC2 becomes bit 6 of PORTA (RA6). Figure4-3 shows the RS(2) pin connections for the ECIO Oscillator mode. C2(1) To Internal Logic FIGURE 4-3: EXTERNAL CLOCK INPUT OPERATION Note 1: See Table4-2 for typical values of C1 and C2. (ECIO CONFIGURATION) 2: A series resistor (RS) may be required. 3: RF varies with the resonator chosen (typically Clock from OSC1/CLKI between 2M to 10M. Ext. System PIC16F818/819 RA6 I/O (OSC2) TABLE 4-2: CERAMIC RESONATORS (FOR DESIGN GUIDANCE ONLY) Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 455 kHz 56 pF 56 pF 2.0 MHz 47 pF 47 pF 4.0 MHz 33 pF 33 pF HS 8.0 MHz 27 pF 27 pF 16.0 MHz 22 pF 22 pF Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode rather than XT mode is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330 DS39598F-page 34  2001-2013 Microchip Technology Inc.

PIC16F818/819 4.4 RC Oscillator 4.5 Internal Oscillator Block For timing insensitive applications, the “RC” and The PIC16F818/819 devices include an internal “RCIO” device options offer additional cost savings. oscillator block which generates two different clock The RC oscillator frequency is a function of the supply signals; either can be used as the system’s clock voltage, the resistor (REXT) and capacitor (CEXT) source. This can eliminate the need for external values and the operating temperature. In addition to oscillator circuits on the OSC1 and/or OSC2 pins. this, the oscillator frequency will vary from unit to unit The main output (INTOSC) is an 8MHz clock source due to normal manufacturing variation. Furthermore, which can be used to directly drive the system clock. It the difference in lead frame capacitance between pack- also drives the INTOSC postscaler which can provide a age types will also affect the oscillation frequency, range of clock frequencies from 125kHz to 4MHz. especially for low CEXT values. The user also needs to take into account variation due to tolerance of external The other clock source is the internal RC oscillator RandC components used. Figure4-4 shows how the (INTRC) which provides a 31.25kHz (32s nominal R/C combination is connected. period) output. The INTRC oscillator is enabled by selecting the INTRC as the system clock source or In the RC Oscillator mode, the oscillator frequency when any of the following are enabled: divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. • Power-up Timer • Watchdog Timer FIGURE 4-4: RC OSCILLATOR MODE These features are discussed in greater detail in VDD Section12.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC REXT direct or INTOSC postscaler) is selected by configuring Internal OSC1 the IRCF bits of the OSCCON register (Register4-2). Clock Note: Throughout this data sheet, when referring CEXT specifically to a generic clock source, the PIC16F818/819 VSS term “INTRC” may also be used to refer to OSC2/CLKO the clock modes using the internal FOSC/4 oscillator block. This is regardless of Recommended values: 3 k  REXT  100 k whether the actual frequency used is CEXT > 20 pF INTOSC (8MHz), the INTOSC postscaler or INTRC (31.25kHz). The RCIO Oscillator mode (Figure4-5) functions like the RC mode except that the OSC2 pin becomes an 4.5.1 INTRC MODES additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, FIGURE 4-5: RCIO OSCILLATOR MODE which can then be used for digital I/O. Two distinct configurations are available: VDD • In INTIO1 mode, the OSC2 pin outputs FOSC/4 REXT while OSC1 functions as RA7 for digital input and Internal output. OSC1 Clock • In INTIO2 mode, OSC1 functions as RA7 and CEXT OSC2 functions as RA6, both for digital input and output. VSS PIC16F818/819 RA6 I/O (OSC2) Recommended values: 3 k  REXT  100 k CEXT > 20 pF  2001-2013 Microchip Technology Inc. DS39598F-page 35

PIC16F818/819 4.5.2 OSCTUNE REGISTER When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new fre- The internal oscillator’s output has been calibrated at the quency. The INTRC clock will reach the new frequency factory but can be adjusted in the application. This is within 8clock cycles (approximately 8*32s=256s); done by writing to the OSCTUNE register (Register4-1). the INTOSC clock will stabilize within 1ms. Code execu- The tuning sensitivity is constant throughout the tuning tion continues during this shift. There is no indication that range. The OSCTUNE register has a tuning range of the shift has occurred. Operation of features that depend ±12.5%. on the 31.25kHz INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. REGISTER 4-1: OSCTUNE: OSCILLATOR TUNING REGISTER (ADDRESS 90h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 = • • • 100000 = Minimum frequency Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 36  2001-2013 Microchip Technology Inc.

PIC16F818/819 4.5.3 OSCILLATOR CONTROL REGISTER 4.5.5 CLOCK TRANSITION SEQUENCE WHEN THE IRCF BITS ARE The OSCCON register (Register4-2) controls several MODIFIED aspects of the system clock’s operation. The Internal Oscillator Select bits, IRCF2:IRCF0, select Following are three different sequences for switching the frequency output of the internal oscillator block that the internal RC oscillator frequency. is used to drive the system clock. The choices are the • Clock before switch:31.25kHz (IRCF<2:0> = 000) INTRC source (31.25kHz), the INTOSC source 1. IRCF bits are modified to an INTOSC/INTOSC (8MHz) or one of the six frequencies derived from the postscaler frequency. INTOSC postscaler (125kHz to 4MHz). Changing the 2. The clock switching circuitry waits for a falling configuration of these bits has an immediate change on edge of the current clock, at which point CLKO the multiplexor’s frequency output. is held low. 4.5.4 MODIFYING THE IRCF BITS 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it The IRCF bits can be modified at any time regardless of switches CLKO to this new clock source. which clock source is currently being used as the 4. The IOFS bit is clear to indicate that the clock is system clock. The internal oscillator allows users to unstable and a 4ms (approx.) delay is started. change the frequency during run time. This is achieved Time dependent code should wait for IOFS to by modifying the IRCF bits in the OSCCON register. become set. The sequence of events that occur after the IRCF bits are modified is dependent upon the initial value of the 5. Switchover is complete. IRCF bits before they are modified. If the INTRC • Clock before switch: One of INTOSC/INTOSC (31.25kHz, IRCF<2:0> = 000) is running and the IRCF postscaler (IRCF<2:0>  000) bits are modified to any other value than ‘000’, a 4ms 1. IRCF bits are modified to INTRC (approx.) clock switch delay is turned on. Code execu- (IRCF<2:0>=000). tion continues at a higher than expected frequency 2. The clock switching circuitry waits for a falling while the new frequency stabilizes. Time sensitive code edge of the current clock, at which point CLKO should wait for the IOFS bit in the OSCCON register to is held low. become set before continuing. This bit can be 3. The clock switching circuitry then waits for eight monitored to ensure that the frequency is stable before falling edges of requested clock, after which it using the system clock in time critical applications. switches CLKO to this new clock source. If the IRCF bits are modified while the internal oscillator 4. Oscillator switchover is complete. is running at any other frequency than INTRC (31.25kHz, IRCF<2:0>  000), there is no need for a • Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> 000) 4ms (approx.) clock switch delay. The new INTOSC frequency will be stable immediately after the eight 1. IRCF bits are modified to a different INTOSC/ falling edges. The IOFS bit will remain set after clock INTOSC postscaler frequency. switching occurs. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO Note: Caution must be taken when modifying the is held low. IRCF bits using BCF or BSF instructions. It 3. The clock switching circuitry then waits for eight is possible to modify the IRCF bits to a falling edges of requested clock, after which it frequency that may be out of the VDD spec- switches CLKO to this new clock source. ification range; for example, VDD = 2.0V and IRCF=111 (8 MHz). 4. The IOFS bit is set. 5. Oscillator switchover is complete.  2001-2013 Microchip Technology Inc. DS39598F-page 37

PIC16F818/819 FIGURE 4-6: PIC16F818/819 CLOCK DIAGRAM PIC18F818/819 CONFIG (FO SC2:FOSC0) OSC2 Sleep LP, XT, HS, RC, EC OSC1 Peripherals X U M OSCCON<6:4> Internal Oscillator 8 MHz 111 4 MHz Internal 110 CPU Oscillator 2 MHz 101 Block 8 MHz stscaler 5010 M kHHzz 100101 MUX 31.25 kHz (INTOSC) Po 250 kHz 010 Source 125 kHz 001 31.25 kHz 31.25 kHz 000 WDT (INTRC) REGISTER 4-2: OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh) U-0 R/W-0 R/W-0 R/W-0 U-0 R-0 U-0 U-0 — IRCF2 IRCF1 IRCF0 — IOFS — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8MHz (8MHz source drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31.25kHz (INTRC source drives clock directly) bit 3 Unimplemented: Read as ‘0’ bit 2 IOFS: INTOSC Frequency Stable bit 1 = Frequency is stable 0 = Frequency is not stable bit 1-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 38  2001-2013 Microchip Technology Inc.

PIC16F818/819 5.0 I/O PORTS Pin RA4 is multiplexed with the Timer0 module clock input and with an analog input to become the RA4/AN4/ Some pins for these I/O ports are multiplexed with an T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt alternate function for the peripheral features on the Trigger input and full CMOS output driver. device. In general, when a peripheral is enabled, that Pin RA5 is multiplexed with the Master Clear module pin may not be used as a general purpose I/O pin. input. The RA5/MCLR/VPP pin is a Schmitt Trigger input. Additional information on I/O ports may be found in the Pin RA6 is multiplexed with the oscillator module input “PIC® Mid-Range MCU Family Reference Manual” and external oscillator output. Pin RA7 is multiplexed (DS33023). with the oscillator module input and external oscillator input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI 5.1 PORTA and the TRISA Register are Schmitt Trigger inputs and full CMOS output drivers. PORTA is an 8-bit wide, bidirectional port. The corre- Pins RA<1:0> are multiplexed with analog inputs. Pins sponding data direction register is TRISA. Setting a RA<3:2> are multiplexed with analog inputs and VREF TRISA bit (=1) will make the corresponding PORTA inputs. Pins RA<3:0> have TTL inputs and full CMOS pin an input (i.e., put the corresponding output driver in output drivers. a high-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output (i.e., EXAMPLE 5-1: INITIALIZING PORTA put the contents of the output latch on the selected pin). BANKSEL PORTA ; select bank of PORTA Note: On a Power-on Reset, the pins CLRF PORTA ; Initialize PORTA by PORTA<4:0> are configured as analog ; clearing output inputs and read as ‘0’. ; data latches BANKSEL ADCON1 ; Select Bank of ADCON1 Reading the PORTA register reads the status of the MOVLW 0x06 ; Configure all pins pins, whereas writing to it will write to the port latch. All MOVWF ADCON1 ; as digital inputs write operations are read-modify-write operations. MOVLW 0xFF ; Value used to Therefore, a write to a port implies that the port pins are ; initialize data read, this value is modified and then written to the port ; direction data latch. MOVWF TRISA ; Set RA<7:0> as inputs TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2/VREF- bit2 TTL Input/output, analog input or VREF-. RA3/AN3/VREF+ bit3 TTL Input/output, analog input or VREF+. RA4/AN4/T0CKI bit4 ST Input/output, analog input or external clock input for Timer0. RA5/MCLR/VPP bit5 ST Input, Master Clear (Reset) or programming voltage input. RA6/OSC2/CLKO bit6 ST Input/output, connects to crystal or resonator, oscillator output or 1/4 the frequency of OSC1 and denotes the instruction cycle in RC mode. RA7/OSC1/CLKI bit7 ST/CMOS(1) Input/output, connects to crystal or resonator or oscillator input. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxx0 0000 uuu0 0000 85h TRISA TRISA7 TRISA6 TRISA5(1) PORTA Data Direction Register 1111 1111 1111 1111 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.  2001-2013 Microchip Technology Inc. DS39598F-page 39

PIC16F818/819 FIGURE 5-1: BLOCK DIAGRAM OF FIGURE 5-3: BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS RA2/AN2/VREF- PIN Data Data Bus D Q Bus D Q WR VDD WR VDD PORTA VDD PORTA VDD CK Q P CK Q P Data Latch Data Latch D Q D Q WR N I/O pin WR N I/O pin TRISA TRISA CK Q CK Q VSS VSS TRIS Latch VSS TRIS Latch VSS Analog Analog Input Mode Input Mode TTL Input Buffer TTL RD TRISA Input Buffer RD TRISA Q D Q D EN EN RD PORTA RD PORTA To A/D Module VREF- Input To A/D Module Channel Input To A/D Module Channel Input FIGURE 5-2: BLOCK DIAGRAM OF FIGURE 5-4: BLOCK DIAGRAM OF RA3/AN3/VREF+ PIN RA4/AN4/T0CKI PIN Data Data Bus Bus D Q D Q WR VDD WR VDD PORTA VDD PORTA VDD CK Q CK Q P P Data Latch Data Latch D Q D Q WR N I/O pin WR N I/O pin TRISA TRISA CK Q CK Q VSS VSS TRIS Latch VSS TRIS Latch VSS Analog Analog Input Mode Input Mode TTL Schmitt Trigger Input Buffer Input Buffer RD TRISA RD TRISA Q D Q D EN EN RD PORTA RD PORTA To A/D Module VREF+ Input TMR0 Clock Input To A/D Module Channel Input To A/D Module Channel Input DS39598F-page 40  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/VPP PIN MCLRE MCLR Circuit Schmitt Trigger Buffer MCLR Filter Data Bus RD TRIS VSS Schmitt Trigger RA5/MCLR/VPP Input Buffer VSS Q D EN MCLRE RD Port FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN From OSC1 Oscillator CLKO (FOSC/4) Circuit VDD VDD P RA6/OSC2/CLKO (FOSC = 1x1) N VSS Data Bus D Q VSS VDD WR PORTA Q CK P Data Latch D Q WR N TRISA CK Q (FOSC = 1x0,011) TRIS Latch VSS RD TRISA Schmitt Trigger Input Buffer Q D EN RD PORTA (FOSC = 1x0,011) Note 1: I/O pins have protection diodes to VDD and VSS. 2: CLKO signal is 1/4 of the FOSC frequency.  2001-2013 Microchip Technology Inc. DS39598F-page 41

PIC16F818/819 FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN From OSC2 Oscillator Circuit VDD (FOSC = 011) Data Bus D Q RA7/OSC1/CLKI VDD WR PORTA Q VSS CK P Data Latch D Q WR TRISA N CK Q TRIS Latch FOSC = 10x VSS RD TRISA Schmitt Trigger Input Buffer Q D EN FOSC = 10x RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS. DS39598F-page 42  2001-2013 Microchip Technology Inc.

PIC16F818/819 5.2 PORTB and the TRISB Register A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and PORTB is an 8-bit wide, bidirectional port. The corre- allow flag bit RBIF to be cleared. sponding data direction register is TRISB. Setting a The interrupt-on-change feature is recommended for TRISB bit (=1) will make the corresponding PORTB wake-up on key depression operation and operations pin an input (i.e., put the corresponding output driver in where PORTB is only used for the interrupt-on-change a high-impedance mode). Clearing a TRISB bit (=0) feature. Polling of PORTB is not recommended while will make the corresponding PORTB pin an output (i.e., using the interrupt-on-change feature. put the contents of the output latch on the selected pin). RB0/INT is an external interrupt input pin and is Each of the PORTB pins has a weak internal pull-up. A configured using the INTEDG bit (OPTION_REG<6>). single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). PORTB is multiplexed with several peripheral functions The weak pull-up is automatically turned off when the (see Table5-3). PORTB pins have Schmitt Trigger port pin is configured as an output. The pull-ups are input buffers. disabled on a Power-on Reset. When enabling peripheral functions, care should be Four of PORTB’s pins, RB7:RB4, have an interrupt-on- taken in defining TRIS bits for each PORTB pin. Some change feature. Only pins configured as inputs can peripherals override the TRIS bit to make a pin an out- cause this interrupt to occur (i.e., any RB7:RB4 pin put, while other peripherals override the TRIS bit to configured as an output is excluded from the interrupt- make a pin an input. Since the TRIS bit override is in on-change comparison). The input pins (of RB7:RB4) effect while the peripheral is enabled, read-modify- are compared with the old value latched on the last write instructions (BSF, BCF, XORWF) with TRISB as read of PORTB. The “mismatch” outputs of RB7:RB4 the destination should be avoided. The user should are ORed together to generate the RB Port Change refer to the corresponding peripheral section for the Interrupt with Flag bit, RBIF (INTCON<0>). correct TRIS bit settings. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF.  2001-2013 Microchip Technology Inc. DS39598F-page 43

PIC16F818/819 TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1/SDI/SDA bit1 TTL/ST(5) Input/output pin, SPI data input pin or I2C™ data I/O pin. Internal software programmable weak pull-up. RB2/SDO/CCP1 bit2 TTL/ST(4) Input/output pin, SPI data output pin or Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up. RB3/CCP1/PGM(3) bit3 TTL/ST(2) Input/output pin, Capture input/Compare output/PWM output pin or programming in LVP mode. Internal software programmable weak pull-up. RB4/SCK/SCL bit4 TTL/ST(5) Input/output pin or SPI and I2C clock pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5/SS bit5 TTL Input/output pin or SPI slave select pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6/T1OSO/T1CKI/ bit6 TTL/ST(2) Input/output pin, Timer1 oscillator output pin, Timer1 clock input pin or PGC serial programming clock (with interrupt-on-change). Internal software programmable weak pull-up. RB7/T1OSI/PGD bit7 TTL/ST(2) Input/output pin, Timer1 oscillator input pin or serial programming data (with interrupt-on-change). Internal software programmable weak pull-up. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: Low-Voltage ICSP™ Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 18-pin mid-range devices. 4: This buffer is a Schmitt Trigger input when configured for CCP or SSP mode. 5: This buffer is a Schmitt Trigger input when configured for SPI or I2C mode. TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS39598F-page 44  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 5-8: BLOCK DIAGRAM OF RB0 PIN VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q WR PORTB I/O pin(1) CK TRIS Latch D Q WR TTL TRISB CK Input Buffer RD TRISB Q D RD PORTB EN To INT0 or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.  2001-2013 Microchip Technology Inc. DS39598F-page 45

PIC16F818/819 FIGURE 5-9: BLOCK DIAGRAM OF RB1 PIN I2C™ Mode Port/SSPEN Select SDA Output 1 0 VDD RBPU(2) Weak PPull-up Data Latch VDD Data Bus WR D Q P PORTB CK I/O pin(1) N VSS TRIS Latch D Q WR TRISB CK Q RD TRISB TTL SDA Drive Input Buffer Q D RD PORTB EN Schmitt Trigger Buffer RD PORTB SDA(3) SDI Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SDA Schmitt Trigger conforms to the I2C specification. DS39598F-page 46  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 5-10: BLOCK DIAGRAM OF RB2 PIN CCPMX Module Select SDO 0 0 CCP 1 1 VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q WR PORTB CK I/O pin(1) TRIS Latch D Q WR TTL TRISB Input CK Buffer RD TRISB Q D RD PORTB EN RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.  2001-2013 Microchip Technology Inc. DS39598F-page 47

PIC16F818/819 FIGURE 5-11: BLOCK DIAGRAM OF RB3 PIN CCP1<M3:M0> = 1000, 1001, 11xx and CCPMX = 0 CCP1<M3:M0> = 0100, 0101, 0110, 0111 and CCPMX = 0 CCP 0 or LVP = 1 1 VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q WR PORTB CK I/O pin(1) TRIS Latch D Q WR TTL TRISB Input CK Buffer RD TRISB Q D RD PORTB EN To PGM or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS39598F-page 48  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 5-12: BLOCK DIAGRAM OF RB4 PIN Port/SSPEN SCK/SCL 1 0 VDD RBPU(2) Weak P Pull-up VDD SCL Drive P Data Latch Data Bus D Q WR PORTB N I/O pin(1) CK TRIS Latch D Q VSS WR TRISB CK TTL Input RD TRISB Buffer Latch Q D RD PORTB EN Q1 Set RBIF From other Q D RD PORTB RB7:RB4 pins EN Q3 SCK SCL(3) Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SCL Schmitt Trigger conforms to the I2C™ specification.  2001-2013 Microchip Technology Inc. DS39598F-page 49

PIC16F818/819 FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU(2) VDD Port/SSPEN Weak P Pull-up Data Latch Data Bus D Q WR I/O pin(1) PORTB CK TRIS Latch D Q WR TRISB CK TTL Input RD TRISB Buffer Latch Q D RD PORTB EN Q1 Set RBIF From other Q D RD PORTB RB7:RB4 pins EN Q3 SS Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS39598F-page 50  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 5-14: BLOCK DIAGRAM OF RB6 PIN VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q WR PORTB I/O pin(1) CK TRIS Latch D Q WR TRISB CK T1OSCEN RD TRISB TTL T1OSCEN/ICD/ Input Buffer Program Mode Latch Q D RD PORTB EN Q1 Set RBIF From other Q D RD PORTB RB7:RB4 pins EN Q3 T1CKI/PGC From T1OSO Output Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.  2001-2013 Microchip Technology Inc. DS39598F-page 51

PIC16F818/819 FIGURE 5-15: BLOCK DIAGRAM OF RB7 PIN Port/Program Mode/ICD PGD 1 0 VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D Q WPORRTB I/O pin(1) CK TRIS Latch D Q 0 WR TRISB CK 1 RD TRISB T1OSCEN T1OSCEN Analog Input Mode PGD DRVEN TTL Input Buffer Latch Q D RD PORTB EN Q1 Set RBIF From other Q D RB7:RB4 pins RD PORTB EN Q3 PGD To T1OSI Input Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS39598F-page 52  2001-2013 Microchip Technology Inc.

PIC16F818/819 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will The Timer0 module timer/counter has the following increment either on every rising or falling edge of pin features: RA4/AN4/T0CKI. The incrementing edge is determined • 8-bit timer/counter by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the • Readable and writable rising edge. Restrictions on the external clock input are • 8-bit software programmable prescaler discussed in detail in Section6.3 “Using Timer0 with • Internal or external clock select an External Clock”. • Interrupt-on-overflow from FFh to 00h The prescaler is mutually exclusively shared between • Edge select for external clock the Timer0 module and the Watchdog Timer. The Additional information on the Timer0 module is prescaler is not readable or writable. Section6.4 available in the “PIC® Mid-Range MCU Family Refer- “Prescaler” details the operation of the prescaler. ence Manual” (DS33023). 6.2 Timer0 Interrupt Figure6-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets 6.1 Timer0 Operation bit, TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit, TMR0IE (INTCON<5>). Bit Timer0 operation is controlled through the TMR0IF must be cleared in software by the Timer0 OPTION_REG register (see Register2-2). Timer mode module Interrupt Service Routine before re-enabling is selected by clearing bit T0CS (OPTION_REG<5>). this interrupt. The TMR0 interrupt cannot awaken the In Timer mode, the Timer0 module will increment every processor from Sleep since the timer is shut-off during instruction cycle (without prescaler). If the TMR0 regis- Sleep. ter is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKO (= FOSC/4) Data Bus 8 M 0 1 U M Sync X 1 0 U 2 TMR0 reg RA4/AN4/T0CKI X Cycles pin T0SE T0CS PSA Set Flag bit TMR0IF on Overflow PRESCALER 0 8-bit Prescaler M WDT Timer U 1 X 8 31.25kHz 8-to-1 MUX PS2:PS0 WDT Enable bit PSA 0 1 MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  2001-2013 Microchip Technology Inc. DS39598F-page 53

PIC16F818/819 6.3 Using Timer0 with an Timer0 module means that there is no prescaler for the External Clock Watchdog Timer and vice versa. This prescaler is not readable or writable (see Figure6-1). When no prescaler is used, the external clock input is The PSA and PS2:PS0 bits (OPTION_REG<3:0>) the same as the prescaler output. The synchronization determine the prescaler assignment and prescale ratio. of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and When assigned to the Timer0 module, all instructions Q4 cycles of the internal phase clocks. Therefore, it is writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, necessary for T0CKI to be high for at least 2TOSC (and BSF 1, x....etc.) will clear the prescaler. When a small RC delay of 20 ns) and low for at least 2TOSC assigned to WDT, a CLRWDT instruction will clear the (and a small RC delay of 20 ns). Refer to the electrical prescaler along with the Watchdog Timer. The specification of the desired device. prescaler is not readable or writable. Note: Writing to TMR0 when the prescaler is 6.4 Prescaler assigned to Timer0 will clear the prescaler There is only one prescaler available which is mutually count but will not change the prescaler exclusively shared between the Timer0 module and the assignment. Watchdog Timer. A prescaler assignment for the REGISTER 6-1: OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device Reset, the instruction sequence shown in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS39598F-page 54  2001-2013 Microchip Technology Inc.

PIC16F818/819 EXAMPLE 6-1: CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT BANKSEL OPTION_REG ; Select Bank of OPTION_REG MOVLW b'xx0x0xxx' ; Select clock source and prescale value of MOVWF OPTION_REG ; other than 1:1 BANKSEL TMR0 ; Select Bank of TMR0 CLRF TMR0 ; Clear TMR0 and prescaler BANKSEL OPTION_REG ; Select Bank of OPTION_REG MOVLW b'xxxx1xxx' ; Select WDT, do not change prescale value MOVWF OPTION_REG CLRWDT ; Clears WDT and prescaler MOVLW b'xxxx1xxx' ; Select new prescale value and WDT MOVWF OPTION_REG EXAMPLE 6-2: CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0 CLRWDT ; Clear WDT and prescaler BANKSEL OPTION_REG ; Select Bank of OPTION_REG MOVLW b'xxxx0xxx' ; Select TMR0, new prescale MOVWF OPTION_REG ; value and clock source TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.  2001-2013 Microchip Technology Inc. DS39598F-page 55

PIC16F818/819 NOTES: DS39598F-page 56  2001-2013 Microchip Technology Inc.

PIC16F818/819 7.0 TIMER1 MODULE The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). The Timer1 module is a 16-bit timer/counter consisting In Timer mode, Timer1 increments every instruction of two 8-bit registers (TMR1H and TMR1L) which are cycle. In Counter mode, it increments on every rising readable and writable. The TMR1 register pair edge of the external clock input. (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, Timer1 can be enabled/disabled by setting/clearing is generated on overflow which is latched in interrupt control bit, TMR1ON (T1CON<0>). flag bit, TMR1IF (PIR1<0>). This interrupt can be Timer1 also has an internal “Reset input”. This Reset enabled/disabled by setting/clearing TMR1 Interrupt can be generated by the CCP1 module as the special Enable bit, TMR1IE (PIE1<0>). event trigger (see Section9.1 “Capture Mode”). Timer1 can also be used to provide Real-Time Clock Register7-1 shows the Timer1 Control register. (RTC) functionality to applications with only a minimal When the Timer1 oscillator is enabled (T1OSCEN is addition of external components and code overhead. set), the RB6/T1OSO/T1CKI/PGC and RB7/T1OSI/ PGD pins become inputs. That is, the TRISB<7:6> 7.1 Timer1 Operation value is ignored and these pins read as ‘0’. Timer1 can operate in one of three modes: Additional information on timer modules is available in the “PIC® Mid-Range MCU Family Reference Manual” • as a timer (DS33023). • as a synchronous counter • as an asynchronous counter REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 57

PIC16F818/819 7.2 Timer1 Operation in Timer Mode 7.4 Timer1 Operation in Synchronized Counter Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the Counter mode is selected by setting bit TMR1CS. In timer is FOSC/4. The synchronize control bit, T1SYNC this mode, the timer increments on every rising edge of (T1CON<2>), has no effect since the internal clock is clock input on pin RB7/T1OSI/PGD when bit always in sync. T1OSCEN is set, or on pin RB6/T1OSO/T1CKI/PGC when bit T1OSCEN is cleared. 7.3 Timer1 Counter Operation If T1SYNC is cleared, then the external clock input is Timer1 may operate in Asynchronous or Synchronous synchronized with internal phase clocks. The synchro- mode depending on the setting of the TMR1CS bit. nization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 In this configuration, during Sleep mode, Timer1 will not is enabled in Counter mode, the module must first have increment even if the external clock is present, since a falling edge before the counter begins to increment. the synchronization circuit is shut-off. The prescaler, however, will continue to increment. FIGURE 7-1: TIMER1 INCREMENTING EDGE T1CKI (Default High) T1CKI (Default Low) Note: Arrows indicate counter increments. FIGURE 7-2: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow Synchronized TMR1 0 Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC 1 Synchronize Prescaler RB6/T1OSO/T1CKI/PGC T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 Oscillator(1) Clock 2 Q Clock RB7/T1OSI/PGD T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. DS39598F-page 58  2001-2013 Microchip Technology Inc.

PIC16F818/819 7.5 Timer1 Operation in 7.5.1 READING AND WRITING TIMER1 Asynchronous Counter Mode IN ASYNCHRONOUS COUNTER MODE If control bit, T1SYNC (T1CON<2>), is set, the external clock input is not synchronized. The timer continues to Reading TMR1H or TMR1L while the timer is running increment asynchronous to the internal phase clocks. from an external asynchronous clock will ensure a valid The timer will continue to run during Sleep and can read (taken care of in hardware). However, the user generate an interrupt on overflow that will wake-up the should keep in mind that reading the 16-bit timer in two processor. However, special precautions in software 8-bit values itself poses certain problems, since the are needed to read/write the timer. timer may overflow between the reads. In Asynchronous Counter mode, Timer1 cannot be For writes, it is recommended that the user simply stop used as a time base for capture or compare operations. the timer and write the desired values. A write conten- tion may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. The example codes provided in Example7-1 and Example7-2 demonstrate how to write to and read Timer1 while it is running in Asynchronous mode. EXAMPLE 7-1: WRITING A 16-BIT FREE RUNNING TIMER ; All interrupts are disabled CLRF TMR1L ; Clear Low byte, Ensures no rollover into TMR1H MOVLW HI_BYTE ; Value to load into TMR1H MOVWF TMR1H, F ; Write High byte MOVLW LO_BYTE ; Value to load into TMR1L MOVWF TMR1H, F ; Write Low byte ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code EXAMPLE 7-2: READING A 16-BIT FREE RUNNING TIMER ; All interrupts are disabled MOVF TMR1H, W ; Read high byte MOVWF TMPH MOVF TMR1L, W ; Read low byte MOVWF TMPL MOVF TMR1H, W ; Read high byte SUBWF TMPH, W ; Sub 1st read with 2nd read BTFSC STATUS, Z ; Is result = 0 GOTO CONTINUE ; Good 16-bit read ; TMR1L may have rolled over between the read of the high and low bytes. ; Reading the high and low bytes now will read a good value. MOVF TMR1H, W ; Read high byte MOVWF TMPH MOVF TMR1L, W ; Read low byte MOVWF TMPL ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code  2001-2013 Microchip Technology Inc. DS39598F-page 59

PIC16F818/819 7.6 Timer1 Oscillator TABLE 7-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by Osc Type Freq C1 C2 setting control bit, T1OSCEN (T1CON<3>). The LP 32 kHz 33 pF 33 pF oscillator is a low-power oscillator, rated up to 32.768kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. The circuit for a Note1: Microchip suggests this value as a starting typical LP oscillator is shown in Figure7-3. Table7-1 point in validating the oscillator circuit. shows the capacitor selection for the Timer1 oscillator. 2: Higher capacitance increases the stability The user must provide a software time delay to ensure of the oscillator but also increases the proper oscillator start-up. start-up time. Note: The Timer1 oscillator shares the T1OSI 3: Since each resonator/crystal has its own and T1OSO pins with the PGD and PGC characteristics, the user should consult pins used for programming and the resonator/crystal manufacturer for debugging. appropriate values of external components. When using the Timer1 oscillator, In-Circuit Serial Programming™ (ICSP™) may not 4: Capacitor values are for design guidance function correctly (high-voltage or low- only. voltage) or the In-Circuit Debugger (ICD) may not communicate with the controller. 7.7 Timer1 Oscillator Layout As a result of using either ICSP or ICD, the Considerations Timer1 crystal may be damaged. The Timer1 oscillator circuit draws very little power If ICSP or ICD operations are required, the during operation. Due to the low-power nature of the crystal should be disconnected from the oscillator, it may also be sensitive to rapidly changing circuit (disconnect either lead) or installed signals in close proximity. after programming. The oscillator loading capacitors may remain in-circuit during The oscillator circuit, shown in Figure7-3, should be ICSP or ICD operation. located as close as possible to the microcontroller. There should be no circuits passing within the oscillator FIGURE 7-3: EXTERNAL circuit boundaries other than VSS or VDD. COMPONENTS FOR THE If a high-speed circuit must be located near the oscilla- TIMER1 LP OSCILLATOR tor, a grounded guard ring around the oscillator circuit, as shown in Figure7-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. C1 PIC16F818/819 33 pF T1OSI FIGURE 7-4: OSCILLATOR CIRCUIT WITH GROUNDED XTAL 32.768 kHz GUARD RING T1OSO C2 33 pF VSS Note: See the Notes with Table7-1 for additional OSC1 information about capacitor selection. OSC2 RB7 RB6 RB5 DS39598F-page 60  2001-2013 Microchip Technology Inc.

PIC16F818/819 7.8 Resetting Timer1 Using a CCP 7.11 Using Timer1 as a Trigger Output Real-Time Clock If the CCP1 module is configured in Compare mode to Adding an external LP oscillator to Timer1 (such as the generate a “special event trigger” signal one described in Section7.6 “Timer1 Oscillator”), (CCP1M3:CCP1M0 = 1011), the signal will reset gives users the option to include RTC functionality in Timer1 and start an A/D conversion (if the A/D module their applications. This is accomplished with an inex- is enabled). pensive watch crystal to provide an accurate time base and several lines of application code to calculate the Timer1 must be configured for either Timer or Synchro- time. When operating in Sleep mode and using a nized Counter mode to take advantage of this feature. battery or supercapacitor as a power source, it can If Timer1 is running in Asynchronous Counter mode, completely eliminate the need for a separate RTC this Reset operation may not work. device and battery backup. In the event that a write to Timer1 coincides with a The application code routine, RTCisr, shown in special event trigger from CCP1, the write will take Example7-3, demonstrates a simple method to precedence. increment a counter at one-second intervals using an In this mode of operation, the CCPR1H:CCPR1L Interrupt Service Routine. Incrementing the TMR1 register pair effectively becomes the period register for register pair to overflow, triggers the interrupt and calls Timer1. the routine which increments the seconds counter by one; additional counters for minutes and hours are 7.9 Resetting Timer1 Register Pair incremented as the previous counter overflows. (TMR1H, TMR1L) Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768kHz clock TMR1H and TMR1L registers are not reset to 00h on a would take 2 seconds. To force the overflow at the POR or any other Reset, except by the CCP1 special required one-second intervals, it is necessary to pre- event triggers. load it; the simplest method is to set the MSb of TMR1H T1CON register is reset to 00h on a Power-on Reset or with a BSF instruction. Note that the TMR1L register is a Brown-out Reset, which shuts off the timer and never preloaded or altered; doing so may introduce leaves a 1:1 prescale. In all other Resets, the register cumulative error over many cycles. is unaffected. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt 7.10 Timer1 Prescaler must be enabled (PIE1<0> = 1) as shown in the routine, The prescaler counter is cleared on writes to the RTCinit. The Timer1 oscillator must also be enabled TMR1H or TMR1L registers. and running at all times.  2001-2013 Microchip Technology Inc. DS39598F-page 61

PIC16F818/819 EXAMPLE 7-3: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit BANKSEL TMR1H MOVLW 0x80 ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins MOVLW .12 MOVWF hours BANKSEL PIE1 BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BANKSEL TMR1H BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVF secs, w SUBLW .60 BTFSS STATUS, Z ; 60 seconds elapsed? RETURN ; No, done CLRF seconds ; Clear seconds INCF mins, f ; Increment minutes MOVF mins, w SUBLW .60 BTFSS STATUS, Z ; 60 seconds elapsed? RETURN ; No, done CLRF mins ; Clear minutes INCF hours, f ; Increment hours MOVF hours, w SUBLW .24 BTFSS STATUS, Z ; 24 hours elapsed? RETURN ; No, done CLRF hours ; Clear hours RETURN ; Done TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. DS39598F-page 62  2001-2013 Microchip Technology Inc.

PIC16F818/819 8.0 TIMER2 MODULE 8.1 Timer2 Prescaler and Postscaler Timer2 is an 8-bit timer with a prescaler and a The prescaler and postscaler counters are cleared postscaler. It can be used as the PWM time base for the when any of the following occurs: PWM mode of the CCP1 module. The TMR2 register is • A write to the TMR2 register readable and writable and is cleared on any device • A write to the T2CON register Reset. • Any device Reset (Power-on Reset, MCLR, WDT The input clock (FOSC/4) has a prescale option of 1:1, Reset or Brown-out Reset) 1:4 or 1:16, selected by control bits, TMR2 is not cleared when T2CON is written. T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. 8.2 Output of TMR2 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is The output of TMR2 (before the postscaler) is fed to the a readable and writable register. The PR2 register is Synchronous Serial Port module which optionally uses initialized to FFh upon Reset. it to generate a shift clock. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) FIGURE 8-1: TIMER2 BLOCK DIAGRAM to generate a TMR2 interrupt (latched in flag bit, Sets Flag TMR2IF (PIR1<1>)). TMR2 bit TMR2IF Output(1) Timer2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. Reset Prescaler TMR2 reg FOSC/4 Register8-1 shows the Timer2 Control register. 1:1, 1:4, 1:16 Additional information on timer modules is available in Postscaler Comparator 2 1:1 to 1:16 EQ the “PIC® Mid-Range MCU Family Reference Manual” (DS33023). 4 PR2 reg Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.  2001-2013 Microchip Technology Inc. DS39598F-page 63

PIC16F818/819 REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale 0010 =1:3 Postscale • • • 1111 =1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. DS39598F-page 64  2001-2013 Microchip Technology Inc.

PIC16F818/819 9.0 CAPTURE/COMPARE/PWM The CCP module’s input/output pin (CCP1) can be (CCP) MODULE configured as RB2 or RB3. This selection is set in bit 12 (CCPMX) of the Configuration Word register. The Capture/Compare/PWM (CCP) module contains a Additional information on the CCP module is available 16-bit register that can operate as a: in the “PIC® Mid-Range MCU Family Reference Man- • 16-bit Capture register ual” (DS33023) and in Application Note AN594, “Using • 16-bit Compare register the CCP Module(s)” (DS00594). • PWM Master/Slave Duty Cycle register TABLE 9-1: CCP MODE – TIMER Table9-1 shows the timer resources of the CCP RESOURCE module modes. CCP Mode Timer Resource Capture/Compare/PWM Register 1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and Capture Timer1 CCPR1H (high byte). The CCP1CON register controls Compare Timer1 the operation of CCP1. The special event trigger is PWM Timer2 generated by a compare match which will reset Timer1 and start an A/D conversion (if the A/D module is enabled). REGISTER 9-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCP1 module) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 65

PIC16F818/819 9.1 Capture Mode 9.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchro- 16-bit value of the TMR1 register when an event occurs nized Counter mode for the CCP module to use the on the CCP1 pin. An event is defined as: capture feature. In Asynchronous Counter mode, the capture operation may not work. • Every falling edge • Every rising edge 9.1.3 SOFTWARE INTERRUPT • Every 4th rising edge When the Capture mode is changed, a false capture • Every 16th rising edge interrupt may be generated. The user should keep bit, CCP1IE (PIE1<2>), clear to avoid false interrupts and An event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the inter- should clear the flag bit, CCP1IF, following any such change in operating mode. rupt request flag bit, CCP1IF (PIR1<2>), is set. It must be cleared in software. If another capture occurs before 9.1.4 CCP PRESCALER the value in register CCPR1 is read, the old captured value is overwritten by the new captured value. There are four prescaler settings specified by bits CCP1M3:CCP1M0. Whenever the CCP module is 9.1.1 CCP PIN CONFIGURATION turned off, or the CCP module is not in Capture mode, In Capture mode, the CCP1 pin should be configured the prescaler counter is cleared. This means that any as an input by setting the TRISB<x> bit. Reset will clear the prescaler counter. Switching from one capture prescaler to another may Note1: If the CCP1 pin is configured as an generate an interrupt. Also, the prescaler counter will output, a write to the port can cause a not be cleared; therefore, the first capture may be from capture condition. a non-zero prescaler. Example9-1 shows the 2: The TRISB bit (2 or 3) is dependent upon recommended method for switching between capture the setting of configuration bit 12 prescalers. This example also clears the prescaler (CCPMX). counter and will not generate the “false” interrupt. FIGURE 9-1: CAPTURE MODE EXAMPLE 9-1: CHANGING BETWEEN OPERATION BLOCK CAPTURE PRESCALERS DIAGRAM CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with Set Flag bit CCP1IF (PIR1<2>) ;the new prescaler Prescaler ;move value and CCP ON  1, 4, 16 MOVWF CCP1CON ;Load CCP1CON with this CCP1 pin CCPR1H CCPR1L ;value and Capture Edge Detect Enable TMR1H TMR1L CCP1CON<3:0> Q’s DS39598F-page 66  2001-2013 Microchip Technology Inc.

PIC16F818/819 9.2 Compare Mode 9.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is The user must configure the CCP1 pin as an output by constantly compared against the TMR1 register pair clearing the TRISB<x> bit. value. When a match occurs, the CCP1 pin is: Note1: Clearing the CCP1CON register will force • Driven high the CCP1 compare output latch to the default low level. This is not the data • Driven low latch. • Remains unchanged 2: The TRISB bit (2 or 3) is dependent upon The action on the pin is based on the value of control the setting of configuration bit 12 bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the (CCPMX). same time, interrupt flag bit CCP1IF is set. 9.2.2 TIMER1 MODE SELECTION FIGURE 9-2: COMPARE MODE Timer1 must be running in Timer mode or Synchro- OPERATION BLOCK nized Counter mode if the CCP module is using the DIAGRAM compare feature. In Asynchronous Counter mode, the Special Event Trigger compare operation may not work. Set Flag bit CCP1IF 9.2.3 SOFTWARE INTERRUPT MODE (PIR1<2>) CCPR1H CCPR1L When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if CCP1 pin Q RS OLuotgpicut Match Comparator enabled). TRISB<x> TMR1H TMR1L 9.2.4 SPECIAL EVENT TRIGGER Output Enable CCP1CON<3:0> Mode Select In this mode, an internal hardware trigger is generated Special event trigger will: that may be used to initiate an action. • Reset Timer1 but not set interrupt flag bit, TMR1IF The special event trigger output of CCP1 resets the (PIR1<0>) TMR1 register pair and starts an A/D conversion (if the • Set GO/DONE bit (ADCON0<2>) which starts an A/D conversion A/D module is enabled). This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Note: The special event trigger from the CCP1 module will not set interrupt flag bit, TMR1IF (PIR1<0>). TABLE 9-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10BH,18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.  2001-2013 Microchip Technology Inc. DS39598F-page 67

PIC16F818/819 9.3 PWM Mode 9.3.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP1 pin is multiplexed with the PORTB data latch, following formula. the TRISB<x> bit must be cleared to make the CCP1 pin an output. EQUATION 9-1: Note: Clearing the CCP1CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC • the CCP1 PWM output latch to the default (TMR2 Prescale Value) low level. This is not the PORTB I/O data latch. PWM frequency is defined as 1/[PWM period]. Figure9-3 shows a simplified block diagram of the When TMR2 is equal to PR2, the following three events CCP module in PWM mode. occur on the next increment cycle: For a step by step procedure on how to set up the CCP • TMR2 is cleared module for PWM operation, see Section9.3.3 “Setup • The CCP1 pin is set (exception: if PWM duty for PWM Operation”. cycle=0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into FIGURE 9-3: SIMPLIFIED PWM BLOCK CCPR1H DIAGRAM CCP1CON<5:4> Note: The Timer2 postscaler (see Section8.0 Duty Cycle Registers “Timer2 Module”) is not used in the CCPR1L determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. CCPR1H (Slave) 9.3.2 PWM DUTY CYCLE Comparator R Q The PWM duty cycle is specified by writing to the CCP1 pin CCPR1L register and to the CCP1CON<5:4> bits. Up TMR2 (Note 1) to 10-bit resolution is available. The CCPR1L contains S the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by Comparator TRISB<x> CCPR1L:CCP1CON<5:4>. The following equation is Clear Timer, CCP1 pin and used to calculate the PWM duty cycle in time. latch D.C. PR2 EQUATION 9-2: Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base. PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) A PWM output (Figure9-4) has a time base (period) and a time that the output stays high (duty cycle). The CCPR1L and CCP1CON<5:4> can be written to at any frequency of the PWM is the inverse of the period time but the duty cycle value is not latched into (1/period). CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, FIGURE 9-4: PWM OUTPUT CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are Period used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, Duty Cycle concatenated with an internal 2-bit Q clock or 2 bits of TMR2 = PR2 the TMR2 prescaler, the CCP1 pin is cleared. TMR2 = Duty Cycle TMR2 = PR2 DS39598F-page 68  2001-2013 Microchip Technology Inc.

PIC16F818/819 The maximum PWM resolution (bits) for a given PWM 9.3.3 SETUP FOR PWM OPERATION frequency is given by the following formula. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 9-3: 1. Set the PWM period by writing to the PR2 register. (FOSC ) log 2. Set the PWM duty cycle by writing to the FPWM Resolution = bits CCPR1L register and CCP1CON<5:4> bits. log(2) 3. Make the CCP1 pin an output by clearing the TRISB<x> bit. Note: If the PWM duty cycle value is longer than 4. Set the TMR2 prescale value and enable Timer2 the PWM period, the CCP1 pin will not be by writing to T2CON. cleared. 5. Configure the CCP1 module for PWM operation. Note: The TRISB bit (2 or 3) is dependant upon the setting of configuration bit 12 (CCPMX). TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 9-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 Module Register 0000 0000 0000 0000 92h PR2 Timer2 Module Period Register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.  2001-2013 Microchip Technology Inc. DS39598F-page 69

PIC16F818/819 NOTES: DS39598F-page 70  2001-2013 Microchip Technology Inc.

PIC16F818/819 10.0 SYNCHRONOUS SERIAL PORT 10.2 SPI Mode (SSP) MODULE This section contains register definitions and operational characteristics of the SPI module. 10.1 SSP Module Overview SPI mode allows 8 bits of data to be synchronously The Synchronous Serial Port (SSP) module is a serial transmitted and received simultaneously. To interface useful for communicating with other periph- accomplish communication, typically three pins are eral or microcontroller devices. These peripheral used: devices may be serial EEPROMs, shift registers, • Serial Data Out (SDO) RB2/SDO/CCP1 display drivers, A/D converters, etc. The SSP module • Serial Data In (SDI) RB1/SDI/SDA can operate in one of two modes: • Serial Clock (SCK) RB4/SCK/SCL • Serial Peripheral Interface (SPI) Additionally, a fourth pin may be used when in a Slave • Inter-Integrated Circuit (I2C) mode of operation: An overview of I2C operations and additional informa- • Slave Select (SS) RB5/SS tion on the SSP module can be found in the “PIC® Mid- When initializing the SPI, several options need to be Range MCU Family Reference Manual” (DS33023). specified. This is done by programming the appropriate Refer to Application Note AN578, “Use of the SSP control bits in the SSPCON register (SSPCON<5:0>) Module in the I2C™ Multi-Master Environment” and the SSPSTAT register (SSPSTAT<7:6>). These (DS00578). control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • Clock Polarity (Idle state of SCK) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) Note: Before enabling the module in SPI Slave mode, the state of the clock line (SCK) must match the polarity selected for the Idle state. The clock line can be observed by reading the SCK pin. The polarity of the Idle state is determined by the CKP bit (SSPCON<4>).  2001-2013 Microchip Technology Inc. DS39598F-page 71

PIC16F818/819 REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: This bit must be cleared when SPI is used in Slave mode. I 2 C mode: This bit must be maintained clear. bit 6 CKE: SPI Clock Edge Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPCON<4>). I 2 C mode: This bit must be maintained clear. bit 5 D/A: Data/Address bit (I2C mode only) In I 2 C Slave mode: 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was address bit 4 P: Stop bit(1) (I2C mode only) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) (I2C mode only) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only) Holds the R/W bit information following the last address match and is only valid from address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (In I 2 C mode only): 1 = Transmit in progress, SSPBUF is full (8 bits) 0 = Transmit complete, SSPBUF is empty Note1: This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 72  2001-2013 Microchip Technology Inc.

PIC16F818/819 REGISTER 10-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER 1 (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = An attempt to write the SSPBUF register failed because the SSP module is busy (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit(1) In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note1: In both modes, when enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Transmit happens on falling edge, receive on rising edge. Idle state for clock is a high level. 0 = Transmit happens on rising edge, receive on falling edge. Idle state for clock is a low level. In I 2 C Slave mode: SCK release control. 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 =SPI Master mode, clock = OSC/4 0001 =SPI Master mode, clock = OSC/16 0010 =SPI Master mode, clock = OSC/64 0011 =SPI Master mode, clock = TMR2 output/2 0100 =SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 =SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 =I2C Slave mode, 7-bit address 0111 =I2C Slave mode, 10-bit address 1011 =I2C Firmware Controlled Master mode (Slave Idle) 1110 =I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 =I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1000, 1001, 1010, 1100, 1101 = Reserved Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 73

PIC16F818/819 FIGURE 10-1: SSP BLOCK DIAGRAM To enable the serial port, SSP Enable bit, SSPEN (SPIMODE) (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear bit SSPEN, reinitialize the SSPCON register and then set bit SSPEN. This configures the Internal Data Bus SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must Read Write have their data direction bits (in the TRISB register) appropriately programmed. That is: SSPBUF reg • SDI must have TRISB<1> set • SDO must have TRISB<2> cleared • SCK (Master mode) must have TRISB<4> cleared SSPSR reg • SCK (Slave mode) must have TRISB<4> set RB1/SDI/SDA bit 0 Shift • SS must have TRISB<5> set Clock Note1: When the SPI is in Slave mode RB2/SDO/ with the SS pin control enabled CCP1 (SSPCON<3:0>=0100), the SPI module SS Control will reset if the SS pin is set to VDD. Enable 2: If the SPI is used in Slave mode with RB5/SS Edge CKE=1, then the SS pin control must be Select enabled. 3: When the SPI is in Slave mode 2 with the SS pin control enabled Clock Select (SSPCON<3:0>=0100), the state of the SS pin can affect the state read back from SSPM3:SSPM0 TMR2 Output the TRISB<2> bit. The peripheral OE 4 2 signal from the SSP module into PORTB Edge controls the state that is read back from Select Prescaler TCY the TRISB<2> bit. If read-modify-write RB4/SCK/ 4, 16, 64 instructions, such as BSF are performed SCL TRISB<4> on the TRISB register while the SS pin is high, this will cause the TRISB<2> bit to be set, thus disabling the SDO output. TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. DS39598F-page 74  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 10-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SDI (SMP = 1) bit 7 bit 0 SSPIF FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE=0) SS (Optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SSPIF FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE=1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 SSPIF  2001-2013 Microchip Technology Inc. DS39598F-page 75

PIC16F818/819 10.3 SSP I2C Mode Operation To ensure proper communication of the I2C Slave mode, the TRIS bits (TRISx [SDA, SCL]) corresponding to the The SSP module in I2C mode fully implements all slave I2C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>) functions, except general call support and provides of the port containing the I2C pins (PORTx [SDA, SCL]) interrupts on Start and Stop bits in hardware to facilitate are changed in software during I2C communication firmware implementations of the master functions. The using a Read-Modify-Write instruction (BSF, BCF), then SSP module implements the standard mode the I2C mode may stop functioning properly and I2C specifications, as well as 7-bit and 10-bit addressing. communication may suspend. Do not change any of the Two pins are used for data transfer. These are the TRISx bits (TRIS bits of the port containing the I2C pins) RB4/SCK/SCL pin, which is the clock (SCL) and the using the instruction BSF or BCF during I2C communica- RB1/SDI/SDA pin, which is the data (SDA). The user tion. If it is absolutely necessary to change the TRISx must configure these pins as inputs or outputs through bits during communication, the following method can be the TRISB<4,1> bits. used: EXAMPLE 10-1: MOVF TRISC, W ; Example for an 18-pin part such as the PIC16F818/819 IORLW 0x18 ; Ensures <4:3> bits are ‘11’ ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits ; User can use their own logic here, such as IORLW, XORLW and ANDLW MOVWF TRISC The SSP module functions are enabled by setting SSP The SSPCON register allows control of the I2C opera- Enable bit, SSPEN (SSPCON<5>). tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: FIGURE 10-5: SSP BLOCK DIAGRAM • I2C Slave mode (7-bit address) (I2C™ MODE) • I2C Slave mode (10-bit address) Internal • I2C Slave mode (7-bit address) with Start and Data Bus Stop bit interrupts enabled to support Firmware Read Write Master mode • I2C Slave mode (10-bit address) with Start and RB4/SCK/ SSPBUF Reg Stop bit interrupts enabled to support Firmware SCL Master mode Shift • I2C Firmware Controlled Master mode with Start Clock and Stop bit interrupts enabled, slave is Idle SSPSR Reg Selection of any I2C mode, with the SSPEN bit set, RB1/ MSb LSb forces the SCL and SDA pins to be open-drain, SDI/ provided these pins are programmed to inputs by SDA Match Detect Addr Match setting the appropriate TRISB bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. SSPADD Reg Additional information on SSP I2C operation may be found in the “PIC® Mid-Range MCU Family Reference Start and Set, Reset Manual” (DS33023). Stop Bit Detect S, P Bits (SSPSTAT Reg) The SSP module has five registers for I2C operation: • SSP Control Register (SSPCON) • SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) – Not directly accessible • SSP Address Register (SSPADD) DS39598F-page 76  2001-2013 Microchip Technology Inc.

PIC16F818/819 10.3.1 SLAVE MODE The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: In Slave mode, the SCL and SDA pins must be config- ured as inputs (TRISB<4,1> set). The SSP module will 1. Receive first (high) byte of address (bits SSPIF, override the input state with the output data when BF and bit UA (SSPSTAT<1>) are set). required (slave-transmitter). 2. Update the SSPADD register with second (low) When an address is matched, or the data transfer after byte of address (clears bit UA and releases the an address match is received, the hardware automati- SCL line). cally will generate the Acknowledge (ACK) pulse and 3. Read the SSPBUF register (clears bit BF) and then load the SSPBUF register with the received value clear flag bit, SSPIF. currently in the SSPSR register. 4. Receive second (low) byte of address (bits Either or both of the following conditions will cause the SSPIF, BF and UA are set). SSP module not to give this ACK pulse: 5. Update the SSPADD register with the first (high) byte of address; if match releases SCL line, this a) The Buffer Full bit, BF (SSPSTAT<0>), was set will clear bit UA. before the transfer was received. 6. Read the SSPBUF register (clears bit BF) and b) The overflow bit, SSPOV (SSPCON<6>), was clear flag bit, SSPIF. set before the transfer was received. 7. Receive Repeated Start condition. In this case, the SSPSR register value is not loaded 8. Receive first (high) byte of address (bits SSPIF into the SSPBUF but bit, SSPIF (PIR1<3>), is set. and BF are set). Table10-2 shows what happens when a data transfer byte is received, given the status of bits BF and 9. Read the SSPBUF register (clears bit BF) and SSPOV. The shaded cells show the condition where clear flag bit, SSPIF. user software did not properly clear the overflow condi- 10.3.1.2 Reception tion. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT The SCL clock input must have a minimum high and register is cleared. The received address is loaded into low for proper operation. The high and low times of the I2C specification, as well as the requirement of the SSP the SSPBUF register. module, are shown in timing parameter #100 and When the address byte overflow condition exists, then parameter #101. a no Acknowledge (ACK) pulse is given. An overflow condition is indicated if either bit, BF (SSPSTAT<0>), is 10.3.1.1 Addressing set or bit, SSPOV (SSPCON<6>), is set. Once the SSP module has been enabled, it waits for a An SSP interrupt is generated for each data transfer Start condition to occur. Following the Start condition, byte. Flag bit, SSPIF (PIR1<3>), must be cleared in the eight bits are shifted into the SSPSR register. All software. The SSPSTAT register is used to determine incoming bits are sampled with the rising edge of the the status of the byte. clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The 10.3.1.3 Transmission address is compared on the falling edge of the eighth When the R/W bit of the incoming address byte is set clock (SCL) pulse. If the addresses match and the BF and an address match occurs, the R/W bit of the and SSPOV bits are clear, the following events occur: SSPSTAT register is set. The received address is a) The SSPSR register value is loaded into the loaded into the SSPBUF register. The ACK pulse will SSPBUF register. be sent on the ninth bit and pin RB4/SCK/SCL is held b) The Buffer Full bit, BF, is set. low. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. c) An ACK pulse is generated. Then pin RB4/SCK/SCL should be enabled by setting d) SSP Interrupt Flag bit, SSPIF (PIR1<3>), is set bit, CKP (SSPCON<4>). The master device must (interrupt is generated if enabled) – on the falling monitor the SCL pin prior to asserting another clock edge of the ninth SCL pulse. pulse. The slave devices may be holding off the master In 10-bit Address mode, two address bytes need to be device by stretching the clock. The eight data bits are received by the slave device. The five Most Significant shifted out on the falling edge of the SCL input. This bits (MSbs) of the first address byte specify if this is a ensures that the SDA signal is valid during the SCL 10-bit address. Bit R/W (SSPSTAT<2>) must specify a high time (Figure10-7). write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address.  2001-2013 Microchip Technology Inc. DS39598F-page 77

PIC16F818/819 An SSP interrupt is generated for each data transfer the data transfer is complete. When the ACK is latched byte. Flag bit SSPIF must be cleared in software and by the slave device, the slave logic is reset (resets the SSPSTAT register is used to determine the status SSPSTAT register) and the slave device then monitors of the byte. Flag bit SSPIF is set on the falling edge of for another occurrence of the Start bit. If the SDA line the ninth clock pulse. was low (ACK), the transmit data must be loaded into the SSPBUF register which also loads the SSPSR As a slave-transmitter, the ACK pulse from the master- register. Then pin RB4/SCK/SCL should be enabled by receiver is latched on the rising edge of the ninth SCL setting bit, CKP. input pulse. If the SDA line was high (not ACK), then TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received SSPSR  SSPBUF Generate ACK Pulse Set bit SSPIF (SSP interrupt occurs if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition. FIGURE 10-6: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W = 0 ACK Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF (PIR1<3>) Cleared in software Bus master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full ACK is not sent FIGURE 10-7: I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data is SCL held low Sampled while CPU responds to SSPIF SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) From SSP Interrupt SSPBUF is written in software Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) DS39598F-page 78  2001-2013 Microchip Technology Inc.

PIC16F818/819 10.3.2 MASTER MODE OPERATION 10.3.3 MULTI-MASTER MODE OPERATION Master mode operation is supported in firmware using In Multi-Master mode operation, the interrupt genera- interrupt generation on the detection of the Start and tion on the detection of the Start and Stop conditions Stop conditions. The Stop (P) and Start (S) bits are allows the determination of when the bus is free. The cleared from a Reset or when the SSP module is dis- Stop (P) and Start (S) bits are cleared from a Reset or abled. The Stop (P) and Start (S) bits will toggle based when the SSP module is disabled. The Stop (P) and on the Start and Stop conditions. Control of the I2C bus Start (S) bits will toggle based on the Start and Stop may be taken when the P bit is set or the bus is Idle and conditions. Control of the I2C bus may be taken when both the S and P bits are clear. bit P (SSPSTAT<4>) is set or the bus is Idle and both the S and P bits clear. When the bus is busy, enabling In Master mode operation, the SCL and SDA lines are the SSP interrupt will generate the interrupt when the manipulated in firmware by clearing the corresponding Stop condition occurs. TRISB<4,1> bit(s). The output level is always low, irrespective of the value(s) in PORTB<4,1>. So when In Multi-Master mode operation, the SDA line must be transmitting data, a ‘1’ data bit must have the monitored to see if the signal level is the expected TRISB<1> bit set (input) and a ‘0’ data bit must have output level. This check only needs to be done when a the TRISB<1> bit cleared (output). The same scenario high level is output. If a high level is expected and a low is true for the SCL line with the TRISB<4> bit. Pull-up level is present, the device needs to release the SDA resistors must be provided externally to the SCL and and SCL lines (set TRISB<4,1>). There are two stages SDA pins for proper operation of the I2C module. where this arbitration can be lost: The following events will cause the SSP Interrupt Flag • Address Transfer bit, SSPIF, to be set (SSP interrupt if enabled): • Data Transfer • Start condition When the slave logic is enabled, the Slave device • Stop condition continues to receive. If arbitration was lost during the • Data transfer byte transmitted/received address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be Master mode operation can be done with either the generated. If arbitration was lost during the data Slave mode Idle (SSPM3:SSPM0 = 1011) or with the transfer stage, the device will need to retransfer the Slave mode active. When both Master mode operation data at a later time. and Slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on Multi-Master mode operation, see AN578, “Use of the SSP Module in the I2C™ For more information on Master mode operation, see Multi-Master Environment” (DS00578). AN554, “Software Implementation of I2C™ Bus Master” (DS00554). TABLE 10-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C™ mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP(1) CKE(1) D/A P S R/W UA BF 0000 0000 0000 0000 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in SPI mode. Note 1: Maintain these bits clear in I2C mode.  2001-2013 Microchip Technology Inc. DS39598F-page 79

PIC16F818/819 NOTES: DS39598F-page 80  2001-2013 Microchip Technology Inc.

PIC16F818/819 11.0 ANALOG-TO-DIGITAL The A/D module has four registers: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) converter module has five • A/D Control Register 0 (ADCON0) inputs for 18/20 pin devices. • A/D Control Register 1 (ADCON1) The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module The ADCON0 register, shown in Register11-1, has a high and low-voltage reference input that is controls the operation of the A/D module. The software selectable to some combination of VDD, VSS, ADCON1 register, shown in Register11-2, configures RA2 or RA3. the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage The A/D converter has a unique feature of being able reference) or as digital I/Os. to operate while the device is in Sleep mode. To oper- ate in Sleep, the A/D conversion clock must be derived Additional information on using the A/D module can be from the A/D’s internal RC oscillator. found in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023). REGISTER 11-1: ADCON0: A/D CONTROL REGISTER 0 (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits If ADCS2 = 0: 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) If ADCS2 = 1: 00 = FOSC/4 01 = FOSC/16 10 = FOSC/64 11 = FRC (clock derived from the internal A/D module RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 =Channel 0 (RA0/AN0) 001 =Channel 1 (RA1/AN1) 010 =Channel 2 (RA2/AN2) 011 =Channel 3 (RA3/AN3) 100 =Channel 4 (RA4/AN4) bit 2 GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 Unimplemented: Read as ‘0’ bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown  2001-2013 Microchip Technology Inc. DS39598F-page 81

PIC16F818/819 REGISTER 11-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified, 6 Most Significant bits of ADRESH are read as ‘0’ 0 = Left justified, 6 Least Significant bits of ADRESL are read as ‘0’ bit 6 ADCS2: A/D Clock Divide by 2 Select bit 1 = A/D clock source is divided by 2 when system clock is used 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits PCFG AN4 AN3 AN2 AN1 AN0 VREF+ VREF- C/R 0000 A A A A A AVDD AVSS 5/0 0001 A VREF+ A A A AN3 AVSS 4/1 0010 A A A A A AVDD AVSS 5/0 0011 A VREF+ A A A AN3 AVSS 4/1 0100 D A D A A AVDD AVSS 3/0 0101 D VREF+ D A A AN3 AVSS 2/1 011x D D D D D AVDD AVSS 0/0 1000 A VREF+ VREF- A A AN3 AN2 3/2 1001 A A A A A AVDD AVSS 5/0 1010 A VREF+ A A A AN3 AVSS 4/1 1011 A VREF+ VREF- A A AN3 AN2 3/2 1100 A VREF+ VREF- A A AN3 AN2 3/2 1101 D VREF+ VREF- A A AN3 AN2 2/2 1110 D D D D A AVDD AVSS 1/0 1111 D VREF+ VREF- D A AN3 AN2 1/2 A = Analog input D = Digital I/O C/R = Number of analog input channels/Number of A/D voltage references Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39598F-page 82  2001-2013 Microchip Technology Inc.

PIC16F818/819 The ADRESH:ADRESL registers contain the result of These steps should be followed for doing an A/D the A/D conversion. When the A/D conversion is conversion: complete, the result is loaded into the A/D Result register 1. Configure the A/D module: pair, the GO/DONE bit (ADCON0<2>) is cleared and • Configure analog pins/voltage reference and A/D Interrupt Flag bit, ADIF, is set. The block diagram of digital I/O (ADCON1) the A/D module is shown in Figure11-1. • Select A/D input channel (ADCON0) After the A/D module has been configured as desired, • Select A/D conversion clock (ADCON0) the selected channel must be acquired before the conversion is started. The analog input channels must • Turn on A/D module (ADCON0) have their corresponding TRIS bits selected as inputs. 2. Configure A/D interrupt (if desired): To determine sample time, see Section11.1 “A/D • Clear ADIF bit Acquisition Requirements”. After this sample time • Set ADIE bit has elapsed, the A/D conversion can be started. • Set GIE bit 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete by either: • Polling for the GO/DONE bit to be cleared (with interrupts disabled); OR • Waiting for the A/D interrupt 6. Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required. 7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before the next acquisition starts. FIGURE 11-1: A/D BLOCK DIAGRAM CHS<3:0> 100 RA4/AN4/T0CKI 011 RA3/AN3/VREF+ 010 VIN RA2/AN2/VREF- (Input Voltage) 001 RA1/AN1 000 AVDD RA0/AN0 A/D Converter VREF+ (Reference Voltage) PCFG<3:0> VREF- (Reference Voltage) AVSS PCFG<3:0>  2001-2013 Microchip Technology Inc. DS39598F-page 83

PIC16F818/819 11.1 A/D Acquisition Requirements After the analog input channel is selected (changed), this acquisition must be done before the conversion For the A/D converter to meet its specified accuracy, can be started. the charge holding capacitor (CHOLD) must be allowed To calculate the minimum acquisition time, to fully charge to the input channel voltage level. The Equation11-1 may be used. This equation assumes analog input model is shown in Figure11-2. The source that 1/2 LSb error is used (1024 steps for the A/D). The impedance (RS) and the internal sampling switch (RSS) 1/2 LSb error is the maximum error allowed for the A/D impedance directly affect the time required to charge to meet its specified resolution. the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see To calculate the minimum acquisition time, TACQ, see Figure11-2. The maximum recommended imped- the “PIC® Mid-Range MCU Family Reference Manual” ance for analog sources is 2.5 k. As the impedance (DS33023). is decreased, the acquisition time may be decreased. EQUATION 11-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2 s + TC + [(Temperature – 25°C)(0.05 s/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = -120 pF (1 k + 7 k + 10 k) In(0.0004885) = 16.47 s TACQ = 2 s + 16.47 s + [(50°C – 25C)(0.05 s/C) = 19.72 s Note1: The reference voltage (VREF) has no effect on the equation since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel. FIGURE 11-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC  1K SS RSS CHOLD VA C5 PpIFN VT = 0.6V I±L E5A0K0A nGAE == D12A0C p CFapacitance VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V ILEAKAGE = leakage current at the pin due to VDD4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (k) DS39598F-page 84  2001-2013 Microchip Technology Inc.

PIC16F818/819 11.2 Selecting the A/D Conversion 11.3 Configuring Analog Port Pins Clock The ADCON1 and TRISA registers control the opera- The A/D conversion time per bit is defined as TAD. The tion of the A/D port pins. The port pins that are desired A/D conversion requires 9.0TAD per 10-bit conversion. as analog inputs must have their corresponding TRIS The source of the A/D conversion clock is software bits set (input). If the TRIS bit is cleared (output), the selectable. The seven possible options for TAD are: digital output level (VOH or VOL) will be converted. • 2TOSC The A/D operation is independent of the state of the CHS<2:0> bits and the TRIS bits. • 4TOSC • 8TOSC Note1: When reading the Port register, all pins • 16TOSC configured as analog input channels will read as cleared (a low level). Pins config- • 32TOSC ured as digital inputs will convert an • 64TOSC analog input. Analog levels on a digitally • Internal A/D module RC oscillator (2-6s) configured input will not affect the For correct A/D conversions, the A/D conversion clock conversion accuracy. (TAD) must be selected to ensure a minimum TAD time 2: Analog levels on any pin that is defined as as small as possible, but no less than 1.6s and not a digital input (including the AN4:AN0 greater than 6.4 s. pins) may cause the input buffer to Table11-1 shows the resultant TAD times derived from consume current out of the device the device operating frequencies and the A/D clock specification. source selected. TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F)) AD Clock Source (TAD) Maximum Device Frequency Operation ADCS<2> ADCS<1:0> 2 TOSC 0 00 1.25 MHz 4 TOSC 1 00 2.5 MHz 8 TOSC 0 01 5 MHz 16 TOSC 1 01 10 MHz 32 TOSC 0 10 20 MHz 64 TOSC 1 10 20 MHz RC(1,2,3) X 11 (Note 1) Note 1: The RC source has a typical TAD time of 4 s but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for Sleep operation. 3: For extended voltage devices (LF), please refer to Section15.0 “Electrical Characteristics”.  2001-2013 Microchip Technology Inc. DS39598F-page 85

PIC16F818/819 11.4 A/D Conversions 11.4.1 A/D RESULT REGISTERS Clearing the GO/DONE bit during a conversion will The ADRESH:ADRESL register pair is the location abort the current conversion. The A/D Result register where the 10-bit A/D result is loaded at the completion pair will NOT be updated with the partially completed of the A/D conversion. This register pair is 16 bits wide. A/D conversion sample. That is, the ADRESH:ADRESL The A/D module gives the flexibility to left or right justify registers will continue to contain the value of the last the 10-bit result in the 16-bit result register. The A/D completed conversion (or the last value written to the Format Select bit (ADFM) controls this justification. ADRESH:ADRESL registers). After the A/D conversion Figure11-4 shows the operation of the A/D result is aborted, a 2-TAD wait is required before the next justification. The extra bits are loaded with ‘0’s. When acquisition is started. After this 2-TAD wait, acquisition an A/D result will not overwrite these locations (A/D on the selected channel is automatically started. The disable), these registers may be used as two general GO/DONE bit can then be set to start the conversion. purpose 8-bit registers. In Figure11-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 11-3: A/D CONVERSION TAD CYCLES TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding Capacitor is disconnected from analog input (typically 100 ns) Set GO bit ADRES is loaded, GO bit is cleared, ADIF bit is set, Holding Capacitor is connected to analog input FIGURE 11-4: A/D RESULT JUSTIFICATION 10-bit Result ADFM = 1 ADFM = 0 7 2 1 0 7 0 7 0 7 6 5 0 0000 00 0000 00 ADRESH ADRESL ADRESH ADRESL 10-bit Result 10-bit Result Right Justified Left Justified DS39598F-page 86  2001-2013 Microchip Technology Inc.

PIC16F818/819 11.5 A/D Operation During Sleep 11.6 Effects of a Reset The A/D module can operate during Sleep mode. This A device Reset forces all registers to their Reset state. requires that the A/D clock source be set to RC The A/D module is disabled and any conversion in (ADCS1:ADCS0 = 11). When the RC clock source is progress is aborted. All A/D input pins are configured selected, the A/D module waits one instruction cycle as analog inputs. before starting the conversion. This allows the SLEEP The value that is in the ADRESH:ADRESL registers instruction to be executed which eliminates all digital is not modified for a Power-on Reset. The switching noise from the conversion. When the conver- ADRESH:ADRESL registers will contain unknown data sion is completed, the GO/DONE bit will be cleared and after a Power-on Reset. the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from 11.7 Use of the CCP Trigger Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit An A/D conversion can be started by the “special event will remain set. trigger” of the CCP module. This requires that the When the A/D clock source is another clock option (not CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be RC), a SLEEP instruction will cause the present conver- programmed as ‘1011’ and that the A/D module is sion to be aborted and the A/D module to be turned off, enabled (ADON bit is set). When the trigger occurs, the though the ADON bit will remain set. GO/DONE bit will be set, starting the A/D conversion and the Timer1 counter will be reset to zero. Timer1 is Turning off the A/D places the A/D module in its lowest reset to automatically repeat the A/D acquisition period current consumption state. with minimal software overhead (moving the Note: For the A/D module to operate in Sleep, ADRESH:ADRESL to the desired location). The appro- the A/D clock source must be set to RC priate analog input channel must be selected and the (ADCS1:ADCS0 = 11). To perform an A/D minimum acquisition done before the “special event conversion in Sleep, ensure the SLEEP trigger” sets the GO/DONE bit (starts a conversion). instruction immediately follows the If the A/D module is not enabled (ADON is cleared), instruction that sets the GO/DONE bit. then the “special event trigger” will be ignored by the A/D module but will still reset the Timer1 counter. TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets 0Bh,8Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000 05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxx0 0000 uuu0 0000 85h TRISA TRISA7 TRISA6 TRISA5 PORTA Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.  2001-2013 Microchip Technology Inc. DS39598F-page 87

PIC16F818/819 NOTES: DS39598F-page 88  2001-2013 Microchip Technology Inc.

PIC16F818/819 12.0 SPECIAL FEATURES OF Sleep mode is designed to offer a very low-current THE CPU power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up or These devices have a host of features intended to through an interrupt. maximize system reliability, minimize cost through elimi- Several oscillator options are also made available to nation of external components, provide power-saving allow the part to fit the application. The RC oscillator operating modes and offer code protection: option saves system cost while the LP crystal option • Reset saves power. Configuration bits are used to select the - Power-on Reset (POR) desired oscillator mode. - Power-up Timer (PWRT) Additional information on special features is available - Oscillator Start-up Timer (OST) in the “PIC® Mid-Range MCU Family Reference Man- ual” (DS33023). - Brown-out Reset (BOR) • Interrupts 12.1 Configuration Bits • Watchdog Timer (WDT) • Sleep The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select • Code Protection various device configurations. These bits are mapped • ID Locations in program memory location 2007h. • In-Circuit Serial Programming The user will note that address 2007h is beyond the There are two timers that offer necessary delays on user program memory space which can be accessed power-up. One is the Oscillator Start-up Timer (OST), only during programming. intended to keep the chip in Reset until the crystal oscil- lator is stable. The other is the Power-up Timer (PWRT) which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in Reset while the power supply stabilizes and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external Reset circuitry.  2001-2013 Microchip Technology Inc. DS39598F-page 89

PIC16F818/819 REGISTER 12-1: CONFIGURATION WORD (ADDRESS 2007h)(1) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP CCPMX DEBUG WRT1 WRT0 CPD LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit 0 bit 13 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code-protected bit 12 CCPMX: CCP1 Pin Selection bit 1 = CCP1 function on RB2 0 = CCP1 function on RB3 bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger bit 10-9 WRT1:WRT0: Flash Program Memory Write Enable bits For PIC16F818: 11 = Write protection off 10 = 000h to 01FF write-protected, 0200 to 03FF may be modified by EECON control 01 = 000h to 03FF write-protected For PIC16F819: 11 = Write protection off 10 = 0000h to 01FFh write-protected, 0200h to 07FFh may be modified by EECON control 01 = 0000h to 03FFh write-protected, 0400h to 07FFh may be modified by EECON control 00 = 0000h to 05FFh write-protected, 0600h to 07FFh may be modified by EECON control bit 8 CPD: Data EE Memory Code Protection bit 1 = Code protection off 0 = Data EE memory locations code-protected bit 7 LVP: Low-Voltage Programming Enable bit 1 = RB3/PGM pin has PGM function, Low-Voltage Programming enabled 0 = RB3/PGM pin has digital I/O function, HV on MCLR must be used for programming bit 6 BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled bit 5 MCLRE: RA5/MCLR/VPP Pin Function Select bit 1 = RA5/MCLR/VPP pin function is MCLR 0 = RA5/MCLR/VPP pin function is digital I/O, MCLR internally tied to VDD bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 4, 1-0 FOSC2:FOSC0: Oscillator Selection bits 111 =EXTRC oscillator; CLKO function on RA6/OSC2/CLKO pin 110 =EXTRC oscillator; port I/O function on RA6/OSC2/CLKO pin 101 =INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin 100 =INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin 011 =EXTCLK; port I/O function on RA6/OSC2/CLKO pin 010 =HS oscillator 001 =XT oscillator 000 =LP oscillator Note1: The erased (unprogrammed) value of the Configuration Word is 3FFFh. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ -n = Value when device is unprogrammed u = Unchanged from programmed state DS39598F-page 90  2001-2013 Microchip Technology Inc.

PIC16F818/819 12.2 Reset Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any The PIC16F818/819 differentiates between various other Reset. Most other registers are reset to a “Reset kinds of Reset: state” on Power-on Reset (POR), on the MCLR and • Power-on Reset (POR) WDT Reset, on MCLR Reset during Sleep and Brown- out Reset (BOR). They are not affected by a WDT • MCLR Reset during normal operation wake-up which is viewed as the resumption of normal • MCLR Reset during Sleep operation. The TO and PD bits are set or cleared • WDT Reset during normal operation differently in different Reset situations as indicated in • WDT wake-up during Sleep Table12-3. These bits are used in software to • Brown-out Reset (BOR) determine the nature of the Reset. Upon a POR, BOR or wake-up from Sleep, the CPU requires approximately 5-10s to become ready for code execution. This delay runs in parallel with any other timers. See Table12-4 for a full description of Reset states of all registers. A simplified block diagram of the on-chip Reset circuit is shown in Figure12-1. FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR Sleep WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset S BOREN OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1 PWRT INTRC 10-bit Ripple Counter 31.25 kHz Enable PWRT Enable OST  2001-2013 Microchip Technology Inc. DS39598F-page 91

PIC16F818/819 12.3 MCLR 12.5 Power-up Timer (PWRT) PIC16F818/819 device has a noise filter in the MCLR The Power-up Timer (PWRT) of the PIC16F818/819 is Reset path. The filter will detect and ignore small a counter that uses the INTRC oscillator as the clock pulses. input. This yields a count of 72ms. While the PWRT is counting, the device is held in Reset. It should be noted that a WDT Reset does not drive MCLR pin low. The power-up time delay depends on the INTRC and will vary from chip-to-chip due to temperature and The behavior of the ESD protection on the MCLR pin process variation. See DC parameter #33 for details. has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification The PWRT is enabled by clearing configuration bit, can result in both MCLR and excessive current beyond PWRTEN. the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no 12.6 Oscillator Start-up Timer (OST) longer be tied directly to VDD. The use of an RCnetwork, as shown in Figure12-2, is suggested. The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the The RA5/MCLR/VPP pin can be configured for MCLR PWRT delay is over (if enabled). This helps to ensure (default) or as an I/O pin (RA5). This is configured that the crystal oscillator or resonator has started and through the MCLRE bit in the Configuration Word stabilized. register. The OST time-out is invoked only for XT, LP and HS FIGURE 12-2: RECOMMENDED MCLR modes and only on Power-on Reset or wake-up from Sleep. CIRCUIT VDD 12.7 Brown-out Reset (BOR) PIC16F818/819 The configuration bit, BOREN, can enable or disable R1 the Brown-out Reset circuit. If VDD falls below VBOR 1 k (or greater) (parameter #D005, about 4V) for longer than TBOR MCLR (parameter #35, about 100s), the brown-out situation will reset the device. If VDD falls below VBOR for less C1 than TBOR, a Reset may not occur. 0.1 F (optional, not critical) Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer (if enabled) will keep the device in Reset for TPWRT (parameter #33, about 72ms). If VDD should fall below VBOR during TPWRT, the Brown-out 12.4 Power-on Reset (POR) Reset process will restart when VDD rises above VBOR A Power-on Reset pulse is generated on-chip when with the Power-up Timer Reset. Unlike previous PIC16 VDD rise is detected (in the range of 1.2V-1.7V). To take devices, the PWRT is no longer automatically enabled advantage of the POR, tie the MCLR pin to VDD as when the Brown-out Reset circuit is enabled. The described in Section12.3 “MCLR”. A maximum rise PWRTEN and BOREN configuration bits are time for VDD is specified. See Section15.0 “Electrical independent of each other. Characteristics” for details. 12.8 Time-out Sequence When the device starts normal operation (exits the Reset condition), device operating parameters (volt- On power-up, the time-out sequence is as follows: the age, frequency, temperature, ...) must be met to ensure PWRT delay starts (if enabled) when a POR occurs. operation. If these conditions are not met, the device Then, OST starts counting 1024 oscillator cycles when must be held in Reset until the operating conditions are PWRT ends (LP, XT, HS). When the OST ends, the met. For more information, see Application Note device comes out of Reset. AN607, “Power-up Trouble Shooting” (DS00607). If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F818/819 device operating in parallel. Table12-3 shows the Reset conditions for the Status, PCON and PC registers, while Table12-4 shows the Reset conditions for all the registers. DS39598F-page 92  2001-2013 Microchip Technology Inc.

PIC16F818/819 12.9 Power Control/Status Register bit BOR cleared, indicating a Brown-out Reset (PCON) occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. The Power Control/Status register, PCON, has two bits Bit 1 is Power-on Reset Status bit, POR. It is cleared on to indicate the type of Reset that last occurred. a Power-on Reset and unaffected otherwise. The user Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is must set this bit following a Power-on Reset. unknown on a Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS Oscillator Power-up Brown-out Reset Wake-up Configuration PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 from Sleep XT, HS, LP TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC EXTRC, EXTCLK, INTRC TPWRT 5-10s(1) TPWRT 5-10s(1) 5-10s(1) Note 1: CPU start-up is always invoked on POR, BOR and wake-up from Sleep. TABLE 12-2: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep Legend: u = unchanged, x = unknown TABLE 12-3: RESET CONDITION FOR SPECIAL REGISTERS Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  2001-2013 Microchip Technology Inc. DS39598F-page 93

PIC16F818/819 TABLE 12-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, MCLR Reset, Wake-up via WDT or Register Brown-out Reset WDT Reset Interrupt W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA xxx0 0000 uuu0 0000 uuuu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) PIR1 -0-- 0000 -0-- 0000 -u-- uuuu(1) PIR2 ---0 ---- ---0 ---- ---u ----(1) TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON --00 0000 --uu uuuu --uu uuuu TMR2 0000 0000 0000 0000 uuuu uuuu T2CON -000 0000 -000 0000 -uuu uuuu SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 0000 0000 0000 0000 uuuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON --00 0000 --00 0000 --uu uuuu ADRESH xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 1111 1111 1111 1111 uuuu uuuu TRISA 1111 1111 1111 1111 uuuu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu PIE1 -0-- 0000 -0-- 0000 -u-- uuuu PIE2 ---0 ---- ---0 ---- ---u ---- PCON ---- --qq ---- --uu ---- --uu OSCCON -000 -0-- -000 -0-- -uuu -u-- OSCTUNE --00 0000 --00 0000 --uu uuuu PR2 1111 1111 1111 1111 1111 1111 SSPADD 0000 0000 0000 0000 uuuu uuuu SSPSTAT 0000 0000 0000 0000 uuuu uuuu ADRESL xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 00-- 0000 00-- 0000 uu-- uuuu EEDATA xxxx xxxx uuuu uuuu uuuu uuuu EEADR xxxx xxxx uuuu uuuu uuuu uuuu EEDATH --xx xxxx --uu uuuu --uu uuuu EEADRH ---- -xxx ---- -uuu ---- -uuu EECON1 x--x x000 u--x u000 u--u uuuu EECON2 ---- ---- ---- ---- ---- ---- Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table12-3 for Reset value for specific conditions. DS39598F-page 94  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 12-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset  2001-2013 Microchip Technology Inc. DS39598F-page 95

PIC16F818/819 FIGURE 12-6: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V VDD 0V 1V MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset 12.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in The PIC16F818/819 has up to nine sources of inter- the INTCON register. rupt. The Interrupt Control register (INTCON) records The peripheral interrupt flags are contained in the individual interrupt requests in flag bits. It also has Special Function Register, PIR1. The corresponding individual and global interrupt enable bits. interrupt enable bits are contained in Special Function Note: Individual interrupt flag bits are set Register, PIE1 and the peripheral interrupt enable bit is regardless of the status of their contained in Special Function Register, INTCON. corresponding mask bit or the GIE bit. When an interrupt is serviced, the GIE bit is cleared to A Global Interrupt Enable bit, GIE (INTCON<7>), disable any further interrupt, the return address is enables (if set) all unmasked interrupts or disables (if pushed onto the stack and the PC is loaded with 0004h. cleared) all interrupts. When bit GIE is enabled and an Once in the Interrupt Service Routine, the source(s) of interrupt’s flag bit and mask bit are set, the interrupt will the interrupt can be determined by polling the interrupt vector immediately. Individual interrupts can be flag bits. The interrupt flag bit(s) must be cleared in disabled through their corresponding enable bits in software before re-enabling interrupts to avoid various registers. Individual interrupt bits are set recursive interrupts. regardless of the status of the GIE bit. The GIE bit is For external interrupt events, such as the INT pin or cleared on Reset. PORTB change interrupt, the interrupt latency will be The “return from interrupt” instruction, RETFIE, exits three or four instruction cycles. The exact latency the interrupt routine, as well as sets the GIE bit, which depends on when the interrupt event occurs relative to re-enables interrupts. the current Q cycle. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit, PEIE bit or the GIE bit. FIGURE 12-7: INTERRUPT LOGIC EEIF TMR0IF Wake-up (if in Sleep mode) EEIE TMR0IE ADIF INTF ADIE INTE Interrupt to CPU SSPIF RBIF SSPIE RBIE CCP1IF CCP1IE PEIE TMR1IF TMR1IE GIE TMR2IF TMR2IE DS39598F-page 96  2001-2013 Microchip Technology Inc.

PIC16F818/819 12.10.1 INT INTERRUPT 12.10.3 PORTB INTCON CHANGE External interrupt on the RB0/INT pin is edge triggered, An input change on PORTB<7:4> sets flag bit, RBIF either rising if bit INTEDG (OPTION_REG<6>) is set, (INTCON<0>). The interrupt can be enabled/disabled or falling if the INTEDG bit is clear. When a valid edge by setting/clearing enable bit, RBIE (INTCON<3>). See appears on the RB0/INT pin, flag bit, INTF Section3.2 “EECON1 and EECON2 Registers”. (INTCON<1>), is set. This interrupt can be disabled by clearing enable bit, INTE (INTCON<4>). Flag bit INTF 12.11 Context Saving During Interrupts must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT inter- During an interrupt, only the return PC value is saved rupt can wake-up the processor from Sleep if bit INTE on the stack. Typically, users may wish to save key was set prior to going into Sleep. The status of Global registers during an interrupt (i.e., W, Status registers). Interrupt Enable bit, GIE, decides whether or not the This will have to be implemented in software as shown processor branches to the interrupt vector following in Example12-1. wake-up. See Section12.13 “Power-Down Mode For PIC16F818 devices, the upper 64 bytes of each (Sleep)” for details on Sleep mode. bank are common. Temporary holding registers, W_TEMP and STATUS_TEMP, should be placed here. 12.10.2 TMR0 INTERRUPT These 64 locations do not require banking and An overflow (FFh  00h) in the TMR0 register will set therefore, make it easier for context save and restore. flag bit, TMR0IF (INTCON<2>). The interrupt can be For PIC16F819 devices, the upper 16 bytes of each enabled/disabled by setting/clearing enable bit, bank are common. TMR0IE (INTCON<5>) (see Section6.0 “Timer0 Module”). EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS, W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP, W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP, F ;Swap W_TEMP SWAPF W_TEMP, W ;Swap W_TEMP into W  2001-2013 Microchip Technology Inc. DS39598F-page 97

PIC16F818/819 12.12 Watchdog Timer (WDT) WDT time-out period values may be found in Section15.0 “Electrical Characteristics” under For PIC16F818/819 devices, the WDT is driven by the parameter #31. Values for the WDT prescaler (actually INTRC oscillator. When the WDT is enabled, the a postscaler but shared with the Timer0 prescaler) may INTRC (31.25kHz) oscillator is enabled. The nominal be assigned using the OPTION_REG register. WDT period is 16 ms and has the same accuracy as the INTRC oscillator. Note1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler if During normal operation, a WDT time-out generates a assigned to the WDT and prevent it from device Reset (Watchdog Timer Reset). If the device is timing out and generating a device Reset in Sleep mode, a WDT time-out causes the device to condition. wake-up and continue with normal operation (Watchdog Timer wake-up). The TO bit in the Status register will be 2: When a CLRWDT instruction is executed cleared upon a Watchdog Timer time-out. and the prescaler is assigned to the WDT, the prescaler count will be cleared but the The WDT can be permanently disabled by clearing con- prescaler assignment is not changed. figuration bit, WDTEN (see Section12.1 “Configuration Bits”). FIGURE 12-8: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure6-1) 0 M Postscaler 1 INTRC U 31.25kHz X 8 8-to-1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure6-1) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. TABLE 12-5: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 2007h Configuration bits(1) LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register12-1 for operation of these bits. DS39598F-page 98  2001-2013 Microchip Technology Inc.

PIC16F818/819 12.13 Power-Down Mode (Sleep) Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. Power-Down mode is entered by executing a SLEEP When the SLEEP instruction is being executed, the next instruction. instruction (PC + 1) is prefetched. For the device to If enabled, the Watchdog Timer will be cleared but wake-up through an interrupt event, the corresponding keeps running, the PD bit (Status<3>) is cleared, the interrupt enable bit must be set (enabled). Wake-up TO (Status<4>) bit is set and the oscillator driver is occurs regardless of the state of the GIE bit. If the GIE turned off. The I/O ports maintain the status they had bit is clear (disabled), the device continues execution at before the SLEEP instruction was executed (driving the instruction after the SLEEP instruction. If the GIE bit high, low or high-impedance). is set (enabled), the device executes the instruction For lowest current consumption in this mode, place all after the SLEEP instruction and then branches to the I/O pins at either VDD or VSS, ensure no external cir- interrupt address (0004h). In cases where the cuitry is drawing current from the I/O pin, power-down execution of the instruction following SLEEP is not the A/D and disable external clocks. Pull all I/O pins desirable, the user should have a NOP after the SLEEP that are high-impedance inputs, high or low externally, instruction. to avoid switching currents caused by floating inputs. 12.13.2 WAKE-UP USING INTERRUPTS The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from When global interrupts are disabled (GIE cleared) and on-chip pull-ups on PORTB should also be considered. any interrupt source has both its interrupt enable bit The MCLR pin must be at a logic high level (VIHMC). and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a 12.13.1 WAKE-UP FROM SLEEP SLEEP instruction, the SLEEP instruction will The device can wake-up from Sleep through one of the complete as a NOP. Therefore, the WDT and WDT following events: postscaler will not be cleared, the TO bit will not be set and PD bit will not be cleared. 1. External Reset input on MCLR pin. • If the interrupt occurs during or after the 2. Watchdog Timer wake-up (if WDT was execution of a SLEEP instruction, the device will enabled). immediately wake-up from Sleep. The SLEEP 3. Interrupt from INT pin, RB port change or a instruction will be completely executed before the peripheral interrupt. wake-up. Therefore, the WDT and WDT External MCLR Reset will cause a device Reset. All postscaler will be cleared, the TO bit will be set other events are considered a continuation of program and the PD bit will be cleared. execution and cause a “wake-up”. The TO and PD bits Even if the flag bits were checked before executing a in the Status register can be used to determine the SLEEP instruction, it may be possible for flag bits to cause of the device Reset. The PD bit, which is set on become set before the SLEEP instruction completes. To power-up, is cleared when Sleep is invoked. The TO bit determine whether a SLEEP instruction executed, test is cleared if a WDT time-out occurred and caused the PD bit. If the PD bit is set, the SLEEP instruction wake-up. was executed as a NOP. The following peripheral interrupts can wake the device To ensure that the WDT is cleared, a CLRWDT instruction from Sleep: should be executed before a SLEEP instruction. 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. CCP Capture mode interrupt. 3. Special event trigger (Timer1 in Asynchronous mode using an external clock). 4. SSP (Start/Stop) bit detect interrupt. 5. SSP transmit or receive in Slave mode (SPI/I2C). 6. A/D conversion (when A/D clock source is RC). 7. EEPROM write operation completion.  2001-2013 Microchip Technology Inc. DS39598F-page 99

PIC16F818/819 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKO(4) TOST(2) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Instruction Executed Inst(PC – 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode. 3: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 4: CLKO is not available in these oscillator modes but shown here for timing reference. 12.14 In-Circuit Debugger 12.15 Program Verification/Code Protection When the DEBUG bit in the Configuration Word is programmed to a ‘0’, the In-Circuit Debugger function- If the code protection bit(s) have not been ality is enabled. This function allows simple debugging programmed, the on-chip program memory can be functions when used with MPLAB® ICD. When the read out for verification purposes. microcontroller has this feature enabled, some of the resources are not available for general use. Table12-6 12.16 ID Locations shows which features are consumed by the background debugger. Four memory locations (2000h-2003h) are designated as ID locations, where the user can store checksum or TABLE 12-6: DEBUGGER RESOURCES other code identification numbers. These locations are not accessible during normal execution but are I/O pins RB6, RB7 readable and writable during program/verify. It is Stack 1 level recommended that only the four Least Significant bits Program Memory Address 0000h must be NOP of the ID location are used. Last 100h words Data Memory 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB-0x1EF To use the In-Circuit Debugger function of the micro- controller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the in-circuit debugger module available from Microchip or one of the third party development tool companies. DS39598F-page 100  2001-2013 Microchip Technology Inc.

PIC16F818/819 12.17 In-Circuit Serial Programming FIGURE 12-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING PIC16F818/819 microcontrollers can be serially CONNECTION programmed while in the end application circuit. This is simply done with two lines for clock and data and three To Normal other lines for power, ground and the programming Connections voltage (see Figure12-10 for an example). This allows External customers to manufacture boards with unprogrammed Connector * PIC16F818/819 Signals devices and then program the microcontroller just before shipping the product. This also allows the most +5V VDD recent firmware or a custom firmware to be 0V VSS programmed. VPP MCLR/VPP For more information on serial programming, please refer CLK RB6 to the “PIC16F818/819 Flash Memory Programming Data I/O RB7 Specification” (DS39603). RB3† Note: The Timer1 oscillator shares the T1OSI RB3/PGM and T1OSO pins with the PGD and PGC pins used for programming and debugging. * * * When using the Timer1 oscillator, In-Circuit VDD Serial Programming™ (ICSP™) may not To Normal function correctly (high voltage or low Connections voltage) or the In-Circuit Debugger (ICD) * Isolation devices (as required). may not communicate with the controller. † RB3 only used in LVP mode. As a result of using either ICSP or ICD, the Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead) or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation.  2001-2013 Microchip Technology Inc. DS39598F-page 101

PIC16F818/819 12.18 Low-Voltage ICSP Programming Note1: The High-Voltage Programming mode is The LVP bit of the Configuration Word register enables always available, regardless of the state Low-Voltage ICSP Programming. This mode allows the of the LVP bit, by applying VIHH to the microcontroller to be programmed via ICSP using a MCLR pin. VDD source in the operating voltage range. This only 2: While in Low-Voltage ICSP mode means that VPP does not have to be brought to VIHH but (LVP=1), the RB3 pin can no longer be can instead be left at the normal operating voltage. In used as a general purpose I/O pin. this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general 3: When using Low-Voltage ICSP Program- purpose I/O pin. ming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register If Low-Voltage Programming mode is not used, the LVP must be cleared to disable the pull-up on bit can be programmed to a ‘0’ and RB3/PGM becomes RB3 and ensure the proper operation of a digital I/O pin. However, the LVP bit may only be the device. programmed when Programming mode is entered with VIHH on MCLR. The LVP bit can only be changed when 4: RB3 should not be allowed to float if LVP using high voltage on MCLR. is enabled. An external pull-down device should be used to default the device to It should be noted that once the LVP bit is programmed normal operating mode. If RB3 floats to ‘0’, only the High-Voltage Programming mode is high, the PIC16F818/819 device will available and only this mode can be used to program enter Programming mode. the device. 5: LVP mode is enabled by default on all When using Low-Voltage ICSP, the part must be devices shipped from Microchip. It can be supplied at 4.5V to 5.5V if a bulk erase will be executed. disabled by clearing the LVP bit in the This includes reprogramming of the code-protect bits Configuration Word register. from an ON state to an OFF state. For all other cases of Low-Voltage ICSP, the part may be programmed at the 6: Disabling LVP will provide maximum normal operating voltage. This means calibration values, compatibility to other PIC16CXXX unique user IDs or user code can be reprogrammed or devices. added. The following LVP steps assume the LVP bit is set in the Configuration Word register. 1. Apply VDD to the VDD pin. 2. Drive MCLR low. 3. Apply VDD to the RB3/PGM pin. 4. Apply VDD to the MCLR pin. 5. Follow with the associated programming steps. DS39598F-page 102  2001-2013 Microchip Technology Inc.

PIC16F818/819 13.0 INSTRUCTION SET SUMMARY For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result The PIC16 instruction set is highly orthogonal and is back to PORTB. This example would have the comprised of three basic categories: unintended result that the condition that sets the RBIF • Byte-oriented operations flag would be cleared. • Bit-oriented operations TABLE 13-1: OPCODE FIELD • Literal and control operations DESCRIPTIONS Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or Field Description more operands, which further specify the operation of f Register file address (0x00 to 0x7F) the instruction. The formats for each of the categories W Working register (accumulator) are presented in Figure13-1, while the various opcode fields are summarized in Table13-1. b Bit address within an 8-bit file register Table13-2 lists the instructions recognized by the k Literal field, constant data or label MPASMTM assembler. A complete description of each x Don’t care location (= 0 or 1). instruction is also available in the “PIC® Mid-Range The assembler will generate code with x = 0. MCU Family Reference Manual” (DS33023). It is the recommended form of use for For byte-oriented instructions, ‘f’ represents a file compatibility with all Microchip software tools. register designator and ‘d’ represents a destination d Destination select; d = 0: store result in W, designator. The file register designator specifies which d = 1: store result in file register f. file register is to be used by the instruction. Default is d = 1. The destination designator specifies where the result of PC Program Counter the operation is to be placed. If ‘d’ is zero, the result is TO Time-out bit placed in the W register. If ‘d’ is one, the result is placed PD Power-Down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the opera- FIGURE 13-1: GENERAL FORMAT FOR tion, while ‘f’ represents the address of the file in which INSTRUCTIONS the bit is located. Byte-oriented file register operations For literal and control operations, ‘k’ represents an 13 8 7 6 0 eight or eleven-bit constant or literal value OPCODE d f (FILE #) One instruction cycle consists of four oscillator periods. d = 0 for destination W For an oscillator frequency of 4 MHz, this gives a nor- d = 1 for destination f mal instruction execution time of 1 s. All instructions f = 7-bit file register address are executed within a single instruction cycle, unless a conditional test is true, or the program counter is Bit-oriented file register operations changed as a result of an instruction. When this occurs, 13 10 9 7 6 0 the execution takes two instruction cycles, with the OPCODE b (BIT #) f (FILE #) second cycle executed as a NOP. b = 3-bit bit address Note: To maintain upward compatibility with f = 7-bit file register address future PIC16F818/819 products, do not use the OPTION and TRIS instructions. Literal and control operations All instruction examples use the format ‘0xhh’ to General represent a hexadecimal number, where ‘h’ signifies a 13 8 7 0 hexadecimal digit. OPCODE k (literal) 13.1 READ-MODIFY-WRITE k = 8-bit immediate value OPERATIONS CALL and GOTO instructions only Any instruction that specifies a file register as part of 13 11 10 0 the instruction performs a Read-Modify-Write (R-M-W) OPCODE k (literal) operation. The register is read, the data is modified and the result is stored according to either the instruction or k = 11-bit immediate value the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.  2001-2013 Microchip Technology Inc. DS39598F-page 103

PIC16F818/819 TABLE 13-2: PIC16F818/819 INSTRUCTION SET Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1 (2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1 (2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO, PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023). DS39598F-page 104  2001-2013 Microchip Technology Inc.

PIC16F818/819 13.2 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d [0,1] Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the eight-bit literal ‘k’ Description: AND the W register with register and the result is placed in the W ‘f’. If ‘d’ = 0, the result is stored in register. the W register. If ‘d’ = 1, the result is stored back in register ‘f’. ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b Operands: 0  f  127 Operands: 0  f  127 d  [0,1] 0  b  7 Operation: (W) + (f)  (destination) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is cleared. with register ‘f’. If ‘d’ = 0, the result is stored in the W register. If ‘d’ = 1, the result is stored back in register ‘f’. ANDLW AND Literal with W BSF Bit Set f Syntax: [ label ] ANDLW k Syntax: [ label ] BSF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) .AND. (k)  (W) Operation: 1  (f<b>) Status Affected: Z Status Affected: None Description: The contents of W register are ANDed with the eight-bit literal ‘k’. Description: Bit ‘b’ in register ‘f’ is set. The result is placed in the W register.  2001-2013 Microchip Technology Inc. DS39598F-page 105

PIC16F818/819 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF f Operands: 0  f  127 Operands: 0  f  127 0  b < 7 Operation: 00h  (f) Operation: skip if (f<b>) = 1 1  Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ = 0, the next Description: The contents of register ‘f’ are instruction is executed. cleared and the Z bit is set. If bit ‘b’ = 1, then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction. BTFSC Bit Test, Skip if Clear CLRW Clear W Syntax: [ label ] BTFSC f,b Syntax: [ label ] CLRW Operands: 0  f  127 Operands: None 0  b  7 Operation: 00h  (W) Operation: skip if (f<b>) = 0 1  Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ = 1, the next Description: W register is cleared. Zero bit (Z) instruction is executed. is set. If bit ‘b’ in register ‘f’ = 0, the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction. CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC) + 1  TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<4:3>)  PC<12:11> 1  TO 1  PD Status Affected: None Status Affected: TO, PD Description: Call subroutine. First, return address (PC + 1) is pushed onto Description: CLRWDT instruction resets the the stack. The eleven-bit Watchdog Timer. It also resets the immediate address is loaded into prescaler of the WDT. Status bits PC bits<10:0>. The upper bits of TO and PD are set. the PC are loaded from PCLATH. CALL is a two-cycle instruction. DS39598F-page 106  2001-2013 Microchip Technology Inc.

PIC16F818/819 COMF Complement f GOTO Unconditional Branch Syntax: [ label ] COMF f,d Syntax: [ label ] GOTO k Operands: 0  f  127 Operands: 0  k  2047 d  [0,1] Operation: k  PC<10:0> Operation: (f)  (destination) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: GOTO is an unconditional branch. complemented. If ‘d’ = 0, the The eleven-bit immediate value is result is stored in W. If ‘d’ = 1, the loaded into PC bits<10:0>. The result is stored back in register ‘f’. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) – 1  (destination) Operation: (f) + 1  (destination) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ = 0, Description: The contents of register ‘f’ are the result is stored in the W incremented. If ‘d’ = 0, the result register. If ‘d’ = 1, the result is is placed in the W register. If stored back in register ‘f’. ‘d’=1, the result is placed back in register ‘f’. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) – 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ = 0, the result incremented. If ‘d’ = 0, the result is is placed in the W register. If placed in the W register. If ‘d’=1, ‘d’=1, the result is placed back in the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a 2 TCY 2 TCY instruction. instruction.  2001-2013 Microchip Technology Inc. DS39598F-page 107

PIC16F818/819 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] IORLW k Syntax: [ label ] MOVLW k Operands: 0  k  255 Operands: 0  k  255 Operation: (W) .OR. k  (W) Operation: k  (W) Status Affected: Z Status Affected: None Description: The contents of the W register are Description: The eight-bit literal ‘k’ is loaded ORed with the eight-bit literal ‘k’. into W register. The don’t cares The result is placed in the W will assemble as ‘0’s. register. IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (W) .OR. (f)  (destination) Status Affected: None Status Affected: Z Description: Move data from W register to Description: Inclusive OR the W register with register ‘f’. register ‘f’. If ‘d’ = 0, the result is placed in the W register. If ‘d’ = 1, the result is placed back in register ‘f’. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  127 Operands: None d  [0,1] Operation: No operation Operation: (f)  (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to a destination dependant upon the status of ‘d’. If ‘d’ = 0, the destination is W register. If ‘d’=1, the destination is file regis- ter ‘f’ itself. ‘d’ = 1 is useful to test a file register since status flag Z is affected. DS39598F-page 108  2001-2013 Microchip Technology Inc.

PIC16F818/819 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] RETFIE Syntax: [ label ] RLF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: TOS  PC, 1  GIE Operation: See description below Status Affected: None Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ = 0, the result is placed in the W register. If ‘d’ = 1, the result is stored back in register ‘f’. C Register f RETLW Return with Literal in W RRF Rotate Right f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RRF f,d Operands: 0  k  255 Operands: 0  f  127 d  [0,1] Operation: k  (W); TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the Description: The contents of register ‘f’ are eight-bit literal ‘k’. The program rotated one bit to the right through counter is loaded from the top of the Carry flag. If ‘d’ = 0, the result the stack (the return address). is placed in the W register. If This is a two-cycle instruction. ‘d’ = 1, the result is placed back in register ‘f’. C Register f RETURN Return from Subroutine SLEEP Enter Sleep mode Syntax: [ label ] RETURN Syntax: [ label ] SLEEP Operands: None Operands: None Operation: TOS  PC Operation: 00h  WDT, 0  WDT prescaler, Status Affected: None 1  TO, Description: Return from subroutine. The stack 0  PD is POPed and the top of the stack Status Affected: TO, PD (TOS) is loaded into the program counter. This is a two-cycle Description: The Power-Down status bit, PD, instruction. is cleared. Time-out status bit, TO, is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.  2001-2013 Microchip Technology Inc. DS39598F-page 109

PIC16F818/819 SUBLW Subtract W from Literal XORLW Exclusive OR Literal with W Syntax: [ label ] SUBLW k Syntax: [ label ] XORLW k Operands: 0 k 255 Operands: 0 k 255 Operation: k – (W) W) Operation: (W) .XOR. k W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s Description: The contents of the W register complement method) from the are XORed with the eight-bit eight-bit literal ‘k’. The result is literal ‘k’. The result is placed in placed in the W register. the W register. SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF f,d Operands: 0 f 127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) – (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the W register from register ‘f’. If W register with register ‘f’. If ‘d’=0, the result is stored in the W ‘d’=0, the result is stored in the register. If ‘d’ = 1, the result is W register. If ‘d’ = 1, the result is stored back in register ‘f’. stored back in register ‘f’. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0  f  127 d  [0,1] Operation: (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’=0, the result is placed in W register. If ‘d’=1, the result is placed in register ‘f’. DS39598F-page 110  2001-2013 Microchip Technology Inc.

PIC16F818/819 14.0 DEVELOPMENT SUPPORT 14.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C® for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2001-2013 Microchip Technology Inc. DS39598F-page 111

PIC16F818/819 14.2 MPLAB C Compilers for Various 14.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 14.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 14.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 14.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39598F-page 112  2001-2013 Microchip Technology Inc.

PIC16F818/819 14.7 MPLAB SIM Software Simulator 14.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 14.10 PICkit 3 In-Circuit Debugger/ Programmer and 14.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2001-2013 Microchip Technology Inc. DS39598F-page 113

PIC16F818/819 14.11 PICkit 2 Development 14.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 14.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39598F-page 114  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................ -40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).............................................................................................-0.3 to +14V Total power dissipation (Note 1)..................................................................................................................................1W Maximum current out of VSS pin...........................................................................................................................200 mA Maximum current into VDD pin..............................................................................................................................200 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA........................................................................................................................100 mA Maximum current sourced by PORTA...................................................................................................................100 mA Maximum current sunk byPORTB........................................................................................................................100 mA Maximum current sourced by PORTB..................................................................................................................100 mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes at the MCLR pin may cause latch-up. A series resistor of greater than 1 k should be used to pull MCLR to VDD, rather than tying the pin directly to VDD. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2001-2013 Microchip Technology Inc. DS39598F-page 115

PIC16F818/819 FIGURE 15-1: PIC16F818/819 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V 4.5V e g a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF818/819 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V e g 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN – 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz. DS39598F-page 116  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.1 DC Characteristics: Supply Voltage PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. VDD Supply Voltage D001 PIC16LF818/819 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode D001 PIC16F818/819 4.0 — 5.5 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section12.4 “Power-on Reset (POR)” to ensure internal for details Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section12.4 “Power-on Reset (POR)” to ensure internal for details Power-on Reset signal VBOR Brown-out Reset Voltage D005 PIC16LF818/819 3.65 — 4.35 V D005 PIC16F818/819 3.65 — 4.35 V FMAX = 14 MHz(2) Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data 2: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.  2001-2013 Microchip Technology Inc. DS39598F-page 117

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC16LF818/819 0.1 0.4 A -40°C 0.1 0.4 A +25°C VDD = 2.0V 0.4 1.5 A +85°C PIC16LF818/819 0.3 0.5 A -40°C 0.3 0.5 A +25°C VDD = 3.0V 0.7 1.7 A +85°C All devices 0.6 1.0 A -40°C 0.6 1.0 A +25°C VDD = 5.0V 1.2 5.0 A +85°C Extended devices 6.0 28 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS39598F-page 118  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC16LF818/819 9 20 A -40°C 7 15 A +25°C VDD = 2.0V 7 15 A +85°C PIC16LF818/819 16 30 A -40°C 14 25 A +25°C VDD = 3.0V FOSC = 32kHZ 14 25 A +85°C (LP Oscillator) All devices 32 40 A -40°C 26 35 A +25°C VDD = 5.0V 26 35 A +85°C Extended devices 35 53 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2001-2013 Microchip Technology Inc. DS39598F-page 119

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC16LF818/819 72 95 A -40°C 76 90 A +25°C VDD = 2.0V 76 90 A +85°C PIC16LF818/819 138 175 A -40°C 136 170 A +25°C VDD = 3.0V FOSC = 1MHZ 136 170 A +85°C (RC Oscillator)(3) All devices 310 380 A -40°C 290 360 A +25°C VDD = 5.0V 280 360 A +85°C Extended devices 350 500 A +125°C PIC16LF818/819 270 315 A -40°C 280 310 A +25°C VDD = 2.0V 285 310 A +85°C PIC16LF818/819 460 610 A -40°C 450 600 A +25°C VDD = 3.0V FOSC = 4MHz 450 600 A +85°C (RC Oscillator)(3) All devices 900 1060 A -40°C 890 1050 A +25°C VDD = 5.0V 890 1050 A +85°C Extended devices .920 1.5 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS39598F-page 120  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 1.8 2.3 mA -40°C 1.6 2.2 mA +25°C VDD = 4.0V 1.3 2.2 mA +85°C FOSC = 20MHZ All devices 3.0 4.2 mA -40°C (HS Oscillator) 2.5 4.0 mA +25°C VDD = 5.0V 2.5 4.0 mA +85°C Extended devices 3.0 5.0 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2001-2013 Microchip Technology Inc. DS39598F-page 121

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC16LF818/819 8 20 A -40°C 7 15 A +25°C VDD = 2.0V 7 15 A +85°C PIC16LF818/819 16 30 A -40°C 14 25 A +25°C VDD = 3.0V FOSC = 31.25kHz (RC_RUN mode, 14 25 A +85°C Internal RC Oscillator) All devices 32 40 A -40°C 29 35 A +25°C VDD = 5.0V 29 35 A +85°C Extended devices 35 45 A +125°C PIC16LF818/819 132 160 A -40°C 126 155 A +25°C VDD = 2.0V 126 155 A +85°C PIC16LF818/819 260 310 A -40°C 230 300 A +25°C VDD = 3.0V FOSC = 1MHz (RC_RUN mode, 230 300 A +85°C Internal RC Oscillator) All devices 560 690 A -40°C 500 650 A +25°C VDD = 5.0V 500 650 A +85°C Extended devices 570 710 A +125°C PIC16LF818/819 310 420 A -40°C 300 410 A +25°C VDD = 2.0V 300 410 A +85°C PIC16LF818/819 550 650 A -40°C 530 620 A +25°C VDD = 3.0V FOSC = 4MHz (RC_RUN mode, 530 620 A +85°C Internal RC Oscillator) All devices 1.2 1.5 mA -40°C 1.1 1.4 mA +25°C VDD = 5.0V 1.1 1.4 mA +85°C Extended devices 1.3 1.6 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS39598F-page 122  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC16LF818/819 .950 1.3 mA -40°C .930 1.2 mA +25°C VDD = 3.0V .930 1.2 mA +85°C FOSC = 8MHz All devices 1.8 3.0 mA -40°C (RC_RUN mode, 1.7 2.8 mA +25°C Internal RC Oscillator) VDD = 5.0V 1.7 2.8 mA +85°C Extended devices 2.0 4.0 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.  2001-2013 Microchip Technology Inc. DS39598F-page 123

PIC16F818/819 15.2 DC Characteristics: Power-Down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC16F818/819 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. D022 Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) (IWDT) Watchdog Timer 1.5 3.8 A -40°C 2.2 3.8 A +25°C VDD = 2.0V 2.7 4.0 A +85°C 2.3 4.6 A -40°C 2.7 4.6 A +25°C VDD = 3.0V 3.1 4.8 A +85°C 3.0 10.0 A -40°C 3.3 10.0 A +25°C VDD = 5.0V 3.9 13.0 A +85°C Extended Devices 5.0 21.0 A +125°C D022A Brown-out Reset 40 60 A -40C to +85C VDD = 5.0V (IBOR) D025 Timer1 Oscillator 1.7 2.3 A -40°C (IOSCB) 1.8 2.3 A +25°C VDD = 2.0V 2.0 2.3 A +85°C 2.2 3.8 A -40°C 2.6 3.8 A +25°C VDD = 3.0V 32kHz on Timer1 2.9 3.8 A +85°C 3.0 6.0 A -40°C 3.2 6.0 A +25°C VDD = 5.0V 3.4 7.0 A +85°C D026 A/D Converter 0.001 2.0 A -40C to +85C VDD = 2.0V (IAD) 0.001 2.0 A -40C to +85C VDD = 3.0V A/D on, Sleep, not converting 0.003 2.0 A -40C to +85C VDD = 5.0V Extended Devices 4.0 8.0 A -40C to +125C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k. DS39598F-page 124  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.3 DC Characteristics: Internal RC Accuracy PIC16F818/819, PIC16F818/819 TSL (Industrial, Extended) PIC16LF818/819, PIC16LF818/819 TSL (Industrial) PIC16LF818/819(3) Standard Operating Conditions (unless otherwise stated) PIC16LF818/819 TSL(3) Operating temperature -40°C  TA  +85°C for industrial (Industrial) PIC16F818/819(3) Standard Operating Conditions (unless otherwise stated) PIC16F818/819 TSL(3) Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC16LF818/819 -5 ±1 5 % +25°C -25 — 25 % -10°C to +85°C VDD = 2.7-3.3V -30 — 30 % -40°C to +85°C PIC16F818/819(4) -5 ±1 5 % +25°C -25 — 25 % -10°C to +85°C VDD = 4.5-5.5V -30 — 30 % -40°C to +85°C -35 — 35 % -40°C to +125°C PIC16LF818/819 TSL -2 ±1 2 % +25°C -5 — 5 % -10°C to +85°C VDD = 2.7-3.3V -10 — 10 % -40°C to +85°C PIC16F818/819 TSL(5) -2 ±1 2 % +25°C -5 — 5 % -10°C to +85°C VDD = 4.5-5.5V -10 — 10 % -40°C to +85°C -15 — 15 % -40°C to +125°C INTRC Accuracy @ Freq = 31 kHz(2) PIC16LF818/819 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC16F818/819(4) 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V PIC16LF818/819 TSL 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC16F818/819 TSL(5) 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration. 3: The only specification difference between a non-TSL device and a TSL device is the internal RC oscillator specifications listed above. All other specifications are maintained. 4: Example part number for the specifications listed above: PIC16F818-I/SS (PIC16F818 device, Industrial temperature, SSOP package). 5: Example part number for the specifications listed above: PIC16F818-I/SSTSL (PIC16F818 device, Industrial temperature, SSOP package).  2001-2013 Microchip Technology Inc. DS39598F-page 125

PIC16F818/819 15.4 DC Characteristics: PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial DC CHARACTERISTICS -40°C  TA  +125°C for extended Operating voltage VDD range as described in Section 15.1 “DC Characteristics: Supply Voltage”. Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer VSS — 0.15 VDD V For entire VDD range D030A VSS — 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS — 0.2 VDD V D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V (Note 1) D033 OSC1 (in XT and LP mode) VSS — 0.3V V OSC1 (in HS mode) VSS — 0.3 VDD V Ports RB1 and RB4: D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range VIH Input High Voltage I/O ports: D040 with TTL buffer 2.0 — VDD V 4.5V  VDD  5.5V D040A 0.25 VDD + 0.8V — VDD V For entire VDD range D041 with Schmitt Trigger buffer 0.8 VDD — VDD V For entire VDD range D042 MCLR 0.8 VDD — VDD V D042A OSC1 (in XT and LP mode) 1.6V — VDD V OSC1 (in HS mode) 0.7 VDD — VDD V D043 OSC1 (in RC mode) 0.9 VDD — VDD V (Note 1) Ports RB1 and RB4: D044 with Schmitt Trigger buffer 0.7 VDD — VDD V For entire VDD range D070 IPURB PORTB Weak Pull-up Current 50 250 400 A VDD = 5V, VPIN = VSS IIL Input Leakage Current (Notes 2, 3) D060 I/O ports — — ±1 A Vss  VPIN  VDD, pin at high-impedance D061 MCLR — — ±5 A Vss  VPIN  VDD D063 OSC1 — — ±5 A Vss  VPIN  VDD, XT, HS and LP oscillator configuration † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F818/819 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS39598F-page 126  2001-2013 Microchip Technology Inc.

PIC16F818/819 15.4 DC Characteristics: PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial DC CHARACTERISTICS -40°C  TA  +125°C for extended Operating voltage VDD range as described in Section 15.1 “DC Characteristics: Supply Voltage”. Param Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC oscillator config) -40C to +125C VOH Output High Voltage D090 I/O ports (Note 3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, (RC oscillator config) -40C to +125C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — — 50 pF (in RC mode) D102 CB SCL, SDA in I2C™ mode — — 400 pF Data EEPROM Memory D120 ED Endurance 100K 1M — E/W -40°C to +85°C 10K 100K — E/W +85°C to +125°C D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write, VMIN=min. operating voltage D122 TDEW Erase/write cycle time — 4 8 ms Program Flash Memory D130 EP Endurance 10K 100K — E/W -40°C to +85°C 1K 10K — E/W +85°C to +125°C D131 VPR VDD for read VMIN — 5.5 V D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write, VMIN=min. operating voltage D133 TPE Erase cycle time — 2 4 ms D134 TPW Write cycle time — 2 4 ms † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F818/819 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2001-2013 Microchip Technology Inc. DS39598F-page 127

PIC16F818/819 15.5 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition FIGURE 15-3: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports 15 pF for OSC2 output DS39598F-page 128  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. FOSC External CLKI Frequency (Note 1) DC — 1 MHz XT and RC Oscillator mode DC — 20 MHz HS Oscillator mode DC — 32 kHz LP Oscillator mode Oscillator Frequency (Note 1) DC — 4 MHz RC Oscillator mode 0.1 — 4 MHz XT Oscillator mode 4 — 20 MHz HS Oscillator mode 5 — 200 kHz LP Oscillator mode 1 TOSC External CLKI Period (Note 1) 1000 — — ns XT and RC Oscillator mode 50 — — ns HS Oscillator mode 5 — — ms LP Oscillator mode Oscillator Period (Note 1) 250 — — ns RC Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 250 ns HS Oscillator mode 5 — — ms LP Oscillator mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3 TOSL, External Clock in (OSC1) High 500 — — ns XT Oscillator TOSH or Low Time 2.5 — — ms LP Oscillator 15 — — ns HS Oscillator 4 TOSR, External Clock in (OSC1) Rise or — — 25 ns XT Oscillator TOSF Fall Time — — 50 ns LP Oscillator — — 15 ns HS Oscillator † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.  2001-2013 Microchip Technology Inc. DS39598F-page 129

PIC16F818/819 FIGURE 15-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 18 12 14 19 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure15-3 for load conditions. TABLE 15-2: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 10* TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11* TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12* TCKR CLKO Rise Time — 35 100 ns (Note 1) 13* TCKF CLKO Fall Time — 35 100 ns (Note 1) 14* TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15* TIOV2CKH Port In Valid before CLKO  TOSC + 200 — — ns (Note 1) 16* TCKH2IOI Port In Hold after CLKO  0 — — ns (Note 1) 17* TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 100 255 ns 18* TOSH2IOI OSC1  (Q2 cycle) to Port PIC16F818/819 100 — — ns Input Invalid (I/O in hold time) PIC16LF818/819 200 — — ns 19* TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns 20* TIOR Port Output Rise Time PIC16F818/819 — 10 40 ns PIC16LF818/819 — — 145 ns 21* TIOF Port Output Fall Time PIC16F818/819 — 10 40 ns PIC16LF818/819 — — 145 ns 22††* TINP INT pin High or Low Time TCY — — ns 23††* TRBP RB7:RB4 Change INT High or Low Time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39598F-page 130  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure15-3 for load conditions. FIGURE 15-7: BROWN-OUT RESET TIMING VDD VBOR 35 TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (Low) 2 — — s VDD = 5V, -40°C to +85°C 31* TWDT Watchdog Timer Time-out Period 13.6 16 18.4 ms VDD = 5V, -40°C to +85°C (no prescaler) 32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* TPWRT Power-up Timer Period 61.2 72 82.8 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O High-Impedance from MCLR — — 2.1 s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  VBOR (D005) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001-2013 Microchip Technology Inc. DS39598F-page 131

PIC16F818/819 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RB6/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure15-3 for load conditions. TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* TT0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet Time Synchronous, PIC16F818/819 15 — — ns parameter 47 Prescaler = 2,4,8 PIC16LF818/819 25 — — ns Asynchronous PIC16F818/819 30 — — ns PIC16LF818/819 50 — — ns 46* TT1L T1CKI Low Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet Synchronous, PIC16F818/819 15 — — ns parameter 47 Prescaler = 2,4,8 PIC16LF818/819 25 — — ns Asynchronous PIC16F818/819 30 — — ns PIC16LF818/819 50 — — ns 47* TT1P T1CKI Input Synchronous PIC16F818/819 Greater of: — — ns N = prescale Period 30 or TCY + 40 value (1, 2, 4, 8) N PIC16LF818/819 Greater of: N = prescale 50 or TCY + 40 value (1, 2, 4, 8) N Asynchronous PIC16F818/819 60 — — ns PIC16LF818/819 100 — — ns FT1 Timer1 Oscillator Input Frequency Range DC — 32.768 kHz (Oscillator enabled by setting bit T1OSCEN) 48 TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC — 7 TOSC — * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39598F-page 132  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1) CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure15-3 for load conditions. TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Symbol Characteristic Min Typ† Max Units Conditions No. 50* TCCL CCP1 No Prescaler 0.5 TCY + 20 — — ns Input Low Time PIC16F818/819 10 — — ns With Prescaler PIC16LF818/819 20 — — ns 51* TCCH CCP1 No Prescaler 0.5 TCY + 20 — — ns Input High PIC16F818/819 10 — — ns Time With Prescaler PIC16LF818/819 20 — — ns 52* TCCP CCP1 Input Period 3 TCY + 40 — — ns N = prescale N value (1,4 or 16) 53* TCCR CCP1 Output Rise Time PIC16F818/819 — 10 25 ns PIC16LF818/819 — 25 50 ns 54* TCCF CCP1 Output Fall Time PIC16F818/819 — 10 25 ns PIC16LF818/819 — 25 45 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2001-2013 Microchip Technology Inc. DS39598F-page 133

PIC16F818/819 FIGURE 15-10: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure15-3 for load conditions. FIGURE 15-11: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 Note: Refer to Figure15-3 for load conditions. DS39598F-page 134  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 15-12: SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 77 SDI MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure15-3 for load conditions. FIGURE 15-13: SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb Bit 6 - - - - - -1 LSb 75, 76 77 SSDDII MSb In Bit 6 - - - -1 LSb In 74 Note: Refer to Figure15-3 for load conditions.  2001-2013 Microchip Technology Inc. DS39598F-page 135

PIC16F818/819 TABLE 15-6: SPI MODE REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 70* TSSL2SCH, SS  to SCK  or SCK  Input TCY — — ns TSSL2SCL 71* TSCH SCK Input High Time (Slave mode) TCY + 20 — — ns 72* TSCL SCK Input Low Time (Slave mode) TCY + 20 — — ns 73* TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — — ns TDIV2SCL 74* TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — — ns TSCL2DIL 75* TDOR SDO Data Output Rise Time PIC16F818/819 — 10 25 ns PIC16LF818/819 — 25 50 ns 76* TDOF SDO Data Output Fall Time — 10 25 ns 77* TSSH2DOZ SS  to SDO Output High-Impedance 10 — 50 ns 78* TSCR SCK Output Rise Time PIC16F818/819 — 10 25 ns (Master mode) PIC16LF818/819 — 25 50 ns 79* TSCF SCK Output Fall Time (Master mode) — 10 25 ns 80* TSCH2DOV, SDO Data Output Valid after SCK PIC16F818/819 — — 50 ns TSCL2DOV Edge PIC16LF818/819 — — 145 ns 81* TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — — ns TDOV2SCL 82* TSSL2DOV SDO Data Output Valid after SS  Edge — — 50 ns 83* TSCH2SSH, SS after SCK Edge 1.5 TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-14: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition Note: Refer to Figure15-3 for load conditions. DS39598F-page 136  2001-2013 Microchip Technology Inc.

PIC16F818/819 TABLE 15-7: I2C™ BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 90* TSU:STA Start Condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — — Start condition 91* THD:STA Start Condition 100 kHz mode 4000 — — ns After this period, the first clock Hold Time 400 kHz mode 600 — — pulse is generated 92* TSU:STO Stop Condition 100 kHz mode 4700 — — ns Setup Time 400 kHz mode 600 — — 93 THD:STO Stop Condition 100 kHz mode 4000 — — ns Hold Time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 15-15: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure15-3 for load conditions.  2001-2013 Microchip Technology Inc. DS39598F-page 137

PIC16F818/819 TABLE 15-8: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100* THIGH Clock High Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s SSP Module 1.5 TCY — 101* TLOW Clock Low Time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s SSP Module 1.5 TCY — 102* TR SDA and SCL Rise 100 kHz mode — 1000 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10-400 pF 103* TF SDA and SCL Fall 100 kHz mode — 300 ns Time 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10-400 pF 90* TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 91* THD:STA Start Condition Hold 100 kHz mode 4.0 — s After this period, the first Time 400 kHz mode 0.6 — s clock pulse is generated 106* THD:DAT Data Input Hold 100 kHz mode 0 — ns Time 400 kHz mode 0 0.9 s 107* TSU:DAT Data Input Setup 100 kHz mode 250 — ns (Note 2) Time 400 kHz mode 100 — ns 92* TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 109* TAA Output Valid from 100 kHz mode — 3500 ns (Note 1) Clock 400 kHz mode — — ns 110* TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start CB Bus Capacitive Loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS39598F-page 138  2001-2013 Microchip Technology Inc.

PIC16F818/819 TABLE 15-9: A/D CONVERTER CHARACTERISTICS:PIC16F818/819 (INDUSTRIAL, EXTENDED) PIC16LF818/819 (INDUSTRIAL) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS  VAIN  VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A06 EOFF Offset Error — — <±2 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A07 EGN Gain Error — — <±1 LSb VREF = VDD = 5.12V, VSS  VAIN  VREF A10 — Monotonicity — guaranteed(3) — — VSS  VAIN  VREF A20 VREF Reference Voltage (VREF+ – VREF-) 2.0 — VDD + 0.3 V A21 VREF+ Reference Voltage High AVDD – 2.5V AVDD + 0.3V V A22 VREF- Reference Voltage Low AVSS – 0.3V VREF+ – 2.0V V A25 VAIN Analog Input Voltage VSS – 0.3V — VREF + 0.3V V A30 ZAIN Recommended Impedance of — — 2.5 k (Note 4) Analog Voltage Source A40 IAD A/D Conversion PIC16F818/819 — 220 — A Average current Current (VDD) PIC16LF818/819 — 90 — A consumption when A/D is on (Note 1) A50 IREF VREF Input Current (Note 2) — — 5 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section11.1 “A/D Acquisition Requirements”. — — 150 A During A/D conversion cycle † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 4: Maximum allowed impedance for analog voltage source is 10 kThis requires higher acquisition time.  2001-2013 Microchip Technology Inc. DS39598F-page 139

PIC16F818/819 FIGURE 15-16: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 A/D DATA 9 8 7   2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE Sampling Stopped SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-10: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D Clock Period PIC16F818/819 1.6 — — s TOSC based, VREF  3.0V PIC16LF818/819 3.0 — — s TOSC based, VREF  2.0V PIC16F818/819 2.0 4.0 6.0 s A/D RC mode PIC16LF818/819 3.0 6.0 9.0 s A/D RC mode 131 TCNV Conversion Time (not including S/H time) — 12 TAD (Note 1) 132 TACQ Acquisition Time (Note 2) 40 — s 10* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D Clock Start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section11.1 “A/D Acquisition Requirements” for minimum conditions. DS39598F-page 140  2001-2013 Microchip Technology Inc.

PIC16F818/819 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean–3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 16-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 7 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 6 Minimum: mean – 3 (-40°C to +125°C) 5.5V 5 5.0V 4.5V 4 mA) 4.0V (D D I 3 3.5V 3.0V 2 2.5V 2.0V 1 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 16-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 7 Minimum: mean – 3 (-40°C to +125°C) 5.5V 6 5.0V 4.5V 5 A) 4.0V m (D 4 3.5V D I 3.0V 3 2.5V 2 2.0V 1 0 4 6 8 10 12 14 16 18 20 FOSC (MHz)  2001-2013 Microchip Technology Inc. DS39598F-page 141

PIC16F818/819 FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 1.4 5.0V 1.2 4.5V 4.0V A) 1.0 m (D 3.5V ID 0.8 3.0V 2.5V 0.6 2.0V 0.4 0.2 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 FOSC (MHz) FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 5.5V 5.0V 1.5 4.5V A) m 4.0V (D D I 3.5V 1.0 3.0V 2.5V 2.0V 0.5 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 FOSC (MHz) DS39598F-page 142  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 16-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 70 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 60 Minimum: mean – 3 (-40°C to +125°C) 5.5V 50 5.0V 4.5V 40 A) 4.0V u (DD 3.5V I 30 3.0V 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 16-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 Typical: statistical mean @ 25°C 5.5V Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 100 5.0V 4.5V 80 4.0V A) (uD 60 3.5V D I 3.0V 2.5V 40 2.0V 20 0 20 30 40 50 60 70 80 90 100 FOSC (kHz)  2001-2013 Microchip Technology Inc. DS39598F-page 143

PIC16F818/819 FIGURE 16-7: TYPICAL IDD vs. VDD, -40C TO +125C, 1MHz TO 8MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 1.6 Typical: statistical mean @ 25°C 1.4 Maximum: mean + 3 (-40°C to +125°C) 5.5V Minimum: mean – 3 (-40°C to +125°C) 5.0V 1.2 4.5V 1.0 4.0V A) (mD 0.8 3.5V D I 3.0V 0.6 2.5V 0.4 2.0V 0.2 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FOSC (MHz) FIGURE 16-8: MAXIMUM IDD vs. VDD, -40C TO +125C, 1MHz TO 8MHz (RC_RUN MODE, ALL PERIPHERALS DISABLED) 4.5 Typical: statistical mean @ 25°C 4.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.5V 3.5 5.0V 3.0 4.5V 4.0V A) 2.5 m (D 3.5V ID 2.0 3.0V 1.5 2.5V 2.0V 1.0 0.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FOSC (MHz) DS39598F-page 144  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 16-9: IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (125°C) 10 Max (85°C) 1 A) u (D P I 0.1 0.01 Typ (25°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-10: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25C) 4.5 Operation above 4 MHz is not recommended 4.0 5.1 kOhm 3.5 3.0 z) 2.5 MH 10 kOhm q ( e Fr 2.0 1.5 1.0 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2001-2013 Microchip Technology Inc. DS39598F-page 145

PIC16F818/819 FIGURE 16-11: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25C) 2.5 2.0 3.3 kOhm 1.5 z) 5.1 kOhm H M q ( e Fr 1.0 10 kOhm 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300pF, +25C) 0.9 0.8 3.3 kOhm 0.7 0.6 5.1 kOhm z) 0.5 H M q ( e Fr 0.4 10 kOhm 0.3 0.2 0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39598F-page 146  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 16-13: IPD TIMER1 OSCILLATOR, -10°C TO +70°C (SLEEP MODE, TMR1 COUNTER DISABLED) 5.0 4.5 Max (-10°C to +70°C) 4.0 3.5 3.0 Typ (+25°C) A) (D 2.5 P I 2.0 1.5 Typical: statistical mean @ 25°C 1.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-14: IPD WDT, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 18 Typical: statistical mean @ 25°C 16 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 14 12 A) 10  Max (-40°C to +125°C) (T D W I 8 6 Max (-40°C to +85°C) 4 2 Typ (25°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2001-2013 Microchip Technology Inc. DS39598F-page 147

PIC16F818/819 FIGURE 16-15: IPD BOR vs. VDD, -40°C TO +125°C (SLEEP MODE, BOR ENABLED AT 2.00V-2.16V) 1,000 Max (125°C) Typ (25°C) Device in Indeterminant Sleep State Device in Reset A) (D 100 D I Note: Device current in Reset Max (125°C) depends on oscillator mode, frequency and circuit. Typical: statistical mean @ 25°C Typ (25°C) Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-16: IPD A/D, -40C TO +125C, SLEEP MODE, A/D ENABLED (NOT CONVERTING) 12 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 10 Max (-40°C to +125°C) 8 A)  (D 6 P I 4 Max (-40°C to +85°C) 2 Typ (+25°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS39598F-page 148  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 16-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 4.0 Max 3.5 Typ (25°C) V) 3.0 (H O V 2.5 Min 2.0 Typical: statistical mean @ 25°C 1.5 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 16-18: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.5 Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.5 Max 2.0 (V)H Typ (25°C) O V 1.5 Min 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA)  2001-2013 Microchip Technology Inc. DS39598F-page 149

PIC16F818/819 FIGURE 16-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.0 0.9 Max (125°C) Typical: statistical mean @ 25°C 0.8 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.7 0.6 Max (85°C) V) (L 0.5 O V Typ (25°C) 0.4 0.3 Min (-40°C) 0.2 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 16-20: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 3.0 Max (125°C) 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.0 V) (L 1.5 O V Max (85°C) 1.0 Typ (25°C) 0.5 Min (-40°C) 0.0 0 5 10 15 20 25 IOL (-mA) DS39598F-page 150  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 16-21: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.3 VTH Max (-40°C) 1.2 1.1 VTH Typ (25°C) V) (N 1.0 VI 0.9 VTH Min (125°C) 0.8 0.7 0.6 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-22: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 3.5 Minimum: mean – 3 (-40°C to +125°C) VIH Max (125°C) 3.0 2.5 VIH Min (-40°C) V) (N 2.0 VI VIL Max (-40°C) 1.5 1.0 VIL Min (125°C) 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2001-2013 Microchip Technology Inc. DS39598F-page 151

PIC16F818/819 FIGURE 16-23: MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40C TO +125C) 3.5 VIH Max Typical: statistical mean @ 25°C 3.0 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.5 2.0 VVIILL MMaaxx V) (N VI VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-24: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) 4 3.5 -4-400°CC SB) 3 L arity ( +2255C°C e 2.5 n nli No +8855C°C al 2 gr e nt al or I 1.5 nti e er Diff 1 0.5 1+2152C5°C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) DS39598F-page 152  2001-2013 Microchip Technology Inc.

PIC16F818/819 FIGURE 16-25: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 2.5 B) S L y ( arilt 2 e n nli o N al 1.5 gr e nt or I MMaaxx ((--4400°CC t oto 1 +2152C5)°C) al nti 1 e er TTyypp ((+2255C°)C) Diff 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V)  2001-2013 Microchip Technology Inc. DS39598F-page 153

PIC16F818/819 NOTES: DS39598F-page 154  2001-2013 Microchip Technology Inc.

PIC16F818/819 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 18-Lead PDIP (300 mil) Example PIC16F818-I/P 0410017 e3 18-Lead SOIC 18-Lead SOIC (7.50 mm) Example PIC16F818-04 /SOe3 0410017 20-Lead SSOP (5.30 mm) Example PIC16F818- 20/SSe3 0410017 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 XXXXXXXX 16F818- XXXXXXXX I/MLe3 0410017 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2001-2013 Microchip Technology Inc. DS39598F-page 155

PIC16F818/819 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:30)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)-(cid:4)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)<<(cid:4) (cid:20)(cid:24)(cid:4)(cid:4) (cid:20)(cid:24)(cid:3)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:23) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:29) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)(cid:5)1 DS39598F-page 156  2001-2013 Microchip Technology Inc.

PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2013 Microchip Technology Inc. DS39598F-page 157

PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39598F-page 158  2001-2013 Microchip Technology Inc.

PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2013 Microchip Technology Inc. DS39598F-page 159

PIC16F818/819 !(cid:24)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)"#$(cid:14)(cid:19)%(cid:9)"(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)&(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)""(cid:21)(cid:9)(cid:22)(cid:9)’((cid:23)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)""&(cid:10)(cid:30)(cid:9) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:24)(cid:4) (cid:5)(cid:20)(cid:3)(cid:4) (cid:5)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:3)1 DS39598F-page 160  2001-2013 Microchip Technology Inc.

PIC16F818/819 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2001-2013 Microchip Technology Inc. DS39598F-page 161

PIC16F818/819 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)./.(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) 0(cid:14)(cid:13)#(cid:9)(cid:24)(’’(cid:9)(cid:25)(cid:25)(cid:9)1(cid:27)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19),(cid:13)# (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# A (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 DS39598F-page 162  2001-2013 Microchip Technology Inc.

PIC16F818/819 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)./.(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) 0(cid:14)(cid:13)#(cid:9)(cid:24)(’’(cid:9)(cid:25)(cid:25)(cid:9)1(cid:27)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19),(cid:13)# (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2001-2013 Microchip Technology Inc. DS39598F-page 163

PIC16F818/819 NOTES: DS39598F-page 164  2001-2013 Microchip Technology Inc.

PIC16F818/819 APPENDIX A: REVISION HISTORY Revision D (November 2003) Updated IRCF bit modification information and changed Revision A (May 2002) the INTOSC stabilization delay from 1ms to 4ms in Section4.0 “Oscillator Configurations”. Updated Original version of this data sheet. Section12.17 “In-Circuit Serial Programming” to clarify LVP programming. In Section15.0 “Electrical Revision B (August 2002) Characteristics”, the DC Characteristics (Section15.2 Added INTRC section. PWRT and BOR are indepen- and Section15.3) have been updated to include the dent of each other. Revised program memory text and Typ, Min and Max values and Table15-1 “External code routine. Added QFN package. Modified PORTB Clock Timing Requirements” has been updated. diagrams. Revision E (September 2004) Revision C (November 2002) This revision includes the DC and AC Characteristics Added various new feature descriptions. Added inter- Graphs and Tables. The Electrical Specifications in nal RC oscillator specifications. Added low-power Section16.0 “DC and AC Characteristics Graphs Timer1 specifications and RTC application example. and Tables” have been updated and there have been minor corrections to the data sheet text. Revision F (November 2011) This revision updated Section17.0 “Packaging Infor- mation”. APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in TableB-1. TABLE B-1: DIFFERENCES BETWEEN THE PIC16F818 AND PIC16F819 Features PIC16F818 PIC16F819 Flash Program Memory (14-bit words) 1K 2K Data Memory (bytes) 128 256 EEPROM Data Memory (bytes) 128 256  2001-2013 Microchip Technology Inc. DS39598F-page 165

PIC16F818/819 NOTES: DS39598F-page 166  2001-2013 Microchip Technology Inc.

PIC16F818/819 INDEX RB6 Pin .....................................................................51 RB7 Pin .....................................................................52 A Recommended MCLR Circuit ....................................92 SSP in I2C Mode ........................................................76 A/D SSP in SPI Mode .......................................................74 Acquisition Requirements ..........................................84 System Clock .............................................................38 ADIF Bit ......................................................................83 Timer0/WDT Prescaler ..............................................53 Analog-to-Digital Converter ........................................81 Timer1 .......................................................................58 Associated Registers .................................................87 Timer2 .......................................................................63 Calculating Acquisition Time ......................................84 Watchdog Timer (WDT) .............................................98 Configuring Analog Port Pins .....................................85 BOR. See Brown-out Reset. Configuring the Interrupt ............................................83 Brown-out Reset (BOR) ..............................89, 91, 92, 93, 94 Configuring the Module ..............................................83 Conversion Clock .......................................................85 C Conversion Requirements .......................................140 C Compilers Conversions ...............................................................86 MPLAB C18 .............................................................112 Converter Characteristics ........................................139 Capture/Compare/PWM (CCP) .........................................65 Delays ........................................................................84 Capture Mode ............................................................66 Effects of a Reset .......................................................87 CCP Prescaler ...................................................66 GO/DONE Bit .............................................................83 Pin Configuration ...............................................66 Internal Sampling Switch (Rss) Impedance ...............84 Software Interrupt ..............................................66 Operation During Sleep .............................................87 Timer1 Mode Selection ......................................66 Result Registers .........................................................86 Capture, Compare and Timer1 Source Impedance .....................................................84 Associated Registers .........................................67 Time Delays ...............................................................84 CCP1IF ......................................................................66 Use of the CCP Trigger ..............................................87 CCPR1 ......................................................................66 Absolute Maximum Ratings .............................................115 CCPR1H:CCPR1L .....................................................66 ACK ....................................................................................77 Compare Mode ..........................................................67 ADCON0 Register ..............................................................81 Pin Configuration ...............................................67 ADCON1 Register ..............................................................81 Software Interrupt Mode ....................................67 ADRESH Register ........................................................13, 81 Special Event Trigger ........................................67 ADRESH, ADRESL Register Pair ......................................83 Special Event Trigger Output of CCP1 ..............67 ADRESL Register ........................................................14, 81 Timer1 Mode Selection ......................................67 Application Notes PWM and Timer2 AN556 (Implementing a Table Read) ........................23 AN578 (Use of the SSP Module in the I2C Associated Registers .........................................69 PWM Mode ................................................................68 Multi-Master Environment) .................................71 Duty Cycle .........................................................68 AN607 (Power-up Trouble Shooting) .........................92 Example Frequencies/Resolutions ....................69 Assembler Period ................................................................68 MPASM Assembler ..................................................112 Setup for Operation ...........................................69 B Timer Resources .......................................................65 CCP1M0 Bit .......................................................................65 BF Bit .................................................................................77 CCP1M1 Bit .......................................................................65 Block Diagrams CCP1M2 Bit .......................................................................65 A/D .............................................................................83 CCP1M3 Bit .......................................................................65 Analog Input Model ....................................................84 CCP1X Bit ..........................................................................65 Capture Mode Operation ...........................................66 CCP1Y Bit ..........................................................................65 Compare Mode Operation .........................................67 CCPR1H Register ..............................................................65 In-Circuit Serial Programming Connections .............101 CCPR1L Register ..............................................................65 Interrupt Logic ............................................................96 Code Examples On-Chip Reset Circuit ................................................91 Changing Between Capture Prescalers .....................66 PIC16F818/819 ............................................................6 Changing Prescaler Assignment from Timer0 PWM ..........................................................................68 to WDT ..............................................................55 RA0/AN0:RA1/AN1 Pins ............................................40 Changing Prescaler Assignment from WDT RA2/AN2/Vref- Pin .....................................................40 to Timer0 ...........................................................55 RA3/AN3/Vref+ Pin ....................................................40 Clearing RAM Using Indirect Addressing ..................23 RA4/AN4/T0CKI Pin ...................................................40 Erasing a Flash Program Memory Row .....................29 RA5/MCLR/Vpp Pin ...................................................41 Implementing a Real-Time Clock Using a RA6/OSC2/CLKO Pin ................................................41 Timer1 Interrupt Service ....................................62 RA7/OSC1/CLKI Pin ..................................................42 Initializing PORTA ......................................................39 RB0 Pin ......................................................................45 Reading a 16-Bit Free Running Timer .......................59 RB1 Pin ......................................................................46 Reading Data EEPROM ............................................27 RB2 Pin ......................................................................47 Reading Flash Program Memory ...............................28 RB3 Pin ......................................................................48 Saving Status and W Registers in RAM ....................97 RB4 Pin ......................................................................49 Writing a 16-Bit Free Running Timer .........................59 RB5 Pin ......................................................................50 Writing to Data EEPROM ..........................................27  2001-2013 Microchip Technology Inc. DS39598F-page 167

PIC16F818/819 Writing to Flash Program Memory .............................31 I Code Protection .........................................................89, 100 I/O Ports .............................................................................39 Computed GOTO ...............................................................23 I2C Configuration Bits ...............................................................89 Associated Registers .................................................79 Crystal Oscillator and Ceramic Resonators .......................33 Master Mode Operation .............................................79 Customer Change Notification Service ............................173 Mode ..........................................................................76 Customer Notification Service ..........................................173 Mode Selection ..........................................................76 Customer Support ............................................................173 Multi-Master Mode Operation ....................................79 D Slave Mode ................................................................77 Addressing .........................................................77 Data EEPROM Memory .....................................................25 Reception ..........................................................77 Associated Registers .................................................32 SCL, SDA Pins ..................................................77 EEADR Register ........................................................25 Transmission .....................................................77 EEADRH Register ......................................................25 ID Locations ................................................................89, 100 EECON1 Register ......................................................25 In-Circuit Debugger ..........................................................100 EECON2 Register ......................................................25 In-Circuit Serial Programming ............................................89 EEDATA Register ......................................................25 In-Circuit Serial Programming (ICSP) ..............................101 EEDATH Register ......................................................25 INDF Register .........................................................14, 15, 23 Operation During Code-Protect ..................................32 Indirect Addressing .......................................................23, 24 Protection Against Spurious Writes ............................32 Instruction Format ............................................................103 Reading ......................................................................27 Instruction Set ..................................................................103 Write Interrupt Enable Flag (EEIF Bit) ........................25 Descriptions .............................................................105 Writing ........................................................................27 Read-Modify-Write Operations ................................103 Data Memory Summary Table .......................................................104 Special Function Registers ........................................13 ADDLW ....................................................................105 DC and AC Characteristics ADDWF ....................................................................105 Graphs and Tables ...................................................141 ANDLW ....................................................................105 DC Characteristics ANDWF ....................................................................105 Internal RC Accuracy ...............................................125 BCF ..........................................................................105 PIC16F818/819, PIC16LF818/819 ...........................126 BSF ..........................................................................105 Power-Down and Supply Current .............................118 BTFSC .....................................................................106 Supply Voltage .........................................................117 BTFSS .....................................................................106 Development Support ......................................................111 CALL ........................................................................106 Device Differences ...........................................................165 CLRF .......................................................................106 Device Overview ..................................................................5 CLRW ......................................................................106 Direct Addressing ...............................................................24 CLRWDT .................................................................106 E COMF ......................................................................107 DECF .......................................................................107 EEADR Register ................................................................25 DECFSZ ..................................................................107 EEADRH Register ..............................................................25 GOTO ......................................................................107 EECON1 Register ..............................................................25 INCF ........................................................................107 EECON2 Register ..............................................................25 INCFSZ ....................................................................107 EEDATA Register ..............................................................25 IORLW .....................................................................108 EEDATH Register ..............................................................25 IORWF .....................................................................108 Electrical Characteristics ..................................................115 MOVF ......................................................................108 Endurance ............................................................................1 MOVLW ...................................................................108 Errata ...................................................................................3 MOVWF ...................................................................108 External Clock Input ...........................................................34 NOP .........................................................................108 External Interrupt Input (RB0/INT). See Interrupt Sources. RETFIE ....................................................................109 F RETLW ....................................................................109 Flash Program Memory ......................................................25 RETURN ..................................................................109 Associated Registers .................................................32 RLF ..........................................................................109 EEADR Register ........................................................25 RRF .........................................................................109 SLEEP .....................................................................109 EEADRH Register ......................................................25 EECON1 Register ......................................................25 SUBLW ....................................................................110 EECON2 Register ......................................................25 SUBWF ....................................................................110 EEDATA Register ......................................................25 SWAPF ....................................................................110 EEDATH Register ......................................................25 XORLW ....................................................................110 Erasing .......................................................................28 XORWF ...................................................................110 Reading ......................................................................28 INT Interrupt (RB0/INT). See Interrupt Sources. Writing ........................................................................30 INTCON Register ...............................................................15 FSR Register .....................................................13, 14, 15, 23 GIE Bit .......................................................................18 INTE Bit .....................................................................18 G INTF Bit ......................................................................18 General Purpose Register File ...........................................10 RBIF Bit .....................................................................18 DS39598F-page 168  2001-2013 Microchip Technology Inc.

PIC16F818/819 TMR0IE Bit .................................................................18 RCIO ..........................................................................33 Internal Oscillator Block .....................................................35 XT .........................................................................33, 93 INTRC Modes ............................................................35 Oscillator Control Register .................................................37 Internet Address ...............................................................173 Modifying IRCF Bits ...................................................37 Interrupt Sources ..........................................................89, 96 Clock Transition Sequence ................................37 RB0/INT Pin, External ................................................97 Oscillator Start-up Timer (OST) ....................................89, 92 TMR0 Overflow ..........................................................97 Oscillator, WDT ..................................................................98 Interrupts P RB7:RB4 Port Change ...............................................43 Synchronous Serial Port Interrupt ..............................20 Packaging Information .....................................................155 Interrupts, Context Saving During ......................................97 Marking ....................................................................155 Interrupts, Enable Bits PCFG0 Bit ..........................................................................82 Global Interrupt Enable (GIE Bit) ...............................96 PCFG1 Bit ..........................................................................82 Interrupt-on-Change (RB7:RB4) Enable PCFG2 Bit ..........................................................................82 (RBIE Bit) ...........................................................97 PCFG3 Bit ..........................................................................82 RB0/INT Enable (INTE Bit) ........................................18 PCL Register ....................................................13, 14, 15, 23 TMR0 Overflow Enable (TMR0IE Bit) ........................18 PCLATH Register .............................................13, 14, 15, 23 Interrupts, Enable bits PCON Register ..................................................................93 Global Interrupt Enable (GIE Bit) ...............................18 POR Bit ......................................................................22 Interrupts, Flag Bits Pinout Descriptions Interrupt-on-Change (RB7:RB4) Flag PIC16F818/819 ...........................................................7 (RBIF Bit) .............................................................18, 97 Pointer, FSR ......................................................................23 RB0/INT Flag (INTF Bit) .............................................18 POP ...................................................................................23 TMR0 Overflow Flag (TMR0IF Bit) .............................97 POR. See Power-on Reset. INTRC Modes PORTA ................................................................................7 Adjustment .................................................................36 Associated Register Summary ..................................39 Functions ...................................................................39 L PORTA Register ........................................................39 Loading of PC ....................................................................23 TRISA Register ..........................................................39 Low-Voltage ICSP Programming .....................................102 PORTA Register ................................................................13 PORTB ................................................................................8 M Associated Register Summary ..................................44 Master Clear (MCLR) Functions ...................................................................44 MCLR Reset, Normal Operation .....................91, 93, 94 PORTB Register ........................................................43 MCLR Reset, Sleep ........................................91, 93, 94 Pull-up Enable (RBPU Bit) ....................................17, 54 Operation and ESD Protection ...................................92 RB0/INT Edge Select (INTEDG Bit) .....................17, 54 Memory Organization ...........................................................9 RB0/INT Pin, External ................................................97 Data Memory .............................................................10 RB7:RB4 Interrupt-on-Change ..................................97 Program Memory .........................................................9 RB7:RB4 Interrupt-on-Change Enable Microchip Internet Web Site .............................................173 (RBIE Bit) ...........................................................97 MPLAB ASM30 Assembler, Linker, Librarian ..................112 RB7:RB4 Interrupt-on-Change Flag MPLAB Integrated Development (RBIF Bit) ......................................................18, 97 Environment Software ..............................................111 TRISB Register ..........................................................43 MPLAB PM3 Device Programmer ....................................114 PORTB Register ...........................................................13, 15 MPLAB REAL ICE In-Circuit Emulator System ................113 Postscaler, WDT MPLINK Object Linker/MPLIB Object Librarian ...............112 Assignment (PSA Bit) ................................................17 Rate Select (PS2:PS0 Bits) .......................................17 O Power-Down Mode. See Sleep. Opcode Field Descriptions ...............................................103 Power-on Reset (POR) ...............................89, 91, 92, 93, 94 OPTION_REG Register .....................................................15 POR Status (POR Bit) ...............................................22 INTEDG Bit ..........................................................17, 54 Power Control (PCON) Register ................................93 PS2:PS0 Bits .............................................................17 Power-Down (PD Bit) .................................................91 PSA Bit .......................................................................17 Time-out (TO Bit) ..................................................16, 91 RBPU Bit ..............................................................17, 54 Power-up Timer (PWRT) ..............................................89, 92 T0CS Bit .....................................................................17 PR2 Register .....................................................................63 T0SE Bit .....................................................................17 Prescaler, Timer0 Oscillator Configuration ......................................................33 Assignment (PSA Bit) ................................................17 ECIO ..........................................................................33 Rate Select (PS2:PS0 Bits) .......................................17 EXTCLK .....................................................................93 Program Counter EXTRC .......................................................................93 Reset Conditions .......................................................93 HS ........................................................................33, 93 INTIO1 .......................................................................33 INTIO2 .......................................................................33 INTRC ........................................................................93 LP .........................................................................33, 93 RC ........................................................................33, 35  2001-2013 Microchip Technology Inc. DS39598F-page 169

PIC16F818/819 Program Memory Revision History ...............................................................165 Interrupt Vector ............................................................9 RP0 Bit ...............................................................................10 Map and Stack RP1 Bit ...............................................................................10 PIC16F818 ...........................................................9 S PIC16F819 ...........................................................9 Reset Vector ................................................................9 Sales and Support ...........................................................175 Program Verification .........................................................100 SCL Clock ..........................................................................77 PUSH .................................................................................23 Sleep .......................................................................89, 91, 99 Software Simulator (MPLAB SIM) ....................................113 R Special Event Trigger .........................................................87 R/W Bit ...............................................................................77 Special Features of the CPU .............................................89 RA0/AN0 Pin ........................................................................7 Special Function Register Summary ..................................13 RA1/AN1 Pin ........................................................................7 Special Function Registers ................................................13 RA2/AN2/Vref- Pin ...............................................................7 SPI Mode RA3/AN3/Vref+ Pin ..............................................................7 Associated Registers .................................................74 RA4/AN4/T0CKI Pin .............................................................7 Serial Clock ................................................................71 RA5/(MCLR/Vpp Pin ............................................................7 Serial Data In .............................................................71 RA6/OSC2/CLKO Pin ..........................................................7 Serial Data Out ..........................................................71 RA7/OSC1/CLKI Pin ............................................................7 Slave Select ...............................................................71 RB0/INT Pin .........................................................................8 SSP RB1/SDI/SDA Pin .................................................................8 ACK ...........................................................................77 RB2/SDO/CCP1 Pin .............................................................8 I2C RB3/CCP1/PGM Pin ............................................................8 I2C Operation .....................................................76 RB4/SCK/SCL Pin ................................................................8 SSPADD Register ..............................................................14 RB5/SS Pin ..........................................................................8 SSPIF ................................................................................20 RB6/T1OSO/T1CKI/PGC Pin ...............................................8 SSPOV ..............................................................................73 RB7/T1OSI/PGD Pin ............................................................8 SSPOV Bit .........................................................................77 RBIF Bit ..............................................................................43 SSPSTAT Register ............................................................14 RCIO Oscillator Mode ........................................................35 Stack ..................................................................................23 Reader Response ............................................................174 Overflow .....................................................................23 Receive Overflow Indicator Bit, SSPOV .............................73 Underflow ...................................................................23 Register File Map Status Register .............................................................13, 15 PIC16F818 .................................................................11 DC Bit ........................................................................16 PIC16F819 .................................................................12 IRP Bit ........................................................................16 Registers PD Bit .........................................................................91 ADCON0 (A/D Control 0) ...........................................81 TO Bit ....................................................................16, 91 ADCON1 (A/D Control 1) ...........................................82 Z Bit ...........................................................................16 CCP1CON (Capture/Compare/PWM Control 1) ........65 Synchronous Serial Port (SSP) ..........................................71 Configuration Word ....................................................90 Overview ....................................................................71 EECON1 (Data EEPROM Access Control 1) .............26 SPI Mode ...................................................................71 Initialization Conditions (table) ...................................94 Synchronous Serial Port Interrupt ......................................20 INTCON (Interrupt Control) ........................................18 T OPTION_REG (Option) ........................................17, 54 OSCCON (Oscillator Control) ....................................38 T1CKPS0 Bit ......................................................................57 OSCTUNE (Oscillator Tuning) ...................................36 T1CKPS1 Bit ......................................................................57 PCON (Power Control) ...............................................22 T1OSCEN Bit .....................................................................57 PIE1 (Peripheral Interrupt Enable 1) ..........................19 T1SYNC Bit .......................................................................57 PIE2 (Peripheral Interrupt Enable 2) ..........................21 T2CKPS0 Bit ......................................................................64 PIR1 (Peripheral Interrupt Request (Flag) 1) .............20 T2CKPS1 Bit ......................................................................64 PIR2 (Peripheral Interrupt Request (Flag) 2) .............21 Tad .....................................................................................85 SSPCON (Synchronous Serial Port Control 1) ..........73 Time-out Sequence ...........................................................92 SSPSTAT (Synchronous Serial Port Status) .............72 Timer0 ................................................................................53 Status .........................................................................16 Associated Registers .................................................55 T1CON (Timer1 Control) ............................................57 Clock Source Edge Select (T0SE Bit) .......................17 T2CON (Timer2 Control) ............................................64 Clock Source Select (T0CS Bit) .................................17 Reset ............................................................................89, 91 External Clock ............................................................54 Brown-out Reset (BOR). See Brown-out Interrupt .....................................................................53 Reset (BOR). Operation ...................................................................53 MCLR Reset. See MCLR. Overflow Enable (TMR0IE Bit) ...................................18 Power-on Reset (POR). See Power-on Overflow Flag (TMR0IF Bit) .......................................97 Reset (POR). Overflow Interrupt ......................................................97 Reset Conditions for All Registers .............................94 Prescaler ....................................................................54 Reset Conditions for PCON Register .........................93 T0CKI .........................................................................54 Reset Conditions for Program Counter ......................93 Reset Conditions for Status Register .........................93 WDT Reset. See Watchdog Timer (WDT). DS39598F-page 170  2001-2013 Microchip Technology Inc.

PIC16F818/819 Timer1 ................................................................................57 TRISA Register ..................................................................14 Associated Registers .................................................62 TRISB Register .............................................................14, 15 Capacitor Selection ....................................................60 V Counter Operation .....................................................58 Operation ...................................................................57 Vdd Pin ................................................................................8 Operation in Asynchronous Counter Mode ................59 Vss Pin .................................................................................8 Operation in Synchronized Counter Mode .................58 W Operation in Timer Mode ...........................................58 Oscillator ....................................................................60 Wake-up from Sleep .....................................................89, 99 Oscillator Layout Considerations ...............................60 Interrupts ..............................................................93, 94 Prescaler ....................................................................61 MCLR Reset ..............................................................94 Resetting Register Pair (TMR1H, TMR1L) .................61 WDT Reset ................................................................94 Resetting Using a CCP Trigger Output ......................61 Wake-up Using Interrupts ..................................................99 TMR1H .......................................................................59 Watchdog Timer (WDT) ................................................89, 98 TMR1L .......................................................................59 Associated Registers .................................................98 Use as a Real-Time Clock .........................................61 Enable (WDTEN Bit) ..................................................98 Timer2 ................................................................................63 INTRC Oscillator ........................................................98 Associated Registers .................................................64 Postscaler. See Postscaler, WDT. Output ........................................................................63 Programming Considerations ....................................98 Postscaler ..................................................................63 Time-out Period .........................................................98 Prescaler ....................................................................63 WDT Reset, Normal Operation .......................91, 93, 94 Prescaler and Postscaler ...........................................63 WDT Reset, Sleep ................................................91, 94 Timing Diagrams WDT Wake-up ...........................................................93 A/D Conversion ........................................................140 WCOL ................................................................................73 Brown-out Reset ......................................................131 Write Collision Detect Bit, WCOL ......................................73 Capture/Compare/PWM (CCP1) ..............................133 WWW Address ................................................................173 CLKO and I/O ..........................................................130 WWW, On-Line Support ......................................................3 External Clock ..........................................................129 I2C Bus Data ............................................................137 I2C Bus Start/Stop Bits .............................................136 I2C Reception (7-Bit Address) ....................................78 I2C Transmission (7-Bit Address) ..............................78 PWM Output ..............................................................68 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ..............................131 Slow Rise Time (MCLR Tied to Vdd Through RC Network) ........................................96 SPI Master Mode .......................................................75 SPI Master Mode (CKE = 0, SMP = 0) ....................134 SPI Master Mode (CKE = 1, SMP = 1) ....................134 SPI Slave Mode (CKE = 0) ................................75, 135 SPI Slave Mode (CKE = 1) ................................75, 135 Time-out Sequence on Power-up (MCLR Tied to Vdd Through Pull-up Resistor) ...............95 Time-out Sequence on Power-up (MCLR Tied to Vdd Through RC Network): Case 1 .......95 Time-out Sequence on Power-up (MCLR Tied to Vdd Through RC Network): Case 2 .......95 Timer0 and Timer1 External Clock ..........................132 Timer1 Incrementing Edge .........................................58 Wake-up from Sleep through Interrupt .....................100 Timing Parameter Symbology ..........................................128 Timing Requirements External Clock ..........................................................129 TMR0 Register ...................................................................15 TMR1CS Bit .......................................................................57 TMR1H Register ................................................................13 TMR1L Register .................................................................13 TMR1ON Bit .......................................................................57 TMR2 Register ...................................................................13 TMR2ON Bit .......................................................................64 TOUTPS0 Bit .....................................................................64 TOUTPS1 Bit .....................................................................64 TOUTPS2 Bit .....................................................................64 TOUTPS3 Bit .....................................................................64  2001-2013 Microchip Technology Inc. DS39598F-page 171

PIC16F818/819 NOTES: DS39598F-page 172  2001-2013 Microchip Technology Inc.

PIC16F818/819 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2001-2013 Microchip Technology Inc. DS39598F-page 173

PIC16F818/819 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16F818/819 Literature Number: DS39598F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39598F-page 174  2001-2013 Microchip Technology Inc.

PIC16F818/819 PIC16F818/819 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16LF818-I/P = Industrial temp., PDIP Range package, Extended VDD limits. b) PIC16F818-I/SO = Industrial temp., SOIC package, normal VDD limits. Device PIC16F818: Standard VDD range PIC16F818T: (Tape and Reel) PIC16LF818: Extended VDD range Temperature Range - = 0°C to +70°C I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package P = PDIP SO = SOIC SS = SSOP ML = QFN Note 1: F = CMOS Flash LF = Low-Power CMOS Flash 2: T = in tape and reel – SOIC, SSOP Pattern QTP, SQTP, ROM Code (factory specified) or packages only. Special Requirements. Blank for OTP and Windowed devices.  2001-2013 Microchip Technology Inc. DS39598F-page 175

PIC16F818/819 NOTES: DS39598F-page 176  2001-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2001-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769393 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2001-2013 Microchip Technology Inc. DS39598F-page 177

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16F818-I/SS PIC16F819-I/P PIC16F819-E/SO PIC16F819-E/SS PIC16F819-E/ML PIC16F818-E/P PIC16F819-E/P PIC16LF819-I/SSG PIC16LF819-I/SOG PIC16F819-I/PG PIC16F819-I/ML PIC16F819-I/SO PIC16F819-I/SS PIC16F818T-E/SS PIC16F818-I/SO PIC16F818-I/ML PIC16LF819T-I/SOG PIC16LF819-I/P PIC16LF819-I/SS PIC16LF819-I/ML PIC16LF819-I/SO PIC16F819T-I/SOG PIC16F818-E/ML PIC16LF818-I/P PIC16F818-E/SO PIC16F818-E/SS PIC16F819T-E/SS PIC16LF818-I/SO PIC16F819T-E/SO PIC16F818T-E/SO PIC16LF818-I/SS PIC16F819-I/SOG PIC16F819-I/SSG PIC16F818T-E/ML PIC16LF818-I/ML PIC16F819T-E/ML PIC16LF818T-I/SO PIC16LF819T-I/SO PIC16LF818T-I/SS PIC16LF819T-I/SS PIC16LF818T-I/ML PIC16LF819T- I/ML PIC16F818-I/P PIC16F818-I/MLTSL PIC16F818-I/PTSL PIC16F818-I/SOTSL PIC16F818-I/SSTSL PIC16F818T-I/MLTSL PIC16F818T-I/SOTSL PIC16F818T-I/SSTSL PIC16F819-I/MLTSL PIC16F819-I/PTSL PIC16F819-I/SOTSL PIC16F819-I/SSTSL PIC16F819T-I/MLTSL PIC16F819T-I/SOTSL PIC16F819T-I/SSTSL PIC16LF818-I/MLTSL PIC16LF818-I/PTSL PIC16LF818-I/SOTSL PIC16LF818-I/SSTSL PIC16LF818T-I/MLTSL PIC16LF818T-I/SOTSL PIC16LF818T-I/SSTSL PIC16LF819-I/MLTSL PIC16LF819-I/PTSL PIC16LF819-I/SOTSL PIC16LF819-I/SSTSL PIC16LF819T-I/MLTSL PIC16LF819T-I/SOTSL PIC16LF819T-I/SSTSL PIC16F818T-I/SS PIC16F819T-I/SO PIC16F818T-I/SO PIC16F819T-I/SS PIC16F819T-I/ML PIC16F818T-I/ML