OPA3691 OPA3691 OPA3691 www.ti.com SBOS227E – DECEMBER 2001 – REVISED JULY 2008 Triple Wideband, Current-Feedback OPERATIONAL AMPLIFIER With Disable FEATURES DESCRIPTION (cid:1) FLEXIBLE SUPPLY RANGE: The OPA3691 sets a new level of performance for broad- +5V to +12V Single-Supply band, triple current-feedback op amps. Operating on a very ±2.5V to ±6V Dual Supply low 5.1mA/ch supply current, the OPA3691 offers a slew (cid:1) UNITY-GAIN STABLE: 280MHz (G = 1) rate and output power normally associated with a much higher supply current. A new output stage architecture (cid:1) HIGH OUTPUT CURRENT: 190mA delivers a high output current with minimal voltage head- (cid:1) OUTPUT VOLTAGE SWING: ±4.0V room and crossover distortion. This gives exceptional single- (cid:1) HIGH SLEW RATE: 2100V/µs supply operation. Using a single +5V supply, the OPA3691 (cid:1) LOW SUPPLY CURRENT: 5.1mA/ch can deliver a 1V to 4V output swing with over 120mA drive (cid:1) LOW DISABLED CURRENT: 150µA/ch current and 150MHz bandwidth. This combination of fea- (cid:1) IMPROVED HIGH-FREQUENCY PINOUT tures makes the OPA3691 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. (cid:1) WIDEBAND +5V OPERATION: 190MHz (G = +2) The OPA3691’s low 5.1mA/ch supply current is precisely APPLICATIONS trimmed at 25°C. This trim, along with low drift over tem- perature, ensures lower maximum supply current than com- (cid:1) RGB AMPLIFIERS peting products. System power may be further reduced by (cid:1) WIDEBAND INA using the optional disable control pin. Leaving this disable (cid:1) BROADBAND VIDEO BUFFERS pin open, or holding it HIGH, gives normal operation. If (cid:1) HIGH-SPEED IMAGING CHANNELS pulled LOW, the OPA3691 supply current drops to less than (cid:1) PORTABLE INSTRUMENTS 150µA/ch while the output goes into a high impedance state. This feature may be used for power savings. (cid:1) ADC BUFFERS (cid:1) ACTIVE FILTERS OPA3691 RELATED PRODUCTS (cid:1) CABLE DRIVERS SINGLES DUALS TRIPLES Voltage-Feedback OPA690 OPA2690 OPA3690 +5V Current-Feedback OPA691 OPA2691 OPA3681 V Fixed Gain OPA692 — OPA3692 1 1/3 OPA3691 250Ω HIGH-SPEED INA FREQUENCY RESPONSE –5V +5V 25 301Ω 10 (V – V) 1/3 1 2 250Ω OPA3691 20 66.5Ω 301Ω 499Ω–5V n (dB) 15 ai G 10 +5V 499Ω 5 1/3 OPA3691 V 2 High-Speed INA (120MHz) 0 –5V 0.1 1 10 100 400 Frequency (MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2001-2008, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Power Supply...............................................................................±6.5V DISCHARGE SENSITIVITY DC Internal Power Dissipation(2) ............................See Thermal Information Differential Input Voltage..................................................................±1.2V Input Voltage Range............................................................................±V This integrated circuit can be damaged by ESD. Texas Instru- S Storage Temperature Range: ID, IDBQ.........................–65°C to +125°C ments recommends that all integrated circuits be handled with Lead Temperature (soldering, 10s).............................................. +300°C appropriate precautions. Failure to observe proper handling Junction Temperature (T )...........................................................+175°C J and installation procedures can cause damage. ESD Resistance: HBM....................................................................2000V CDM...................................................................1500V ESD damage can range from subtle performance degradation MM........................................................................200V to complete device failure. Precision integrated circuits may be NOTES:: (1) Stresses above these ratings may cause permanent damage. more susceptible to damage because very small parametric Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Packages must be derated based on specified θ . changes could cause the device not to meet its published JA Maximum T must be observed. specifications. J PACKAGE/ORDERING INFORMATION(1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY OPA3691 SSOP-16 Surface-Mount DBQ –40°C to +85°C OPA3691 OPA3691IDBQT Tape and Reel, 250 " " " " " OPA3691IDBQR Tape and Reel, 2500 OPA3691 SO-16 Surface-Mount D –40°C to +85°C OPA3691 OPA3691ID Rails, 48 " " " " " OPA3691IDR Tape and Reel, 2500 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. PIN CONFIGURATION Top View SSOP, SO OPA3691 –IN A 1 16 DIS A +IN A 2 15 +V S DIS B 3 14 OUT A –IN B 4 13 –V S +IN B 5 12 OUT B DIS C 6 11 +V S –IN C 7 10 OUT C +IN C 8 9 –V S OPA3691 2 www.ti.com SBOS227E

± ELECTRICAL CHARACTERISTICS: V = 5V S ° Boldface limits are tested at +25 C. R = 402Ω, R = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. F L OPA3691ID, IDBQ TYP MIN/MAX OVER TEMPERATURE 0°C to –40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3) AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth (V = 0.5V ) G = +1, R = 453Ω 280 MHz typ C O PP F G = +2, R = 402Ω 225 200 190 180 MHz min B F G = +5, R = 261Ω 210 MHz typ C F G = +10, R = 180Ω 200 MHz typ C F Bandwidth for 0.1dB Gain Flatness G = +2, V = 0.5V 90 40 35 20 MHz min B O PP Peaking at a Gain of +1 R = 453, V = 0.5V 0.2 1 1.5 2 dB max B F O PP Large-Signal Bandwidth G = +2, V = 5V 200 MHz typ C O PP Slew Rate G = +2, 4V Step 2100 1400 1375 1350 V/µs min B AC PERFORMANCE (Cont.) Rise-and-Fall Time G = +2, V = 0.5V Step 1.6 ns typ C O G = +2, 5V Step 1.9 ns typ C Settling Time to 0.02% G = +2, V = 2V Step 12 ns typ C O 0.1% G = +2, V = 2V Step 8 ns typ C O Harmonic Distortion G = +2, f = 5MHz, V = 2V O PP 2nd-Harmonic R = 100Ω –70 –63 –60 –58 dBc max B L R ≥ 500Ω –79 –70 –67 –65 dBc max B L 3rd-Harmonic R = 100Ω –74 –72 –70 –68 dBc max B L R ≥ 500Ω –93 –87 –82 –78 dBc max B Input Voltage Noise f L> 1MHz 1.7 2.5 2.9 3.1 nV/√Hz max B Noninverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B Inverting Input Current Noise f > 1MHz 15 17 18 19 pA/√Hz max B Differential Gain G = +2, NTSC, V = 1.4V , R = 150Ω 0.07 % typ C O P L R = 37.5Ω 0.17 % typ C L Differential Phase G = +2, NTSC, V = 1.4V , R = 150Ω 0.02 deg typ C O P L R = 37.5Ω 0.07 deg typ C L Crosstalk Input Referred, f = 5MHz, All Hostile –80 dBc typ C DC PERFORMANCE(4) Open-Loop Transimpedance Gain (Z ) V = 0V, R = 100Ω 225 125 110 100 kΩ min A Input Offset Voltage OL O V =L 0V ±0.8 ±3 ±3.7 ±4.3 mV max A CM Average Offset Voltage Drift V = 0V ±12 ±20 µV/°C max B CM Noninverting Input Bias Current V = 0V +15 +35 +43 +45 µA max A CM Average Noninverting Input Bias Current Drift V = 0V –300 –300 nA/°C max B Inverting Input Bias Current VCM = 0V ±5 ±25 ±30 ±40 µA max A CM Average Inverting Input Bias Current Drift V = 0V ±90 ±200 nA°/C max B CM INPUT Common-Mode Input Range(5) ±3.5 ±3.4 ±3.3 ±3.2 V min A Common-Mode Rejection (CMRR) V = 0V 56 52 51 50 dB min A CM Noninverting Input Impedance 100 || 2 kΩ || pF typ C Inverting Input Resistance (R) Open Loop 37 Ω typ C I OUTPUT Voltage Output Swing No Load ±4.0 ±3.8 ±3.7 ±3.6 V min A R = 100Ω ±3.9 ±3.7 ±3.6 ±3.3 V min A L Current Output, Sourcing V = 0 +190 +160 +140 +100 mA min A O Current Output, Sinking V = 0 –190 –160 –140 –100 mA min A O Short-Circuit Current V = 0 ±250 mA typ C O Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ω typ C NOTES: (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit: Junction temperature = ambient +15°C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B)Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V is the input common-mode voltage. CM (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. OPA3691 3 SBOS227E www.ti.com

± ELECTRICAL CHARACTERISTICS: V = 5V (Cont.) S ° Boldface limits are tested at +25 C. R = 402Ω, R = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. F L OPA3691ID, IDBQ TYP MIN/MAX OVER TEMPERATURE 0°C to –40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3) DISABLE (Disabled LOW) Power-Down Supply Current (+V ) V = 0, All Channels –450 –900 –1050 –1200 µA max A S DIS Disable Time V = 1V 400 ns typ C IN DC Enable Time V = 1V 25 ns typ C IN DC Off Isolation G = +2, 5MHz 70 dB typ C Output Capacitance in Disable 4 pF typ C Turn-On Glitch G = +2, R = 150Ω, V = 0 ±50 mV typ C L IN Turn-Off Glitch G = +2, R = 150Ω, V = 0 ±20 mV typ C L IN Enable Voltage 3.3 3.5 3.6 3.7 V min A Disable Voltage 1.8 1.7 1.6 1.5 V max A Control Pin Input Bias Current (DIS) V = 0, Each Channel 75 130 150 160 µA max A DIS POWER SUPPLY Specified Operating Voltage ±5 V typ C Maximum Operating Voltage Range ±6 ±6 ±6 V max A Minimum Operating Voltage Range ±2 V min C Max Quiescent Current (3 Channels) V = ±5V 15.3 15.9 16.5 17.1 mA max A S Min Quiescent Current (3 Channels) V = ±5V 15.3 14.7 14.1 13.5 mA min A S Power-Supply Rejection Ratio (–PSRR) Input Referred 58 52 50 49 dB min A TEMPERATURE RANGE Specification: D, DBQ –40 to +85 °C typ C Thermal Resistance, θ JA DBQ SSOP-16 100 °C/W typ C D SO-16 100 °C/W typ C OPA3691 4 www.ti.com SBOS227E

ELECTRICAL CHARACTERISTICS: V = +5V S ° Boldface limits are tested at +25 C. R = 453Ω, R = 100Ω to V /2, and G = +2, (see Figure 2 for AC performance only), unless otherwise noted. F L S OPA3691ID, IDBQ TYP MIN/MAX OVER TEMPERATURE 0°C to –40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3) AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth (V = 0.5V ) G = +1, R = 499Ω 210 MHz typ C O PP F G = +2, R = 453Ω 190 168 160 140 MHz min B F G = +5, R = 340Ω 180 MHz typ C F G = +10, R = 180Ω 155 MHz typ C F Bandwidth for 0.1dB Gain Flatness G = +2, V < 0.5V 90 40 30 25 MHz min B O PP Peaking at a Gain of +1 R = 649Ω, V < 0.5V 0.2 1 2.5 3.0 dB max B F O PP Large-Signal Bandwidth G = +2, V = 2V 210 MHz typ C O PP Slew Rate G = +2, 2V Step 850 600 575 530 V/µs min B Rise-and-Fall Time G = +2, V = 0.5V Step 2.0 ns typ C O G = +2, V = 2V Step 2.3 ns typ C O Settling Time to 0.02% G = +2, V = 2V Step 14 ns typ C O 0.1% G = +2, V = 2V Step 10 ns typ C O Harmonic Distortion G = +2, f = 5MHz, V = 2V O PP 2nd-Harmonic R = 100Ω to V /2 –66 –58 –57 –56 dBc max B L S R ≥ 500Ω to V /2 –73 –65 –63 –62 dBc max B L S 3rd-Harmonic R = 100Ω to V /2 –71 –68 –67 –65 dBc max B L S R ≥ 500Ω to V /2 –77 –72 –70 –69 dBc max B Input Voltage Noise L f > 1MHz S 1.7 2.5 2.9 3.1 nV/√Hz max B Noninverting Input Current Noise f > 1MHz 12 14 15 15 pA/√Hz max B Inverting Input Current Noise f > 1MHz 15 17 18 19 pA/√Hz max B DC PERFORMANCE(4) Open-Loop Transimpedance Gain (Z ) V = V /2, R = 100Ω to V /2 200 100 90 80 kΩ min A Input Offset Voltage OL O S V L = 2.5V S ±0.8 ±3.5 ±4.1 ±4.8 mV max A CM Average Offset Voltage Drift V = 2.5V ±12 ±20 µV/°C max B CM Noninverting Input Bias Current V = 2.5V +20 +40 +46 +56 µA max A CM Average Noninverting Input Bias Current Drift V = 2.5V –250 –250 nA/°C max B Inverting Input Bias Current VCM = 2.5V ±5 ±20 ±25 ±35 µA max A CM Average Inverting Input Bias Current Drift V = 2.5V ±112 ±250 nA/°C max B CM INPUT Least Positive Input Voltage(5) 1.5 1.6 1.7 1.8 V max A Most Positive Input Voltage(5) 3.5 3.4 3.3 3.2 V min A Common-Mode Rejection (CMRR) V = V /2 54 50 49 48 dB min A CM S Noninverting Input Impedance 100 || 2 kΩ || pF typ C Inverting Input Resistance (R) Open Loop 40 Ω typ C I OUTPUT Most Positive Output Voltage No Load 4 3.8 3.7 3.5 V min A R = 100Ω, 2.5V 3.9 3.7 3.6 3.4 V min A L Least Positive Output Voltage No Load 1 1.2 1.3 1.5 V max A R = 100Ω, 2.5V 1.1 1.3 1.4 1.6 V max A L Current Output, Sourcing V = V /2 +160 +120 +100 +80 mA min A O S Current Output, Sinking V = V /2 –160 –120 –100 –80 mA min A O S Short-Circuit Current V = V /2 250 mA typ C O S Closed-Loop Output Impedance G = +2, f = 100kHz 0.03 Ω typ C DISABLE (Disabled LOW) Power-Down Supply Current (+V ) V = 0, All Channels –450 –900 –1050 –1200 µA max A S DIS Off Isolation G = +2, 5MHz 65 dB typ C Output Capacitance in Disable 4 pF typ C Turn-On Glitch G = +2, R = 150Ω, V = V /2 ±50 mV typ C L IN S Turn-Off Glitch G = +2, R = 150Ω, V = V /2 ±20 mV typ C L IN S Enable Voltage 3.3 3.5 3.6 3.7 V min A Disable Voltage 1.8 1.7 1.6 1.5 V max A Control Pin Input Bias Current (DIS) V = 0, Each Channel 75 130 150 160 µA typ C DIS POWER SUPPLY Specified Single-Supply Operating Voltage 5 V typ C Maximum Single-Supply Operating Voltage 12 12 12 V max A Minimum Single-Supply Operating Voltage 4 V min C Max Quiescent Current (3 Channels) V = +5V 13.5 14.4 15.0 15.6 mA max A S Min Quiescent Current (3 Channels) V = +5V 13.5 12.3 12 11.4 mA min A S Power-Supply Rejection Ratio (+PSRR) Input Referred 55 dB typ C TEMPERATURE RANGE Specification: D, DBQ –40 to +85 °C typ C Thermal Resistance, θ JA DBQ SSOP-16 100 °C/W typ C D SO-16 100 °C/W typ C NOTES: (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit: Junction temperature = ambient +15°C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V is the input common-mode CM voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits. OPA3691 5 SBOS227E www.ti.com

± TYPICAL CHARACTERISTICS: V = 5V S T = +25°C, G = +2, and R = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted. A L SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 1 7.0 G = +1, R = 453Ω G = +2, R = 100Ω F L 0 G = +2, 6.5 2Vp-p 1Vp-p div) –1 RF = 402Ω 6.0 dB/ –2 v) 5.5 ormalized Gain (1 ––––3456 G = +5G, R= F+ =1 02,6 R1FΩ = 180Ω Gain (0.5dB/di 5443....0505 4Vp-p N 3.0 7Vp-p –7 2.5 V = 0.5Vp-p O –8 2.0 0 125MHz 250MHz 0 125MHz 250MHz Frequency (25MHz/div) Frequency (25MHz/div) SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE +400 +4 G = +2 G = +2 +300 +3 V = 0.5Vp-p V = 5Vp-p v) O O V/di +200 div) +2 age (100m +1000 oltage (1V/ +10 utput Volt ––120000 Output V ––12 O –300 –3 –400 –4 Time (5ns/div) Time (5ns/div) COMPOSITE VIDEO dG/dP DISABLED FEEDTHROUGH vs FREQUENCY 0.2 –45 0.18 ViIdneo OP+A15/33691 LVoidaedos NWoit hP u1l.l3-DkΩow Pnull-Down ––5505 VDIS = 0 °dG/dP (%/) 00000....1110.16428 402Ω –5O40pP2tiuΩolnl-aDl o1w.3nkΩ ddGG dthrough (5dB/div) –––––6677805050 Reverse 0.06 dP ee –85 F 0.04 –90 dP Forward 0.02 –95 0 –100 1 2 3 4 0.3 1 10 100 Number of 150Ω Loads Frequency (MHz) OPA3691 6 www.ti.com SBOS227E

± TYPICAL CHARACTERISTICS: V = 5V (Cont.) S T = +25°C, G = +2, and R = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted. A L HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE –60 –60 V = 2Vp-p V = 2Vp-p O O –65 f = 5MHz R = 100Ω L Bc) –70 Bc) –65 2nd-Harmonic f = 5MHz ortion (d –75 2nd-Harmonic ortion (d –70 st –80 st Di Di monic –85 3rd-Harmonic monic –75 3rd-Harmonic ar –90 ar H H –80 –95 –100 –85 100 1000 2.5 3 3.5 4 4.5 5 5.5 6 Load Resistance (Ω) Supply Voltage (V) HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 –65 dBc = dB Below Carrier RL = 100Ω 2nd-Harmonic f = 5MHz n (dBc) –60 VROL == 120V0pΩ-p 2nd-Harmonic n (dBc) –70 ortio –70 ortio nic Dist –80 3rd-Harmonic nic Dist –75 3rd-Harmonic o o m m Har –90 Har –80 –100 –85 0.1 1 10 20 0.1 1 5 Frequency (MHz) Output Voltage Swing (Vp-p) HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN –50 –50 VO = 2Vp-p VO = 2Vp-p RL = 100Ω RL = 100Ω n (dBc) –60 f = 5MHz 2nd-Harmonic n (dBc) –60 Rf F= = 5 4M0H2zΩ 2nd-Harmonic o o orti orti Dist –70 Dist –70 onic onic 3rd-Harmonic m 3rd-Harmonic m ar –80 ar –80 H H –90 –90 1 10 1 10 Gain (V/V) Inverting Gain (V/V) OPA3691 7 SBOS227E www.ti.com

± TYPICAL CHARACTERISTICS: V = 5V (Cont.) S T = +25°C, G = +2, and R = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted. A L 2-TONE, 3RD-ORDER INPUT VOLTAGE AND CURRENT NOISE DENSITY INTERMODULATION SPURIOUS 100 –30 dBc = dB below carriers 50MHz Bc) –40 Hz)Hz) Inverting Input Current Noise (15pA/√Hz) el (d 20MHz √Current Noise (pA/√Voltage Noise (nV/ 10 NoVnionlvtaegrtein Ngo Iinspeu (t1 C.7unrVre/n√tH Nz)oise (12pA/√Hz) Order Spurious Lev –––567000 10MHz d- –80 3r Load Power at Matched 50Ω Load 1 –90 100 1k 10k 100k 1M 10M –8 –6 –4 –2 0 2 4 6 8 10 Frequency (Hz) Single-Tone Load Power (dBm) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 70 B) 9 d 60 d ( a 6 o C = 10pF L L 50 e v citi 3 Ω) 40 apa CL = 22pF R (S3200 d Gain to C –03 VIN OPA1/33691 RS VO CL = 47pF 10 alize –6 402Ω CL 1kΩ m 402Ω C = 100pF or 1kΩ is optional. L 0 N –9 1 10 100 1k 0 125MHz 250MHz Capacitive Load (pF) Frequency (25MHz/div) CMRR AND PSRR vs FREQUENCY OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE 65 120 0 Common-Mode Rejection Ratio (dB)Power-Supply Rejection Ratio (dB) 6554433205050505 –PSRR +PSRR CMRR ΩTransimpedance Gain (20dB/div) 10864200000 ∠ ZOL |ZOL| –––––4811200260000 °Transimpedance Phase (40/div) 20 0 –240 1k 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) OPA3691 8 www.ti.com SBOS227E

± TYPICAL CHARACTERISTICS: V = 5V (Cont.) S T = +25°C, G = +2, and R = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted. A L SUPPLY AND OUTPUT CURRENT vs TEMPERATURE OUTPUT VOLTAGE AND CURRENT LIMITATIONS 18 250 5 Output Current Limit Sourcing Output Current 4 1W Internal Power Limit div) 16 200 div) 3 Single Channel A/ Sinking Output Current A/ 2 m m Supply Current (2 1142 Quiesc(aelnl tc Shaunpnpelyl sC)urrent 11550000 Output Current (50 V (V)O –––10123 1005Ω0 ΩLo LLaoodaa2 Ldd5i ΩnLLeiinnee 1W Internal –4 Output Current Limit Power Limit Single Channel 10 0 –5 –50 –25 0 25 50 75 100 125 –300 –250–200–150 –100 –50 0 +50 +100 +150 +200+250 +300 Ambient Temperature (°C) I (mA) O CLOSED-LOOP OUTPUT IMPEDANCE TYPICAL DC DRIFT OVER TEMPERATURE vs FREQUENCY 2 40 10 +5V 1.5 30 e (mV) 1 Noninverting Input Bias Current (IB+) 20 µs (A) Ωe () 1 50Ω OPA1/33691 ZO Input Offset Voltag –00–..5510 BIiansv eCrtuinrrge nInt p(uIBt–) Input Offset 10––01200 Input Bias Current Output Impedanc 0.1 4–052VΩ 402Ω –1.5 Voltage (V ) –30 OS –2 –40 0.01 –50 –25 0 25 50 75 100 125 10k 100k 1M 10M 100M Ambient Temperature (°C) Frequency (Hz) LARGE-SIGNAL DISABLE/ENABLE RESPONSE ALL HOSTILE CROSSTALK 6.0v) –55 di 4.0V/ –60 V/div) VDIS 20.0V (2DIS –65 0m B) –70 0 2.0 d e (4 1.6 alk ( –75 ut Voltag 10..28 Output Voltage Crosst ––8805 p ut 0.4 –90 O V = +1V 0 IN –95 –100 Time (200ns/div) 0.1 1 10 100 Frequency (MHz) OPA3691 9 SBOS227E www.ti.com

TYPICAL CHARACTERISTICS: V = +5V S T = +25°C, G = +2, and R = 100Ω to +2.5V, (see Figure 2 for AC performance only), unless otherwise noted. A L SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 1 7.0 V = 0.5Vp-p 0 G = +1, 6.5 O R = 499Ω v) –1 F 6.0 di malized Gain (1dB/ ––––2345 RGF = = 3 +450,Ω RGF = = 4 +523,Ω Gain (0.5dB/div) 55443.....50505 VO = 2Vp-p Nor ––67 VO = 0.5Vp-p RGF == 1+8100Ω, 32..05 GRL = = + 1200Ω to 2.5V VO = 1Vp-p –8 2.0 0 125MHz 250MHz 0 125MHz 250MHz Frequency (25MHz/div) Frequency (25MHz/div) SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE 2.9 4.1 G = +2 G = +2 2.8 V = 0.5Vp-p 3.7 O V = 2Vp-p v) v) O V/di 2.7 V/di 3.3 m m 0 2.6 0 2.9 0 0 1 4 e ( 2.5 e ( 2.5 g g a a Volt 2.4 Volt 2.1 ut ut p 2.3 p 1.7 ut ut O O 2.2 1.3 2.1 0.9 Time (5ns/div) Time (5ns/div) RECOMMENDED R vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD S 60 B) 9 d d ( 50 a 6 o C = 10pF L L e 40 citiv 3 Ω) apa CL = 47pF R (S 30 n to C 0 +5V CL = 22pF 2100 alized Gai ––36 VI 507.1.6µΩF 880066ΩΩOPA14/3356931Ω RSCL V1OkΩ CL = 100pF orm 405.13µΩF 1kΩ is optional. 0 N –9 1 10 100 1k 0 125MHz 250MHz Capacitive Load (pF) Frequency (25MHz/div) OPA3691 10 www.ti.com SBOS227E

TYPICAL CHARACTERISTICS: V = +5V (Cont.) S T = +25°C, G = +2, and R = 100Ω to +2.5V, (see Figure 2 for AC performance only), unless otherwise noted. A L HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY –60 –50 VO = 2Vp-p VO = 2Vp-p f = 5MHz RL = 100Ω to 2.5V Bc) –65 Bc) –60 d d n ( n ( 2nd-Harmonic o o orti 2nd-Harmonic orti Dist –70 Dist –70 nic nic mo 3rd-Harmonic mo 3rd-Harmonic ar –75 ar –80 H H –80 –90 100 1000 0.1 1 10 20 Resistance (Ω) Frequency (MHz) 2-TONE, 3RD-ORDER HARMONIC DISTORTION vs OUTPUT VOLTAGE INTERMODULATION SPURIOUS –60 –30 R = 100Ω to 2.5V dBc = dB below carriers L c) f = 5MHz 2nd-Harmonic dBc) –40 50MHz n (dB –65 evel ( –50 o L monic Distorti –70 3rd-Harmonic der Spurious –––678000 2100MMHHzz ar –75 Or H d- 3r –90 Load Power at Matched 50Ω Load –80 –100 0.1 1 3 –14 –12 –10 –8 –6 –4 –2 0 2 Output Voltage Swing (Vp-p) Single-Tone Load Power (dBm) OPA3691 11 SBOS227E www.ti.com

APPLICATIONS INFORMATION capacitor is included between the two power-supply pins. In practical PC board layouts, this optionally added capacitor WIDEBAND CURRENT-FEEDBACK OPERATION will typically improve the 2nd-harmonic distortion perfor- The OPA3691 gives the exceptional AC performance of a mance by 3dB to 6dB. wideband current-feedback op amp with a highly linear, high- Figure 2 shows the AC-coupled, gain of +2, single-supply power output stage. Requiring only 5.1mA/ch quiescent circuit configuration used as the basis of the +5V Specifica- current, the OPA3691 will swing to within 1V of either supply tions and Typical Characteristics. Though not a rail-to-rail rail and deliver in excess of 160mA at room temperature. design, the OPA3691 requires minimal input and output This low output headroom requirement, along with supply voltage headroom compared to other very wideband current- voltage independent biasing, gives remarkable single (+5V) feedback op amps. It will deliver a 3Vp-p output swing on a supply operation. The OPA3691 will deliver greater than single +5V supply with greater than 150MHz bandwidth. The 200MHz bandwidth driving a 2Vp-p output into 100Ω on a key requirement of broadband single-supply operation is to single +5V supply. Previous boosted output stage amplifiers maintain input and output signal swings within the usable have typically suffered from very poor crossover distortion as voltage ranges at both the input and the output. The circuit of the output current goes through zero. The OPA3691 achieves Figure 2 establishes an input midpoint bias using a simple a comparable power gain with much better linearity. The resistive divider from the +5V supply (two 806Ω resistors). primary advantage of a current-feedback op amp over a The input signal is then AC-coupled into this midpoint voltage voltage-feedback op amp is that AC performance (bandwidth bias. The input voltage can swing to within 1.5V of either and distortion) is relatively independent of signal gain. supply pin, giving a 2Vp-p input signal range centered be- Figure 1 shows the DC-coupled, gain of +2, dual power- tween the supply pins. The input impedance matching resis- supply circuit configuration used as the basis of the ±5V tor (57.6Ω) used for testing is adjusted to give a 50Ω input Electrical Characteristics and Typical Characteristics. For match when the parallel combination of the biasing divider test purposes, the input impedance is set to 50Ω with a network is included. The gain resistor (RG) is AC-coupled, resistor to ground and the output impedance is set to 50Ω giving the circuit a DC gain of +1, which puts the input DC bias with a series output resistor. Voltage swings reported in the voltage (2.5V) on the output as well. Again, on a single +5V electrical characteristics are taken directly at the input and supply, the output voltage can swing to within 1V of either output pins while load powers (dBm) are defined at a matched supply pin while delivering more than 120mA output current. 50Ω load. For the circuit of Figure 1, the total effective load A demanding 100Ω load to a midpoint bias is used in this will be 100Ω || 998Ω. The disable control line (DIS) is characterization circuit. The new output stage used in the typically left open to ensure normal amplifier operation. One OPA3691 can deliver large bipolar output currents into this optional component is included in Figure 1. In addition to the midpoint load with minimal crossover distortion, as shown by usual power-supply decoupling capacitors to ground, a 0.01µF the +5V supply, 3rd-harmonic distortion plots. +5V +V +5V 0.1µF S6.8µF +VS + + 0.1µF 6.8µF 50Ω Source 806Ω DIS 50Ω Load 0.1µF VI 50Ω 1/3 VO 50Ω DIS OPA3691 VI 57.6Ω 806Ω 1/3 VO 100Ω OPA3691 VS/2 0.01µF R R F F 499Ω 499Ω R49G9Ω 49R9GΩ +6.8µF 0.1µF 0.1µF –V S –5V FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica- FIGURE 2. AC-Coupled, G = +2, Single-Supply, Specifica- tion and Test Circuit. tion and Test Circuit. OPA3691 12 www.ti.com SBOS227E

TRIPLE ADC BUFFER CHANNEL WIDEBAND RGB MULTIPLEXER The OPAx691 family is ideally suited to single-supply, The OPA3691 is ideally suited to implementing a simple, wideband ADC driving. A current-feedback op amp is ideal very wideband, 2x1 RGB multiplexer. This simple wired-OR where high gains with high bandwidths are required. The video multiplexer can be easily implemented using the circuit wide 3Vp-p output swing with over 150MHz full-power band- shown in Figure 4. width on a single +5V supply is well suited to the This circuit uses two OPA3691s where each package accepts 2Vp-p input range commonly required from modern CMOS the three RGB component video signals from one of two pipelined ADCs. Three channels of very high-speed digitizer possible sources. Each noninverting input is terminated in 75Ω channels are shown in Figure 3 using the OPA3691 driving three ADS831s (8-bit, 80MSPS CMOS converters). Each input is AC-coupled into a 50Ω gain resistor that also will act +5V as a 50Ω impedance match at high frequencies. The amplifier’s V DIS inputs and outputs are centered on the ADC common-mode +5V Power-supply decoupling not shown. input voltage by tying each converter’s V to the noninverting CM U1 inputs of the amplifier. This V acts as the swing midpoint CM R1 for the input to the converter. Since the ADS831 can operate 1/3 82.5Ω 75Ω OPA3691 VOUT Red with differential inputs, driving into the IN input will give a net noninverting signal channel even with the amplifiers operat- 75Ω Line ing at an inverting gain of –6. The other input to the ADS831 340Ω 402Ω is tied to this V as well to give an input signal midpoint CM equal to V . The 300Ω feedback resistor will be the output CM load in this configuration. Harmonic distortion for the OPA3691 G1 will not degrade the converter’s SFDR performance in this 75Ω OPA1/33691 82.5Ω VOUT Green application. 75Ω Line 340Ω 402Ω Power-supply +5V decoupling not shown. 300Ω IN B1 VCM 75Ω OPA1/33691 82.5Ω VOUT Blue 0.1µF 1/3 22Ω ADS831 75Ω Line OPA3691 IN 8-Bit 340Ω 402Ω 80MSPS 47pF –5V 0.1µF 50Ω 300Ω +5V V 1 U2 R2 300Ω IN 1/3 82.5Ω VCM 75Ω OPA3691 0.1µF 1/3 22Ω ADS831 340Ω 402Ω OPA3691 IN 8-Bit 80MSPS 47pF G2 0.1µF 50Ω 300Ω 1/3 82.5Ω V 75Ω OPA3691 1 300Ω IN 340Ω 402Ω V CM 0.1µF 1/3 22Ω ADS831 OPA3691 IN 8-Bit B2 1/3 82.5Ω 47pF 80MSPS 75Ω OPA3691 0.1µF 50Ω 300Ω 340Ω 402Ω V 1 –5V FIGURE 3. Triple-Channel ADC Driver. FIGURE 4. Wideband 2x1 RGB Multiplexer. OPA3691 13 SBOS227E www.ti.com

to match the typical video source impedance. The disable The first op amp buffers the video DAC output and the first control is used to switch between channels by feeding a logic filter section from each other. This first filter section provides control line directly to all three V inputs on one package, group delay equalization. The second and third filter sections DIS and its complement to the three V inputs on the other. provide a 6th-order low-pass filter response that also com- DIS Since the disable feature is intentionally make-before-break pensates for the DAC’s sin(x)/x response. The filter response (to ensure that the output does not float in transition), each of can be seen in Figure 6. the two possible outputs for the three RGB lines are combined through a limiting resistor. This 82.5Ω resistor limits the current between the two outputs during switching. The feedback and 20 f output network connected on the output slightly attenuates the –3dB signal going out onto the 75Ω cable. The gain and output 0 matching resistors (82.5Ω) have been slightly increased to get –20 a signal gain of +1 to the matched load and provide a 75Ω output impedance to the cable. The section on Disable Opera- B) –40 d tion shows the turn-on and turn-off switching glitches, using a n ( grounded input for the single channel, is typically less than Gai –60 ±50mV. Where two outputs are switched (see Figure 4), the –80 output line is always under the control of one amplifier or the other due to the make-before-break disable timing. In this –100 case, the switching glitches for 0V inputs drops to < 20mV. 0 1 10 100 Large output swing can cause the inactive inverting inputs to Frequency (MHz) turn on degrading distortion. Keep the voltages across the inactive channel inputs < ±1.2Vp-p. FIGURE 6. DAC Reconstruction Filter Response. VIDEO DAC RECONSTRUCTION FILTER HIGH-POWER XDSL LINE DRIVER Wideband current-feedback op amps make ideal elements Emerging broadband access technologies are making sig- for implementing high-speed active filters where the amplifier nificant demands on the output stage drivers. Some of the is used as fixed gain block inside a passive RC circuit higher frequency versions, particularly in VDSL, require pas- network. Their relatively constant bandwidth versus gain sive bandpass filters to spectrally isolate the upstream from provides low interaction between the actual filter poles and downstream frequency bands. See Figure 7 for one possible the required gain for the amplifier. Figure 5 shows an ex- implementation of this using single-ended filters and giving ample of a video Digital-to-Analog Converter (DAC) recon- differential push/pull drive into a transformer. The DAC out- struction filter. put from the Analog Front End (AFE) typically requires isolation from the complex filter impedance. The first stage The delay-equalized filter in Figure 5 compensates for the provides a tunable gain (using R ) with a fixed termination for DAC’s sin(x)/x response, and minimizes aliasing artifacts. It G is designed for single +5V operation, with a 13.5MSPS DAC sampling rate, and a 5.5MHz cutoff frequency. 100pF 100pF +5V Video In 100µF 402Ω 402Ω 97.6Ω 237Ω 402Ω +5V 82.5Ω 243Ω 412Ω 1/3 +5V 220pF 56pF OPA3691 1/3 75.5Ω 220pF 56pF OPA3691 VO 1/3 120pF OPA3691 402Ω 402Ω 953Ω 402Ω +5V 100µF 953Ω FIGURE 5. Filter Schematic. OPA3691 14 www.ti.com SBOS227E

the DAC, R . It is very useful from a distortion standpoint to wideband current-feedback op amp, in the OPA3691 will give T scale the characteristic impedance up for the filter. This lower CMRR at DC than using a voltage-feedback part, but reduces the loading at the 1st-stage amplifier output, typi- higher CMRR at higher frequencies. Measured performance, cally improving 3rd-order terms directly, as well as some with no resistor value tuning, gave approximately 75dB at DC improvement in 2nd-order terms. Figure 7 assumes a 100Ω and > 55dB CMRR (input referred) through 10MHz. To characteristic impedance for the filter. The filter is driven from maintain good distortion performance for the input stage a 100Ω source resistor into a 100Ω load that is formed by the amplifiers, the loading at each output has been matched input gain resistor of the inverting amplifier channel. The while achieving the gain of 1 and differential characteristic of other noninverting input is isolated by a series 50Ω resistor— the output stage. To improve DC CMRR, tune the resistor to principally to isolate that input from the out-of-band source ground at the noninverting input of the output stage amplifier. impedance of the filter. In this example, the output stage is set up for a differential gain of 8. The total gain from the WIDEBAND PROGRAMMABLE GAIN output of the bandpass filter to the line will be 4 • n, where n By tying all three inputs together from a single source, and all is the turns ratio used in the transformer. Very broad band- three outputs together to drive a common load, a very widths at high power levels are possible using the OPA3691 wideband, programmable gain function may be implemented. in the circuit of Figure 7. Recognize also, that the output is in See Figure 8 for an example of this application where the fact bandlimited by the filter. Very high dynamic range is three channels have been set up for gains of 1, 2, and 4 to possible inside the filter bandwidth due to the significant the load. The feedback resistor value has been optimized for performance margin provided by the OPA3691. maximum flat bandwidth in each channel. This will give an almost constant > 200MHz bandwidth at any of the three gain WIDEBAND DIFFERENTIAL/SINGLE-ENDED AMPLIFIER settings. The desired gain is selected by using the disable The differential amplifier (three amplifier instrumentation to- control lines to choose one of the three possible amplifiers as pology) on the front page of this data sheet shows a common the active channel. Isolation resistors have been optimized to application applied to this triple current-feedback op amp. match the 50Ω load, and will limit the output current if more The two input stage amplifiers are configured for a relatively than one output is on during gain-select transition. The high differential gain of 10. Lowering the feedback resistor isolation resistors have been adjusted for each amplifier such values in this input stage provides 120MHz bandwidth, even that the load impedance sees a matching 50Ω independant at this high gain setting. The signal is applied to the high from the operating amplifier. This, in turn, requires gain impedance, noninverting inputs at the input stage. The differ- matching so that the gains are 1, 2, and 4 to the load. ential gain is set by (1 + 2RF/RG) = 10 using the values shown The 20Ω series resistors on each noninverting input serves on the front page. The third amplifier performs the differen- to isolate the input parasitic capacitance from the source. tial-to-single-ended conversion in a standard single op amp Also, limit the voltage swing across the inputs of the inactive differential stage. This differential stage, built using the 3rd channels to < ±1.2Vp-p. 50Ω 1/3 +5V OPA3691 Supply decoupling not shown. 400Ω RS 1:n DSL AFE 1/3 100Ω RT OPA3691 133Ω RS Bandpass 100Ω 400Ω 400Ω Filter 1/3 –5V OPA3691 R G FIGURE 7. Single-to-Differential xDSL Line Driver. OPA3691 15 SBOS227E www.ti.com

+5V 74HC238 +5V Power-supply D Y0 decoupling not shown. 1 Y D2 Y1 20Ω 2 73.2Ω 1/3 OPA3691 191Ω 365Ω 20Ω VIN 68.1Ω 50Ω Load 1/3 OPA3691 50Ω 61.2Ω 274Ω 20Ω 63.4Ω 1/3 OPA3691 20Ω 182Ω –5V FIGURE 8. Wideband Programmable Gain. DESIGN-IN TOOLS active devices, like the OPA3691, where parasitic capaci- tance and inductance can have a major effect on frequency DEMONSTRATION FIXTURES response. Two printed circuit boards (PCBs) are available to assist in SPICE models will be available through the TI web page or the initial evaluation of circuit performance using the OPA3691 on a disk (call our Applications Department). These models in its two package options. Both of these are offered free of do a good job of predicting small-signal AC and transient charge as unpopulated PCBs, delivered with a user's guide. performance under a wide variety of operating conditions. The summary information for these fixtures is shown in the They do not do as well in predicting the harmonic distortion table below. or differential gain and phase characteristics. These models do not distinguish between the AC performance of different package types. ORDERING LITERATURE PRODUCT PACKAGE NUMBER NUMBER OPA3691IDBQ SSOP-16 DEM-OPA-SSOP-3A SBOU006 OPERATING SUGGESTIONS OPA3691ID SO-16 DEM-OPA-SO-3A SBOU007 SETTING RESISTOR VALUES TO The demonstration fixtures can be requested at the Texas OPTIMIZE BANDWIDTH Instruments web site (www.ti.com) through the OPA3691 A current-feedback op amp like the OPA3691 can hold an product folder. almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. This is SPICE MODELS shown in the Typical Characteristics; the small-signal band- width decreases only slightly with increasing gain. These Computer simulation of circuit performance using SPICE is curves also show that the feedback resistor has been changed often useful when analyzing the performance of analog for each gain setting. The resistor values on the inverting side circuits and systems. This is particularly true for high-speed OPA3691 16 www.ti.com SBOS227E

of the circuit for a current-feedback op amp can be treated as This is written in a loop-gain analysis format where the errors frequency response compensation elements while their ra- arising from a non-infinite open-loop gain are shown in the tios set the signal gain. Figure 9 shows the small-signal denominator. If Z were infinite over all frequencies, the (S) frequency response analysis circuit for the OPA3691. denominator of Equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation 1 determines the frequency response. Equation 2 shows this as the loop-gain equation: VI α RF Z+(RS)ING=LoopGain (2) V If 20 • log(R + NG • R) were drawn on top of the open-loop O F I transimpedance plot, the difference between the two would R I Z(S) iERR be the loop gain at a given frequency. Eventually, Z(S) rolls off to equal the denominator of Equation 2 at which point the i ERR R F loop gain has reduced to 1 (and the curves have intersected). This point of equality is where the amplifier’s closed-loop frequency response, given by Equation 1, will start to roll off R G and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feed- back op amp. The difference here is that the total impedance in the denominator of Equation 2 may be controlled some- FIGURE 9. Current-Feedback Transfer Function Analysis Circuit. what separately from the desired signal gain (or NG). The OPA3691 is internally compensated to give a maximally The key elements of this current-feedback op amp model are: flat frequency response for R = 402Ω at NG = 2 on ±5V α → Buffer gain from the noninverting input to the inverting input F supplies. Evaluating the denominator of Equation 2 (which is RI → Buffer output impedance the feedback transimpedance) gives an optimal target of 476Ω. iERR → Feedback error current signal As the signal gain changes, the contribution of the NG • RI term Z(s) → Frequency dependent open-loop transimpedance in the feedback transimpedance will change, but the total can gain from iERR to VO be held constant by adjusting RF. Equation 3 gives an approxi- The buffer gain is typically very close to 1.00 and is normally mate equation for optimum RF over signal gain: neglected from signal gain considerations. It will, however, set R =476Ω−NGR (3) F I the CMRR for a single op amp differential amplifier configura- As the desired signal gain increases, this equation will tion. For a buffer gain α < 1.0, the CMRR = –20 • log(1 – α)dB. eventually predict a negative R . A somewhat subjective limit F R, the buffer output impedance, is a critical portion of the I to this adjustment can also be set by holding R to a bandwidth control equation. The OPA3691 is typically 37Ω. minimum value of 20Ω. Lower values will load both theG buffer A current-feedback op amp senses an error current in the stage at the input and the output stage if R gets too low— F inverting node (as opposed to a differential input error volt- actually decreasing the bandwidth. Figure 10 shows the age for a voltage-feedback op amp) and passes this on to the recommended R versus NG for both ±5V and a single +5V F output through an internal frequency dependent transimped- operation. The values shown in Figure 10 give a good ance gain. The Typical Characteristics show this open-loop starting point for design where bandwidth optimization is transimpedance response. This is analogous to the open- desired. loop voltage gain curve for a voltage-feedback op amp. Developing the transfer function for the circuit of Figure 9 600 gives Equation 1: 500 VO = α1+RRGF = αNG Ωstor () 400 +5V VI R +R 1+ RF 1+RF +RING Resi 300 F I RG Z(S) ack ±5V Z db 200 (S) (1) e e F   R  100 NG≡1+ F   RG 0 0 5 10 15 20 Noise Gain FIGURE 10. Recommended Feedback Resistor vs Noise Gain. OPA3691 17 SBOS227E www.ti.com

The total impedance going into the inverting input may be impedance since its value, along with the desired gain, will used to adjust the closed-loop signal bandwidth. Inserting a determine a R which may be non-optimal from a frequency F series resistor between the inverting input and the summing response standpoint. The total input impedance for the junction will increase the feedback impedance (denominator source becomes the parallel combination of R and R . G M of Equation 2), decreasing the bandwidth. The internal buffer The second major consideration, touched on in the previous output impedance for the OPA3691 is slightly influenced by paragraph, is that the signal source impedance becomes the source impedance looking out of the noninverting input part of the noise gain equation and will have slight effect on terminal. High source resistors will have the effect of increas- the bandwidth through Equation 1. The values shown in ing RI, decreasing the bandwidth. For those single-supply Figure 11 have accounted for this by slightly decreasing RF applications which develop a midpoint bias at the noninverting (from Figure 1) to re-optimize the bandwidth for the noise input through high valued resistors, the decoupling capacitor gain of Figure 11 (NG = 2.73) In the example of Figure 11, is essential for power-supply ripple rejection, noninverting the R value combines in parallel with the external 50Ω M input noise current shunting, and to minimize the high- source impedance, yielding an effective driving impedance of frequency value for RI in Figure 9. 50Ω || 68.1Ω = 28.8Ω. This impedance is added in series with R for calculating the noise gain—which gives NG = 2.73. G INVERTING AMPLIFIER OPERATION This value, along with the R of Figure 10 and the inverting F input impedance of 37Ω, are inserted into Equation 3 to get Since the OPA3691 is a general-purpose, wideband current- a feedback transimpedance nearly equal to the 476Ω opti- feedback op amp, most of the familiar op amp application mum value. circuits are available to the designer. Those triple op amp applications that require considerable flexibility in the feedback Note that the noninverting input in this bipolar supply invert- element (for example, integrators, transimpedance, and some ing application is connected directly to ground. It is often filters) should consider the unity-gain stable voltage-feedback suggested that an additional resistor be connected to ground OPA3690, since the feedback resistor is the compensation on the noninverting input to achieve bias current error can- element for a current-feedback op amp. Wideband inverting cellation at the output. The input bias currents for a current operation (especially summing) is particularly suited to the feedback op amp are not generally matched in either magni- OPA3691. Figure 11 shows a typical inverting configuration tude or polarity. Connecting a resistor to ground on the where the I/O impedances and signal gain from Figure 1 are noninverting input of the OPA3691 in the circuit of Figure 11 retained in an inverting circuit configuration. will actually provide additional gain for that input’s bias and noise currents, but will not decrease the output DC error since the input bias currents are not matched. +5V OUTPUT CURRENT AND VOLTAGE Power-supply The OPA3691 provides output voltage and current capabili- decoupling not shown. ties that are unsurpassed in a low-cost dual monolithic op DIS 50Ω Load amp. Under no-load conditions at 25°C, the output voltage 1/3 VO 50Ω typically swings closer than 1V to either supply rail; the tested OPA3691 swing limit is within 1.2V of either rail. Into a 15Ω load (the 50Ω Source minimum tested load), it is tested to deliver more than RG RF ±160mA. 187Ω 374Ω VI The specifications described above, though familiar in the R industry, consider voltage and current limits separately. In M 68.1Ω many applications, it is the voltage • current, or V-I product, which is more relevant to circuit operation. Refer to the –5V Output Voltage and Current Limitations plot in the Typical Characteristics. The X- and Y-axes of this graph show the FIGURE 11. Inverting Gain of –2 with Impedance Matching. zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more In the inverting configuration, two key design considerations detailed view of the OPA3691’s output drive capabilities, must be noted. The first is that the gain resistor (RG) noting that the graph is bounded by a Safe Operating Area becomes part of the signal channel input impedance. If input of 1W maximum internal power dissipation. Superimposing impedance matching is desired (which is beneficial when- resistor load lines onto the plot shows that the OPA3691 can ever the signal is coupled through a cable, twisted-pair, long drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the PC board trace or other transmission line conductor), it is output capabilities or the 1W dissipation limit. A 100Ω load normally necessary to add an additional matching resistor to line (the standard test circuit load) shows the full ±3.9V ground. RG by itself is normally not set to the required input output swing capability, as shown in the Electrical Character- istics Table. OPA3691 18 www.ti.com SBOS227E

The minimum specified output voltage and current over operating on a single +5V supply. Generally, until the funda- temperature are set by worst-case simulations at the cold mental signal reaches very high frequency or power levels, the temperature extreme. Only at cold start-up will the output 2nd-harmonic will dominate the distortion with a negligible 3rd- current and voltage decrease to the numbers shown in the harmonic component. Focusing then on the 2nd-harmonic, electrical characteristic tables. As the output transistors de- increasing the load impedance improves distortion directly. liver power, their junction temperatures will increase, de- Remember that the total load includes the feedback network; creasing their V ’s (increasing the available output voltage in the noninverting configuration (see Figure 1), this is the sum BE swing), and increasing their current gains (increasing the of R + R , while in the inverting configuration it is just R . F G F available output current). In steady-state operation, the avail- Also, providing an additional supply decoupling capacitor able output voltage and current will always be greater than (0.01µF) between the supply pins (for bipolar operation) im- that shown in the over-temperature specifications since the proves the 2nd-order distortion slightly (3dB to 6dB). output stage junction temperatures will be higher than the In most op amps, increasing the output voltage swing in- minimum specified operating ambient. creases harmonic distortion directly. The Typical Character- To protect the output stage from accidental shorts to ground istics show the 2nd-harmonic increasing at a little less than and the power supplies, output short-circuit protection is the expected 2x rate while the 3rd-harmonic increases at a included in the OPA3691. This circuit acts to limit the maxi- little less than the expected 3x rate. Where the test power mum source or sink current to approximately 250mA. doubles, the difference between it and the 2nd-harmonic decreases less than the expected 6dB while the difference DRIVING CAPACITIVE LOADS between it and the 3rd-harmonic decreases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order One of the most demanding and yet very common load intermodulation spurious (IM3) response curves. The 3rd- conditions for an op amp is capacitive loading. Often, the order spurious levels are extremely low at low output power capacitive load is the input of an ADC—including additional levels. The output stage continues to hold them low even as external capacitance which may be recommended to im- the fundamental power reaches very high levels. As the prove the ADC linearity. A high-speed, high open-loop gain Typical Characteristics show, the spurious intermodulation amplifier like the OPA3691 can be very susceptible to de- powers do not increase as predicted by a traditional intercept creased stability and closed-loop response peaking when a model. As the fundamental power level increases, the dy- capacitive load is placed directly on the output pin. When the namic range does not decrease significantly. For two tones amplifier’s open-loop output resistance is considered, this centered at 20MHz, with 10dBm/tone into a matched 50Ω capacitive load introduces an additional pole in the signal load (that is, 2Vp-p for each tone at the load, which requires path that can decrease the phase margin. Several external 8Vp-p for the overall 2-tone envelope at the output pin), the solutions to this problem have been suggested. When the Typical Characteristics show 48dBc difference between the primary considerations are frequency response flatness, pulse test-tone power and the 3rd-order intermodulation spurious response fidelity, and/or distortion, the simplest and most levels. This exceptional performance improves further when effective solution is to isolate the capacitive load from the operating at lower frequencies. feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not NOISE PERFORMANCE eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero Wideband current-feedback op amps generally have a higher acts to cancel the phase lag from the capacitive load pole, output noise than comparable voltage-feedback op amps. The thus increasing the phase margin and improving stability. OPA3691 offers an excellent balance between voltage and The Typical Characteristics show the recommended R vs current noise terms to achieve low output noise. The inverting S Capacitive Load and the resulting frequency response at the current noise (15pA/√Hz) is significantly lower than earlier load. Parasitic capacitive loads greater than 2pF can begin to solutions while the input voltage noise (1.7nV/√Hz) is lower degrade the performance of the OPA3691. Long PC board than most unity-gain stable, wideband, voltage-feedback op traces, unmatched cables, and connections to multiple de- amps. This low input voltage noise was achieved at the price vices can easily cause this value to be exceeded. Always of higher noninverting input current noise (12pA/√Hz). As long consider this effect carefully, and add the recommended as the AC source impedance looking out of the noninverting series resistor as close as possible to the OPA3691 output node is less than 100Ω, this current noise will not contribute pin (see Board Layout Guidelines). significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. DISTORTION PERFORMANCE See Figure 12 for the op amp noise analysis model with all the The OPA3691 provides good distortion performance into a noise terms included. In this model, all noise terms are taken 100Ω load on ±5V supplies. Relative to alternative solutions, to be noise voltage or current density terms in either nV/√Hz it provides exceptional performance into lighter loads and/or or pA/√Hz. OPA3691 19 SBOS227E www.ti.com

contribution to the output is ineffective. Evaluating the con- figuration of Figure 1, using worst-case +25°C input offset E NI voltage and the two input bias currents, gives a worst-case 1/3 output offset range equal to: RS IBN OPA3691 EO ± (NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF) where NG = noninverting signal gain ERS = ± (2 • 3.0mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA) R √4kTRS F = ±6mV + 1.75mV ± 10.05mV √4kTRF = –14.3mV → +17.8mV 4kT RG IBI 4kT = 1.6E – 20J RG at 290°K DISABLE OPERATION The OPA3691 provides an optional disable feature that may FIGURE 12. Op Amp Noise Analysis Model. be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin The total output spot noise voltage can be computed as the is left unconnected, the OPA3691 will operate normally. square root of the sum of all squared output noise voltage To disable, the control pin must be asserted low. Figure 13 contributors. Equation 4 shows the general form for the shows a simplified internal circuit for the disable control output noise voltage using the terms shown in Figure 12. feature. (4) EO = (ENI2 +(IBNRS)2 +4kTRS)NG2 +(IBIRF)2 +4kTRFNG +VS Dividing this expression by the noise gain (NG = (1 + R /R )) F G will give the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 5. 15kΩ EN= ENI2 +(IBNRS)2 +4kTRS +IBNIRGF2+ 4kNTGRF (5) Q1 Evaluating these two equations for the OPA3691 circuit and component values (see Figure 1) will give a total output spot noise voltage of 8.08nV/√Hz and a total equivalent input spot 25kΩ 110kΩ noise voltage of 4.04nV/√Hz. This total input-referred spot noise voltage is higher than the 1.7nV/√Hz specification for V IS DIS Control –V the op amp voltage noise alone. This reflects the noise S added to the output by the inverting current noise times the FIGURE 13. Simplified Disable Control Circuit. feedback resistor. If the feedback resistor is reduced in high gain configurations (as suggested previously), the total input- In normal operation, base current to Q1 is provided through referred voltage noise given by Equation 5 will approach just the 110kΩ resistor while the emitter current through the 15kΩ the 1.7nV/√Hz of the op amp itself. For example, going to a resistor sets up a voltage drop that is inadequate to turn on gain of +10 using RF = 182Ω will give a total input referred the two diodes in Q1’s emitter. As V is pulled low, noise of 2.1nV/√Hz. additional current is pulled through the 15DkΩIS resistor eventu- ally turning on these two diodes (≈ 75µA). At this point, any DC ACCURACY AND OFFSET CONTROL further current pulled out of V goes through those diodes DIS holding the emitter-base voltage of Q1 at approximately 0V. A current-feedback op amp like the OPA3691 provides This shuts off the collector current out of Q1, turning the exceptional bandwidth in high gains, giving fast pulse settling amplifier off. The supply current in the disable mode is that but only moderate DC accuracy. The Electrical Characteris- only required to operate the circuit of Figure 13. Additional tics Table shows an input offset voltage comparable to high- circuitry ensures that turn-on time occurs faster than turn-off speed, voltage-feedback amplifiers. However, the two input time (make-before-break). bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effec- When disabled, the output and input nodes go to a high tive with most voltage-feedback op amps, they do not gener- impedance state. If the OPA3691 is operating in a gain of +1, ally reduce the output DC offset for wideband current-feed- this will show a very high impedance (4pF || 1MΩ) at the back op amps. Since the two input bias currents are unre- output and exceptional signal isolation. If operating at a lated in both magnitude and polarity, matching the source gain greater than +1, the total feedback network resistance impedance looking out of each input to reduce their error (R + R ) will appear as the impedance looking back into the F G OPA3691 20 www.ti.com SBOS227E

output, but the circuit will still show very high forward and As a worst-case example, compute the maximum T using an J reverse isolation. If configured as an inverting amplifier, the OPA3691 SO-16 (see the circuit of Figure 1), operating at the input and output will be connected through the feedback maximum specified ambient temperature of +85°C with all network resistance (R + R ) giving relatively poor input to three outputs driving a grounded 20Ω load to +2.5V: F G output isolation. P = 10V • 17.1mA + 3 • [52/(4 • (20Ω || 804Ω))] = 1.13W D One key parameter in disable operation is the output glitch Maximum T = +85°C + (1.13 • 100°C/W) = 198°C J when switching in and out of the disable mode. Figure 14 This absolute worst-case condition exceeds specified maxi- shows these glitches for the circuit of Figure 1 with the input mum junction temperature. Normally this extreme case will signal set to 0V. The glitch waveform at the output pin is not be encountered. Careful attention to internal power plotted along with the DIS pin voltage. dissipation is required and perhaps airflow considered under extreme conditions. 6.0 v) 4.0 V/di BOARD LAYOUT GUIDELINES 2 2.0 (S Achieving optimum performance with a high-frequency am- DI 0.0 V plifier like the OPA3691 requires careful attention to board div) 30 layout parasitics and external component types. Recommen- mV/ 20 dations that will optimize performance include: 10 10 ge ( 0 a) Minimize parasitic capacitance to any AC ground for all olta –10 of the signal I/O pins. Parasitic capacitance on the output and ut V –20 inverting input pins can cause instability: on the noninverting utp input, it can react with the source impedance to cause O –30 Time (20ns/div) unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all FIGURE 14. Disable/Enable Glitch. of the ground and power planes around those pins. Other- wise, ground and power planes should be unbroken else- The transition edge rate (dv/dt) of the DIS control line will where on the board. influence this glitch. For the plot of Figure 14, the edge rate b) Minimize the distance (< 0.25") from the power-supply was reduced until no further reduction in glitch amplitude was pins to high-frequency 0.1µF decoupling capacitors. At the observed. This approximately 1V/ns maximum slew rate may device pins, the ground and power plane layout should not be achieved by adding a simple RC filter into the V pin DIS be in close proximity to the signal I/O pins. Avoid narrow from a higher speed logic line. If extremely fast transition power and ground traces to minimize inductance between logic is used, a 2kΩ series resistor between the logic gate the pins and the decoupling capacitors. The power-supply and the V input pin will provide adequate bandlimiting DIS connections (on pins 4 and 7) should always be decoupled using just the parasitic input capacitance on the V pin DIS with these capacitors. An optional supply decoupling capaci- while still ensuring adequate logic level swing. tor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF THERMAL ANALYSIS to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be Due to the high output power capability of the OPA3691, placed somewhat farther from the device and may be shared heatsinking or forced airflow may be required under extreme among several devices in the same area of the PCB. operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as c) Careful selection and placement of external compo- described below. In no case should the maximum junction nents will preserve the high-frequency performance of temperature be allowed to exceed 175°C. Operating junction the OPA3691. Resistors should be a very low reactance temperature (T ) is given by T + P • θ . The total internal type. Surface-mount resistors work best and allow a tighter J A D JA power dissipation (P ) is the sum of quiescent power (P ) overall layout. Metal-film and carbon composition, axially D DQ and additional power dissipation in the output stage (P ) to leaded resistors can also provide good high-frequency per- DL deliver load power. Quiescent power is simply the specified formance. Again, keep their leads and PCB trace length as no-load supply current times the total supply voltage across short as possible. Never use wirewound type resistors in a the part. P will depend on the required output signal and high-frequency application. Since the output pin and invert- DL load but would, for a grounded resistive load, be at a ing input pin are the most sensitive to parasitic capacitance, maximum when the output is fixed at a voltage equal to 1/2 always position the feedback and series output resistor, if of either supply voltage (for equal bipolar supplies). Under any, as close as possible to the output pin. Other network this condition, P = V 2/(4 • R ) where R includes feedback components, such as noninverting input termination resis- DL S L L network loading. tors, should also be placed close to the package. Where double-side component mounting is allowed, place the feed- Note that it is the power in the output stage and not into the back resistor directly under the package on the other side of load that determines internal power dissipation. the board between the output and inverting input pins. The OPA3691 21 SBOS227E www.ti.com

frequency response is primarily determined by the feedback trace as a capacitive load in this case and set the series resistor value as described previously. Increasing its value resistor value as shown in the plot of R vs Capacitive Load. S will reduce the bandwidth, while decreasing it will give a more This will not preserve signal integrity as well as a doubly- peaked frequency response. The 402Ω feedback resistor terminated line. If the input impedance of the destination used in the typical performance specifications at a gain of +2 device is low, there will be some signal attenuation due to the on ±5V supplies is a good starting point for design. Note that voltage divider formed by the series output into the terminat- a 453Ω feedback resistor, rather than a direct short, is ing impedance. recommended for the unity-gain follower application. A cur- e) Socketing a high-speed part like the OPA3691 is not rent-feedback op amp requires a feedback resistor even in recommended. The additional lead length and pin-to-pin the unity-gain follower configuration to control stability. capacitance introduced by the socket can create an ex- d) Connections to other wideband devices on the board tremely troublesome parasitic network which can make it may be made with short direct traces or through onboard almost impossible to achieve a smooth, stable frequency transmission lines. For short connections, consider the trace response. Best results are obtained by soldering the OPA3691 and the input to the next device as a lumped capacitive load. onto the board. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around INPUT AND ESD PROTECTION them. Estimate the total capacitive load and set R from the S The OPA3691 is built using a very high-speed complemen- plot of Recommended R vs Capacitive Load. Low parasitic S tary bipolar process. The internal junction breakdown volt- capacitive loads (< 5pF) may not need an R since the S ages are relatively low for these very small geometry de- OPA3691 is nominally compensated to operate with a 2pF vices. These breakdowns are reflected in the Absolute Maxi- parasitic load. If a long trace is required, and the 6dB signal mum Ratings table. All device pins have limited ESD protec- loss intrinsic to a doubly-terminated transmission line is tion using internal diodes to the power supplies as shown in acceptable, implement a matched impedance transmission Figure 15. line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout tech- niques). A 50Ω environment is normally not necessary on +V CC board, and in fact, a higher impedance environment will improve distortion as shown in the Distortion vs Load plots. With a characteristic board trace impedance defined based External Internal Pin Circuitry on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA3691 is used as well as a terminating shunt resistor at the input of the –VCC destination device. Remember also that the terminating im- FIGURE 15. Internal ESD Protection. pedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total These diodes provide moderate protection to input overdrive effective impedance should be set to match the trace imped- voltages above the supplies as well. The protection diodes ance. The high output voltage and current capability of the can typically support 30mA continuous current. Where higher OPA3691 allows multiple destination devices to be handled currents are possible (for example, in systems with ±15V as separate transmission lines, each with their own series supply parts driving into the OPA3691), current limiting and shunt terminations. If the 6dB attenuation of a doubly- series resistors should be added into the two inputs. Keep terminated transmission line is unacceptable, a long trace these resistor values as low as possible since high values can be series-terminated at the source end only. Treat the degrade both noise performance and frequency response. OPA3691 22 www.ti.com SBOS227E

Revision History DATE REVISION PAGE SECTION DESCRIPTION Changed Storage Temperature Range from −40°C to +125C to 2 Abs Max Ratings −65°C to +125C. 7/08 E 4, 5 Electrical Characteristics, Added minimum supply voltage. Power Supply 2/07 D 8 Typical Characteristics Changed Closed-Loop Output Impedance vs Frequency plot. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. OPA3691 23 SBOS227E www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA3691ID ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA3691 & no Sb/Br) OPA3691IDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 3691 OPA3691IDBQT ACTIVE SSOP DBQ 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 3691 OPA3691IDBQTG4 ACTIVE SSOP DBQ 16 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 3691 OPA3691IDG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA3691 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA3691IDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA3691IDBQT SSOP DBQ 16 250 180.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA3691IDBQR SSOP DBQ 16 2500 367.0 367.0 35.0 OPA3691IDBQT SSOP DBQ 16 250 210.0 185.0 35.0 PackMaterials-Page2

None

None

None

PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 14X .0250 [0.635] 16 1 2X .189-.197 .175 [4.81-5.00] [4.45] NOTE 3 8 9 16X .008-.012 B .150-.157 [0.21-0.30] .069 MAX [3.81-3.98] [1.75] NOTE 4 .007 [0.17] C A B .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 0 - 8 [0.11-0.25] .016-.035 [0.41-0.88] DETAIL A (.041 ) TYPICAL [1.04] 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com

EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM SEE DETAILS 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 8 9 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL .002 MAX .002 MIN [0.05] [0.05] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 8 9 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated