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  • 型号: OPA2347YZDT
  • 制造商: Texas Instruments
  • 库位|库存: xxxx|xxxx
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OPA2347YZDT产品简介:

ICGOO电子元器件商城为您提供OPA2347YZDT由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 OPA2347YZDT价格参考¥6.26-¥7.15。Texas InstrumentsOPA2347YZDT封装/规格:线性 - 放大器 - 仪表,运算放大器,缓冲器放大器, 通用 放大器 2 电路 满摆幅 8-DSBGA(2.3x1.3)。您可以下载OPA2347YZDT参考资料、Datasheet数据手册功能说明书,资料中有OPA2347YZDT 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
-3db带宽

-

产品目录

集成电路 (IC)半导体

描述

IC OPAMP GP 350KHZ RRO 8DSBGA运算放大器 - 运放 MicroPwr R-R Op Amp

产品分类

Linear - Amplifiers - Instrumentation, OP Amps, Buffer Amps集成电路 - IC

品牌

Texas Instruments

产品手册

http://www.ti.com/litv/sbos167d

产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

放大器 IC,运算放大器 - 运放,Texas Instruments OPA2347YZDT-

数据手册

点击此处下载产品Datasheet

产品型号

OPA2347YZDT

产品种类

运算放大器 - 运放

供应商器件封装

8-DSBGA(2.3x1.3)

共模抑制比—最小值

70 dB

关闭

No Shutdown

其它名称

296-27698-6

包装

Digi-Reel®

压摆率

0.17 V/µs

双重电源电压

2.3 V to 5.5 V

商标

Texas Instruments

增益带宽生成

0.35 MHz

增益带宽积

350kHz

安装类型

表面贴装

安装风格

SMD/SMT

封装

Reel

封装/外壳

8-VFBGA,DSBGA

封装/箱体

DSBGA-8

工作温度

-55°C ~ 125°C

工作电源电压

2.3 V to 5.5 V

工厂包装数量

250

技术

CMOS

放大器类型

通用

最大双重电源电压

5.5 V

最大工作温度

+ 125 C

最小双重电源电压

2.3 V

最小工作温度

- 55 C

标准包装

1

电压-电源,单/双 (±)

2.3 V ~ 5.5 V, ±1.15 V ~ 2.75 V

电压-输入失调

2mV

电流-电源

20µA

电流-输入偏置

0.5pA

电流-输出/通道

17mA

电源电流

20 uA

电路数

2

系列

OPA2347

设计资源

http://www.digikey.com/product-highlights/cn/zh/texas-instruments-webench-design-center/3176

转换速度

0.17 V/us

输入偏压电流—最大

10 pA

输入参考电压噪声

60 nV

输入补偿电压

6 mV

输出电流

17 mA

输出类型

满摆幅

通道数量

2 Channel

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PDF Datasheet 数据手册内容提取

OPA347 OPA2347 OPA347 OPA347® OPA347 OPA4347 OPA2347 OPA4347 SBOS167D – NOVEMBER 2000– REVISED JULY 2007 Power, Rail-to-Rail micro Operational Amplifiers FEATURES DESCRIPTION (cid:1) LOW I : 20µA The OPA347 is a microPower, low-cost operational amplifier Q (cid:1) microSIZE PACKAGES: WCSP-8, SC70-5 available in micropackages. The OPA347 (single version) is available in the SC-70 and SOT23-5 packages. The OPA2347 SOT23-5, SOT23-8, and TSSOP-14 (dual version) is available in the SOT23-8 and WCSP-8 (cid:1) HIGH SPEED/POWER RATIO WITH packages. Both are also available in the SO-8. The OPA347 BANDWIDTH: 350kHz is also available in the DIP-8. The OPA4347 (quad) is (cid:1) RAIL-TO-RAIL INPUT AND OUTPUT available in the SO-14 and the TSSOP-14. (cid:1) SINGLE SUPPLY: 2.3V to 5.5V The small size and low power consumption (34µA per chan- nel maximum) of the OPA347 make it ideal for portable and APPLICATIONS battery-powered applications. The input range of the OPA347 extends 200mV beyond the rails, and the output range is (cid:1) PORTABLE EQUIPMENT within 5mV of the rails. The OPA347 also features an (cid:1) BATTERY-POWERED EQUIPMENT excellent speed/power ratio with a bandwidth of 350kHz. (cid:1) 2-WIRE TRANSMITTERS The OPA347 can be operated with a single or dual power supply from 2.3V to 5.5V. All models are specified for (cid:1) SMOKE DETECTORS operation from –55°C to +125°C. (cid:1) CO DETECTORS OPA347 OPA347 Out 1 5 V+ +In 1 5 V+ OPA4347 OPA2347 V– 2 V– 2 (bump side down) Out A 1 14 Out D Not to Scale +In 3 4 –In –In 3 4 Out –In A 2 13 –In D 1 SC70-5 A D Out A 1 8 V+ SOT23-5 +In A 3 12 +In D –In A 2 7 Out B V+ 4 11 V– OPA347 OPA2347 +In A 3 6 –In B +In B 5 10 +In C V– 4 5 +In B NC 1 8 NC Out A 1 8 V+ B C –In B 6 9 –In C –In 2 7 V+ –In A 2 A 7 Out B WCSP-8 Out B 7 8 Out C (top view) +In 3 6 Out +In A 3 B 6 –In B TSSOP-14, SO-14 V– 4 5 NC V– 4 5 +In B SO-8, DIP-8 SOT23-8, SO-8 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2000-2007, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Supply Voltage, V+ to V–...................................................................7.5V DISCHARGE SENSITIVITY Signal Input Terminals, Voltage(2)..................(V–) – 0.5V to (V+) + 0.5V Current(2)....................................................10mA This integrated circuit can be damaged by ESD. Texas Output Short-Circuit(3)..............................................................Continuous Operating Temperature..................................................–65°C to +150°C Instruments recommends that all integrated circuits be handled Storage Temperature.....................................................–65°C to +150°C with appropriate precautions. Failure to observe proper Junction Temperature......................................................................150°C handling and installation procedures can cause damage. NOTES: (1) Stresses above these ratings may cause permanent damage. ESD damage can range from subtle performance degrada- Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only. Functional opera- tion to complete device failure. Precision integrated circuits tion of the device at these conditions, or beyond the specified operating may be more susceptible to damage because very small conditions, is not implied. (2) Input terminals are diode-clamped to the parametric changes could cause the device not to meet its power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current-limited to 10mA or less. (3) Short-circuit to published specifications. ground, one amplifier per package. PACKAGE/ORDERING INFORMATION(1) PACKAGE PACKAGE PRODUCT PACKAGE/LEAD DESIGNATOR MARKING OPA347NA SOT23-5 DBV A47 " " " " OPA347PA DIP-8 P OPA347PA OPA347UA SO-8 D OPA347UA " " " " OPA347SA SC-70 DCK S47 " " " " OPA2347EA SOT23-8 DCN B47 " " " " OPA2347UA SO-8 D OPA2347UA " " " " OPA2347YED WCSP-8 YED YMD CCS " " " " OPA2347YZDR Lead-Free WCSP-8 YZD A9 OPA4347EA TSSOP-14 PW OPA4347EA " " " " OPA4347UA SO-14 D OPA4347UA " " " " NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. OPA347, 2347, 4347 2 www.ti.com SBOS167D

ELECTRICAL CHARACTERISTICS: V = 2.5V to 5.5V S ° ° Boldface limits apply over the specified temperature range, T = –55 C to +125 C. A At T = +25°C, R = 100kΩ connected to V /2 and V = V /2, unless otherwise noted. A L S OUT S OPA347NA, UA, PA, SA OPA2347EA, UA, YED OPA4347EA, UA PARAMETER CONDITION MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage V V = 5.5V, V = (V–) + 0.8V 2 6 mV OS S CM over Temperature 2 7 mV Drift dV /dT 3 µV/°C OS vs Power Supply PSRR V = 2.5V to 5.5V, V < (V+) – 1.7V 60 175 µV/V S CM over Temperature V = 2.5V to 5.5V, V < (V+) – 1.7V 300 µV/V S CM Channel Separation, DC 0.3 µV/V f = 1kHz 128 dB INPUT VOLTAGE RANGE Common-Mode Voltage Range V (V–) – 0.2 (V+) + 0.2 V CM Common-Mode Rejection Ratio CMRR V = 5.5V, (V–) – 0.2V < V < (V+) – 1.7V 70 80 dB S CM over Temperature V = 5.5V, V– < V < (V+) – 1.7V 66 dB S CM Vs = 5.5V, (V–) – 0.2V < V < (V+) + 0.2V 54 70 dB CM over Temperature Vs = 5.5V, V– < V < V+ 48 dB CM INPUT BIAS CURRENT(1) Input Bias Current I ±0.5 ±10 pA b Input Offset Current I ±0.5 ±10 pA OS INPUT IMPEDANCE Differential 1013 || 3 Ω || pF Common-Mode 1013 || 6 Ω || pF NOISE V < (V+) – 1.7V CM Input Voltage Noise, f = 0.1Hz to 10Hz 12 µV PP Input Voltage Noise Density, f = 1kHz e 60 nV/√Hz n Input Current Noise Density, f = 1kHz i 0.7 fA/√Hz n OPEN-LOOP GAIN Open-Loop Voltage Gain A V = 5.5V, R = 100kΩ, 0.015V < V < 5.485V 100 115 dB OL S L O over Temperature V = 5.5V, R = 100kΩ, 0.015V < V < 5.485V 88 dB S L O V = 5.5V, R = 5kΩ, 0.125V < V < 5.375V 100 115 dB S L O over Temperature V = 5.5V, R = 5kΩ, 0.125V < V < 5.375V 88 dB S L O A (SC-70 only) V = 5.5V, R = 5kΩ 0.125V < V < 5.375V 96 115 dB OL S L O OUTPUT Voltage Output Swing from Rail R = 100kΩ, A > 100dB 5 15 mV L OL over Temperature R = 100kΩ, A > 88dB 15 mV L OL R = 5kΩ, A > 100dB 90 125 mV L OL over Temperature R = 5kΩ, A > 88dB 125 mV L OL Short-Circuit Current I ±17 mA SC Capacitive Load Drive C See Typical Characteristics LOAD FREQUENCY RESPONSE C = 100pF L Gain-Bandwidth Product GBW 350 kHz Slew Rate SR G = +1 0.17 V/µs Settling Time, 0.1% t V = 5V, 2V Step, G = +1 21 µs S S 0.01% V = 5V, 2V Step, G = +1 27 µs S Overload Recovery Time V × Gain = V 23 µs IN S POWER SUPPLY Specified Voltage Range V 2.5 5.5 V S Minimum Operating Voltage 2.3 V Minimum Operating Voltage (OPA347SA) 2.4 V Quiescent Current (per amplifier) I I = 0 20 34 µA Q O over Temperature 38 µA TEMPERATURE RANGE Specified Range –55 125 °C Operating Range –65 150 °C Storage Range –65 150 °C Thermal Resistance θ JA SOT23-5 Surface-Mount 200 °C/W SOT23-8 Surface-Mount 150 °C/W SO-8 Surface-Mount 150 °C/W SO-14 Surface-Mount 100 °C/W TSSOP-14 Surface-Mount 100 °C/W DIP-8 100 °C/W SC70-5 Surface-Mount 250 °C/W WCSP 250 °C/W NOTE: (1) Input bias current for the OPA2347YED package is specified in the absence of light. See the Photosensitivity section for further detail. OPA347, 2347, 4347 3 SBOS167D www.ti.com

TYPICAL CHARACTERISTICS At T = +25°C, V = +5V, and R = 100kΩ connected to V /2, unless otherwise noted. A S L S POWER-SUPPLY AND COMMON-MODE OPEN-LOOP GAIN/PHASE vs FREQUENCY REJECTION vs FREQUENCY 100 0 100 80 –30 80 op Gain (dB) 6400 ––6900 °ase () CMRR (dB) 60 PSRR CMRR Lo Ph R, 40 n- 20 –120 R e S Op P 0 –150 20 –20 –180 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY 6 140 V = 5.5V S 5 p) VS = 5.0V dB) 120 e (Vp- 4 ation ( oltag 3 VS = 2.5V epar 100 V S Output 2 hannel 80 C 1 0 60 1k 10k 100k 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) QUIESCENT AND SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 30 25 V+ (V+) – 1 A) 25 20 mA) Sourcing µQuiescent Current ( 2105 IQ 1150 hort-Circuit Current ( Output Voltage (V) (V+) – 22 Sinking 125°C 25°C ––5555°°CC S 1 I SC 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 Supply Voltage (V) Output Current (±mA) OPA347, 2347, 4347 4 www.ti.com SBOS167D

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = +5V, and R = 100kΩ connected to V /2, unless otherwise noted. A S L S OPEN-LOOP GAIN AND POWER-SUPPLY COMMON-MODE REJECTION vs TEMPERATURE REJECTION vs TEMPERATURE 100 130 B) 90 120 ection (d 80 V– < VCM < (V+) – 1.7V dB) 110 AOL Rej R ( mon-Mode 7600 V– < VCM < V+ A, PSROL 10900 PSRR m o 50 80 C 40 70 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) QUIESCENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE 30 25 10k I A) 25 SC 20 mA) A) 1k µQuiescent Current ( 2105 IQ 1150 Short-Circuit Current ( Input Bias Current (p 101001 10 5 0.1 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) OFFSET VOLTAGE DRIFT MAGNITUDE OFFSET VOLTAGE PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION 18 25 Typical production 16 distribution of 14 packaged units. %) 20 mplifiers (%) 11208 of Amplifiers ( 15 nt of A 6 ntage 10 e e erc 4 erc 5 P P 2 0 0 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 Offset Voltage (mV) Offset Voltage Drift (µV/°C) OPA347, 2347, 4347 5 SBOS167D www.ti.com

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = +5V, and R = 100kΩ connected to V /2, unless otherwise noted. A S L S SMALL-SIGNAL OVERSHOOT SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE vs LOAD CAPACITANCE 60 50 G = –1V/V G = ±5V/V R = 100kΩ R = 100kΩ 50 FB FB %) %) 40 hoot ( 40 G = +1V/V hoot ( s s 30 Over 30 RL = 100kΩ Over nal nal 20 g g Small-Si 2100 GRF =B –=1 5Vk/ΩV Small-Si 10 0 0 10 100 1k 10k 10 100 1k 10k Load Capacitance (pF) Load Capacitance (pF) SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE G = +1V/V, R = 100kΩ, C = 100pF G = +1V/V, R = 5kΩ, C = 100pF L L L L v v di di V/ V/ m m 0 0 2 2 10µs/div 10µs/div LARGE-SIGNAL STEP RESPONSE INPUT VOLTAGE AND CURRENT NOISE G = +1V/V, RL = 100kΩ, CL = 100pF SPECTRAL DENSITY vs FREQUENCY 10k 100 √V/Hz) 1k 10 √AHz) 0mV/div Noise (n Noise (f 50 e nt g 100 1.0 e Volta Curr 10 0.1 20µs/div 1 10 100 1k 10k 100k Frequency (Hz) OPA347, 2347, 4347 6 www.ti.com SBOS167D

APPLICATIONS INFORMATION OPERATING VOLTAGE The OPA347 series op amps are fully specified and en- The OPA347 series op amps are unity-gain stable and can sured from 2.5V to 5.5V. In addition, many specifications operate on a single supply, making them highly versatile and apply from –55°C to +125°C. Parameters that vary signifi- easy to use. cantly with operating voltages or temperature are shown in Rail-to-rail input and output swing significantly increases dy- the Typical Characteristics. namic range, especially in low supply applications. Figure 1 shows the input and output waveforms for the OPA347 in RAIL-TO-RAIL INPUT unity-gain configuration. Operation is from V = +5V with a S The input common-mode voltage range of the OPA347 100kΩ load connected to V /2. The input is a 5V sinusoid. S PP series extends 200mV beyond the supply rails. This is Output voltage is approximately 4.995V . PP achieved with a complementary input stage—an N-channel Power-supply pins should be bypassed with 0.01µF ceramic input differential pair in parallel with a P-channel differential capacitors. pair, as shown in Figure 2. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.3V to 200mV above the positive supply, while the P-channel pair is on for inputs from 200mV below the negative supply to G = +1, V = +5V S approximately (V+) – 1.3V. There is a small transition region, Input typically (V+) – 1.5V to (V+) – 1.1V, in which both pairs are 5V on. This 400mV transition region can vary 300mV with process variation. Thus, the transition region (both stages 1V/div on) can range from (V+) – 1.65V to (V+) – 1.25V on the low end, up to (V+) – 1.35V to (V+) – 0.95V on the high end. Within the 400mV transition region PSRR, CMRR, offset voltage, and offset drift may be degraded compared to 0V operation outside this region. For more information on de- Output (inverted on scope) signing with rail-to-rail input op amps, see Figure 3, Design 20µs/div Optimization with Rail-to-Rail Input Op Amps. FIGURE 1. Rail-to-Rail Input and Output. V+ Reference Current VIN+ VIN– VBIAS1 Class AB Control V O Circuitry V BIAS2 V– (Ground) FIGURE 2. Simplified Schematic. OPA347, 2347, 4347 7 SBOS167D www.ti.com

DESIGN OPTIMIZATION WITH RAIL-TO-RAIL INPUT OP AMPS Rail-to-rail op amps can be used in virtually any op amp With a unity-gain buffer, for example, signals will traverse configuration. To achieve optimum performance, how- this transition at approximately 1.3V below the V+ supply ever, applications using these special double-input-stage and may exhibit a small discontinuity at this point. op amps may benefit from consideration of their special The common-mode voltage of the noninverting amplifier behavior. is equal to the input voltage. If the input signal always In many applications, operation remains within the com- remains less than the transition voltage, no discontinuity mon-mode range of only one differential input pair. How- will be created. The closed-loop gain of this configuration ever, some applications exercise the amplifier through the can still produce a rail-to-rail output. transition region of both differential input stages. A small Inverting amplifiers have a constant common-mode volt- discontinuity may occur in this transition. Careful selection age equal to V . If this bias voltage is constant, no B of the circuit configuration, signal levels, and biasing can discontinuity will be created. The bias voltage can gener- often avoid this transition region. ally be chosen to avoid the transition region. Unity-Gain Buffer Noninverting Amplifier Inverting Amplifier V+ V+ V+ V V B IN V V V O O O V V IN IN V B V = V = V V = V V = V CM IN O CM IN CM B FIGURE 3. Design Optimization with Rail-to-Rail Input Op Amps. COMMON-MODE REJECTION The CMRR for the OPA347 is specified in several ways so the best match for a given application may be used. First, the 5.5V CMRR of the device in the common-mode range below the transition region (V < (V+) – 1.7V) is given. This specifica- CM tion is the best indicator of the capability of the device when the application requires use of one of the differential input pairs. Second, the CMRR at V = 5.5V over the entire S common-mode range is specified. 0V –0.5V INPUT VOLTAGE The input common-mode range extends from (V–) – 0.2V to 200µs/div (V+) + 0.2V. For normal operation, inputs should be limited to this range. The absolute maximum input voltage is 500mV FIGURE 4. OPA347—No Phase Inversion with Inputs Greater beyond the supplies. Inputs greater than the input than the Power-Supply Voltage. common-mode range but less than the maximum input voltage, while not valid, will not cause any damage to the op amp. Furthermore, if input current is limited the inputs may go beyond the power supplies without phase inversion, as +5V shown in Figure 4, unlike some other op amps. I OVERLOAD Normally, input currents are 0.4pA. However, large inputs 10mA max (greater than 500mV beyond the supply rails) can cause OPA347 VOUT V excessive current to flow in or out of the input pins. There- IN 5kΩ fore, as well as keeping the input voltage below the maxi- mum rating, it is also important to limit the input current to less than 10mA. This is easily accomplished with an input FIGURE 5. Input Current Protection for Voltages Exceeding resistor, as shown in Figure 5. the Supply Voltage. OPA347, 2347, 4347 8 www.ti.com SBOS167D

RAIL-TO-RAIL OUTPUT load, reducing the resistor values from 100kΩ to 5kΩ de- A class AB output stage with common-source transistors is creases overshoot from 40% to 8% (see the characteristic used to achieve rail-to-rail output. This output stage is ca- curve Small-Signal Overshoot vs Load Capacitance). How- pable of driving 5kΩ loads connected to any potential be- ever, when large-valued resistors can not be avoided, a tween V+ and ground. For light resistive loads (> 100kΩ), the small (4pF to 6pF) capacitor, C , can be inserted in the FB output voltage can typically swing to within 5mV from supply feedback, as shown in Figure 7. This significantly reduces rail. With moderate resistive loads (10kΩ to 50kΩ), the output overshoot by compensating the effect of capacitance, C , IN can swing to within a few tens of millivolts from the supply which includes the amplifier input capacitance and PC board rails while maintaining high open-loop gain (see the typical parasitic capacitance. characteristic Output Voltage Swing vs Output Current). CAPACITIVE LOAD AND STABILITY CFB The OPA347 in a unity-gain configuration can directly drive R up to 250pF pure capacitive load. Increasing the gain en- F hances the amplifier’s ability to drive greater capacitive loads R (see the characteristic curve Small-Signal Overshoot vs V I IN Capacitive Load). In unity-gain configurations, capacitive OPA347 VOUT load drive can be improved by inserting a small (10Ω to 20Ω) CIN resistor, RS, in series with the output, as shown in Figure 6. CL This significantly reduces ringing while maintaining Direct Current (DC) performance for purely capacitive loads. How- ever, if there is a resistive load in parallel with the capacitive FIGURE 7. Adding a Feedback Capacitor In the Unity-Gain load, a voltage divider is created, introducing a DC error at Inverter Configuration Improves Capacitative the output and slightly reducing the output swing. The error Load. introduced is proportional to the ratio R /R , and is generally S L negligible. DRIVING ADCs The OPA347 series op amps are optimized for driving medium-speed sampling Analog-to-Digital Converters (ADCs). V+ The OPA347 op amps buffer the ADC’s input capacitance R and resulting charge injection while providing signal gain. S OPA347 VOUT See Figure 8 for the OPA347 in a basic noninverting configu- VIN 1200ΩΩ to RL CL ration driving the ADS7822. The ADS7822 is a 12-bit, microPower sampling converter in the MSOP-8 package. When used with the low-power, miniature packages of the OPA347, the combination is ideal for space-limited, low- power applications. In this configuration, an RC network at FIGURE 6. Series Resistor in Unity-Gain Buffer Configura- the ADC input can be used to provide for anti-aliasing filter tion Improves Capacitive Load Drive. and charge injection current. See Figure 9 for the OPA2347 driving an ADS7822 in a In unity-gain inverter configuration, phase margin can be speech bandpass filtered data acquisition system. This small, reduced by the reaction between the capacitance at the op low-cost solution provides the necessary amplification and amp input, and the gain setting resistors, thus degrading signal conditioning to interface directly with an electret micro- capacitive load drive. Best performance is achieved by using phone. This circuit will operate with V = 2.7V to 5V with less S small valued resistors. For example, when driving a 500pF than 250µA typical quiescent current. OPA347, 2347, 4347 9 SBOS167D www.ti.com

+5V 0.1µF 0.1µF 8 V+ 1 VREF 7 500Ω DCLOCK +In ADS7822 6 Serial OPA347 D 2 12-Bit ADC OUT Interface VIN –In CS/SHDN 5 3300pF 3 GND 4 V = 0V to 5V for IN 0V to 5V output. NOTE: ADC Input = 0V to V REF RC network filters high-frequency noise. FIGURE 8. OPA347 in Noninverting Configuration Driving ADS7822. V+ = +2.7V to 5V Passband 300Hz to 3kHz R 9 510kΩ R1 R2 R4 1.5kΩ 1MΩ 20kΩ C 3 C1 33pF 1000pF R R 1/2 51k7Ω 1508kΩ VREF 1 8 V+ 7 DCLOCK OPA2347 Electret R3 1/2 +IN ADS7822 6 DOUT Serial Microphone(1) 1MΩ 10R06kΩ C10200pF OPA2347 2–IN 12-Bit A/D 5 CS/SHDN Interface 3 4 NOTE: (1) Electret microphone R G = 100 powered by R1. 20k5Ω GND FIGURE 9. Speech Bandpass Filtered Data Acquisition System. OPA347, 2347, 4347 10 www.ti.com SBOS167D

OPA2347 WCSP PACKAGE OPA2347YED The OPA2347YED and OPA2347YZDR are die-level pack- Top View ages using bump-on-pad technology. The OPA2347YED de- 1 vice has tin-lead balls; the OPA2347YZDR has lead-free balls. Unlike devices that are in plastic packages, these Actual Size: YM Package Marking Code: devices have no molding compound, lead frame, wire bonds, DC YMD = year/month/day Exact Size: C CC = indicates OPA2347YED or leads. Using standard surface-mount assembly procedures, 1.008mm x 2.100mm S A9 = indicates OPA2347YZD the WCSP can be mounted to a printed circuit board without S = for engineering purposes only additional under fill. Figures 10 and 11 detail pinout and (bump side down) package marking. FIGURE 11. Top View Package Marking. OPA2347 PHOTOSENSITIVITY (bump side down) Although the OPA2347YED/YZD package has a protective Not to Scale backside coating that reduces the amount of light exposure 1 Out A 1 8 V+ on the die, unless fully shielded, ambient light will still reach the active region of the device. Input bias current for the –In A 2 7 Out B OPA2347YED/YZD package is specified in the absence of +In A 3 6 –In B light. Depending on the amount of light exposure in a given V– 4 5 +In B application, an increase in bias current, and possible in- creases in offset voltage should be expected. In circuit board WCSP-8 tests under ambient light conditions, a typical increase in bias (top view) current reached 100pA. Flourescent lighting may introduce noise or hum due to their time varying light output. Best practice should include end-product packaging that provides FIGURE 10. Pin Description. shielding from possible light souces during operation. RELIABILITY TESTING To ensure reliability, the OPA2347YED and OPA2347YZDR devices have been verified to successfully pass a series of reliability stress tests. A summary of JEDEC standard reli- ability tests is shown in Table I. TEST CONDITION ACCEPT CRITERIA (ACTUAL) SAMPLE SIZE Temperature Cycle –40°C to 125°C, 1 Cycle/hr, 15 Minute Ramp(1) 10 Minute Dwell 500 (1600) Cycles, R < 1.2X from R 36 0 Drop 50cm 10 (129) Drops, R < 1.2X from R 8 0 Key Push 100 Cycles/min, 5K (6.23K) Cycles, R < 1.2X from R 8 0 1300 µε, Displacement = 2.7mm Max 3 Point Bend Strain Rate 5 mm/min, 85 mm Span R < 1.2X from R 8 0 NOTE: (1) Per IPC9701. TABLE I. Reliability Test Results. OPA347, 2347, 4347 11 SBOS167D www.ti.com

LAND PATTERNS AND ASSEMBLY The recommended land pattern for the OPA2347YED pack- age is detailed in Figure 12 with specifications listed in Table II. The maximum amount of force during assembly should be limited to 30 grams of force per bump. FIGURE 12. Recommended Land Area. SOLDER PAD SOLDER MASK COPPER DEFINITION COPPER PAD OPENING THICKNESS STENCIL OPENING STENCIL THICKNESS Non-Solder Mask 275µm 375µm 1 oz max 275µm X 275µm, sq 125µm Thick Defined (NSMD) (+0.0, –25µm) (+0.0, –25µm) NOTES: (1) Circuit traces from NSMD-defined PWB lands should be less tham 100µm (preferrably = 75µm) wide in the exposed area inside the solder mask opening. Wider trace widths will reduce device stand off and impact reliability. (2) Recommended solder paste is type 3 or type 4. (3) Best reliability results are achieved when the PWB laminate glass transistion temperature is above the operating range of the intended application. (4) For PWB using an Ni/Au surface finish, the gold thickness should be less than 0.5um to avoid solder embrittlement and a reduction in thermal fatigue performance. (5) Solder mask thickness should be less than 20um on top of the copper circuit pattern. (6) Best solder stencil performance will be achieved using laser-cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control. (7) Trace routing away from the WLCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces. TABLE II. Recommended Land Pattern. OPA347, 2347, 4347 12 www.ti.com SBOS167D

PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA2347EA/250 ACTIVE SOT-23 DCN 8 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 B47 & no Sb/Br) OPA2347EA/250G4 ACTIVE SOT-23 DCN 8 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 B47 & no Sb/Br) OPA2347EA/3K ACTIVE SOT-23 DCN 8 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 B47 & no Sb/Br) OPA2347EA/3KG4 ACTIVE SOT-23 DCN 8 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 B47 & no Sb/Br) OPA2347UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 2347UA OPA2347UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 2347UA OPA2347UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 2347UA OPA2347YZDR ACTIVE DSBGA YZD 8 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM (A9, OPA2347) & no Sb/Br) OPA2347YZDT ACTIVE DSBGA YZD 8 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -55 to 125 OPA2347 & no Sb/Br) OPA347NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 A47 & no Sb/Br) OPA347NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 A47 & no Sb/Br) OPA347PA ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU | Call TI N / A for Pkg Type -55 to 125 OPA347PA & no Sb/Br) OPA347PAG4 ACTIVE PDIP P 8 50 Green (RoHS Call TI N / A for Pkg Type -55 to 125 OPA347PA & no Sb/Br) OPA347SA/250 ACTIVE SC70 DCK 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 S47 & no Sb/Br) OPA347SA/3K ACTIVE SC70 DCK 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 S47 & no Sb/Br) OPA347SA/3KG4 ACTIVE SC70 DCK 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 S47 & no Sb/Br) OPA347UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 347UA Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA347UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 347UA OPA347UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 347UA OPA4347EA/250 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 4347EA OPA4347EA/2K5 ACTIVE TSSOP PW 14 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA & no Sb/Br) 4347EA OPA4347UA ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA4347UA & no Sb/Br) OPA4347UA/2K5 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA4347UA & no Sb/Br) OPA4347UA/2K5G4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 OPA4347UA & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA2347EA/250 SOT-23 DCN 8 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA2347EA/3K SOT-23 DCN 8 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA2347UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2347YZDR DSBGA YZD 8 3000 178.0 9.2 1.23 2.27 0.73 4.0 8.0 Q1 OPA2347YZDT DSBGA YZD 8 250 178.0 9.2 1.23 2.27 0.73 4.0 8.0 Q1 OPA347NA/250 SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA347NA/3K SOT-23 DBV 5 3000 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3 OPA347SA/250 SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA347SA/3K SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA347UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4347EA/250 TSSOP PW 14 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4347EA/2K5 TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4347UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA2347EA/250 SOT-23 DCN 8 250 203.0 203.0 35.0 OPA2347EA/3K SOT-23 DCN 8 3000 203.0 203.0 35.0 OPA2347UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA2347YZDR DSBGA YZD 8 3000 220.0 220.0 35.0 OPA2347YZDT DSBGA YZD 8 250 220.0 220.0 35.0 OPA347NA/250 SOT-23 DBV 5 250 445.0 220.0 345.0 OPA347NA/3K SOT-23 DBV 5 3000 445.0 220.0 345.0 OPA347SA/250 SC70 DCK 5 250 203.0 203.0 35.0 OPA347SA/3K SC70 DCK 5 3000 203.0 203.0 35.0 OPA347UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA4347EA/250 TSSOP PW 14 250 210.0 185.0 35.0 OPA4347EA/2K5 TSSOP PW 14 2500 367.0 367.0 35.0 OPA4347UA/2K5 SOIC D 14 2500 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE YZD0008 DSBGA - 0.625 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D C 0.625 MAX SEATING PLANE 0.35 BALL TYP 0.05 C 0.15 SYMM D 1.5 C TYP SYMM D: Max = 2.092 mm, Min =2 .031 mm B E: Max = 0.999 mm, Min =0 .938 mm 0.5 TYP A 0.35 1 2 8X 0.25 0.015 C A B 0.5 TYP 4219545/A 12/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com

EXAMPLE BOARD LAYOUT YZD0008 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.245) 1 2 A (0.5) TYP B SYMM C D SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 30X 0.05 MAX 0.05 MIN METAL UNDER ( 0.245) SOLDER MASK METAL EXPOSED ( 0.245) SOLDER MASK METAL EXPOSED SOLDER MASK OPENING METAL OPENING SOLDER MASK NON-SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4219545/A 12/2018 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com

EXAMPLE STENCIL DESIGN YZD0008 DSBGA - 0.625 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 8X ( 0.25) (R0.05) TYP 1 2 A (0.5) TYP B SYMM METAL TYP C D SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 30X 4219545/A 12/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/D 11/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/D 11/2018 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/D 11/2018 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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