NCV7340 High Speed Low Power CAN Transceiver Description The NCV7340 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical http://onsemi.com bus and may be used in both 12 V and 24 V systems. The transceiver provides differential transmit capability to the bus and differential MARKING DIAGRAM receive capability to the CAN controller. The NCV7340 is a new addition to the CAN high−speed transceiver 8 8 family and is an improved drop−in replacement for the AMIS−42665. NV7340−x Due to the wide common−mode voltage range of the receiver inputs, 1 FALYW (cid:2) (cid:2) the NCV7340 is able to reach outstanding levels of electromagnetic SOIC−8 susceptibility (EMS). Similarly, extremely low electromagnetic CASE 751AZ 1 emission (EME) is achieved by the excellent matching of the output signals. NV7340− = Specific Device Code x = 3 (NCV7340D13R2G) Features = 2 (NCV7340D12R2G) • Compatible with the ISO 11898 Standard (ISO 11898−2, ISO = 4 (NCV7340D14R2G) F = Fab Location Code* 11898−5 and SAE J2284) *For NCV7340D14R2G only • Low Quiescent Current A = Assembly Location • L = Wafer Lot High Speed (up to 1 Mbps) Y = Year • Ideally Suited for 12 V and 24 V Industrial and Automotive W = Work Week Applications (cid:2) = Pb−Free Package • Extremely Low Current Standby Mode with Wakeup via the Bus • Low EME Common−Mode Choke is No Longer Required • PIN ASSIGNMENT Voltage Source via V Pin for Stabilizing the Recessive Bus SPLIT Level (Further EMC Improvement) 1 8 • TxD STB No Disturbance of the Bus Lines with an Un−powered Node 2 7 • Transmit Data (TxD) Dominant Time−out Function GND N CANH • C Thermal Protection 3 V 6 7 • Bus Pins Protected Against Transients in an Automotive VCC 34 CANL 0 4 5 Environment • RxD VSPLIT Bus and V Pins Short−Circuit Proof to Supply Voltage and SPLIT Ground NCV7340DxxR2G • (Top View) Logic Level Inputs Compatible with 3.3 V Devices • Up to 110 Nodes can be Connected to the Same Bus in Function of Topology ORDERING INFORMATION • NCV Prefix for Automotive and Other Applications Requiring See detailed ordering and shipping information in the package Unique Site and Control Change Requirements; AEC−Q100 dimensions section on page 9 of this data sheet. Qualified and PPAP Capable • These are Pb−Free Devices Typical Applications • Automotive • Industrial Networks © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 − Rev. 8 NCV7340/D

NCV7340 Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol Parameter Conditions Min Max Unit VCC Power supply voltage 4.75 5.25 V VSTB DC voltage at pin STB 0 VCC V VTxD DC voltage at pin TxD 0 VCC V VRxD DC voltage at pin RxD 0 VCC V VCANH DC voltage at pin CANH 0 < VCC < 5.25 V; no time limit −50 +50 V VCANL DC voltage at pin CANL 0 < VCC < 5.25 V; no time limit −50 +50 V VSPLIT DC voltage at pin VSPLIT 0 < VCC < 5.25 V; no time limit −40 +40 V VO(dif)(bus_dom) Differential bus output voltage in 42.5 (cid:2) < RLT < 60 (cid:2) 1.5 3 V dominant state CM−range Input common−mode range for Guaranteed differential receiver threshold −35 +35 V comparator and leakage current Cload Load capacitance on IC outputs 15 pF tpd(rec−dom) Propagation delay TxD to RxD See Figure 7 60 230 ns tpd(dom−rec) Propagation delay TxD to RxD See Figure 7 60 245 ns TJ Junction temperature −40 150 °C BLOCK DIAGRAM V CC 3 NCV7340 VCC 7 CANH 1 TxD Thermal VCC Timer shutdown 5 VCC V V SPLIT SPLIT STB 8 Mwaokdeeu &p Driver 6 CANL control control 4 RxD Wakeup COMP Filter 2 GND COMP Figure 1. Block Diagram http://onsemi.com 2

NCV7340 TYPICAL APPLICATION Application Schematics VBAT IN OUT 5V−reg V V CC CC 3 STB RLT=60(cid:2) 8 7 CANH N C CAN RxD V VSPLIT CLT=47nF CAN 4 5 controller 7 BUS 3 4 TxD 0 CANL 1 6 R =60(cid:2) LT 2 GND GND Figure 2. Application Diagram Pin Description TxD 1 8 STB N C GND 2 7 CANH V 7 VCC 3 3 6 CANL 4 0 RxD 4 5 VSPLIT Figure 3. NCV7340 Pin Assignment Table 2. PIN FUNCTION DESCRIPTION Pin Name Description 1 TxD Transmit data input; low input → dominant driver; internal pullup current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter → low output 5 VSPLIT Common−mode stabilization output 6 CANL Low−level CAN bus line (low in dominant mode) 7 CANH High−level CAN bus line (high in dominant mode) 8 STB Standby mode control input http://onsemi.com 3

NCV7340 FUNCTIONAL DESCRIPTION Operating Modes Split Circuit NCV7340 provides two modes of operation as illustrated The V pin is operational only in normal mode. In SPLIT in Table 3. These modes are selectable through pin STB. standby mode this pin is floating. The V can be SPLIT connected as shown in Figure 2 or, if it’s not used, can be left Table 3. OPERATING MODES floating. Its purpose is to provide a stabilized DC voltage of Pin RXD 0.5 x VCC to the bus avoiding possible steps in the Pin common−mode signal therefore reducing EME. These STB Mode Low High unwanted steps could be caused by an un−powered node on Low Normal Bus dominant Bus recessive the network with excessive leakage current from the bus that High Standby Wakeup request No wakeup shifts the recessive voltage from its nominal 0.5 x VCC detected request detected voltage. Normal Mode Wakeup In the normal mode, the transceiver is able to When a valid wakeup (dominant state longer than t ) Wake communicate via the bus lines. The signals are transmitted is received during the standby mode the RxD pin is driven and received to the CAN controller via the pins TxD and low. The wakeup detection is not latched: RxD returns to RxD. The slopes on the bus lines outputs are optimized to High state after twakedr when the bus signal is released back give extremely low EME. to recessive – see Figure 4. Wake−up behavior in case of a permanent dominant − due to, for example, a bus short − Standby Mode represents the only difference between the circuit functional In standby mode both the transmitter and receiver are sub−versions listed in the Ordering Information table. When disabled and a very low−power differential receiver the standby mode is entered while a dominant is present on monitors the bus lines for CAN bus activity. The bus lines the bus, the “unconditioned bus wake−up” versions will are terminated to ground and supply current is reduced to a minimum, typically 10 (cid:3)A. When a wake−up request is signal a bus−wakeup immediately after the state transition (signal RxD in Figure 4). The other version will signal detected by the low−power differential receiver, the signal 1 bus−wakeup only after the initial dominant is released is first filtered and then verified as a valid wake signal after (signal RxD in Figure 4). In this way it’s ensured, that a a time period of t , the RxD pin is driven low by the 2 dwakerd CAN bus can be put to a low−power mode even if the nodes transceiver to inform the controller of the wake−up request. have a level sensitivity to RxD pin and a permanent dominant is present on the bus. >tWake <tWake CANH CANL STB RxD2 (NCV7340−4) RxD1 (NCV7340−2, 3) tdwakerd tdwakedr tWake(RxD) normal standby time Figure 4. NCV7340 Wakeup Behavior Overtemperature Detection dissipation and temperature of the IC is reduced. All other A thermal protection circuit protects the IC from damage IC functions continue to operate. The transmitter off−state by switching off the transmitter if the junction temperature resets when the temperature decreases below the shutdown exceeds a value of approximately 160°C. Because the threshold and pin TxD goes high. The thermal protection transmitter dissipates most of the power, the power circuit is particularly needed when a bus line short circuits. http://onsemi.com 4

NCV7340 TxD Dominant Time−out Function Fail Safe Features A TxD dominant time−out timer circuit prevents the bus A current−limiting circuit protects the transmitter output lines being driven to a permanent dominant state (blocking stage from damage caused by accidental short circuit to all network communication) if pin TxD is forced either positive or negative supply voltage, although power permanently low by a hardware and/or software application dissipation increases during this fault condition. failure. The timer is triggered by a negative edge on pin TxD. The pins CANH and CANL are protected from If the duration of the low−level on pin TxD exceeds the automotive electrical transients (according to ISO 7637; see internal timer value t , the transmitter is disabled, Figure 5). Pins TxD and STB are pulled high internally dom(TxD) driving the bus into a recessive state. The timer is reset by a should the input become disconnected. Pins TxD, STB and positive edge on pin TxD. RxD will be floating, preventing reverse supply should the This TxD dominant time−out time (t ) defines the V supply be removed. dom(TxD) CC minimum possible bit rate to 40 kbps. ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. Table 4. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Min Max Unit VCC Supply voltage −0.3 +6 V VCANH DC voltage at pin CANH 0 < VCC < 5.25 V; no time limit −50 +50 V VCANL DC voltage at pin CANL 0 < VCC < 5.25 V; no time limit −50 +50 V VSPLIT DC voltage at pin VSPLIT 0 < VCC < 5.25 V; no time limit −40 +40 V VTxD DC voltage at pin TxD −0.3 6 V VRxD DC voltage at pin RxD −0.3 6 V VSTB DC voltage at pin STB −0.3 6 V Vesd Electrostatic discharge voltage at all pins Note 1 −6 6 kV Note 2 −500 500 V Electrostatic discharge voltage at CANH and CANL pins Note 3 −12 12 kV Vschaff Transient voltage, see Figure 5 Note 5 −150 100 V Latchup Static latchup at all pins Note 4 120 mA Tstg Storage temperature −55 +150 °C TA Ambient temperature −40 +125 °C TJ Maximum junction temperature −40 +170 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF capacitor through a 1.5 k(cid:2) resistor. 2. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999. 3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 (cid:2) resistor. 4. Static latchup immunity: Static latchup protection level when tested according to EIA/JESD78. 5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Verification by external test house. Table 5. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit R(cid:4)JA_1 Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6) Free air 125 K/W R(cid:4)JA_2 Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7) Free air 75 K/W 6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage. 7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage. http://onsemi.com 5

NCV7340 Table 6. CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = −40 to +150°C; RLT = 60 (cid:2) unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit SUPPLY (Pin VCC) ICC Supply current in normal mode Dominant; VTxD = 0 V 57 75 mA Recessive; VTxD = VCC 7.5 10 ICCS Supply current in standby mode TJ,max = 100°C 10 15 (cid:3)A TRANSMITTER DATA INPUT (Pin TxD) VIH High−level input voltage Output recessive 2.0 − VCC V VIL Low−level input voltage Output dominant −0.3 − +0.8 V IIH High−level input current VTxD = VCC −5 0 +5 (cid:3)A IIL Low−level input current VTxD = 0 V −350 −200 −75 (cid:3)A Ci Input capacitance Not tested − 5.0 10 pF TRANSMITTER MODE SELECT (Pin STB) VIH High−level input voltage Standby mode 2.0 − VCC V VIL Low−level input voltage Normal mode −0.3 − +0.8 V IIH High−level input current VSTB = VCC −5 0 +5 (cid:3)A IIL Low−level input current VSTB = 0 V −10 −4 −1 (cid:3)A Ci Input capacitance Not tested − 5.0 10 pF RECEIVER DATA OUTPUT (Pin RxD) Ioh High−level output current normal mode −1 −0.4 −0.1 mA VRxD = VCC – 0.4 V Iol Low−level output current VRxD = 0.4 V 2 6 12 mA Voh High−level output voltage standby mode VCC – VCC – VCC – V IRxD = −100 (cid:3)A 1.1 0.7 0.4 BUS LINES (Pins CANH and CANL) Vo(reces) (norm) Recessive bus voltage on pins CANH and VTxD = VCC; no load 2.0 2.5 3.0 V CANL normal mode Vo(reces) (stby) Recessive bus voltage on pins CANH and VTxD = VCC; no load −100 0 100 mV CANL standby mode Io(reces) (CANH) Recessive output current at pin CANH −35 V < VCANH < +35 V; −2.5 − +2.5 mA 0 V < VCC < 5.25 V Io(reces) (CANL) Recessive output current at pin CANL −35 V < VCANL < +35 V; −2.5 − +2.5 mA 0 V < VCC < 5.25 V ILI(CANH) Input leakage current to pin CANH VCC = 0 V −10 0 10 (cid:3)A VCANL = VCANH = 5 V ILI(CANL) Input leakage current to pin CANL VCC = 0 V −10 0 10 (cid:3)A VCANL = VCANH = 5 V Vo(dom) (CANH) Dominant output voltage at pin CANH VTxD = 0 V 3.0 3.6 4.25 V Vo(dom) (CANL) Dominant output voltage at pin CANL VTxD = 0 V 0. 5 1.4 1.75 V Vo(dif) (bus_dom) Differential bus output voltage (VCANH − VTxD = 0 V; dominant; 1.5 2.25 3.0 V VCANL) 42.5 (cid:2) < RLT < 60 (cid:2) Vo(dif) (bus_rec) Differential bus output voltage (VCANH − VTxD = VCC; recessive; no −120 0 +50 mV VCANL) load Io(sc) (CANH) Short circuit output current at pin CANH for VCANH = 0 V; VTxD = 0 V −100 −70 −45 mA the NCV7340D13(R2)G Short circuit output current at pin CANH for VCANH = 0 V; VTxD = 0 V −120 −70 −45 mA NCV7340D12(R2)G & NCV7340D14(R2)G http://onsemi.com 6

NCV7340 Table 6. CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = −40 to +150°C; RLT = 60 (cid:2) unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit BUS LINES (Pins CANH and CANL) Io(sc) (CANL) Short circuit output current at pin CANL for VCANL = 36 V; VTxD = 0 V 45 70 100 mA the NCV7340D13(R2)G Short circuit output current at pin CANL for VCANL = 36 V; VTxD = 0 V 45 70 120 mA NCV7340D12(R2)G & NCV7340D14(R2)G Vi(dif) (th) Differential receiver threshold voltage (see −5 V < VCANL < +12 V; 0.5 0.7 0.9 V Figure 6) −5 V < VCANH < +12 V; Vihcm(dif) (th) Differential receiver threshold voltage for −35 V < VCANL < +35 V; 0.40 0.7 1.0 V high common−mode (see Figure 6) −35 V < VCANH < +35 V; Vi(dif) (th)_STDBY Differential receiver threshold voltage in −12 V < VCANL < +12 V; 0.4 0.8 1.15 V standby mode (see Figure 6) −12 V < VCANH < +12 V; Ri(cm) (CANH) Common−mode input resistance at pin 15 26 37 k(cid:2) CANH Ri(cm) (CANL) Common−mode input resistance at pin 15 26 37 k(cid:2) CANL Ri(cm) (m) Matching between pin CANH and pin CANL VCANH = VCANL −0.8 0 +0.8 % common mode input resistance Ri(dif) Differential input resistance 25 50 75 k(cid:2) Ci(CANH) Input capacitance at pin CANH VTxD = VCC; not tested 7.5 20 pF Ci(CANL) Input capacitance at pin CANL VTxD = VCC; not tested 7.5 20 pF Ci(dif) Differential input capacitance VTxD = VCC; not tested 3.75 10 pF COMMON−MODE STABILIZATION (Pin VSPLIT) VSPLIT Reference output voltage at pin VSPLIT Normal mode; 0.3 x − 0.7 x −500 (cid:3)A < ISPLIT < 500 (cid:3)A VCC VCC ISPLIT(i) VSPLIT leakage current Standby mode −5 +5 (cid:3)A ISPLIT(lim) VSPLIT limitation current Normal mode 1.3 5.0 mA THERMAL SHUTDOWN TJ(sd) Shutdown junction temperature junction temperature rising 150 160 185 °C TIMING CHARACTERISTICS (see Figures 7 and 8) td(TxD−BUSon) Delay TxD to bus active Cl = 100 pF between 20 85 135 ns CANH to CANL td(TxD−BUSoff) Delay TxD to bus inactive Cl = 100 pF between 5.0 60 105 ns CANH to CANL td(BUSon−RXD) Delay bus active to RxD Crxd = 15 pF 25 55 105 ns td(BUSoff−RXD) Delay bus inactive to RxD Crxd = 15 pF 30 100 105 ns tpd(rec−dom) Propagation delay TxD to RxD from Cl = 100 pF between 60 230 ns recessive to dominant CANH to CANL td(dom−rec) Propagation delay TxD to RxD from Cl = 100 pF between 60 245 ns dominant to recessive CANH to CANL td(stb−nm) Delay standby mode to normal mode 5.0 7.5 10 (cid:3)s tWake Dominant time for wake−up via bus Vdif(dom) > 1.4 V 0.75 2.5 5.0 (cid:3)s Vdif(dom) > 1.2 V 0.75 3 5.8 (cid:3)s tdwakerd Delay to flag wake event (recessive to Valid bus wake up event, 1.0 3.4 10 (cid:3)s dominant transitions) (See Figure 4) CRxD = 15 pF tdwakedr Delay to flag end of wake event (dominant Valid bus wake up event, 0.5 2.9 6.0 (cid:3)s to recessive transition) (See Figure 4) CRxD = 15 pF tWake(RxD) Minimum pulse width on RxD (See Figure 4) 5 (cid:3)s twake, CRxD = 15 pF 0.5 (cid:3)s tdom(TxD) TxD dominant time for time out VTxD = 0 V 300 650 1000 (cid:3)s http://onsemi.com 7

NCV7340 MEASUREMENT SETUPS AND DEFINITIONS +5 V 100 nF V CC 3 CANH 7 TxD 1 N 1 nF C V Transient V SPLIT 5 7 Generator 3 4 RxD 0 1 nF 4 6 CANL 8 2 15 pF STB GND Figure 5. Test Circuit for Automotive Transients V RxD High Low Hysteresis 0.5 0.9 V i(dif)(hys) Figure 6. Hysteresis of the Receiver +5 V 100 nF V CC 3 CANH 7 TxD 1 N R C LT C V VSPLIT LT 5 7 34 60(cid:2) 100 pF RxD 0 4 6 CANL 8 2 15 pF STB GND Figure 7. Test Circuit for Timing Characteristics http://onsemi.com 8

NCV7340 HIGH TxD LOW CANH CANL dominant V = 0.9V i(dif) V − V 0.5V CANH CANL recessive RxD 0.7 x V 0.3 x V CC CC td(TxD−BUSon) td(TxD−BUSoff) t t d(BUSon−RxD) d(BUSoff−RxD) t t pd(rec−dom) pd(dom−rec) Figure 8. Timing Diagram for AC Characteristics DEVICE ORDERING INFORMATION Temperature Part Number Description Range Package Type Shipping† NCV7340D12G 96 Tube / Tray HS LP CAN Transceiver NCV7340D12R2G (Unconditioned Bus Wakeup) 3000 / Tape & Reel NCV7340D13G EMC Improved SOIC 150 8 (Mate Sn, JEDEC 96 Tube / Tray HS LP CAN Transceiver −40°C to +125°C MS−012) NCV7340D13R2G (Unconditioned Bus Wakeup) (Pb−Free) 3000 / Tape & Reel NCV7340D14G HS LP CAN Transceiver 96 Tube / Tray (Bus Wakeup Inactive in NCV7340D14R2G Case of Bus Fault) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9

NCV7340 PACKAGE DIMENSIONS SOIC 8 CASE 751AZ ISSUE O http://onsemi.com 10

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