MCP4802/4812/4822 8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter with Internal V and SPI Interface REF Features Description • MCP4802: Dual 8-Bit Voltage Output DAC The MCP4802/4812/4822 devices are dual 8-bit, 10-bit • MCP4812: Dual 10-Bit Voltage Output DAC and 12-bit buffered voltage output Digital-to-Analog Converters (DACs), respectively. The devices operate • MCP4822: Dual 12-Bit Voltage Output DAC from a single 2.7V to 5.5V supply with SPI compatible • Rail-to-Rail Output Serial Peripheral Interface. • SPI Interface with 20MHz Clock Support The devices have a high precision internal voltage • Simultaneous Latching of the Dual DACs reference (V = 2.048V). The user can configure the REF with LDAC pin full-scale range of the device to be 2.048V or 4.096V by • Fast Settling Time of 4.5µs setting the Gain Selection Option bit (gain of 1 of 2). • Selectable Unity or 2x Gain Output Each DAC channel can be operated in Active or • 2.048V Internal Voltage Reference Shutdown mode individually by setting the Configuration • 50ppm/°C V Temperature Coefficient register bits. In Shutdown mode, most of the internal REF circuits in the shutdown channel are turned off for power • 2.7V to 5.5V Single-Supply Operation savings and the output amplifier is configured to present • Extended Temperature Range:-40°C to +125°C a known high resistance output load (500ktypical. The devices include double-buffered registers, Applications allowing synchronous updates of two DAC outputs • Set Point or Offset Trimming using the LDAC pin. These devices also incorporate a Power-on Reset (POR) circuit to ensure reliable power- • Sensor Calibration up. • Precision Selectable Voltage Reference The devices utilize a resistive string architecture, with • Portable Instrumentation (Battery-Powered) its inherent advantages of low DNL error, low ratio • Calibration of Optical Communication Devices metric temperature coefficient and fast settling time. These devices are specified over the extended Related Products(1) temperature range (+125°C). The devices provide high accuracy and low noise Voltage DAC No. of performance for consumer and industrial applications P/N Reference Resolution Channels where calibration or compensation of signals (such as (V ) REF temperature, pressure and humidity) are required. MCP4801 8 1 The MCP4802/4812/4822 devices are available in the MCP4811 10 1 PDIP, SOIC and MSOP packages. MCP4821 12 1 Internal Package Types MCP4802 8 2 (2.048V) 8-Pin PDIP, SOIC, MSOP MCP4812 10 2 MCP4822 12 2 VDD 1 8 VOUTA 2 MCP4901 8 1 CS 2 8X 7 VSS MCP4911 10 1 SCK 3 P4 6 VOUTB C MCP4921 12 1 SDI 4 M 5 LDAC External MCP4902 8 2 MCP4802: 8-bit dual DAC MCP4912 10 2 MCP4812: 10-bit dual DAC MCP4922 12 2 MCP4822: 12-bit dual DAC Note1: The products listed here have similar AC/DC performances.  2010-2015 Microchip Technology Inc. DS20002249B-page 1

MCP4802/4812/4822 Block Diagram CS SDI SCK LDAC V DD Power-on Interface Logic Reset V SS Input Input Register A Register B 2.048V V REF DAC DAC A B Register Register String String DAC DAC A B Gain Gain Logic Output Logic Op Amps Output Logic V V OUTA OUTB DS20002249B-page 2  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum CHARACTERISTICS Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those Absolute Maximum Ratings † indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions V ....................................................................... 6.5V DD for extended periods may affect device reliability. All inputs and outputs ..........V – 0.3V to V + 0.3V SS DD Current at Input Pins .........................................±2mA Current at Supply Pins ....................................±50mA Current at Output Pins ....................................±25mA Storage temperature..........................-65°C to +150°C Ambient temp. with power applied.....-55°C to +125°C ESD protection on all pins 4kV (HBM), 400V (MM) Maximum Junction Temperature (T )................+150°C J ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, DD SS REF Output Buffer Gain (G) = 2x, R = 5k to GND, C = 100pF, T = -40 to +85°C. Typical values are at +25°C. L L A Parameters Sym Min Typ Max Units Conditions Power Requirements Input Voltage V 2.7 — 5.5 V DD Input Current I — 415 750 µA All digital inputs are grounded, DD all analog outputs (V ) are OUT unloaded. Code = 0x000h Software Shutdown Current I — 3.3 6 µA SHDN_SW Power-on Reset Threshold V — 2.0 — V POR DC Accuracy MCP4802 Resolution n 8 — — Bits INL Error INL -1 ±0.125 1 LSb DNL DNL -0.5 ±0.1 +0.5 LSb Note1 MCP4812 Resolution n 10 — — Bits INL Error INL -3.5 ±0.5 3.5 LSb DNL DNL -0.5 ±0.1 +0.5 LSb Note1 MCP4822 Resolution n 12 — — Bits INL Error INL -12 ±2 12 LSb DNL DNL -0.75 ±0.2 +0.75 LSb Note1 Offset Error V -1 ±0.02 1 % of FSR Code = 0x000h OS Offset Error Temperature V /°C — 0.16 — ppm/°C -45°C to +25°C OS Coefficient — -0.44 — ppm/°C +25°C to +85°C Gain Error g -2 -0.10 2 % of FSR Code = 0xFFFh, E not including offset error Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested.  2010-2015 Microchip Technology Inc. DS20002249B-page 3

MCP4802/4812/4822 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, DD SS REF Output Buffer Gain (G) = 2x, R = 5k to GND, C = 100pF, T = -40 to +85°C. Typical values are at +25°C. L L A Parameters Sym Min Typ Max Units Conditions Internal Voltage Reference (V ) REF Internal Reference Voltage V 2.008 2.048 2.088 V V when G = 1x and REF OUTA Code = 0xFFFh Temperature Coefficient V /°C — 125 325 ppm/°C -40°C to 0°C REF (Note2) — 0.25 0.65 LSb/°C -40°C to 0°C — 45 160 ppm/°C 0°C to +85°C — 0.09 0.32 LSb/°C 0°C to +85°C Output Noise (V Noise) E — 290 — µV Code = 0xFFFh, G = 1x REF NREF p-p (0.1- 10Hz) Output Noise Density e — 1.2 — µV/Hz Code = 0xFFFh, G = 1x NREF (1kHz) e — 1.0 — µV/Hz Code = 0xFFFh, G = 1x NREF (10kHz) 1/f Corner Frequency f — 400 — Hz CORNER Output Amplifier Output Swing V — 0.01 to — V Accuracy is better than 1LSb for OUT V – 0.04 V = 10mV to (V –40mV) DD OUT DD Phase Margin PM — 66 — Degree C = 400pF, R =  L L (°) Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 15 24 mA SC Settling Time t — 4.5 — µs Within 1/2 LSb of final value from SETTLING 1/4 to 3/4 full-scale range Dynamic Performance (Note2) DAC-to-DAC Crosstalk — <10 — nV-s Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry (0111...1111 to 1000...0000) Digital Feedthrough — <10 — nV-s Analog Crosstalk — <10 — nV-s Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested. DS20002249B-page 4  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, Output Buffer Gain (G) = 2x, DD SS REF R = 5k to GND, C = 100pF. Typical values are at +125°C by characterization or simulation. L L Parameters Sym Min Typ Max Units Conditions Power Requirements Input Voltage V 2.7 — 5.5 V DD Input Current I — 440 — µA All digital inputs are grounded, DD Input Curren all analog outputs (V ) are OUT unloaded. Code = 0x000h. Software Shutdown Current I — 5 — µA SHDN_SW Power-On Reset threshold V — 1.85 — V POR DC Accuracy MCP4802 Resolution n 8 — — Bits INL Error INL — ±0.25 — LSb DNL DNL — ±0.2 — LSb Note1 MCP4812 Resolution n 10 — — Bits INL Error INL — ±1 — LSb DNL DNL — ±0.2 — LSb Note1 MCP4822 Resolution n 12 — — Bits INL Error INL — ±4 — LSb DNL DNL — ±0.25 — LSb Note1 Offset Error V — ±0.02 — % of FSR Code = 0x000h OS Offset Error Temperature V /°C — -5 — ppm/°C +25°C to +125°C OS Coefficient Gain Error g — -0.10 — % of FSR Code = 0xFFFh, E not including offset error Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Internal Voltage Reference (V ) REF Internal Reference Voltage V — 2.048 — V V when G = 1x and REF OUTA Code = 0xFFFh Temperature Coefficient V /°C — 125 — ppm/°C -40°C to 0°C REF (Note2) — 0.25 — LSb/°C -40°C to 0°C — 45 — ppm/°C 0°C to +85°C — 0.09 — LSb/°C 0°C to +85°C Output Noise (V Noise) E — 290 — µV Code = 0xFFFh, G = 1x REF NREF p-p (0.1 – 10Hz) Output Noise Density e — 1.2 — µV/ Hz Code = 0xFFFh, G = 1x NREF  (1kHz) e — 1.0 — µV/ Hz Code = 0xFFFh, G = 1x NREF  (10kHz) 1/f Corner Frequency f — 400 — Hz CORNER Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested.  2010-2015 Microchip Technology Inc. DS20002249B-page 5

MCP4802/4812/4822 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, Output Buffer Gain (G) = 2x, DD SS REF R = 5k to GND, C = 100pF. Typical values are at +125°C by characterization or simulation. L L Parameters Sym Min Typ Max Units Conditions Output Amplifier Output Swing V — 0.01 to — V Accuracy is better than 1LSb OUT V – 0.04 for DD V = 10mV to (V – OUT DD 40mV) Phase Margin PM — 66 — Degree (°) C = 400pF, R =  L L Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 17 — mA SC Settling Time t — 4.5 — µs Within 1/2 LSb of final value SETTLING from 1/4 to 3/4 full-scale range Dynamic Performance (Note2) DAC-to-DAC Crosstalk — <10 — nV-s Major Code Transition — 45 — nV-s 1 LSb change around major Glitch carry (0111...1111 to 1000...0000) Digital Feedthrough — <10 — nV-s Analog Crosstalk — <10 — nV-s Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested. AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, V = 2.7V – 5.5V, T = -40 to +125°C. DD A Typical values are at +25°C. Parameters Sym Min Typ Max Units Conditions Schmitt Trigger High-Level V 0.7V — — V IH DD Input Voltage (All digital input pins) Schmitt Trigger Low-Level V — — 0.2V V IL DD Input Voltage (All digital input pins) Hysteresis of Schmitt Trigger V — 0.05V — V HYS DD Inputs Input Leakage Current I -1 — 1 A LDAC = CS = SDI = SCK = LEAKAGE V or V DD SS Digital Pin Capacitance C , — 10 — pF V = 5.0V, T = +25°C, IN DD A (All inputs/outputs) C f = 1MHz (Note1) OUT CLK Clock Frequency F — — 20 MHz T = +25°C (Note1) CLK A Clock High Time t 15 — — ns Note1 HI Clock Low Time t 15 — — ns Note1 LO CS Fall to First Rising CLK t 40 — — ns Applies only when CS falls with CSSR Edge CLK high. (Note1) Data Input Setup Time t 15 — — ns Note1 SU Data Input Hold Time t 10 — — ns Note1 HD SCK Rise to CS Rise Hold t 15 — — ns Note1 CHS Time Note 1: This parameter is ensured by design and not 100% tested. DS20002249B-page 6  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, V = 2.7V – 5.5V, T = -40 to +125°C. DD A Typical values are at +25°C. Parameters Sym Min Typ Max Units Conditions CS High Time t 15 — — ns Note1 CSH LDAC Pulse Width t 100 — — ns Note1 LD LDAC Setup Time t 40 — — ns Note1 LS SCK Idle Time before CS Fall t 40 — — ns Note1 IDLE Note 1: This parameter is ensured by design and not 100% tested. t CSH CS t IDLE tCSSR tHI tLO tCHS Mode 1,1 SCKMode 0,0 t t SU HD SDI MSb in LSb in LDAC t t LS LD FIGURE 1-1: SPI Input Timing Data. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-MSOP  — 211 — °C/W JA Thermal Resistance, 8L-PDIP  — 90 — °C/W JA Thermal Resistance, 8L-SOIC  — 150 — °C/W JA Note 1: The MCP4802/4812/4822 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause T to exceed the maximum junction temperature J of +150°C.  2010-2015 Microchip Technology Inc. DS20002249B-page 7

MCP4802/4812/4822 NOTES: DS20002249B-page 8  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2x, R = 5k, C = 100pF. A DD SS REF L L 0.3 5 Ambient Temperature 4 0.2 125C 85 25 3 NL (LSB) 0.01 L (LSB) -1012 D -0.1 N I -2 -0.2 -3 -4 -0.3 -5 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Code (Decimal) Code (Decimal) FIGURE 2-1: DNL vs. Code (MCP4822). FIGURE 2-4: INL vs. Code and Temperature (MCP4822). 0.2 2.5 2 0.1 B) S SB) L (L 1.5 L 0 N L ( e I 1 DN olut -0.1 bs 0.5 A -0.2 0 0 1024 2048 3072 4096 -40 -20 0 20 40 60 80 100 120 Code (Decimal) 125C 85C 25C Ambient Temperature (ºC) FIGURE 2-2: DNL vs. Code and FIGURE 2-5: Absolute INL vs. Temperature (MCP4822). Temperature (MCP4822). 0.0766 2 0.0764 B) S 0.0762 0 L L ( 0.076 B) N S D 0.0758 L -2 ute 0.0756 NL ( ol I s 0.0754 -4 b A 0.0752 0.075 -6 -40 -20 0 20 40 60 80 100 120 0 1024 2048 3072 4096 Ambient Temperature (ºC) Code (Decimal) FIGURE 2-3: Absolute DNL vs. FIGURE 2-6: INL vs. Code (MCP4822). Temperature (MCP4822). Note: Single device graph for illustration of 64 code effect.  2010-2015 Microchip Technology Inc. DS20002249B-page 9

MCP4802/4812/4822 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2x, R = 5k, C = 100pF. A DD SS REF L L 0.3 0.6 - 40oC - 40oC 0.5 0.2 0.4 85oC B) 0.1 B) 0.3 S S 0.2 DNL (L -0.10 INL (L 0.01 -0.1 125oC 25oC -0.2 -0.2 +25oC to +125oC -0.3 -0.3 0 32 64 96 128 160 192 224 256 0 128 256 384 512 640 768 896 1024 Code Code FIGURE 2-7: DNL vs. Code and FIGURE 2-10: INL vs. Code and Temperature (MCP4812). Temperature (MCP4802). 2.050 1.5 2.049 1 V) 2.048 0.5 (UT 2.047 85oC VO 2.046 B) 0 ale 2.045 VVDDDD:: 43VV S-0.5 c 2.044 L S VDD: 2.7V L ( -1 ull 2.043 IN-1.5 F 2.042 -2 25oC 2.041 -2.5 - 40oC 2.040 125oC -40 -20 0 20 40 60 80 100 120 -3 Ambient Temperature (°C) 0 128 256 384 512 640 768 896 1024 Code FIGURE 2-11: Full-Scale V vs. OUTA FIGURE 2-8: INL vs. Code and Ambient Temperature and V . Gain = 1x. DD Temperature (MCP4812). 0.15 4.100 Temperature: - 40oC to +125oC 0.1 4.096 V) B) 0.05 (UT4.092 NL (LS 0 34 cale VO4.088 VVDDDD:: 55.V5V D-0.05 ull S 4.084 -0.1 F 4.080 -0.15 4.076 0 32 64 96 128 160 192 224 256 -40 -20 0 20 40 60 80 100 120 Code Ambient Temperature (°C) FIGURE 2-9: DNL vs. Code and FIGURE 2-12: Full-Scale V vs. OUTA Temperature (MCP4802). Ambient Temperature and V . Gain = 2x. DD DS20002249B-page 10  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2x, R = 5k, C = 100pF. A DD SS REF L L 11.E0-004 25 y sit n 20 e D oise Voltage (µV/Hz)11..EE1--100065 Occurrence 1105 ut N 5 p Out 1.0E.-107 0 0 5 0 5 0 5 0 5 0 5 0 5 0 10E.1-1 1E1+0 11E0+1 11E0+02 11Ek+3 11E0+k4 11E00+k5 38 38 39 39 40 40 41 41 42 42 43 43 44 I (µA) Frequency (Hz) DD FIGURE 2-13: Output Noise Voltage FIGURE 2-16: I Histogram (V = 2.7V). DD DD Density (V Noise Density) vs. Frequency. REF Gain = 1x. 22 1.E1-00.20 20 V) 18 m e ( 16 oltag1.E1-.0030 Eni (in VP-P) ence 1124 Noise V1.E0-.0140 Occurr 1680 utput Eni (in VRMS) 24 O 0 Maximum Measurement Time = 10s 1.E0-.0051 5 0 5 0 5 0 5 0 5 0 5 8 9 9 0 0 1 1 2 2 3 3 11E0+02 1E1k+3 11E0+k4 11E00+k5 11EM+6 3 3 3 4 4 I4 (µ4A) 4 4 4 4 Bandwidth (Hz) DD FIGURE 2-14: Output Noise Voltage FIGURE 2-17: I Histogram (V = 5.0V). DD DD (V Noise Voltage) vs. Bandwidth. Gain = 1x. REF 340 5.5V 320 5.0V 4.0V 300 3.0V 2.7V A)280 VDD (µD260 D I240 220 200 180 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) FIGURE 2-15: I vs. Temperature and V . DD DD  2010-2015 Microchip Technology Inc. DS20002249B-page 11

MCP4802/4812/4822 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2x, R = 5k, C = 100pF. A DD SS REF L L 4 5.5V 4 VDD 3.5 5.0V 3.5 5.5V V) 5.0V (µA)N_SW2.53 43..00VV hreshold ( 2.53 4.0V ISHD 2 V2D.7DV Hi TN 2 3.0V 1.5 VI 1.5 2.7V 1 1 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-18: Software Shutdown Current FIGURE 2-21: VIN High Threshold vs. vs. Temperature and VDD. Temperature and VDD. 1.6 0.11 VDD or (%) 00..0079 eshold (V) 111...345 55..50VV Offset Err 000...000135 5V.D5DV V Low ThrIN11..112 4.0V -0.01 5.0V 3.0V 4.0V 0.9 2.7V 3.0V -0.03 2.7V 0.8 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-19: Offset Error vs. Temperature FIGURE 2-22: VIN Low Threshold vs. and VDD. Temperature and VDD. -0.05 -0.1 VDD -0.15 5.5V Error (%) -0--.002..532 4532....0007VVVV n ai -0.35 G -0.4 -0.45 -0.5 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-20: Gain Error vs. Temperature and V . DD DS20002249B-page 12  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2x, R = 5k, C = 100pF. A DD SS REF L L 2.5 16 2.25 VDD 55..50VV steresis (V) 11..127.5525 545...500VVV (mA)ORTED 111345 V432...D007DVVV y H V_ HINSPI 0.07.515 32..07VV IOUT_HI_S 1112 0.25 0 10 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-23: Input Hysteresis vs. FIGURE 2-26: I High Short vs. OUT Temperature and V . Temperature and V . DD DD 0.035 6.0 4.0V 0.033 V) 0.031 5.0 mit (V-Y)(DD 000...000222579 3.0V (V)OUT 34..00 OuVtRpEuFt = S 4h.0o9rt6eVd to VDD Li 0.023 2.7V V 2.0 V OUT_HI 000...000112791 VDD 1.0 Output Shorted to VSS 0.0 0.015 -40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 Ambient Temperature (ºC) IOUT (mA) FIGURE 2-24: V High Limit FIGURE 2-27: I vs. V . Gain = 2x. OUT OUT OUT vs.Temperature and V . DD 0.0028 VDD V) 0.0026 )(S 0.0024 5.5V S AV 0.0022 5.0V Y- 0.0020 mit ( 0.0018 4.0V LiW 0.0016 32..07VV OUT_LO 00..00001124 V 0.0010 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-25: V Low Limit vs. OUT Temperature and V . DD  2010-2015 Microchip Technology Inc. DS20002249B-page 13

MCP4802/4812/4822 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2x, R = 5k, C = 100pF. A DD SS REF L L V OUT V OUT SCK LDAC LDAC Time (1µs/div) Time (1µs/div) FIGURE 2-28: V Rise Time. FIGURE 2-31: V Rise Time. OUT OUT V OUT V OUT SCK SCK LDAC LDAC Time (1µs/div) Time (1µs/div) FIGURE 2-29: V Fall Time. FIGURE 2-32: V Rise Time Exit OUT OUT Shutdown. ) B d n ( o VOUT cti e SCK ej R e pl p Ri LDAC Time (1µs/div) Frequency (Hz) FIGURE 2-30: V Rise Time. FIGURE 2-33: PSRR vs. Frequency. OUT DS20002249B-page 14  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE FOR MCP4802/4812/4822 MCP4802/4812/4822 Symbol Description MSOP, PDIP, SOIC 1 V Supply Voltage Input (2.7V to 5.5V) DD 2 CS Chip Select Input 3 SCK Serial Clock Input 4 SDI Serial Data Input 5 LDAC Synchronization Input. This pin is used to transfer DAC settings (Input Registers) to the output registers (V ) OUT 6 V DAC Output OUTB B 7 V Ground reference point for all circuitry on the device SS 8 V DAC Output OUTA A 3.1 Supply Voltage Pins (V V ) 3.4 Serial Data Input (SDI) DD, SS V is the positive supply voltage input pin. The input SDI is the SPI compatible serial data input pin. DD supply voltage is relative to V and can range from SS 2.7V to 5.5V. The power supply at the VDD pin should 3.5 Latch DAC Input (LDAC) be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass LDAC (latch DAC synchronization input) pin is used to capacitor of about 0.1µF (ceramic) to ground. An transfer the input latch registers to their corresponding additional 10µF capacitor (tantalum) in parallel is also DAC registers (output latches, VOUT). When this pin is recommended to further attenuate high-frequency low, both VOUTA and VOUTB are updated at the same noise present in application boards. time with their input register contents. This pin can be tied to low (V ) if the V update is desired at the V is the analog ground pin and the current return path SS OUT SS rising edge of the CS pin. This pin can be driven by an of the device. The user must connect the V pin to a SS external control device such as an MCU I/O pin. ground plane through a low-impedance connection. If an analog ground path is available in the application 3.6 Analog Outputs (V , V ) Printed Circuit Board (PCB), it is highly recommended OUTA OUTB that the VSS pin be tied to the analog ground path or VOUTA is the DAC A output pin, and VOUTB is the DAC isolated within an analog ground plane of the circuit B output pin. Each output has its own output amplifier. board. The full-scale range of the DAC output is from V toG* V , where G is the gain selection option SS REF 3.2 Chip Select (CS) (1x or 2x). The DAC analog output cannot go higher than the supply voltage (V ). CS is the Chip Select input pin, which requires an DD active-low to enable serial clock and data functions. 3.3 Serial Clock Input (SCK) SCK is the SPI compatible serial clock input pin.  2010-2015 Microchip Technology Inc. DS20002249B-page 15

MCP4802/4812/4822 NOTES: DS20002249B-page 16  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 4.0 GENERAL OVERVIEW 1LSb is the ideal voltage difference between two successive codes. Table4-1 illustrates the LSb The MCP4802, MCP4812 and MCP4822 are dual calculation of each device. voltage output 8-bit, 10-bit and 12-bit DAC devices, respectively. These devices include rail-to-rail output TABLE 4-1: LSb OF EACH DEVICE amplifiers, internal voltage reference, shutdown and Gain reset-management circuitry. The devices use an SPI Device Selection LSb Size serial communication interface and operate with a sin- MCP4802 1x 2.048V/256 = 8 mV gle supply voltage from 2.7V to 5.5V. (n = 8) 2x 4.096V/256 = 16 mV The DAC input coding of these devices is straight MCP4812 1x 2.048V/1024 = 2 mV binary. Equation4-1 shows the DAC analog output voltage calculation. (n = 10) 2x 4.096V/1024 = 4 mV MCP4822 1x 2.048V/4096 = 0.5 mV EQUATION 4-1: ANALOG OUTPUT (n = 12) 2x 4.096V/4096 = 1 mV VOLTAGE (V ) OUT 4.0.1 INL ACCURACY 2.048VD  V = -------------------------------n----G Integral Non-Linearity (INL) error for these devices is OUT 2n the maximum deviation between an actual code transi- tion point and its corresponding ideal transition point Where: once offset and gain errors have been removed. The 2.048V = Internal voltage reference two end points method (from 0x000 to 0xFFF) is used D = DAC input code for the calculation. Figure4-1 shows the details. n G = Gain selection A positive INL error represents transition(s) later than ideal. A negative INL error represents transition(s) = 2 for <GA> bit = 0 earlier than ideal. = 1 for <GA> bit = 1 n = DAC Resolution = 8 for MCP4802 INL < 0 = 10 for MCP4812 111 Actual = 12 for MCP4822 110 Transfer Function 101 The ideal output range of each device is: • MCP4802 (n = 8) Digital 100 Input (a) 0.0V to 255/256 * 2.048V when gain setting=1x. Code 011 Ideal Transfer (b) 0.0V to 255/256 * 4.096V when gainsetting=2x. Function 010 • MCP4812 (n = 10) (a) 0.0V to 1023/1024 * 2.048V when gain setting=1x. 001 (b) 0.0V to 1023/1024 * 4.096V when gainsetting=2x. 000 • MCP4822 (n = 12) INL < 0 (a) 0.0V to 4095/4096 * 2.048V when gain setting=1x. (b) 0.0V to 4095/4096 * 4.096V when gain setting=2x. DAC Output FIGURE 4-1: Example for INL Error. Note: See the output swing voltage specification in Section1.0 “Electrical Characteris- tics”.  2010-2015 Microchip Technology Inc. DS20002249B-page 17

MCP4802/4812/4822 4.0.2 DNL ACCURACY 4.1 Circuit Descriptions A Differential Non-Linearity (DNL) error is the measure 4.1.1 OUTPUT AMPLIFIERS of variations in code widths from the ideal code width. A DNL error of zero indicates that every code is exactly The DAC’s outputs are buffered with a low-power, 1LSb wide. precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section1.0 “Electrical 111 Actual Characteristics” for the analog output voltage range Transfer and load conditions. 110 Function In addition to resistive load-driving capability, the amplifier will also drive high capacitive loads without 101 oscillation. The amplifier’s strong outputs allow V to OUT Digital 100 be used as a programmable voltage reference in a Input Ideal Transfer system. Code 011 Function 4.1.1.1 Programmable Gain Block 010 The rail-to-rail output amplifier has two configurable 001 gain options: a gain of 1x (<GA> = 1) or a gain of 2x Wide Code, >1LSb (<GA> = 0). The default value for this bit is a gain 000 of2(<GA> = 0). This results in an ideal full-scale Narrow Code, <1LSb output of 0.000V to 4.096V due to the internal reference (V =2.048V). DAC Output REF 4.1.2 VOLTAGE REFERENCE FIGURE 4-2: Example for DNL Error. The MCP4802/4812/4822 devices utilize internal 4.0.3 OFFSET ERROR 2.048V voltage reference. The voltage reference has a low temperature coefficient and low noise An offset error is the deviation from zero voltage output characteristics. Refer to Section1.0 “Electrical Char- when the digital input code is zero. acteristics” for the voltage reference specifications. 4.0.4 GAIN ERROR A gain error is the deviation from the ideal output, V –1 LSb, excluding the effects of offset error. REF DS20002249B-page 18  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 4.1.3 POWER-ON RESET CIRCUIT 4.1.4 SHUTDOWN MODE The internal Power-on Reset (POR) circuit monitors the The user can shut down each DAC channel selectively power supply voltage (VDD) during the device using a software command (<SHDN> = 0). During operation. The circuit also ensures that the DAC Shutdown mode, most of the internal circuits in the powers up with high output impedance (<SHDN> = 0, channel that was shut down are turned off for power typically 500k. The devices will continue to have a savings. The internal reference is not affected by the high-impedance output until a valid write command is shutdown command. The serial interface also remains received and the LDAC pin meets the input low active, thus allowing a write command to bring the threshold. device out of the Shutdown mode. There will be no analog output at the channel that was shut down and If the power supply voltage is less than the POR the V pin is internally switched to a known resistive threshold (V = 2.0V, typical), the DACs will be held OUT POR load (500ktypical. Figure4-4 shows the analog in their Reset state. The DACs will remain in that state output stage during the Shutdown mode. until V > V and a subsequent write command is DD POR received. The device will remain in Shutdown mode until the <SHDN> bit = 1 is latched into the device. When a Figure4-3 shows a typical power supply transient DAC channel is changed from Shutdown to Active pulse and the duration required to cause a reset to mode, the output settling time takes < 10µs, but occur, as well as the relationship between the duration greater than the standard active mode settling time and trip voltage. A 0.1µF decoupling capacitor, (4.5µs). mounted as close as possible to the V pin, can DD provide additional transient immunity. V OUT Op Amp 5V s e ag VPOR Power-Down olt VDD - VPOR Control Circuit V y pl Transient Duration Resistive p 500k u Load S Resistive String DAC Time 10 s) TA = +25°C FIGURE 4-4: Output Stage for Shutdown µ Mode. n ( 8 o rati 6 u D nt 4 e Transients above the curve si will cause a reset n 2 a Tr Transients below the curve will NOT cause a reset 0 1 2 3 4 5 V - V (V) DD POR FIGURE 4-3: Typical Transient Response.  2010-2015 Microchip Technology Inc. DS20002249B-page 19

MCP4802/4812/4822 NOTES: DS20002249B-page 20  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 5.0 SERIAL INTERFACE 5.2 Write Command The write command is initiated by driving the CS pin 5.1 Overview low, followed by clocking the four Configuration bits and the 12data bits into the SDI pin on the rising edge of The MCP4802/4812/4822 devices are designed to SCK. The CS pin is then raised, causing the data to be interface directly with the Serial Peripheral Interface latched into the selected DAC’s input registers. (SPI) port, available on many microcontrollers, and supports Mode 0,0 and Mode 1,1. Commands and data The MCP4802/4812/4822 devices utilize a double- are sent to the device via the SDI pin, with data being buffered latch structure to allow both DAC ’s and A clocked-in on the rising edge of SCK. The DAC ’s outputs to be synchronized with the LDAC pin, B communications are unidirectional and, thus, data if desired. cannot be read out of the MCP4802/4812/4822 By bringing down the LDAC pin to a low state, the con- devices. The CS pin must be held low for the duration tents stored in the DAC’s input registers are transferred of a write command. The write command consists of into the DAC’s output registers (V ), and both V OUT OUTA 16bits and is used to configure the DAC’s control and and V are updated at the same time. OUTB data latches. Register5-1 to Register5-3 detail the input register that is used to configure and load the All writes to the MCP4802/4812/4822 devices are DAC and DAC registers for each device. Figure5-1 16-bit words. Any clocks after the first 16th clock will be A B to Figure5-3 show the write command for each device. ignored. The Most Significant four bits are Configuration bits. The remaining 12bits are data bits. Refer to Figure1-1 and SPI Timing Specifications No data can be transferred into the device with CS Table for detailed input and output timing specifications high. The data transfer will only occur if 16 clocks have for both Mode 0,0 and Mode 1,1 operation. been transferred into the device. If the rising edge of CS occurs prior, shifting of data into the input registers will be aborted.  2010-2015 Microchip Technology Inc. DS20002249B-page 21

MCP4802/4812/4822 REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4822 (12-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x A/B — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 bit 15 bit 0 REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4812 (10-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x A/B — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x bit 15 bit 0 REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4802 (8-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x A/B — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 x x x x bit 15 bit 0 Where: bit 15 A/B: DAC or DAC Selection bit A B 1 = Write to DACB 0 = Write to DACA bit 14 — Don’t Care bit 13 GA: Output Gain Selection bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096), where internal VREF = 2.048V. bit 12 SHDN: Output Shutdown Control bit 1 = Active mode operation. VOUT is available.  0 = Shutdown the selected DAC channel. Analog output is not available at the channel that was shut down. V pin is connected to 500ktypical) OUT bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored. Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown DS20002249B-page 22  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) SCK (Mode 0,0) config bits 12 data bits SDI A/B — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC V OUT FIGURE 5-1: Write Command for MCP4822 (12-bit DAC). CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) SCK (Mode 0,0) config bits 12 data bits SDI A/B — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X LDAC V OUT Note: X = “don’t care” bits. FIGURE 5-2: Write Command for MCP4812 (10-bit DAC). CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) SCK (Mode 0,0) config bits 12 data bits SDI A/B — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 X X X X LDAC V OUT Note: X = “don’t care” bits. FIGURE 5-3: Write Command for MCP4802 (8-bit DAC).  2010-2015 Microchip Technology Inc. DS20002249B-page 23

MCP4802/4812/4822 NOTES: DS20002249B-page 24  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 6.0 TYPICAL APPLICATIONS 6.3 Output Noise Considerations The MCP4802/4812/4822 family of devices are The voltage noise density (in µV/Hz) is illustrated in general purpose DACs for various applications where Figure2-13. This noise appears at VOUTX, and is a precision operation with low-power and internal primarily a result of the internal reference voltage. voltage reference is required. Its1/fcorner (fCORNER) is approximately 400Hz. Applications generally suited for the devices are: Figure2-14 illustrates the voltage noise (in mVRMS or mV ). A small bypass capacitor on V is an • Set Point or Offset Trimming P-P OUTX effective method to produce a single-pole Low-Pass • Sensor Calibration Filter (LPF) that will reduce this noise. For instance, a • Precision Selectable Voltage Reference bypass capacitor sized to produce a 1kHz LPF would • Portable Instrumentation (Battery-Powered) result in an E of about 100 µV . This would be NREF RMS • Calibration of Optical Communication Devices necessary when trying to achieve the low DNL error performance (at G=1) that the MCP4802/4812/4822 6.1 Digital Interface devices are capable of. The tested range for stability is .001µF through 4.7 µF. The MCP4802/4812/4822 devices utilize a 3-wire synchronous serial protocol to transfer the DAC’s setup V V DD DD and input codes from the digital devices. The serial protocol can be interfaced to SPI or Microwire C1 = 10µF peripherals that is common on many microcontroller C2 = 0.1µF C1 C2 C1 C2 units (MCUs), including Microchip’s PIC® MCUs and dsPIC® DSCs. VDD V OUTA CS 1 In addition to the three serial connections (CS, SCK 1µF 2 and SDI), the LDAC signal synchronizes the two DAC C1 x SDI outputs. By bringing down the LDAC pin to “low”, all C2 48 P DAC input codes and settings in the two DAC input reg- C M V r isters are latched into their DAC output registers at the OUTB e same time. Therefore, both DAC and DAC outputs oll A B r are updated at the same time. Figure6-1 shows an nt o example of the pin connections. Note that the LDAC pin VOUTA x2 SDI AVSS SDO oc ccoannn ebceti ontise dfr omlo wfo ur( VtoS Sth)r eteo I /Ore pdinusc.e I n tthheis craesqeu,i rtehde P48 SCK Micr DAC output can be immediately updated when a valid 1µF MC ®C 16clock transmission has been received and the CS V LDAC PI OUTB pin has been raised. CS 0 6.2 Power Supply Considerations AV V The typical application will require a bypass capacitor SS SS in order to filter out the noise in the power supply FIGURE 6-1: Typical Connection traces. The noise can be induced onto the power Diagram. supply's traces from various events such as digital switching or as a result of changes on the DAC's 6.4 Layout Considerations output. The bypass capacitor helps to minimize the effect of these noise sources. Figure6-1 illustrates an Inductively-coupled AC transients and digital switching appropriate bypass strategy. In this example, two noises can degrade the output signal integrity, and bypass capacitors are used in parallel: (a) 0.1µF potentially reduce the device performance. Careful (ceramic) and (b)10µF (tantalum). These capacitors board layout will minimize these effects and increase should be placed as close to the device power pin the Signal-to-Noise Ratio (SNR). Bench testing has (V ) as possible (within 4mm). DD shown that a multi-layer board utilizing a The power source supplying these devices should be low-inductance ground plane, isolated inputs and as clean as possible. If the application circuit has isolated outputs with proper decoupling, is critical for separate digital and analog power supplies, V and the best performance. Particularly harsh environments DD V of the device should reside on the analog plane. may require shielding of critical signals. SS Breadboards and wire-wrapped boards are not recommended if low noise is desired.  2010-2015 Microchip Technology Inc. DS20002249B-page 25

MCP4802/4812/4822 6.5 Single-Supply Operation 6.5.1.1 Decreasing Output Step Size The MCP4802/4812/4822 family of devices are rail-to- If the application is calibrating the bias voltage of a rail voltage output DAC devices designed to operate diode or transistor, a bias voltage range of 0.8V may be with a V range of 2.7V to 5.5V. Its output amplifier is desired with about 200µV resolution per step. Two DD robust enough to drive small-signal loads directly. common methods to achieve a 0.8V range are to either Therefore, it does not require any external output buffer reduce VREF to 0.82V (using the MCP49XX family for most applications. device that uses external reference) or use a voltage divider on the DAC’s output. 6.5.1 DC SET POINT OR CALIBRATION Using a V is an option if the V is available with REF REF A common application for the devices is a digitally- the desired output voltage range. However, controlled set point and/or calibration of variable occasionally, when using a low-voltage VREF, the noise parameters, such as sensor offset or slope. For floor causes SNR error that is intolerable. Using a example, the MCP4822 provides 4096 output steps. If voltage divider method is another option and provides G=1 is selected, the internal 2.048V VREF would some advantages when VREF needs to be very low or produce 500µV of resolution. If G=2 is selected, the when the desired output voltage is not available. In this internal 2.048 VREF would produce 1mV of resolution. case, a larger value VREF is used while two resistors scale the output range down to the precise desired level. Example6-1 illustrates this concept. Note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environ- ment. EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION V DD (a) Single Output DAC: MCP4801 MCP4811 MCP4821 V + CC (b) Dual Output DAC: RSENSE V DD MCP4802 MCP4812 Comparator MCP4822 VOUT R1 VTRIP DAC V – R 0.1µF CC 2 SPI 3-wire D V = 2.048G-----n- G = Gain selection (1x or 2x) OUT N 2 D = Digital value of DAC (0-255) for MCP4801/MCP4802 n = Digital value of DAC (0-1023) for MCP4811/MCP4812  R2  = Digital value of DAC (0-4095) for MCP4821/MCP4822 V = V -------------------- trip OUTR1+R2 N = DAC bit resolution DS20002249B-page 26  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 6.5.1.2 Building a “Window” DAC If the threshold is not near V , 2V or V , then REF REF SS creating a “window” around the threshold has several When calibrating a set point or threshold of a sensor, advantages. One simple method to create this typically only a small portion of the DAC output range is “window” is to use a voltage divider network with a pull- utilized. If the LSb size is adequate enough to meet the up and pull-down resistor. Example6-2 shows this application’s accuracy needs, the unused range is concept. sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC (a) Single Output DAC: MCP4801 MCP4811 MCP4821 (b) Dual Output DAC: MCP4802 MCP4812 V MCP4822 VCC+ RSENSE CC+ V DD R 3 Comparator R VOUT 1 VTRIP DAC V R 0.1µF CC- 2 SPI 3-wire V CC- D V = 2.048G-----n- OUT N 2 G = Gain selection (1x or 2x) D = Digital value of DAC (0-255) for MCP4801/MCP4802 n = Digital value of DAC (0-1023) for MCP4811/MCP4812 = Digital value of DAC (0-4095) for MCP4821/MCP4822 N = DAC bit resolution R R R = --------2------3----- R1 23 R +R Thevenin 2 3 VOUT VO Equivalent V R +V R  CC+ 2 CC- 3 V = ------------------------------------------------------ R 23 R +R 23 2 3 V R +V R OUT 23 23 1 Vtrip = ------------R--------+-----R-------------------- V23 1 23  2010-2015 Microchip Technology Inc. DS20002249B-page 27

MCP4802/4812/4822 6.6 Bipolar Operation Example6-3 illustrates a simple bipolar voltage source configuration. R and R allow the gain to be selected, 1 2 Bipolar operation is achievable using the while R and R shift the DAC's output to a selected 3 4 MCP4802/4812/4822 family of devices by utilizing an offset. Note that R4 can be tied to V , instead of V , DD SS external operational amplifier (op amp). This if a higher offset is desired. Also note that a pull-up to configuration is desirable due to the wide variety and V could be used instead of R or in addition to R , if DD 4, 4 availability of op amps. This allows a general purpose a higher offset is desired. DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE R 2 (a) Single Output DAC: V DD MCP4801 V MCP4811 DD R VCC+ 1 MCP4821 VOUT R3 VO (b) Dual Output DAC: DAC V + MCP4802 IN V – CC MCP4812 R 0.1µF 4 MCP4822 SPI 3-wire D V = 2.048G-----n- OUT 2N G = Gain selection (1x or 2x) D = Digital value of DAC (0-255) for MCP4801/MCP4802 V R n V = ----O----U----T-------4- = Digital value of DAC (0-1023) for MCP4811/MCP4812 IN+ R +R 3 4 = Digital value of DAC (0-4095) for MCP4821/MCP4822 R R N = DAC bit resolution  2  2 V = V 1+------ –V ------ O IN+ R  DDR  1 1 6.6.1 DESIGN EXAMPLE: DESIGN A The equation can be simplified to: BIPOLAR DAC USING Example6-3 WITH 12-BIT MCP4822 OR –----R----2- = --–----2---.-0---5---- R----2-- = 1--- MCP4821 R 4.096V R 2 1 1 An output step magnitude of 1mV, with an output range If R = 20k and R = 10k, the gain will be 0.5. of ±2.05V, is desired for a particular application. 1 2 Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V. Step 4: Next, solve for R and R by setting the DAC to Step 2: Calculate the resolution needed: 3 4 4096, knowing that the output needs to be 4.1V/1mV = 4100 +2.05V. Since 212 = 4096, 12-bit resolution is desired. ----------R---4----------- = 2---.--0---5---V------+--------0---.-5--------4---.-0---9---6---V----- = 2--- Step 3:The amplifier gain (R /R ), multiplied by full- R +R  1.54.096V 3 2 1 3 4 scale V (4.096V), must be equal to the OUT desired minimum output to achieve bipolar If R4 = 20k, then R3 = 10k operation. Since any gain can be realized by choosing resistor values (R +R ), the V 1 2 REF value must be selected first. If a V of 4.096V REF is used (G=2), solve for the amplifier’s gain by setting the DAC to 0, knowing that the output needs to be -2.05V. DS20002249B-page 28  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 6.7 Selectable Gain and This circuit is typically used for linearizing a sensor Offset Bipolar Voltage Output whose slope and offset varies. Using a Dual Output DAC The equation to design a bipolar “window” DAC would be utilized if R , R and R are populated. 3 4 5 In some applications, precision digital control of the output range is desirable. Example6-4 illustrates how to use the MCP4802/4812/4822 family of devices to achieve this in a bipolar or single-supply application. EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET R 2 V DD V + CC R V 1 OUTA DAC A Dual Output DAC: (DAC for Gain Adjust) V + A CC MCP4802 VDD VO MCP4812 R 5 MCP4822 V R3 V + OUTB IN DAC B (DAC for Offset Adjust) B SPI R 4 0.1µF V – 3 CC D VCC– V = 2.048G -----n- OUTA A N 2 D G = Gain selection (1x or 2x) V = 2.048G -----n- OUTB B N N = DAC bit resolution 2 D D = Digital value of DAC (0-255) for MCP4802 A , B V = V----O----U----T---B---R----4----+-----V----C---C------R----3-- = Digital value of DAC (0-1023) for MCP4812 IN+ R3+R4 = Digital value of DAC (0-4095) for MCP4822 R R  2  2 V = V 1+------ –V ------ O IN+ R  OUTAR  1 1 Offset Adjust Gain Adjust Bipolar “Window” DAC using R and R 4 5 Thevenin V R +V R R R V = ----C---C----+-------4-------------C---C----------5-- R = --------4------5----- Equivalent 45 R +R 45 R +R 4 5 4 5 V R +V R R R OUTB 45 45 3  2  2 V = ------------------------------------------------ V = V 1+------ –V ------ IN+ R +R O IN+ R  OUTAR  3 45 1 1 Offset Adjust Gain Adjust  2010-2015 Microchip Technology Inc. DS20002249B-page 29

MCP4802/4812/4822 6.8 Designing a Double-Precision Step 1: Calculate the resolution needed: DAC Using a Dual DAC 4.1V/1µV=4.1x106. Since 222=4.2x106, 22-bit resolution is desired. Since Example6-5 illustrates how to design a single-supply DNL=±0.75LSb, this design can be done voltage output capable of up to 24-bit resolution from a with the 12-bit MCP4822 DAC. dual 12-bit DAC (MCP4822). This design is simply a voltage divider with a buffered output. Step 2: Since DACB’s VOUTB has a resolution of 1mV, its output only needs to be “pulled” 1/1000 to As an example, if an application similar to the one meet the 1µV target. Dividing V by 1000 developed in Section6.6.1 “Design Example: OUTA would allow the application to compensate for Design a Bipolar DAC Using Example6-3 with 12- DAC ’s DNL error. bit MCP4822 or MCP4821” required a resolution of B 1µV instead of 1mV, and a range of 0V to 4.1V, then Step 3: If R2 is 100, then R1 needs to be 100k. 12-bit resolution would not be adequate. Step 4: The resulting transfer function is shown in the equation of Example6-5. EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4822 V DD V + CC V OUTA MCP4822 (DAC for Fine Adjustment) A R1 VO R >> R 1 2 V DD V – CC VOUTB R2 0.1µF MCP4822 (DAC for Course Adjustment) B SPI 3-wire D A VOUTA = 2.048GA----1--2- Gx = Gain selection (1x or 2x) 2 DB Dn = Digital value of DAC (0-4096) V = 2.048G ------- OUTB B 12 2 V R +V R OUTA 2 OUTB 1 V = ------------------------------------------------------ O R +R 1 2 DS20002249B-page 30  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 6.9 Building Programmable Current However, this also reduces the resolution that the Source current can be controlled with. The voltage divider, or “window”, DAC configuration would allow the range to Example6-6 shows an example of building a be reduced, thus increasing resolution around the programmable current source using a voltage follower. range of interest. When working with very small sensor The current sensor (sensor resistor) is used to convert voltages, plan on eliminating the amplifier’s offset error the DAC voltage output into a digitally-selectable by storing the DAC’s setting under known sensor current source. conditions. Adding the resistor network from Example6-2 would be advantageous in this application. The smaller R is, the less power dissipated across it. SENSE EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE V or V DD REF (a) Single Output DAC: V DD Load MCP4801 V + CC MCP4811 V I OUT L MCP4821 DAC (b) Dual Output DAC: I b MCP4802 SPI V – CC MCP4812 3-wire MCP4822 R SENSE I L I = ---- G = Gain selection (1x or 2x) b  D = Digital value of DAC (0-255) for MCP4801/MCP4802 n VOUT  = Digital value of DAC (0-1023) for MCP4811/MCP4812 I = ---------------------------- L R +1 = Digital value of DAC (0-4095) for MCP4821/MCP4822 sense where Common-Emitter Current Gain N = DAC bit resolution  2010-2015 Microchip Technology Inc. DS20002249B-page 31

MCP4802/4812/4822 NOTES: DS20002249B-page 32  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation and Demonstration Boards The Mixed Signal PICtail™ Demo Board supports the MCP4802/4812/4822 family of devices. Refer to www.microchip.com for further information on this product’s capabilities and availability.  2010-2015 Microchip Technology Inc. DS20002249B-page 33

MCP4802/4812/4822 NOTES: DS20002249B-page 34  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead MSOP (3x3 mm) Example 4822E 009256 8-Lead PDIP (300 mil) Example XXXXXXXX MCP4802 XXXXXNNN E/P e 3 256 YYWW 1009 8-Lead SOIC (3.90 mm) Example MCP4812E SN e 3 1009 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. DS20002249B-page 35

MCP4802/4812/4822 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS20002249B-page 36  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS20002249B-page 37

MCP4802/4812/4822 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002249B-page 38  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS20002249B-page 39

MCP4802/4812/4822 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS20002249B-page 40  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS20002249B-page 41

MCP4802/4812/4822 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002249B-page 42  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2010-2015 Microchip Technology Inc. DS20002249B-page 43

MCP4802/4812/4822 NOTES: DS20002249B-page 44  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 APPENDIX A: REVISION HISTORY Revision B (May 2015) • Updated MSOP package marking drawing to correctly display the part’s orientation. Revision A (April 2010) • Original Release of this Document.  2010-2015 Microchip Technology Inc. DS20002249B-page 45

MCP4802/4812/4822 NOTES: DS20002249B-page 46  2010-2015 Microchip Technology Inc.

MCP4802/4812/4822 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Examples: Device Temperature Package a) MCP4802-E/MS: Extended temperature, Range MSOP package. b) MCP4802T-E/MS: Extended temperature, MSOP package, Tape and Reel. Device: MCP4802: Dual 8-Bit Voltage Output DAC c) MCP4802-E/P: Extended temperature, MCP4802T: Dual 8-Bit Voltage Output DAC PDIP package. (Tape and Reel, MSOP and SOIC only) d) MCP4802-E/SN: Extended temperature, MCP4812: Dual 10-Bit Voltage Output DAC SOIC package. MCP4812T: Dual 10-Bit Voltage Output DAC e) MCP4802T-E/SN: Extended temperature, (Tape and Reel, MSOP and SOIC only) SOIC package, MCP4822: Dual 12-Bit Voltage Output DAC Tape and Reel. MCP4822T: Dual 12-Bit Voltage Output DAC (Tape and Reel, MSOP and SOIC only) a) MCP4812-E/MS: Extended temperature, MSOP package. b) MCP4812T-E/MS: Extended temperature, Temperature E = -40C to +125C (Extended) MSOP package, Range: Tape and Reel. c) MCP4812-E/P: Extended temperature, PDIP package. Package: MS = 8-Lead Plastic Micro Small Outline (MSOP) d) MCP4812-E/SN: Extended temperature, P = 8-Lead Plastic Dual In-Line (PDIP) SOIC package. SN = 8-Lead Plastic Small Outline - Narrow, 150mil (SOIC) e) MCP4812T-E/SN: Extended temperature, SOIC package, Tape and Reel. a) MCP4822-E/MS: Extended temperature, MSOP package. b) MCP4822T-E/MS: Extended temperature, MSOP package, Tape and Reel. c) MCP4822-E/P: Extended temperature, PDIP package. d) MCP4822-E/SN: Extended temperature, SOIC package. e) MCP4822T-E/SN: Extended temperature, SOIC package, Tape and Reel.  2010-2015 Microchip Technology Inc. DS20002249B-page 47

MCP4802/4812/4822 NOTES: DS20002249B-page 48  2010-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-374-6 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010-2015 Microchip Technology Inc. DS20002249B-page 49

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP4802-E/MS MCP4802-E/P MCP4802-E/SN MCP4802T-E/MS MCP4812-E/MS MCP4812-E/P MCP4812-E/SN MCP4812T-E/MS MCP4802-E/SNVAO