M MCP3204/3208 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI™ Serial Interface Features Description • 12-bit resolution The Microchip Technology Inc. MCP3204/3208 • ± 1LSB max DNL devices are successive approximation 12-bit Analog- to-Digital (A/D) Converters with on-board sample and • ± 1LSB max INL (MCP3204/3208-B) hold circuitry. The MCP3204 is programmable to pro- • ± 2LSB max INL (MCP3204/3208-C) vide two pseudo-differential input pairs or four single- • 4 (MCP3204) or 8 (MCP3208) input channels ended inputs. The MCP3208 is programmable to pro- • Analog inputs programmable as single-ended or vide four pseudo-differential input pairs or eight single- pseudo-differential pairs ended inputs. Differential Nonlinearity (DNL) is speci- • On-chip sample and hold fied at ±1LSB, while Integral Nonlinearity (INL) is • SPI serial interface (modes 0,0 and 1,1) offered in ±1LSB (MCP3204/3208-B) and ±2LSB (MCP3204/3208-C) versions. • Single supply operation: 2.7V - 5.5V • 100ksps max. sampling rate at V = 5V Communication with the devices is accomplished using DD a simple serial interface compatible with the SPI proto- • 50ksps max. sampling rate at V = 2.7V DD col. The devices are capable of conversion rates of up • Low power CMOS technology: to 100ksps. The MCP3204/3208 devices operate over - 500 nA typical standby current, 2µA max. a broad voltage range (2.7V - 5.5V). Low current - 400 µA max. active current at 5V design permits operation with typical standby and • Industrial temp range: -40°C to +85°C active currents of only 500nA and 320µA, respec- tively. The MCP3204 is offered in 14-pin PDIP, 150mil • Available in PDIP, SOIC and TSSOP packages SOIC and TSSOP packages. The MCP3208 is offered Applications in 16-pin PDIP and SOIC packages. • Sensor Interface Functional Block Diagram • Process Control • Data Acquisition VDD VSS V REF • Battery Operated Systems CH0 Package Types CH1 Input Channel DAC PDIP, SOIC, TSSOP Mux CH7* CH0 1 14 VDD Comparator CH1 2 M 13 VREF 12-Bit SAR CH2 3 C 12 AGND Sample CH3 4 P3 11 CLK Hanodld NC 5 20 10 DOUT NC 6 4 9 DIN Control Logic Shift DGND 7 8 CS/SHDN Register PDIP, SOIC CS/SHDN DIN CLK DOUT CH0 1 16 VDD * Note: Channels 5-7 available on MCP3208 Only CH1 2 15 VREF CH2 3 M 14 AGND C CH3 4 P 13 CLK CH4 5 32 12 DOUT CH5 6 08 11 DIN CH6 7 10 CS/SHDN CH7 8 9 DGND  2002 Microchip Technology Inc. DS21298C-page 1

MCP3204/3208 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function Absolute Maximum Ratings* V +2.7V to 5.5V Power Supply DD V ...................................................................................7.0V DGND Digital Ground DD All inputs and outputs w.r.t. V ...............-0.6V to V +0.6V AGND Analog Ground SS DD Storage temperature.....................................-65°C to +150°C CH0-CH7 Analog Inputs Ambient temp. with power applied................-65°C to +125°C CLK Serial Clock Soldering temperature of leads (10 seconds).............+300°C D Serial Data In IN ESD protection on all pins.............................................> 4kV D Serial Data Out OUT *Notice: Stresses above those listed under "Maximum CS/SHDN Chip Select/Shutdown Input Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at VREF Reference Voltage Input those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, V = 5V, DD SS REF T = -40°C to +85°C,f = 100ksps and f = 20*f AMB SAMPLE CLK SAMPLE Parameters Sym Min Typ Max Units Conditions Conversion Rate Conversion Time t — — 12 clock CONV cycles Analog Input Sample Time t 1.5 clock SAMPLE cycles Throughput Rate f — — 100 ksps V = V = 5V SAMPLE DD REF — — 50 ksps V = V = 2.7V DD REF DC Accuracy Resolution 12 bits Integral Nonlinearity INL — ±0.75 ±1 LSB MCP3204/3208-B — ±1.0 ±2 MCP3204/3208-C Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes over-temperature Offset Error — ±1.25 ±3 LSB Gain Error — ±1.25 ±5 LSB Dynamic Performance Total Harmonic Distortion — -82 — dB V = 0.1V to 4.9V@1kHz IN Signal to Noise and Distortion — 72 — dB V = 0.1V to 4.9V@1kHz IN (SINAD) Spurious Free Dynamic — 86 — dB V = 0.1V to 4.9V@1kHz IN Range Reference Input Voltage Range 0.25 — V V Note2 DD Current Drain — 100 150 µA — 0.001 3.0 µA CS = V = 5V DD Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, particularly at elevated temperatures. See Section6.2, “Maintaining Minimum Clock Speed”, for more information. DS21298C-page 2  2002 Microchip Technology Inc.

MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, V = 5V, DD SS REF T = -40°C to +85°C,f = 100ksps and f = 20*f AMB SAMPLE CLK SAMPLE Parameters Sym Min Typ Max Units Conditions Analog Inputs Input Voltage Range for CH0- V — V V SS REF CH7 in Single-Ended Mode Input Voltage Range for IN+ in IN- — V +IN- REF pseudo-differential Mode Input Voltage Range for IN- in V -100 — V +100 mV SS SS pseudo-differential Mode Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure4-1 Sample Capacitor — 20 — pF See Figure4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage V 0.7 V — — V IH DD Low Level Input Voltage V — — 0.3 V V IL DD High Level Output Voltage V 4.1 — — V I = -1mA, V = 4.5V OH OH DD Low Level Output Voltage V — — 0.4 V I = 1mA, V = 4.5V OL OL DD Input Leakage Current I -10 — 10 µA V = V or V LI IN SS DD Output Leakage Current I -10 — 10 µA V = V or V LO OUT SS DD Pin Capacitance C ,C — — 10 pF V = 5.0V (Note1) IN OUT DD (All Inputs/Outputs) T = 25°C, f = 1MHz AMB Timing Parameters Clock Frequency f — — 2.0 MHz V = 5V (Note3) CLK DD — — 1.0 MHz V = 2.7V (Note3) DD Clock High Time t 250 — — ns HI Clock Low Time t 250 — — ns LO CS Fall To First Rising CLK t 100 — — ns SUCS Edge Data Input Setup Time t — — 50 ns SU Data Input Hold Time t — — 50 ns HD CLK Fall To Output Data Valid t — — 200 ns See Figures1-2 and 1-3 DO CLK Fall To Output Enable t — — 200 ns See Figures1-2 and 1-3 EN CS Rise To Output Disable t — — 100 ns See Figures1-2 and 1-3 DIS CS Disable Time t 500 — — ns CSH D Rise Time t — — 100 ns See Figures1-2 and 1-3 (Note1) OUT R D Fall Time t — — 100 ns See Figures1-2 and 1-3 (Note1) OUT F Power Requirements Operating Voltage V 2.7 — 5.5 V DD Operating Current I — 320 400 µA V =V = 5V, D unloaded DD DD REF OUT — 225 — V =V = 2.7V, D unloaded DD REF OUT Standby Current I — 0.5 2.0 µA CS = V = 5.0V DDS DD Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, particularly at elevated temperatures. See Section6.2, “Maintaining Minimum Clock Speed”, for more information.  2002 Microchip Technology Inc. DS21298C-page 3

MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5V, V = 0V, V = 5V, DD SS REF T = -40°C to +85°C,f = 100ksps and f = 20*f AMB SAMPLE CLK SAMPLE Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C A Operating Temperature T -40 — +85 °C A Range Storage Temperature Range T -65 — +150 °C A Thermal Package Resistance Thermal Resistance, θ — 70 — °C/W JA 14L-PDIP Thermal Resistance, θ — 108 — °C/W JA 14L-SOIC Thermal Resistance, θ — 100 — °C/W JA 14L-TSSOP Thermal Resistance, θ — 70 — °C/W JA 16L-PDIP Thermal Resistance, θ — 90 — °C/W JA 16L-SOIC Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to V levels. REF 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, particularly at elevated temperatures. See Section6.2, “Maintaining Minimum Clock Speed”, for more information. t CSH CS t SUCS t t HI LO CLK t t SU HD DIN MSB IN tDO tR tF tDIS t EN DOUT Null Bit MSB OUT LSB FIGURE 1-1: Serial Interface Timing. DS21298C-page 4  2002 Microchip Technology Inc.

MCP3204/3208 1.4V Test Point V DD 3kΩ tDIS Waveform 2 Test Point 3kΩ VDD/2 DOUT DOUT tEN Waveform CL = 100pF 100pF tDIS Waveform 1 V SS Voltage Waveforms for t , t R F Voltage Waveforms for t EN V OH V D OL OUT CS tR tF CLK 1 2 3 4 Voltage Waveforms for t DO D B11 OUT CLK t EN t DO Voltage Waveforms for t DIS D OUT V CS IH FIGURE 1-2: Load Circuit for t , t , t . D R F DO OUT 90% Waveform 1* T DIS D 10% OUT Waveform 2† * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: Load circuit for t and t . DIS EN  2002 Microchip Technology Inc. DS21298C-page 5

MCP3204/3208 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 1.0 2.0 0.8 Positive INL 1.5 VDD = VREF = 2.7 V 0.6 1.0 0.4 Positive INL INL (LSB)--0000....0242 Negative INL INL (LSB)--1000....0505 Negative INL -0.6 -1.5 -0.8 -2.0 -1.0 0 10 20 30 40 50 60 70 80 0 25 50 75 100 125 150 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate. vs. Sample Rate (V = 2.7V). DD 2.5 2.0 2.0 1.5 1.5 Positive INL 1.0 LSB) 01..50 Positive INL SB)0.5 NL ( 0.0 L (L0.0 I-0.5 N-0.5 I -1.0 Negative INL -1.0 Negative INL -1.5 -1.5 -2.0 -2.0 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-2: Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL) vs. V . vs. V (V = 2.7V). REF REF DD 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V 0.6 0.6 FSAMPLE = 50 ksps 0.4 0.4 NL (LSB)-000...022 NL (LSB)-000...022 I I -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part). vs. Code (Representative Part, V = 2.7V). DD DS21298C-page 6  2002 Microchip Technology Inc.

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 1.0 1.0 0.8 Positive INL 0.8 VFSDADM =P LVE R=E F5 =0 k2.s7p Vs 0.6 0.6 Positive INL 0.4 0.4 B) 0.2 B) 0.2 S S NL (L-00..02 Negative INL NL (L-00..02 I-0.4 I-0.4 -0.6 -0.6 Negative INL -0.8 -0.8 -1.0 -1.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-7: Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature. vs. Temperature (V = 2.7V). DD 1.0 2.0 VDD = VREF = 2.7 V 0.8 1.5 0.6 1.0 0.4 SB)0.2 SB)0.5 L (L0.0 Positive DNL L (L0.0 Positive DNL DN-0.2 DN-0.5 Negative DNL -0.4 -0.6 Negative DNL -1.0 -0.8 -1.5 -1.0 -2.0 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate. (DNL) vs. Sample Rate (V = 2.7V). DD 3.0 3.0 VDD = VREF = 2.7 V 2.0 2.0 FSAMPLE = 50 ksps Positive DNL B)1.0 Positive DNL B) 1.0 S S L (L0.0 L (L 0.0 N N D-1.0 Negative DNL D-1.0 Negative DNL -2.0 -2.0 -3.0 -3.0 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-9: Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity (DNL) vs. V . (DNL) vs. V (V = 2.7V) REF REF DD .  2002 Microchip Technology Inc. DS21298C-page 7

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V FSAMPLE = 50 ksps 0.6 0.6 0.4 0.4 SB) 0.2 SB) 0.2 L L L ( 0.0 L ( 0.0 N-0.2 N-0.2 D D -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-13: Differential Nonlinearity FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part). (DNL) vs. Code (Representative Part, V = DD 2.7V). 1.0 1.0 0.8 0.8 VDD = VREF = 2.7 V 0.6 0.6 FSAMPLE = 50 ksps 0.4 Positive DNL 0.4 Positive DNL SB)0.2 SB) 0.2 NL (L-00..02 NL (L-00..02 D D -0.4 -0.4 Negative DNL Negative DNL -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-14: Differential Nonlinearity FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature. (DNL) vs. Temperature (V = 2.7V). DD 4 20 3 VDD = VREF = 2.7 V 18 n Error (LSB)-1012 FSAMPLE = 50 ksps et Error (LSB)111102468 VFSDADM =P LVE R=E F1 =0 0V5 VDkDs p=s VREF = 2.7V Gai--32 VFSDADM =P LVE R=E F1 =0 05 kVsps Offs 46 FSAMPLE = 50 ksps 2 -4 0 0 1 2 3 4 5 0 1 2 3 4 5 VREF (V) VREF (V) FIGURE 2-15: Gain Error vs. V . FIGURE 2-18: Offset Error vs. V . REF REF DS21298C-page 8  2002 Microchip Technology Inc.

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 0.2 2.0 0.0 VDD = VREF = 2.7 V 1.8 Gain Error (LSB)-------1110000.......4208642 FSAMPLE = 5VF0 SDkADsM =pPL sVE R=E F1 =00 5 kVsps Offset Error (LSB)0001111.......4680246 VFVFSSDDAADDMM ==PP LL VVEE RR==EE FF51 =0=0 0 k25 .s k7Vps Vpss -1.6 0.2 -1.8 0.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature. 100 100 90 VDD = VREF = 5 V 90 VDD = VREF = 5 V 80 FSAMPLE = 100 ksps 80 FSAMPLE = 100 ksps 70 70 dB)60 dB)60 R (50 R (50 VDD = VREF = 2.7 V SN3400 VFSDADM =PL VE R=E F5 =0 k2.s7pVs SFD3400 FSAMPLE = 50 ksps 20 20 10 10 0 0 1 10 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise (SNR) vs. FIGURE 2-23: Signal to Noise and Input Frequency. Distortion (SINAD) vs. Input Frequency. 0 80 -10 VDD = VREF = 5 V -20 70 FSAMPLE = 100 ksps -30 60 D (dB)--5400 VFSDADM =PL VE R=E F5 =0 k2.s7pVs D (dB)4500 VFSDADM =P LVE R=E F5 =0 k2.s7p Vs TH-60 NA30 -70 SI 20 -80 -90 VFSDADM =PL VE R=E F1 =00 5 Vksps 10 -100 0 1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion FIGURE 2-24: Signal to Noise and (THD) vs. Input Frequency. Distortion (SINAD) vs. Input Signal Level.  2002 Microchip Technology Inc. DS21298C-page 9

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 12.0 12.00 11.75 11.5 11.50 11.25 11.0 ms)11.00 VDD = VREF = 5 V ms)10.5 OB (r111000...257505 VFSDADM =P LVE R=E F5 =0 k2.s7p Vs FSAMPLE =100 ksps OB (r10.0 VFSDADM =P LVE R=E F1 =00 5 kVsps N N9.5 E10.00 E 9.75 9.0 VDD = VREF = 2.7 V 9.50 FSAMPLE = 50 ksps 8.5 9.25 9.00 8.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 VREF (V) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs. V . (ENOB) vs. Input Frequency. REF 100 0 8900 VFSDADM =P LVE R=E F1 =00 5 kVsps n (dB)-10 o-20 dB)6700 ejecti-30 SFDR (23450000 VFSDADM =PL VE R=E F5 =0 k2.s7p Vs er Supply R---654000 w-70 10 o P 0 -80 1 10 100 1 10 100 1000 10000 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic FIGURE 2-29: Power Supply Rejection Range (SFDR) vs. Input Frequency. (PSR) vs. Ripple Frequency. 0 0 -10 VDD = VREF = 5 V -10 VDD = VREF = 2.7 V -20 FSAMPLE = 100 ksps -20 FSAMPLE = 50 ksps -30 FINPUT = 9.985 kHz -30 FINPUT = 998.76 Hz Amplitude (dB)------987654000000 4096 points Amplitude (dB) ------987654000000 4096 points -100 -100 -110 -110 -120 -120 -130 -130 0 10000 20000 30000 40000 50000 0 5000 10000 15000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of FIGURE 2-30: Frequency Spectrum of 10kHz input (Representative Part). 1kHz input (Representative Part, V = 2.7V). DD DS21298C-page 10  2002 Microchip Technology Inc.

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 500 100 450 VREF = VDD 90 VREF = VDD 345000 Aatl lV pRoEFin =t sV aDtD F=C 2LK.5 = V 2, FMCHLKz ,= e 1x cMeHpzt 7800 Aatl lV pRoEFin =ts V aDtD F=C L2K.5 = V 2, FMCHLKz =e x1c MepHtz A)300 A) 60 I (µDD220500 (µREF 4500 I 150 30 100 20 50 10 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V (V) V (V) DD DD FIGURE 2-31: I vs. V . FIGURE 2-34: I vs. V . DD DD REF DD 400 100 350 90 VDD = VREF = 5 V 80 300 VDD = VREF = 5 V 70 I (µA)DD122505000 VDD = VREF = 2.7 V I (µA)REF 34560000 VDD = VREF = 2.7 V 100 20 50 10 0 0 10 100 1000 10000 10 100 1000 10000 Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: I vs. Clock Frequency. FIGURE 2-35: I vs. Clock Frequency. DD REF 400 100 350 VFCDLDK = = V 2R EMF H=z 5 V 90 VFCDLDK = = V 2R EMF H=z 5 V 80 300 70 250 A) A) 60 I (µDD125000 VFCDLDK = = V 1R EMF H=z 2.7 V I (µREF 345000 VDD = VREF = 2.7 V 100 FCLK = 1 MHz 20 50 10 0 0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-33: I vs. Temperature. FIGURE 2-36: I vs. Temperature. DD REF  2002 Microchip Technology Inc. DS21298C-page 11

MCP3204/3208 Note: Unless otherwise indicated, V = V = 5V, V = 0V, f = 100ksps, f = 20* f ,T = 25°C. DD REF SS SAMPLE CLK SAMPLE A 80 2.0 70 VREF = CS = VDD A)1.8 n 60 e (1.6 g1.4 a I (pA)DDS345000 nput Leak011...802 VFCDLDK = = V 2R EMF H=z 5 V 20 alog I00..46 10 An0.2 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 VDD (V) Temperature (°C) FIGURE 2-37: I vs. V . FIGURE 2-39: Analog Input Leakage DDS DD Current vs. Temperature. 100.00 VDD = VREF = CS = 5 V 10.00 A) n (S 1.00 D D I 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 2-38: I vs. Temperature. DDS DS21298C-page 12  2002 Microchip Technology Inc.

MCP3204/3208 3.0 PIN DESCRIPTIONS 3.7 Chip Select/Shutdown (CS/SHDN) The descriptions of the pins are listed in Table3-1. The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conver- TABLE 3-1: PIN FUNCTION TABLE sion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high Name Function between conversions. V +2.7V to 5.5V Power Supply DD DGND Digital Ground 4.0 DEVICE OPERATION AGND Analog Ground The MCP3204/3208 A/D converters employ a conven- CH0-CH7 Analog Inputs tional SAR architecture. With this architecture, a sam- CLK Serial Clock ple is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the D Serial Data In IN serial clock after the start bit has been received. Fol- DOUT Serial Data Out lowing this sample time, the device uses the collected CS/SHDN Chip Select/Shutdown Input charge on the internal sample/hold capacitor to pro- V Reference Voltage Input duce a serial 12-bit digital output code. Conversion REF rates of 100ksps are possible on the MCP3204/3208. 3.1 DGND See Section6.2, “Maintaining Minimum Clock Speed”, for information on minimum clock rates. Communica- Digital ground connection to internal digital circuitry. tion with the device is accomplished using a 4-wire SPI- compatible interface. 3.2 AGND 4.1 Analog Inputs Analog ground connection to internal analog circuitry. The MCP3204/3208 devices offer the choice of using 3.3 CH0 - CH7 the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3204 can Analog inputs for channels 0 - 7 for the multiplexed be configured to provide two pseudo-differential input inputs. Each pair of channels can be programmed to be pairs or four single-ended inputs, while the MCP3208 used as two independent channels in single-ended can be configured to provide four pseudo-differential mode or as a single pseudo-differential input, where input pairs or eight single-ended inputs. Configuration one channel is IN+ and one channel is IN. See is done as part of the serial command before each con- Section4.1, “Analog Inputs”, and Section5.0, “Serial version begins. When used in the pseudo-differential Communications”, for information on programming the mode, each channel pair (i.e., CH0 and CH1, CH2 and channel configuration. CH3 etc.) is programmed to be the IN+ and IN- inputs 3.4 Serial Clock (CLK) as part of the command string transmitted to the device. The IN+ input can range from IN- to (V + IN- REF The SPI clock pin is used to initiate a conversion and ). The IN- input is limited to ±100mV from the V rail. SS clock out each bit of the conversion as it takes place. The IN- input can be used to cancel small signal com- See Section6.2, “Maintaining Minimum Clock Speed”, mon-mode noise which is present on both the IN+ and for constraints on clock speed. IN- inputs. When operating in the pseudo-differential mode, if the 3.5 Serial Data Input (D ) IN voltage level of IN+ is equal to or less than IN-, the The SPI port serial data input pin is used to load resultant code will be 000h. If the voltage at IN+ is channel configuration data into the device. equal to or greater than {[VREF + (IN-)] - 1LSB}, then the output code will be FFFh. If the voltage level at IN- 3.6 Serial Data Output (D ) is more than 1LSB below V , the voltage level at the OUT SS IN+ input will have to go below V to see the 000h SS The SPI serial data output pin is used to shift out the output code. Conversely, if IN- is more than 1LSB results of the A/D conversion. Data will always change above V , then the FFFh code will not be seen unless SS on the falling edge of each clock as the conversion the IN+ input level goes above V level. REF takes place. For the A/D converter to meet specification, the charge holding capacitor (C ) must be given enough SAMPLE time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure4-1.  2002 Microchip Technology Inc. DS21298C-page 13

MCP3204/3208 This diagram illustrates that the source impedance (R ) EQUATION S adds to the internal sampling switch (RSS) impedance, 4096×V directly effecting the time that is required to charge the Digital Output Code = -----------------------I-N--- V capacitor (Csample). Consequently, larger source REF impedances increase the offset, gain and integral V = analog input voltage linearity errors of the conversion (see Figure4-2). IN V = reference voltage REF 4.2 Reference Input When using an external voltage reference device, the For each device in the family, the reference input system designer should always refer to the manufac- (VREF) determines the analog input voltage range. As turer’s recommendations for circuit layout. Any instabil- the reference input is reduced, the LSB size is reduced ity in the operation of the reference device will have a accordingly. The theoretical digital output code pro- direct effect on the operation of the A/D converter. duced by the A/D converter is a function of the analog input signal and the reference input, as shown below. V DD Sampling Switch V = 0.6V RSS CHx T SS RS = 1kΩ C C I SAMPLE VA PIN V = 0.6V LEAKAGE = DAC capacitance 7pF T ±1nA = 20pF V SS Legend VA = Signal Source Ileakage = Leakage Current At The Pin Due To Various Junctions Rss = Source Impedance SS = Sampling switch CHx = Input Channel Pad Rs = Sampling switch resistor Cpin = Input Pin Capacitance Csample = Sample/hold capacitance Vt = Threshold Voltage FIGURE 4-1: Analog Input Model. 2.5 Hz)2.0 VDD = 5 V M y ( c1.5 n e u q e1.0 k Fr VDD = 2.7 V c o0.5 Cl 0.0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (R ) to maintain less than a S 0.1LSB deviation in INL from nominal conditions. DS21298C-page 14  2002 Microchip Technology Inc.

MCP3204/3208 5.0 SERIAL COMMUNICATIONS TABLE 5-1: CONFIGURATION BITS FOR THE MCP3204 Communication with the MCP3204/3208 devices is accomplished using a standard SPI-compatible serial Control Bit Selections interface. Initiating communication with either device is Input Channel done by bringing the CS line low (see Figure5-1). If the Configuration Selection Single/ device was powered up with the CS pin low, it must be D2* D1 D0 Diff brought high and back low to initiate communication. The first clock received with CS low and D high will 1 X 0 0 single-ended CH0 IN constitute a start bit. The SGL/DIFF bit follows the start 1 X 0 1 single-ended CH1 bit and will determine if the conversion will be done 1 X 1 0 single-ended CH2 using single-ended or differential input mode. The next 1 X 1 1 single-ended CH3 three bits (D0, D1 and D2) are used to select the input channel configuration. Table5-1 and Table5-2 show 0 X 0 0 differential CH0 = IN+ the configuration bits for the MCP3204 and MCP3208, CH1 = IN- respectively. The device will begin to sample the ana- 0 X 0 1 differential CH0 = IN- log input on the fourth rising edge of the clock after the CH1 = IN+ start bit has been received. The sample period will end 0 X 1 0 differential CH2 = IN+ on the falling edge of the fifth clock following the start CH3 = IN- bit. 0 X 1 1 differential CH2 = IN- Once the D0 bit is input, one more clock is required to CH3 = IN+ complete the sample and hold period (D is a “don’t IN * D2 is a “don’t care” for MCP3204 care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 clocks will output the result of the conversion with MSB TABLE 5-2: CONFIGURATION BITS FOR first, as shown in Figure5-1. Data is always output from THE MCP3208 the device on the falling edge of the clock. If all 12 data Control Bit bits have been transmitted and the device continues to Selections Input Channel receive clocks while the CS is held low, the device will Configuration Selection output the conversion result LSB first, as shown in Single D2 D1 D0 Figure5-2. If more clocks are provided to the device /Diff while CS is still low (after the LSB first data has been 1 0 0 0 single-ended CH0 transmitted), the device will clock out zeros indefinitely. 1 0 0 1 single-ended CH1 If necessary, it is possible to bring CS low and clock in 1 0 1 0 single-ended CH2 leading zeros on the D line before the start bit. This is IN often done when dealing with microcontroller-based 1 0 1 1 single-ended CH3 SPI ports that must send 8 bits at a time. Refer to 1 1 0 0 single-ended CH4 Section6.1 for more details on using the MCP3204/ 1 1 0 1 single-ended CH5 3208 devices with hardware SPI ports. 1 1 1 0 single-ended CH6 1 1 1 1 single-ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = IN- CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+  2002 Microchip Technology Inc. DS21298C-page 15

MCP3204/3208 tCYC tCYC t CSH CS t SUCS CLK DIN StartSDGIFLF/ D2 D1 D0 Don’t Care StartSDGIFLF/ D2 HI-Z Null HI-Z DOUT Bit B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* t CONV t t ** SAMPLE DATA * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, followed by zeros indefinitely (see Figure5-2 below). ** t : during this time, the bias current and the comparator power down while the reference input becomes DATA a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with the MCP3204 or MCP3208. t CYC t CSH CS t SUCS Power Down CLK Start DIN D2D1D0 Don’t Care SGL/ DIFF HI-Z Null * HI-Z DOUT Bit B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9B10B11 (MSB) t tCONV tDATA ** SAMPLE * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** t : During this time, the bias circuit and the comparator power down while the reference input becomes a DATA high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3204 or MCP3208 in LSB First Format. DS21298C-page 16  2002 Microchip Technology Inc.

MCP3204/3208 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the ris- ing edge. Because communication with the MCP3204/ 3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. As an example, Figure6-1 and Figure6-2 illustrate how the MCP3204/3208 can be interfaced to a MCU with a hardware SPI port. Figure6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As is shown in Figure6-1, the first byte transmitted to the A/D converter contains five leading zeros before the start bit. Arranging the leading zeros this way allows the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 12. Once the second eight clocks have been sent to the device, the MCU’s receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. Figure6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock.  2002 Microchip Technology Inc. DS21298C-page 17

MCP3204/3208 CS MCU latches data from A/D converter on rising edges of SCLK SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2233 24 Data is clocked out of A/D converter on falling edges DIN StartDSGIFLF/ D2 D1 DO DDono’nt’ tC Caarree DOUT HI-Z NUBLITL B11B10 B9 B8 B7 B6 B5 B4 B3 B2 BB11 B0 Start MCU Transmitted Data Bit (eAdlgigen oefd c wloitchk )falling 00 00 00 00 00 11 DSSDGIGIFFLFLF//DD22 DD11 DDOO XX XX XX XX XX XXX XX XX XX XX XX XX XX XX MCU Received Data (eAdlgigen oefd c wloicthk )rising ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ((NN00uullll))BB1111BB1100 BB99 BB88 BB77 BB66 BB55 BB44 BB33 BB22 BB11 BB00 Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of first register after transmission of register after transmission of last X = “Don’t Care” Bits 8 bits second 8 bits 8 bits FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from A/D converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK Data is clocked out of A/D converter on falling edges DIN StartSDGIFLF/ D2 D1 DDOO Don’t Care DOUT HI-Z NBUILTLB11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Start MCU Transmitted Data Bit (Aligned with falling 0 0 0 0 0 1 SGL/ D2 D1 DO X X X X X X X X X X X X X X edge of clock) DIFF MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? ? ? ? 0 B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (Null) edge of clock) Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive register after transmission of first register after transmission of register after transmission of last X = “Don’t Care” Bits 8 bits second 8 bits 8 bits FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). DS21298C-page 18  2002 Microchip Technology Inc.

MCP3204/3208 6.2 Maintaining Minimum Clock 6.3 Buffering/Filtering the Analog Speed Inputs When the MCP3204/3208 initiates the sample period, If the signal source for the A/D converter is not a low charge is stored on the sample capacitor. When the impedance source, it will have to be buffered or inaccu- sample period is complete, the device converts one bit rate conversion results may occur (see Figure4-2). It is for each clock that is received. It is important for the also recommended that a filter be used to eliminate any user to note that a slow clock rate will allow charge to signals that may be aliased back into the conversion bleed off the sample capacitor while the conversion is results, as is illustrated in Figure6-3, where an op amp taking place. At 85°C (worst case condition), the part is used to drive the analog input of the MCP3204/3208. will maintain proper charge on the sample capacitor for This amplifier provides a low impedance source for the at least 1.2ms after the sample period has ended. This converter input, and a low pass filter, which eliminates means that the time between the end of the sample unwanted high frequency noise. period and the time that all 12 data bits have been Low pass (anti-aliasing) filters can be designed using clocked out must not exceed 1.2ms (effective clock Microchip’s free interactive FilterLab™ software. Filter- frequency of 10kHz). Failure to meet this criterion may Lab will calculate capacitor and resistor values, as well introduce linearity errors into the conversion outside as determine the number of poles that are required for the rated specifications. It should be noted that during the application. For more information on filtering sig- the entire conversion cycle, the A/D converter does not nals, see AN699, “Anti-Aliasing Analog Filters for Data require a constant clock speed or duty cycle, as long as Acquisition Systems”. all timing specifications are met. V DD 10µF 4.096V Reference 0.1µF 1µF MCP1541 1µF IN+ V REF MCP3204 C1 MCP601 IN- R 1 V + IN R 2 - C 2 R 4 R 3 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3204.  2002 Microchip Technology Inc. DS21298C-page 19

MCP3204/3208 6.4 Layout Considerations 6.5 Utilizing the Digital and Analog Ground Pins When laying out a printed circuit board for use with analog components, care should be taken to reduce The MCP3204/3208 devices provide both digital and noise wherever possible. A bypass capacitor should analog ground connections to provide another means always be used with this device, placed as close as of noise reduction. As shown in Figure6-5, the analog possible to the device pin. A bypass capacitor value of and digital circuitry is separated internal to the device. 1µF is recommended. This reduces noise from the digital portion of the device Digital and analog traces should be separated as much being coupled into the analog portion of the device. The as possible on the board, with no traces running under- two grounds are connected internally through the sub- neath the device or the bypass capacitor. Extra precau- strate, which has a resistance of 5 -10Ω. tions should be taken to keep traces with high If no ground plane is utilized, then both grounds must frequency signals (such as clock lines) as far as be connected to V on the board. If a ground plane is SS possible from analog traces. available, both digital and analog ground pins should Use of an analog ground plane is recommended in be connected to the analog ground plane. If both an order to keep the ground potential the same for all analog and a digital ground plane are available, both devices on the board. Providing V connections to the digital and the analog ground pins should be con- DD devices in a “star” configuration can also reduce noise nected to the analog ground plane. Following these by eliminating return current paths and associated steps will reduce the amount of digital noise from the errors (see Figure6-4). For more information on layout rest of the board being coupled into the A/D converter. tips when using A/D converters, refer to AN688, “Layout Tips for 12-Bit A/D converter Applications”. V DD V DD MCP3204/08 Connection Digital Side Analog Side -SPI Interface -Sample Cap -Shift Register -Capacitor Array -Control Logic -Comparator Substrate Device 4 Device 1 5 - 10Ω DGND AGND 0.1µF Device 3 Analog Ground Plane Device 2 FIGURE 6-5: Separation of Analog and Digital Ground Pins. FIGURE 6-4: V traces arranged in a DD ‘Star’ configuration in order to reduce errors caused by current return paths. DS21298C-page 20  2002 Microchip Technology Inc.

MCP3204/3208 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX MCP3204-B XXXXXXXXXXXXXX I/P YYWWNNN YYWWNNN 14-Lead SOIC (150 mil) Example: XXXXXXXXXXX MCP3204-B XXXXXXXXXXX XXXXXXXXXXX YYWWNNN YYWWNNN 14-Lead TSSOP (4.4mm) * Example: XXXXXXXX 3204-C YYWW IYWW NNN NNN * Please contact Microchip Factory for B-Grade TSSOP devices Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.  2002 Microchip Technology Inc. DS21298C-page 21

MCP3204/3208 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3304) Example: XXXXXXXXXXXXXX MCP3208-B XXXXXXXXXXXXXX I/P YYWWNNN YYWWNNN 16-Lead SOIC (150 mil) (MCP3304) Example: XXXXXXXXXXXXX MCP3208-B XXXXXXXXXXXXX XXXXXXXXXX YYWWNNN IYWWNNN DS21298C-page 22  2002 Microchip Technology Inc.

MCP3204/3208 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005  2002 Microchip Technology Inc. DS21298C-page 23

MCP3204/3208 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21298C-page 24  2002 Microchip Technology Inc.

MCP3204/3208 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ β A1 A2 L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B1 .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087  2002 Microchip Technology Inc. DS21298C-page 25

MCP3204/3208 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 α n 1 E A A2 c L β A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 .036 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 DS21298C-page 26  2002 Microchip Technology Inc.

MCP3204/3208 16-Lead Plastic Small Outline (SL) –Narrow 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A A2 φ L A1 β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 16 16 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .057 .061 1.32 1.44 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .386 .390 .394 9.80 9.91 10.01 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108  2002 Microchip Technology Inc. DS21298C-page 27

MCP3204/3208 NOTES: DS21298C-page 28  2002 Microchip Technology Inc.

MCP3204/3208 ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and Connecting to the Microchip Internet Web Site 1-480-792-7302 for the rest of the world. The Microchip web site is available at the following URL: 092002 www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2002 Microchip Technology Inc. DS21298C-page29

MCP3204/3208 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: MCP3204/3208 Literature Number: DS21298C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21298C-page30  2002 Microchip Technology Inc.

MCP3204/08 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X X /XX Examples: Device Grade Temperature Package a) MCP3204-BI/P: ±1LSB INL, Industrial Tem- Range perature, PDIP package. b) MCP3204-BI/SL: ±1LSB INL, Industrial Temperature, SOIC package. Device: MCP3204: 4-Channel 12-Bit Serial A/D Converter c) MCP3204-CI/ST: ±2LSB INL, Industrial MCP3204T: 4-Channel 12-Bit Serial A/D Converter Temperature, TSSOP package. (Tape and Reel) MCP3208: 8-Channel 12-Bit Serial A/D Converter MCP3208T: 8-Channel 12-Bit Serial A/D Converter a) MCP3208-BI/P: ±1LSB INL, Industrial (Tape and Reel) Temperature, PDIP package. b) MCP3208-BI/SL: ±1LSB INL, Industrial Grade: B = ±1LSB INL Temperature, SOIC package. C = ±2LSB INL c) MCP3208-CI/ST: ±2LSB INL, Industrial Temperature, TSSOP package. Temperature Range: I = -40°C to +85°C Package: P = Plastic DIP (300 mil Body), 14-lead, 16-lead SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2002 Microchip Technology Inc. DS21298C-page31

MCP3204/08 NOTES: DS21298C-page 32  2002 Microchip Technology Inc.

Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, KEELOQ, ensure that your application meets with your specifications. MPLAB, PIC, PICmicro, PICSTART and PRO MATE are No representation or warranty is given and no liability is registered trademarks of Microchip Technology Incorporated assumed by Microchip Technology Incorporated with respect in the U.S.A. and other countries. to the accuracy or use of such information, or infringement of FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL patents or other intellectual property rights arising from such and The Embedded Control Solutions Company are use or otherwise. Use of Microchip’s products as critical com- registered trademarks of Microchip Technology Incorporated ponents in life support systems is not authorized except with in the U.S.A. express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, rights. FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc. DS21298C - page 33

M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia Microchip Technology Japan K.K. Benex S-1 6F 2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd 3-18-20, Shinyokohama Chandler, AZ 85224-6199 Suite 22, 41 Rawson Street Kohoku-Ku, Yokohama-shi Tel: 480-792-7200 Fax: 480-792-7277 Epping 2121, NSW Kanagawa, 222-0033, Japan Technical Support: 480-792-7627 Australia Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Web Address: http://www.microchip.com Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Korea Rocky Mountain China - Beijing Microchip Technology Korea 2355 West Chandler Blvd. Microchip Technology Consulting (Shanghai) 168-1, Youngbo Bldg. 3 Floor Chandler, AZ 85224-6199 Co., Ltd., Beijing Liaison Office Samsung-Dong, Kangnam-Ku Tel: 480-792-7966 Fax: 480-792-4338 Unit 915 Seoul, Korea 135-882 Bei Hai Wan Tai Bldg. Atlanta Tel: 82-2-554-7200 Fax: 82-2-558-5934 No. 6 Chaoyangmen Beidajie 500 Sugar Mill Road, Suite 200B Singapore Beijing, 100027, No. China Atlanta, GA 30350 Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Singapore Pte Ltd. Tel: 770-640-0034 Fax: 770-640-0307 200 Middle Road China - Chengdu Boston #07-02 Prime Centre Microchip Technology Consulting (Shanghai) 2 Lan Drive, Suite 120 Singapore, 188980 Westford, MA 01886 Co., Ltd., Chengdu Liaison Office Tel: 65-6334-8870 Fax: 65-6334-8850 Rm. 2401, 24th Floor, Tel: 978-692-3848 Fax: 978-692-3821 Taiwan Ming Xing Financial Tower Chicago Microchip Technology (Barbados) Inc., No. 88 TIDU Street 333 Pierce Road, Suite 180 Chengdu 610016, China Taiwan Branch Itasca, IL 60143 Tel: 86-28-86766200 Fax: 86-28-86766599 11F-3, No. 207 Tel: 630-285-0071 Fax: 630-285-0075 Tung Hua North Road China - Fuzhou Dallas Taipei, 105, Taiwan 4570 Westgrove Drive, Suite 160 Microchip Technology Consulting (Shanghai) Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Co., Ltd., Fuzhou Liaison Office Addison, TX 75001 Unit 28F, World Trade Plaza Tel: 972-818-7423 Fax: 972-818-2924 No. 71 Wusi Road EUROPE Detroit Fuzhou 350001, China Austria Tri-Atria Office Building Tel: 86-591-7503506 Fax: 86-591-7503521 32255 Northwestern Highway, Suite 190 China - Shanghai Microchip Technology Austria GmbH Farmington Hills, MI 48334 Microchip Technology Consulting (Shanghai) Durisolstrasse 2 Tel: 248-538-2250 Fax: 248-538-2260 A-4600 Wels Co., Ltd. Kokomo Room 701, Bldg. B Austria 2767 S. Albright Road Far East International Plaza Tel: 43-7242-2244-399 Kokomo, Indiana 46902 No. 317 Xian Xia Road Fax: 43-7242-2244-393 Denmark Tel: 765-864-8360 Fax: 765-864-8387 Shanghai, 200051 Los Angeles Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Microchip Technology Nordic ApS Regus Business Centre 18201 Von Karman, Suite 1090 China - Shenzhen Lautrup hoj 1-3 Irvine, CA 92612 Microchip Technology Consulting (Shanghai) Ballerup DK-2750 Denmark Tel: 949-263-1888 Fax: 949-263-1338 Co., Ltd., Shenzhen Liaison Office Tel: 45 4420 9895 Fax: 45 4420 9910 New York Rm. 1315, 13/F, Shenzhen Kerry Centre, France 150 Motor Parkway, Suite 202 Renminnan Lu Microchip Technology SARL Hauppauge, NY 11788 Shenzhen 518001, China Parc d’Activite du Moulin de Massy Tel: 631-273-5305 Fax: 631-273-5335 Tel: 86-755-2350361 Fax: 86-755-2366086 43 Rue du Saule Trapu San Jose China - Hong Kong SAR Batiment A - ler Etage Microchip Technology Inc. Microchip Technology Hongkong Ltd. 91300 Massy, France 2107 North First Street, Suite 590 Unit 901-6, Tower 2, Metroplaza Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 San Jose, CA 95131 223 Hing Fong Road Germany Tel: 408-436-7950 Fax: 408-436-7955 Kwai Fong, N.T., Hong Kong Microchip Technology GmbH Toronto Tel: 852-2401-1200 Fax: 852-2401-3431 Steinheilstrasse 10 6285 Northam Drive, Suite 108 India D-85737 Ismaning, Germany Mississauga, Ontario L4V 1X5, Canada Microchip Technology Inc. Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Tel: 905-673-0699 Fax: 905-673-6509 India Liaison Office Italy Divyasree Chambers Microchip Technology SRL 1 Floor, Wing A (A3/A4) Centro Direzionale Colleoni No. 11, O’Shaugnessey Road Palazzo Taurus 1 V. Le Colleoni 1 Bangalore, 560 025, India 20041 Agrate Brianza Tel: 91-80-2290061 Fax: 91-80-2290062 Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 08/01/02 DS21298C-page 34  2002 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: MCP3204-BI/SL MCP3204-CI/ST MCP3204-CI/SL MCP3204-CI/P MCP3204T-CI/ST MCP3204T-CI/SL MCP3204T-BI/SL MCP3204-BI/P