MC74HC4538A Dual Precision Monostable Multivibrator (Retriggerable, Resettable) The MC74HC4538A is identical in pinout to the MC14538B. Thedevice inputs are compatible with standard CMOS outputs; with http://onsemi.com pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces aprecision output pulse over a wide range of pulse widths. Because the device has conditioned trigger inputs, there are no trigger−input SOIC−16 TSSOP−16 rise and fall time restrictions. The output pulse width is determined by D SUFFIX DT SUFFIX the external timing components, R and C . The device has a reset CASE 751B CASE 948F x x function which forces the Q output low and the Q output high, PIN ASSIGNMENT regardless of the state of the output pulse circuitry. Features GND 1 16 VCC • CX1/RX1 2 15 GND Unlimited Rise and Fall Times Allowed on the Trigger Inputs • RESET 1 3 14 CX2/RX2 Output Pulse is Independent of the Trigger Pulse Width A1 4 13 RESET 2 • ± 10% Guaranteed Pulse Width Variation from Part to Part B1 5 12 A2 (Using the Same Test Jig) Q1 6 11 B2 • Output Drive Capability: 10 LSTTL Loads Q1 7 10 Q2 • Outputs Directly Interface to CMOS, NMOS and TTL GND 8 9 Q2 • Operating Voltage Range: 3.0 to 6.0 V • Low Input Current: 1.0 (cid:2)A MARKING DIAGRAMS • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard 16 No. 7A HC4538AG • Chip Complexity: 145 FETs or 36 Equivalent Gates AWLYWW • NLV Prefix for Automotive and Other Applications Requiring 1 Unique Site and Control Change Requirements; AEC−Q100 SOIC−16 Qualified and PPAP Capable • 16 These Devices are Pb−Free, Halogen Free and are RoHS Compliant HC45 38A ALYW(cid:2) (cid:2) 1 TSSOP−16 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or (cid:2) = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: August, 2014 − Rev. 15 MC74HC4538A/D

MC74HC4538A FUNCTION TABLE Inputs Outputs Reset A B Q Q H H H L H X L Not Triggered H H X Not Triggered H L,H, H Not Triggered H L L,H, Not Triggered L X X L H X X Not Triggered CX1 RX1 VCC 1 2 PIN 16 = VCC TRIGGER A1 4 6 Q1 PRIXN A 8N =D G CNXD ARE EXTERNAL COMPONENTS INPUTS B1 5 7 Q1 PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND 3 RESET 1 CX2 RX2 VCC 15 14 TRIGGER A2 12 10 Q2 INPUTS B2 11 9 Q2 13 RESET 2 Figure 1. Logic Diagram ORDERING INFORMATION Device Package Shipping† MC74HC4538ADG SOIC−16 48 Units / Rail (Pb−Free) MC74HC4538ADR2G SOIC−16 2500 / Tape & Reel (Pb−Free) NLV74HC4538ADR2G* SOIC−16 2500 / Tape & Reel (Pb−Free) MC74HC4538ADTR2G TSSOP−16 2500 / Tape & Reel (Pb−Free) NLVHC4538ADTR2G* TSSOP−16 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable http://onsemi.com 2

MC74HC4538A MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VI DC Input Voltage −0.5 ≤ VI ≤ VCC + 0.5 V VO DC Output Voltage (Note 1) −0.5 ≤ VO ≤ VCC + 0.5 V IIK DC Input Diode Current A, B, Reset ±20 mA CX, RX ±30 IOK DC Output Diode Current ±25 mA IO DC Output Sink Current ±25 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 (cid:3)C TL Lead temperature, 1 mm from Case for 10 Seconds 260 (cid:3)C TJ Junction temperature under Bias +150 (cid:3)C (cid:3)JA Thermal resistance SOIC 112 (cid:3)C/W TSSOP 148 PD Power Dissipation in Still Air at 85(cid:3)C SOIC 500 mW TSSOP 450 MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% − 35% UL−94−VO (0.125 in) VESD ESD Withstand Voltage Human Body Model (Note 2) > 2000 V Machine Model (Note 3) > 100 Charged Device Model (Note 4) > 500 ILatchup Latchup Performance Above VCC and Below GND at 85(cid:3)C (Note 5) ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types –55 +125 (cid:3)C tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns (Figure 6) VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 A or B (Figure 4) − No Limit Rx External Timing Resistor VCC < 4.5 V 1.0 † k(cid:4) VCC ≥ 4.5 V 2.0 † Cx External Timing Capacitor 0 † (cid:2)F Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. †The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10(cid:2)F/1.0M(cid:4). Values of Cx>1.0(cid:2)F may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for Rx>1.0M(cid:4). 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 3

MC74HC4538A DC CHARACTERISTICS Guaranteed Limits –55 to 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C VCC Symbol Parameter Test Conditions V Min Typ Max Min Typ Max Min Typ Max Unit VIH Minimum Vout = 0.1 V or VCC – 2.0 1.5 1.5 1.5 V High−Level 0.1 V 4.5 3.15 3.15 3.15 Input Voltage |Iout| ≤ 20 (cid:2)A 6.0 4.2 4.2 4.2 VIL Maximum Vout = 0.1 V or VCC – 2.0 0.5 0.5 0.5 V Low−Level 0.1 V 4.5 1.35 1.35 1.35 Input Voltage |Iout| ≤ 20 (cid:2)A 6.0 1.8 1.8 1.8 VOH Minimum Vin = VIH or VIL 2.0 1.9 1.9 1.9 V High−Level |Iout| ≤ 20 (cid:2)A 4.5 4.4 4.4 4.4 Output Voltage 6.0 5.9 5.9 5.9 Vin = VIH or VIL |Iout| ≤ −4.0 mA 4.5 3.98 3.84 3.7 |Iout| ≤ −5.2 mA 6.0 5.48 5.34 5.2 VOL Maximum Vin = VIH or VIL 2.0 0.1 0.1 0.1 V Low−Level |Iout| ≤ 20 (cid:2)A 4.5 0.1 0.1 0.1 Output Voltage 6.0 0.1 0.1 0.1 Vin = VIH or VIL |Iout| ≤ 4.0 mA 4.5 0.26 0.33 0.4 |Iout| ≤ 5.2 mA 6.0 0.26 0.33 0.4 Iin Maximum Input Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A Leakage Current (A, B, Reset) Iin Maximum Input Vin = VCC or GND 6.0 ±50 ±500 ±500 nA Leakage Current (Rx, Cx) ICC Maximum Vin = VCC or GND 6.0 130 220 350 (cid:2)A Quiescent Q1 and Q2 = Low Supply Current Iout = 0 (cid:2)A (per package) Standby State ICC Maximum Supply Vin = VCC or GND Current Q1 and Q2 = High 25(cid:3)C –45(cid:3)C to 85(cid:3)C –55(cid:3)C to 125(cid:3)C (per package) Iout = 0 (cid:2)A Active State Pins 2 and 14 = 0.5 VCC 6.0 400 600 800 (cid:2)A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 4

MC74HC4538A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limits –55 to 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C VCC Symbol Parameter V Min Max Min Max Min Max Unit tPLH Maximum Propagation Delay 2.0 175 220 265 ns Input A or B to Q 4.5 35 44 53 (Figures 5 and 7) 6.0 30 37 45 tPHL Maximum Propagation Delay 2.0 195 245 295 ns Input A or B to NQ 4.5 39 49 59 (Figures 5 and 7) 6.0 33 42 50 tPHL Maximum Propagation Delay 2.0 175 220 265 ns Reset to Q 4.5 35 44 53 (Figures 6 and 7) 6.0 30 37 45 tPLH Maximum Propagation Delay 2.0 175 220 265 ns Reset to NQ 4.5 35 44 53 (Figures 6 and 7) 6.0 30 37 45 tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns tTHL (Figures 6 and 7) 4.5 15 19 22 6.0 13 16 19 Cin Maximum Input Capacitance (A. B, Reset) − 10 10 10 pF (Cx, Rx) 25 25 25 Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (per Multivibrator)* 150 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. TIMING CHARACTERISTICS (Input tr = tf = 6.0 ns) Guaranteed Limits –55 to 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C VCC Symbol Parameter V Min Max Min Max Min Max Unit trr Minimum Retrigger Time, Input A or B 2.0 − − ns (Figure 6) (Note 7) 4.5 − − 6.0 − − trec Minimum Recovery Time, Inactive to A or B 2.0 0 0 0 ns (Figure 6) 4.5 0 0 0 6.0 0 0 0 tw Minimum Pulse Width, Input A or B 2.0 60 75 90 ns (Figure 5) 4.5 12 15 18 6.0 10 13 15 tw Minimum Pulse Width, Reset 2.0 60 75 90 ns (Figure 6) 4.5 12 15 18 6.0 10 13 15 tr, tf Maximum Input Rise and Fall Times, Reset 2.0 1000 1000 1000 ns (Figure 6) 4.5 500 500 500 6.0 400 400 400 A or B 2.0 (Figure 6) 4.5 No Limit 6.0 7. V (volts)(cid:3)C (pF) t (ns)(cid:2) CC x rr 30.5 http://onsemi.com 5

MC74HC4538A OUTPUT PULSE WIDTH CHARACTERISTICS (Rx = 10 k(cid:4), Cx = 0.1 (cid:2)F, CL = 50 pF) Conditions Guaranteed Limits –55 to 25(cid:3)C ≤ 85(cid:3)C ≤ 125(cid:3)C VCC Symbol Parameter Timing Components V Min Max Min Max Min Max Unit Output Pulse Width (Note 8) 0.63 0.77 0.6 0.8 0.59 0.81 ms (Figures 5 and 6) τ Pulse Width Match Between Rx = 10 k(cid:4), 5.0 ±5.0 % Circuits in the same Package Cx = 0.1 (cid:2)F Pulse Width Match Variation ±10 % (Part to Part) (Note 10) OUTPUT PULSE WIDTH CHARACTERISTICS (Rx = 100 k(cid:4), Cx = 1 nF, CL = 50 pF) Conditions Guaranteed Limits Timing VCC Ambient Symbol Parameter Components V Temperature Min Typ Max Unit Output Pulse Width (Note 9) 25°C − 79 − (cid:2)s Pulse Width Match Between Circuits in the −55 to 125°C −5.0 − +5.0 % τ same Package Pulse Width Match Variation (Part to Part) Rx = 100 k(cid:4), 5.0 −55 to 125°C −10 − +10 % (Note 10) Cx = 1 nF − Temperature Variance −55 to 125°C − +0.05 − (cid:2)s/°C − Power Supply Variance −55 to 125°C − −8.0 − (cid:2)s/V 8. τ = kRxCx and k = 0.7 for the output pulse width corresponding to Rx = 10 k(cid:4), Cx = 0.1 (cid:2)F. 9. τ = kRxCx and k = 0.79 for the output pulse width corresponding to Rx = 100 k(cid:4), Cx = 1 nF. 10.Pulse width match variation between ICs (part−to−part) is defined with identical Rx, Cx, VCC and a specific temperature. http://onsemi.com 6

MC74HC4538A TYPICAL CHARACTERISTICS 0.70 10 s NT TA = 25°C VCC = 5 V, TA = 25°C A 1 s ST τ) ON 0.65 TH ( 100 ms C D H WI 10 ms WIDTCAL)0.60 LSE 1 ms E PI U LSTY T P 100 (cid:2)s 1 M(cid:4) U( U P P 100 k(cid:4) T 0.55 T 10 (cid:2)s U U P O 10 k(cid:4) T 1 (cid:2)s U O 1 k(cid:4) k, 0.50 100 ns 1 2 3 4 5 6 7 0.00001 0.0001 0.001 0.01 0.1 1 10 VCC, POWER SUPPLY VOLTAGE (VOLTS) CAPACITANCE ((cid:2)F) Figure 2. Typical Output Pulse Width Constant, Figure 3. Output Pulse Width versus Timing k, versus Supply Voltage Capacitance (For output pulse widths > 100 (cid:2)s: τ = kR C ) x x 1.30 τH () MBER) 1.20 RCxx == 10 .M1 (cid:4)(cid:2)F TA = 25°C T U D N WI V SE O 5 1.10 L T U D P E 1.00 T Z U LI P A UT RM 0.90 Rx = 100 k(cid:4) O NO Cx = 1000 pF ( 0.80 1 2 3 4 5 6 7 VCC, POWER SUPPLY VOLTAGE (VOLTS) Figure 4. Normalized Output Pulse Width versus Power Supply Voltage 1.075 1.025 R) R) τOUTPUT PULSE WIDTH ()(cid:3)RMALIZED TO 25C NUMBE101..091.027.0555 VCCV C=C 3 = V 6 V τOUTPUT PULSE WIDTH ()(cid:3)RMALIZED TO 25C NUMBE 1111..00..00102155 VCC =V C5C.5 = V 4.V5C VC = 5 V O O N N ( ( 0.95 1.00 −75 −50 −25 0 25 50 75 100 125 150 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 5. Normalized Output Pulse Width Figure 6. Normalized Output Pulse Width versus versus Power Supply Voltage Power Supply Voltage http://onsemi.com 7

MC74HC4538A tw(H) VCC 50% A GND tw(L) B VCC 50% GND tPLH τ tPLH τ 50% Q tPHL τ tPHL τ Q 50% Figure 7. Switching Waveform tr tf 90% VCC A 10% GND trr VCC 50% B GND tf tf VCC 90% RESET 50% 10% GND tTLH tw(L) trec τ + trr tPHL 90% (RETRIGGERED PULSE) 50% 50% Q 10% tTHL tPLH Q 90% 50% 10% Figure 8. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 9. Test Circuit http://onsemi.com 8

MC74HC4538A PIN DESCRIPTIONS INPUTS capacitors (see the Block Diagram). Polystyrene capacitors are recommended for optimum pulse width control. A1, A2 (Pins 4, 12) Electrolytic capacitors are not recommended due to high Positive−edge trigger inputs. A rising−edge signal on leakages associated with these type capacitors. either of these pins triggers the corresponding multivibrator when there is a high level on the B1 or B2 input. GND (Pins 1 and 15) External ground. The external timing capacitors discharge B1, B2 (Pins 5, 11) to ground through these pins. Negative−edge trigger inputs. A falling−edge signal on either of these pins triggers the corresponding multivibrator OUTPUTS when there is a low level on the A1 or A2 input. Q1, Q2 (Pins 6, 10) Reset 1, Reset 2 (Pins 3, 13) Noninverted monostable outputs. These pins (normally Reset inputs (active low). When a low level is applied to low) pulse high when the multivibrator is triggered at either one of these pins, the Q output of the corresponding the A or the B input. The width of the pulse is determined by multivibrator is reset to a low level and the Q output is set to the external timing components, R and C . X X a high level. Q1, Q2 (Pins 7, 9) C 1/R 1 and C 2/R 2 (Pins 2 and 14) Inverted monostable outputs. These pins (normally high) X X X X External timing components. These pins are tied to the pulse low when the multivibrator is triggered at either the A common points of the external timing resistors and or the B input. These outputs are the inverse of Q1 and Q2. RxCx UPPER REFERENCE OUTPUT CIRCUIT LATCH − VCC + Vre, UPPER LOWER M1 VCC REFERENCE CIRCUIT 2 k(cid:4) − M2 + Q Vre, LOWER M3 Q TRIGGER CONTROL CIRCUIT A C Q TRIGGER CONTROL RESET CIRCUIT B CBR RESET POWER ON RESET RESET LATCH Figure 10. Logic Detail (1/2 the Device) http://onsemi.com 9

MC74HC4538A CIRCUIT OPERATION Figure 11 shows the HC4538A configured in the TRIGGER OPERATION retriggerable mode. Briefly, the device operates as follows The HC4538A is triggered by either a rising−edge signal (refer to Figure 10): In the quiescent state, the external at input A (#7) or a falling−edge signal at input B (#8), with timing capacitor, C , is charged to V . When a trigger the unused trigger input and the Reset input held at the x CC occurs, the Q output goes high and C discharges quickly to voltage levels shown in the Function Table. Either trigger x the lower reference voltage (V Lower (cid:4) 1/3 V ). C signal will cause the output of the trigger−control circuit to ref CC x then charges, through R , back up to the upper reference go high (#9). x voltage (V Upper (cid:4) 2/3 V ), at which point the The trigger−control circuit going high simultaneously ref CC one−shot has timed out and the Q output goes low. initiates two events. First, the output latch goes low, thus The following, more detailed description of the circuit taking the Q output of the HC4538A to a high state (#10). operation refers to both the logic detail (Figure 10) and the Second, transistor M3 is turned on, which allows the timing diagram (Figure 11). external timing capacitor, Cx, to rapidly discharge toward ground (#11). (Note that the voltage across C appears at the x QUIESCENT STATE input of both the upper and lower reference circuit In the quiescent state, before an input trigger appears, the comparator). output latch is high and the reset latch is high (#1 in Figure When C discharges to the reference voltage of the lower x 11). Thus the Q output (pin 6 or 10) of the monostable reference circuit (#12), the outputs of both reference circuits multivibrator is low (#2, Figure 11). will be high (#13). The trigger−control reset circuit goes high, The output of the trigger−control circuit is low (#3), and resetting the trigger−control circuit flip−flop to a low state transistors M1, M2, and M3 are turned off. The external (#14). This turns transistor M3 off again, allowing C to begin x timing capacitor, C , is charged to V (#4), and both the x CC to charge back up toward V , with a time constant t = R C CC x x upper and lower reference circuit has a low output (#5). (#15). Once the voltage across C charges to above the lower x In addition, the output of the trigger−control reset circuit reference voltage, the lower reference circuit will go low is low. allowing the monostable multivibrator to be retriggered. QUIESCENT TRIGGER CYCLE TRIGGER CYCLE STATE (A INPUT) (B INPUT) RESET RETRIGGER 7 trr TRIGGER INPUT A (PIN 4 OR 12) TRIGGER INPUT B (PIN 5 OR 11) 8 24 9 TRIGGER-CONTROL 3 14 CIRCUIT OUTPUT 4 11 21 23 RX/CX INPUT 15 17 12 (PIN 2 OR 14) Vref UPPER 25 Vref LOWER 13 UPPER REFERENCE 5 18 CIRCUIT 13 LOWER REFERENCE 6 16 CIRCUIT RESET INPUT (PIN 3 OR 13) 20 1 RESET LATCH 22 10 Q OUTPUT 2 19 (PIN 6 OR 10) τ τ τ + trr Figure 11. Timing Diagram http://onsemi.com 10

MC74HC4538A When C charges up to the reference voltage of the upper occurs, the output of the reset latch goes low (#22), turning x reference circuit (#17), the output of the upper reference on transistor M1. Thus C is allowed to quickly charge up to x circuit goes low (#18). This causes the output latch to toggle, V (#23) to await the next trigger signal. CC taking the Q output of the HC4538A to a low state (#19), and On power up of the HC4538A the power−on reset circuit completing the time−out cycle. will be high causing a reset condition. This will prevent the trigger−control circuit from accepting a trigger input during POWER−DOWN CONSIDERATIONS this state. The HC4538A’s Q outputs are low and the Q not Large values of C may cause problems when powering x outputs are high. down the HC4538A because of the amount of energy stored in the capacitor. When a system containing this device is RETRIGGER OPERATION powered down, the capacitor may discharge from V When used in the retriggerable mode (Figure 13), the CC through the input protection diodes at pin 2 or pin 14. HC4538A may be retriggered during timing out of the Current through the protection diodes must be limited to 30 output pulse at any time after the trigger−control circuit mA; therefore, the turn−off time of the V power supply flip−flop has been reset (#24), and the voltage across C is CC x must not be faster than t = V (cid:2)C /(30 mA). For example, above the lower reference voltage. As long as the C voltage CC x x if V = 5.0 V and C = 15 (cid:2)F, the V supply must turn off is below the lower reference voltage, the reset of the CC x CC no faster than t = (5.0 V)(cid:2)(15 (cid:2)F)/30 mA = 2.5 ms. This is flip−flop is high, disabling any trigger pulse. This prevents usually not a problem because power supplies are heavily M3 from turning on during this period resulting in an output filtered and cannot discharge at this rate. pulse width that is predictable. When a more rapid decrease of V to zero volts occurs, The amount of undershoot voltage on R C during the CC x x the HC4538A may sustain damage. To avoid this possibility, trigger mode is a function of loop delay, M3 conductivity, use an external damping diode, D , connected as shown in and V . Minimum retrigger time, trr (Figure 7), is a x DD Figure 12. Best results can be achieved if diode D is chosen function of 1) time to discharge R C from V to lower x x x DD to be a germanium or Schottky type diode able to withstand reference voltage (T ); 2) loop delay (T ); 3) discharge delay large current surges. time to charge R C from the undershoot voltage back to the x x lower reference voltage (T ). charge RESET AND POWER ON RESET OPERATION Figure 14 shows the device configured in the A low voltage applied to the Reset pin always forces the non−retriggerable mode. Q output of the HC4538A to a low state. For additional information, please see Application Note The timing diagram illustrates the case in which reset (AN1558/D) titled Characterization of Retrigger Time in occurs (#20) while C is charging up toward the reference x the HC4538A Dual Precision Monostable Multivibrator. voltage of the upper reference circuit (#21). When a reset DX CX VCC RX Q A B Q RESET Figure 12. Discharge Protection During Power Down http://onsemi.com 11

MC74HC4538A TYPICAL APPLICATIONS CX RX CX RX RISING−EDGE RISING−EDGE TRIGGER VCC TRIGGER VCC Q Q A A B Q B Q B = VCC RESET = VCC RESET = VCC CX RX CX RX FALLING−EDGE A = GND VCC TRIGGER VCC Q Q A B B Q Q FALLING−EDGE TRIGGER RESET = VCC RESET = VCC Figure 13. Retriggerable Monostable Circuitry Figure 14. Non−retriggerable Monostable Circuitry GND N/C A = GND RXCX Q N/C VCC B Q N/C RESET Figure 15. Connection of Unused Section ONE−SHOT SELECTION GUIDE 100ns 1(cid:2)s 10(cid:2)s100(cid:2)s 1ms 10ms 100ms 1s 10s MC14528B MC14536B 23 HR MC14538B MC14541B 5 MIN HC4538A* *Limited operating voltage (2−6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE http://onsemi.com 12

MC74HC4538A PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF NOTES: 0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S K 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD K1 FLASH. PROTRUSIONS OR GATE BURRS. ÇÉÇÉÇÉ MOLD FLASH OR GATE BURRS SHALL NOT 16 9 EXCEED 0.15 (0.006) PER SIDE. 2XL/2 J1 ÇÉÇÉÇÉ 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL B SECTION N−N NOT EXCEED 0.25 (0.010) PER SIDE. L −U− J 5D.ADMIMBAERN SPIROONT KR UDSOIEOSN N. AOLTL OINWCALUBLDEE DAMBAR PROTRUSION SHALL BE 0.08 PIN 1 (0.003) TOTAL IN EXCESS OF THE K IDENT. N DIMENSION AT MAXIMUM MATERIAL 1 8 0.25 (0.010) CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. M 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 0.15 (0.006) T U S A N MILLIMETERS INCHES −V− DIM MIN MAX MIN MAX F A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 DETAIL E C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC C −W− H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 0.10 (0.004) K 0.19 0.30 0.007 0.012 −T− SEATING H DETAIL E K1 0.19 0.25 0.007 0.010 PLANE D G ML 06 .(cid:3) 4 0 BSC8 (cid:3) 00. 2(cid:3) 52 BS8C (cid:3) SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13

MC74HC4538A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION 1 8 0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 F D 0.35 0.49 0.014 0.019 K R X 45(cid:3) F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X1.12 1 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74HC4538A/D 14

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