19-3185; Rev 4; 4/10 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers General Description Features M The MAX5417/MAX5418/MAX5419 nonvolatile, linear- (cid:1) Power-On Recall of Wiper Position from A taper, digital potentiometers perform the function of a Nonvolatile Memory mechanical potentiometer by replacing the mechanics (cid:1) Tiny 3mm x 3mm 8-Pin TDFN Package X with a simple 2-wire digital interface, allowing communi- cation with multiple devices. Each device performs the (cid:1) 35ppm/°C End-to-End Resistance Temperature 5 same function as a discrete potentiometer or variable Coefficient 4 resistor and has 256 tap points. (cid:1) 5ppm/°C Ratiometric Temperature Coefficient 1 The devices feature an internal, nonvolatile EEPROM (cid:1) 50kΩ/100kΩ/200kΩResistor Values 7 used to store the wiper position for initialization during power-up. The fast-mode I2C-compatible serial interface (cid:1) Fast I2C-Compatible Serial Interface /M allows communication at data rates up to 400kbps, mini- (cid:1) 500nA (typ) Static Supply Current mizing board space and reducing interconnection com- A (cid:1) Single-Supply Operation: +2.7V to +5.25V plexity in many applications. Each device is available with one of four factory-preset addresses (see the Ordering (cid:1) 256 Tap Positions X Information/Selector Guide) and features an address (cid:1) ±0.5 LSB DNL in Voltage-Divider Mode 5 input for a total of eight unique address combinations. (cid:1) ±0.5 LSB INL in Voltage-Divider Mode 4 The MAX5417/MAX5418/MAX5419 provide three nomi- 1 nal resistance values: 50kΩ (MAX5417), 100kΩ 8 (MAX5418), or 200kΩ (MAX5419). The nominal resistor Functional Diagram temperature coefficient is 35ppm/°C end-to-end, and / M only 5ppm/°C ratiometric. This makes the devices ideal for applications requiring a low-temperature-coefficient A variable resistor, such as low-drift, programmable gain- amplifier circuit configurations. H X The MAX5417/MAX5418/MAX5419 are available in a VDD S8H-BIFITT 8 L8A-TBCITH 8 PO2S5IT6I-ON 256 W 5 3mm x 3mm 8-pin TDFN package, and are specified GND REGISTER DECODER 4 over the extended -40°C to +85°C temperature range. L 1 Applications SDA I2C POR MAX5417 9 SCL INTERFACE 8-BIT MAX5418 Mechanical Potentiometer Replacement NV MAX5419 A0 MEMORY Low-Drift Programmable-Gain Amplifiers Volume Control Liquid-Crystal Display (LCD) Contrast Control Ordering Information/Selector Guide PART TEMP RANGE I2C ADDRESS R (kΩ) PIN-PACKAGE TOP MARK MAX5417LETA+ -40°C to +85°C 010100A0 50 8 TDFN-EP** AIB MAX5417META+ -40°C to +85°C 010101A0 50 8 TDFN-EP** ALS MAX5417NETA+ -40°C to +85°C 010110A0 50 8 TDFN-EP** ALT MAX5417PETA+ -40°C to +85°C 010111A0 50 8 TDFN-EP** ALU MAX5418LETA+ -40°C to +85°C 010100A0 100 8 TDFN-EP** AIC MAX5418META+ -40°C to +85°C 010101A0 100 8 TDFN-EP** ALV MAX5418NETA+ -40°C to +85°C 010110A0 100 8 TDFN-EP** ALW MAX5418PETA+ -40°C to +85°C 010111A0 100 8 TDFN-EP** ALX MAX5419LETA+ -40°C to +85°C 010100A0 200 8 TDFN-EP** AID MAX5419META+ -40°C to +85°C 010101A0 200 8 TDFN-EP** ALY MAX5419NETA+ -40°C to +85°C 010110A0 200 8 TDFN-EP** ALZ MAX5419PETA+ -40°C to +85°C 010111A0 200 8 TDFN-EP** AMA +Denotes a lead(Pb)-free/RoHS-compliant package. **Exposed pad. Pin Configuration appears at end of data sheet. ________________________________________________________________Maxim Integrated Products 1 For pricing, delivery, and ordering information,please contact Maxim Directat 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 ABSOLUTE MAXIMUM RATINGS 1 VDDto GND...........................................................-0.3V to +6.0V Continuous Power Dissipation (TA= +70°C) 4 All Other Pins to GND.................................-0.3V to (VDD+ 0.3V) 8-Pin TDFN (derate 24.4mW/°C above +70°C).........1951mW 5 Maximum Continuous Current into H, L, and W Operating Temperature Range...........................-40°C to +85°C MAX5417......................................................................±1.3mA Junction Temperature......................................................+150°C X MAX5418......................................................................±0.6mA Storage Temperature Range.............................-60°C to +150°C A MAX5419......................................................................±0.3mA Lead Temperature (soldering, 10s).................................+300°C Soldering Temperature (reflow).......................................+260°C M Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to / 8 absolute maximum rating conditions for extended periods may affect device reliability. 1 4 5 ELECTRICAL CHARACTERISTICS X (VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.) A M PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC PERFORMANCE (VOLTAGE-DIVIDER MODE) / 7 Resolution 256 Taps 1 Integral Nonlinearity INL (Note 1) ±0.5 LSB 4 Differential Nonlinearity DNL (Note 1) ±0.5 LSB 5 End-to-End Temperature X Coefficient TCR 35 ppm/°C A Ratiometric Temperature 5 ppm/°C M Coefficient MAX5417_, 50Ω -0.6 Full-Scale Error MAX5418_, 100kΩ -0.3 LSB MAX5419_, 200kΩ -0.15 MAX5417_, 50kΩ 0.6 Zero-Scale Error MAX5418_, 100kΩ 0.3 LSB MAX5419_, 200kΩ 0.15 DC PERFORMANCE (VARIABLE-RESISTOR MODE) Integral Nonlinearity VDD = 3V ±3 INL LSB (Note 2) VDD = 5V ±1.5 VDD = 3V, MAX5417_, 50kΩ -1 +2 Differential Nonlinearity VDD = 3V, MAX5418_, 100kΩ ±1 DNL LSB (Note 2) VDD = 3V, MAX5419_, 200kΩ ±1 VDD = 5V ±1 DC PERFORMANCE (RESISTOR CHARACTERISTICS) Wiper Resistance RW VDD = 3V to 5.25V (Note 3) 325 675 Ω Wiper Capacitance CW 10 pF MAX5417_ 37.5 50 62.5 End-to-End Resistance RHL MAX5418_ 75 100 125 kΩ MAX5419_ 150 200 250 2 _______________________________________________________________________________________

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers ELECTRICAL CHARACTERISTICS (continued) M (VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.) A DIGITAL INPUTS X VDD = 3.4V to 5.25V 2.4 5 Input High Voltage (Note 4) VIH V VDD < 3.4V 0.7 x VDD 4 Input Low Voltage VIL VDD = 2.7V to 5.25V (Note 4) 0.8 V 1 Low-Level Output Voltage VOL 3mA sink current 0.4 V 7 Input Leakage Current ILEAK ±1 µA /M Input Capacitance 5 pF A DYNAMIC CHARACTERISTICS X MAX5417_ 100 Wiper -3dB Bandwidth (Note 5) MAX5418_ 50 kHz 5 MAX5419_ 25 4 NONVOLATILE MEMORY 1 8 Data Retention TA = +85°C 50 Years / TA = +25°C 200,000 M Endurance Stores TA = +85°C 50,000 A POWER SUPPLY X Power-Supply Voltage VDD 2.70 5.25 V 5 Digital inputs = VDD or GND, Standby Current IDD 0.5 1 µA 4 TA = +25°C 1 During nonvolatile write; Programming Current 200 400 µA 9 digital inputs = VDD or GND (Note 6) TIMING CHARACTERISTICS (VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C. See Figures 1 and 2.) (Note 7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG SECTION MAX5417_ 500 Wiper Settling Time (Note 8) tIL MAX5418_ 600 ns MAX5419_ 1000 DIGITAL SECTION SCL Clock Frequency fSCL 400 kHz Setup Time for START Condition tSU-STA 0.6 µs Hold Time for START Condition tHD-STA 0.6 µs CLK High Time tHIGH 0.6 µs CLK Low Time tLOW 1.3 µs _______________________________________________________________________________________ 3

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 TIMING CHARACTERISTICS (continued) 1 (VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= 4 +25°C. See Figures 1 and 2.) (Note 7) 5 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X Data Setup Time tSU-DAT 100 ns A Data Hold Time tHD-DAT 0 0.9 µs M SDA, SCL Rise Time tR 300 ns 8/ SDA, SCL Fall Time tF 300 ns 1 Setup Time for STOP Condition tSU-STO 0.6 µs 4 Bus Free Time Between STOP tBUF Minimum power-up rate = 0.2V/ms 1.3 µs and START Condition 5 X Pulse Width of Spike Suppressed tSP 50 ns A Maximum Capacitive Load for CB (Note 9) 400 pF Each Bus Line M Write NV Register Busy Time tBUSY (Note 10) 12 ms / 7 Note 1: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDDand L = GND. The 1 wiper terminal is unloaded and measured with a high-input-impedance voltmeter. 4 Note 2: The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = GND. 5 For the 5V condition, the wiper terminal is driven with a source current of 80µA for the 50kΩconfiguration, 40µA for the 100kΩconfiguration, and 20µA for the 200kΩconfiguration. For the 3V condition, the wiper terminal is driven with a source X current of 40µA for the 50kΩconfiguration, 20µA for the 100kΩconfiguration, and 10µA for the 200kΩconfiguration. A Note 3: The wiper resistance is measured using the source currents given in Note 2. For operation to VDD= 2.7V, see Wiper Resistance vs. Temperature in the Typical Operating Characteristics. M Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD- 0.5V) and (GND + 0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 5: Wiper at midscale with a 10pF load (DC measurement). L = GND; an AC source is applied to H; and the W output is mea- sured. A 3dB bandwidth occurs when the AC W/H value is 3dB lower than the DC W/H value. Note 6: The programming current operates only during power-up and NV writes. Note 7: SCL clock period includes rise and fall times tRand tF. All digital input signals are specified with tR= tF= 2ns and timed from a voltage level of (VIL+ VIH) / 2. Note 8: Wiper settling time is the worst-case 0% to 50% rise time measured between consecutive wiper positions. H = VDD, L = GND, and the wiper terminal is unloaded and measured with a 10pF oscilloscope probe (see the Typical Operating Characteristicsfor the tap-to-tap switching transient). Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf. Note 10: The idle time begins from the initiation of the stop pulse. 4 _______________________________________________________________________________________

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers Typical Operating Characteristics M (VDD= +5V, TA= +25°C, unless otherwise noted.) A X 5 DNL vs. TAP POSITION INL vs. TAP POSITION WIPER RESISTANCE vs. TAP POSITION 4 000...212055 VOLTAGE-DIVIDER MODE MAX5417 toc01 000...212055 VOLTAGE-DIVIDER MODE MAX5417 toc02 670000 VISDRDC == 25.07µVA MAX5417 toc03 17 / 0.10 0.10 500 M Ω) DNL (LSB)-00..00055 INL (LSB)-00..00055 SISTANCE ( 340000 AX E R -0.10 -0.10 200 5 -0.15 -0.15 4 100 -0.20 -0.20 1 -0.25 -0.25 0 8 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 / TAP POSITION TAP POSITION TAP POSITION M END-TO-END RESISTANCE % CHANGE A WIPER TRANSIENT AT POWER-ON vs. TEMPERATURE MAX5417 toc04 V2VD/Ddiv ANGE 001...680 MAX5417 toc05 X54 H C % 0.4 1 W E 1V/div ANC 0.2 9 ST 0 SI E D R -0.2 N O-E -0.4 CL = 10pF D-T -0.6 TAP = 128 N E H = VDD -0.8 -1.0 4µs/div -40 -15 10 35 60 85 TEMPERATURE (°C) STANDBY SUPPLY CURRENT vs. TEMPERATURE WIPER RESISTANCE vs. TEMPERATURE µNT (A) 01..80 MAX5417 toc06 567000000 VDD = 2.7V MAX5417 toc07 RE Ω) Y CUR 0.6 NCE ( 400 VDD = 3.0V L A P T Y SUP 0.4 RESIS 300 VDD = 4.5V B AND 200 VDD = 5.25V T 0.2 S 100 0 0 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) _______________________________________________________________________________________ 5

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 Typical Operating Characteristics (continued) 1 (VDD= +5V, TA= +25°C, unless otherwise noted.) 4 5 SUPPLY CURRENT INL vs. TAP POSITION X vs. DIGITAL INPUT VOLTAGE THD+N RESPONSE (MAX5417) MA 560000 MAX5417 toc08 11000 12:01H Rz ATTOIO 20kHz BANDPASS MAX5417 toc09 23..50 VVISDARDRC I =A= B25L.07EµV-A RESISTOR MODE MAX5417 toc10 5418/ µPLY CURRENT (A) 340000 THD+N (%) 0.11 INL (LSB) 0112....5050 UP 200 0.01 X S 0 A 100 0.001 -0.5 M 0 0.0001 -1.0 0 1 2 3 4 5 10 100 1k 10k 100k 0 32 64 96 128 160 192 224 256 / 7 DIGITAL INPUT VOLTAGE (V) FREQUENCY (Hz) TAP POSITION 1 INL vs. TAP POSITION INL vs. TAP POSITION 4 (MAX5418) (MAX5419) AX5 12..50 VVISDARDRC I =A= B22L.07EµV-A RESISTOR MODE MAX5417 toc11 01..7050 VVISADRDRC I =A= B21L.07EµV-ARESISTOR MODE MAX5417 toc12 0.50 M 1.0 0.25 NL (LSB) 0.5 NL (LSB) 0 I I -0.25 0 -0.50 -0.5 -0.75 -1.0 -1.00 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 TAP POSITION TAP POSITION DNL vs. TAP POSITION DNL vs. TAP POSITION (MAX5417) (MAX5418) 00..45 VARIABLE-RESISTOR MODE MAX5417 toc13 00..23 VVISDARDRC I =A= B22L.07EµV-ARESISTOR MODE MAX5417 toc14 0.3 0.1 0.2 DNL (LSB) 0.1 DNL (LSB) 0 0 -0.1 -0.1 -0.2 -0.2 -0.3 -0.3 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 TAP POSITION TAP POSITION 6 _______________________________________________________________________________________

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers Typical Operating Characteristics (continued) M (VDD= +5V, TA= +25°C, unless otherwise noted.) A X DNL vs. TAP POSITION MIDSCALE WIPER RESPONSE vs. FREQUENCY MIDSCALE WIPER RESPONSE vs. FREQUENCY 5 (MAX5419) (MAX5417) (MAX5418) DNL (LSB) -0000....10123 VVISADRDRC I =A= B21L.07EµV-ARESISTOR MODE MAX5417 toc15 WIPER RESPONSE (dB) ---211-00550 MTAAPX =5 411278 CL =C L5 0=p 1F0pF MAX5417 toc16 WIPER RESPONSE (dB) ---211-50005 MTAAPX =5 411288 CL = 50pCFL = 10pF MAX5417 toc17 417/MAX5 -0.2 -25 -25 4 1 -0.3 -30 -30 8 0 32 64 96 128 160 192 224 256 1 10 100 1000 1 10 100 1000 TAP POSITION FREQUENCY (kHz) FREQUENCY (kHz) / M MIDSCALE WIPER RESPONSE vs. FREQUENCY TAP-TO-TAP SWITCHING TRANSIENT A (MAX5419) (MAX5417) 0 MAX5417 toc19 X -1-50 MTAAPX =5 411298 CL = 10pF MAX5417 toc18 54 E (dB) -15 S2VD/Adiv 1 ONS -20 9 P RES -25 CL = 50pF R WIPE -30 MCLA =X 51401p7F W -35 FROM TAP 127 10mV/div TO TAP 128 -40 H = VDD -45 1 10 100 1000 1µs/div FREQUENCY (kHz) TAP-TO-TAP SWITCHING TRANSIENT TAP-TO-TAP SWITCHING TRANSIENT (MAX5418) (MAX5419) MAX5417 toc20 MAX5417 toc21 SDA SDA 2V/div 2V/div W W 10mV/div 10mV/div MAX5418 MAX5419 CL = 10pF CL = 10pF FROM TAP 127 FROM TAP 127 TO TAP 128 TO TAP 128 H = VDD H = VDD 1µs/div 1µs/div _______________________________________________________________________________________ 7

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 Pin Description 1 4 PIN NAME FUNCTION 5 1 VDD Power-Supply Input. 2.7V to 5.25V voltage range. Bypass with a 0.1µF capacitor from VDD to GND. X 2 SCL I2C-Interface Clock Input A 3 SDA I2C-Interface Data Input M 4 A0 Address Input. Sets the A0 bit in the device ID address. 5 GND Ground / 8 6 L Low Terminal 1 7 W Wiper Terminal 4 8 H High Terminal 5 Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal — EP X performance. Not intended as an electrical point. A M / 7 tR tF 1 SDA 4 5 tSU-DAT tHD-DAT tHD-STA tBUF X tLOW tSU-STA tSU-STO A SCL M tHD-STA tHIGH tR tF S Sr A P S PARAMETERS ARE MEASURED FROM 30% TO 70%. Figure 1. I2C Serial-Interface Timing Diagram Detailed Description VDD The MAX5417/MAX5418/MAX5419 contain a resistor array with 255 resistive elements. The MAX5417 has a IOL = 3mA total end-to-end resistance of 50kΩ, the MAX5418 has an end-to-end resistance of 100kΩ, and the MAX5419 has an end-to-end resistance of 200kΩ. The MAX5417/MAX5418/MAX5419 allow access to the high, SDA VOUT low, and wiper terminals for a standard voltage-divider 400pF configuration. H, L, and W can be connected in any desired configuration as long as their voltages fall IOH = 0mA between GND and VDD. A simple 2-wire I2C-compatible serial interface moves the wiper among the 256 tap points. A nonvolatile mem- ory stores the wiper position and recalls the stored wiper Figure 2. Load Circuit position in the nonvolatile memory upon power-up. The nonvolatile memory is guaranteed for 50 years for wiper data retention and up to 200,000 wiper store cycles. 8 _______________________________________________________________________________________

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers Analog Circuitry Serial Addressing M The MAX5417/MAX5418/MAX5419 consist of a resistor The MAX5417/MAX5418/MAX5419 operate as a slave array with 255 resistive elements; 256 tap points are that receives data through an I2C- and SMBus™-com- A accessible to the wiper, W, along the resistor string patible 2-wire interface. The interface uses a serial data X between H and L. The wiper tap point is selected by access (SDA) line and a serial clock line (SCL) to 5 programming the potentiometer through the 2-wire (I2C) achieve communication between master(s) and interface. Eight data bits, an address byte, and a con- slave(s). A master, typically a microcontroller, initiates 4 trol byte program the wiper position. The H and L termi- all data transfers to the MAX5417/MAX5418/MAX5419, 1 nals of the MAX5417/MAX5418/MAX5419 are similar to and generates the SCL clock that synchronizes the 7 the two end terminals of a mechanical potentiometer. data transfer (Figure 1). / The MAX5417/MAX5418/MAX5419 feature power-on M The MAX5417/MAX5418/MAX5419 SDA line operates reset circuitry that loads the wiper position from non- as both an input and an open-drain output. A pullup A volatile memory at power-up. resistor, typically 4.7kΩ, is required on the SDA bus. X The MAX5417/MAX5418/MAX5419 SCL operates only Digital Interface as an input. A pullup resistor, typically 4.7kΩ, is 5 The MAX5417/MAX5418/MAX5419 feature an internal, required on the SCL bus if there are multiple masters 4 nonvolatile EEPROM that stores the wiper state for ini- on the 2-wire interface, or if the master in a single-mas- tialization during power-up. The shift register decodes 1 ter system has an open-drain SCL output. the control and address bits, routing the data to the 8 proper memory registers. Data can be written to a Each transmission consists of a START (S) condition / volatile memory register, immediately updating the (Figure 3) sent by a master, followed by the M wiper position, or data can be written to a nonvolatile MAX5417/MAX5418/MAX5419 7-bit slave address plus A register for storage. the 8th bit (Figure 4), 1 command byte (Figure 7) and 1 data byte, and finally a STOP (P) condition (Figure 3). X The volatile register retains data as long as the device is powered. Once power is removed, the volatile regis- 5 Start and Stop Conditions ter is cleared. The nonvolatile register retains data even Both SCL and SDA remain high when the interface is 4 after power is removed. Upon power-up, the power-on not busy. A master signals the beginning of a transmis- 1 reset circuitry controls the transfer of data from the non- sion with a START condition by transitioning SDA from 9 volatile register to the volatile register. high to low while SCL is high. When the master has fin- ished communicating with the slave, it issues a STOP condition by transitioning the SDA from low to high while SCL is high. The bus is then free for another SDA transmission (Figure 3). Bit Transfer One data bit is transferred during each clock pulse. SCL S P The data on the SDA line must remain stable while SCL is high (Figure 5). START STOP CONDITION CONDITION Figure 3. Start and Stop Conditions SDA 0 1 0 1 0* 0* A0 NOP/W ACK MSB LSB SCL *See the Ordering Information/Selector Guide section for other address options. Figure 4. Slave Address SMBus is a trademark of Intel Corporation. _______________________________________________________________________________________ 9

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 Table 1. MAX5417/MAX5418/MAX5419 Address Codes 1 ADDRESS BYTE 4 PART SUFFIX A6 A5 A4 A3 A2 A1 A0 NOP/W 5 X L 0 1 0 1 0 0 0 NOP/W L 0 1 0 1 0 0 1 NOP/W A M 0 1 0 1 0 1 0 NOP/W M M 0 1 0 1 0 1 1 NOP/W 8/ N 0 1 0 1 1 0 0 NOP/W 1 N 0 1 0 1 1 0 1 NOP/W 4 P 0 1 0 1 1 1 0 NOP/W 5 P 0 1 0 1 1 1 1 NOP/W X A Acknowledge slave address is the NOP/Wbit. Set the NOP/Wbit low for The acknowledge bit is a clocked 9th bit that the recipient a write command and high for a no-operation command. M uses to handshake receipt of each byte of data (Figure The MAX5417/MAX5418/MAX5419 are available in one 7/ 6). Thus, each byte transferred effectively requires 9 bits. of four possible slave addresses (Table 1). The first 4 The master generates the 9th clock pulse, and the recipi- bits (MSBs) of the MAX5417/MAX5418/MAX5419 slave 1 ent pulls down SDA during the acknowledge clock pulse, addresses are always 0101. The next 2 bits are factory 4 so the SDA line is stable low during the high period of the programmed (see Table 1). Connect the A0 input to 5 clock pulse. When the master transmits to the either GND or VDD to toggle between two unique MAX5417/MAX5418/MAX5419, the devices generate the X device addresses for a part. Each device must have a acknowledge bit because the MAX5417/MAX5418/ unique address to share the bus. Therefore, a maxi- A MAX5419 are the recipients. mum of eight MAX5417/MAX5418/MAX5419 devices M can share the same bus. Slave Address The MAX5417/MAX5418/MAX5419 have a 7-bit-long slave address (Figure 4). The 8th bit following the 7-bit CLOCK PULSE FOR ACKNOWLEDGMENT START SDA CONDITION SCL 1 2 8 9 NOT ACKNOWLEDGE SCL SDA DATA STABLE, CHANGE OF DATA VALID DATA ALLOWED ACKNOWLEDGE Figure 5. Bit Transfer Figure 6. Acknowledge 10 ______________________________________________________________________________________

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers M A CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION D15 D14 D13 D12 D11 D10 D9 D8 X ACKNOWLEDGE FROM 5 MAX5417/MAX5418/MAX5419 4 S SLAVE ADDRESS 0 A CONTROL BYTE A P 1 7 ACKNOWLEDGE FROM NOP/W MAX5417/MAX5418/MAX5419 / M A Figure 7. Command Byte Received X 5 4 1 ACKNOWLEDGE FROM ACKNOWLEDGE FROM 8 MAX5417/MAX5418/MAX5419 MAX5417/MAX5418/MAX5419 HOW CONTROL BYTE AND DATA BYTE MAP INTO / MAX5417/MAX5418/MAX5419 REGISTERS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 M ACKNOWLEDGE FROM A MAX5417/MAX5418/MAX5419 X S SLAVE ADDRESS 0 A CONTROL BYTE A DATA BYTE A P 5 NOP/W 1 BYTE 4 1 9 Figure 8. Command and Single Data Byte Received Message Format for Writing Command Descriptions A write to the MAX5417/MAX5418/MAX5419 consists of VREG:The data byte writes to the volatile memory reg- the transmission of the device’s slave address with the ister and the wiper position updates with the data in the 8th bit set to zero, followed by at least 1 byte of infor- volatile memory register. mation (Figure 7). The 1st byte of information is the NVREG: The data byte writes to the nonvolatile memo- command byte. The bytes received after the command ry register. The wiper position is unchanged. byte are the data bytes. The 1st data byte goes into the NVREGxVREG: Data transfers from the nonvolatile internal register of the MAX5417/MAX5418/MAX5419 as memory register to the volatile memory register (wiper selected by the command byte (Figure 8). position updates). Command Byte VREGxNVREG: Data transfers from the volatile memo- Use the command byte to select the source and desti- ry register into the nonvolatile memory register. nation of the wiper data (nonvolatile or volatile memory registers) and swap data between nonvolatile and volatile memory registers (see Table 2). ______________________________________________________________________________________ 11

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 Table 2. Command Byte Summary 1 ADDRESS BYTE CONTROL BYTE DATA BYTE 4 5 SCL CYCLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 P S NUMBER X A6 A5 A4 A3 A2 A1 A0 ACK TX NV V R3 R2 R1 R0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK A VREG 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 NVREG 0 1 0 1 A2 A1 A0 0 0 0 1 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 M NVREGxVREG 0 1 0 1 A2 A1 A0 0 0 1 1 0 0 0 0 1 X X X X X X X X VREGxNVREG 0 1 0 1 A2 A1 A0 0 0 1 0 1 0 0 0 1 X X X X X X X X / 8 X = Don’t care. 1 Nonvolatile Memory Positive LCD Bias Control 4 The internal EEPROM consists of an 8-bit nonvolatile Figures 9 and 10 show an application where the volt- 5 register that retains the value written to it before the age-divider or variable resistor is used to make an X device is powered down. The nonvolatile register is adjustable, positive LCD bias voltage. The op amp pro- A programmed with the midscale value at the factory. vides buffering and gain to the resistor-divider network made by the potentiometer (Figure 9) or to a fixed M Power-Up resistor and a variable resistor (see Figure 10). Upon power-up, the MAX5417/MAX5418/MAX5419 / 7 load the data stored in the nonvolatile memory register Programmable Filter into the volatile memory register, updating the wiper Figure 11 shows the configuration for a 1st-order pro- 1 position with the data stored in the nonvolatile memory grammable filter. The gain of the filter is adjusted by 4 register. This initialization period takes 10µs. R2, and the cutoff frequency is adjusted by R3. Use the 5 following equations to calculate the gain (G) and the X Standby 3dB cutoff frequency (fC): The MAX5417/MAX5418/MAX5419 feature a low-power A standby. When the device is not being programmed, it M goes into standby mode and power consumption is G = 1 + R1 typically 500nA. R2 1 Applications Information f = C 2π × R3 × C The MAX5417/MAX5418/MAX5419 are intended for cir- cuits requiring digitally controlled adjustable resis- tance, such as LCD contrast control (where voltage biasing adjusts the display contrast), or for programma- ble filters with adjustable gain and/or cutoff frequency. 5V 5V H 30V 30V W MAX5417 MMAAXx55441198 VOUT H VOUT L MAX5417 MAX5418 W MAX5419 L Figure 9. Positive LCD Bias Control Using a Voltage-Divider Figure 10. Positive LCD Bias Control Using a Variable Resistor 12 ______________________________________________________________________________________

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers M W 5V L A VIN H R3 C VOUT MMAAXX55441178 X MAX5419 5 7 3 1 4 R1 8 1 6 MAX410 7 H 2 / M W 4 MAX5417 MMAAXX55441189 R2 W L -5V A L R1 H X 5 Figure 11. Programmable Filter Figure 13. Offset Voltage and Gain Adjustment Circuit 4 1 Pin Configuration 8 / M TOP VIEW +5V A X VIN + V0 REF VDD 1 8 H 5 OUT H 4 SCL 2 7 W MAX6160 MAX5417 1 W SDA 3 MAX5418 6 L 9 ADJ MAX5419 MAX5417 GND A0 4 5 GND L MAX5418 MAX5419 TDFN Figure 12. Adjustable Voltage Reference Adjustable Voltage Reference Chip Information Figure 12 shows the MAX5417/MAX5418/MAX5419 used PROCESS: BiCMOS as the feedback resistors in multiple adjustable voltage- reference applications. Independently adjust the output voltage of the MAX6160 from 1.23V to VIN - 0.2V by changing the wiper positions of the MAX5417/ Package Information MAX5418/MAX5419. For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in Offset Voltage and Gain Adjustment the package code indicates RoHS status only. Package draw- Connect the high and low terminals of one potentiometer ings may show a different suffix character, but the drawing per- of a MAX5417 between the NULL inputs of a MAX410 tains to the package regardless of RoHS status. and the wiper to the op amp’s positive supply to nullify the offset voltage over the operating temperature range. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. Install the other potentiometer in the feedback path to 8 TDFN-EP T833-1 21-0137 adjust the gain of the MAX410 (see Figure 13). ______________________________________________________________________________________ 13

256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers 9 Revision History 1 4 REVISION REVISION PAGES DESCRIPTION 5 NUMBER DATE CHANGED X 0 2/04 Initial release — A 1 4/04 Adding future product — M 2 8/04 Adding new part — 3 3/09 Changes to add details about exposed pad, corrections to Table 2, style edits 1, 8, 12–15 / 8 Add ed l ead -f r ee pa ckag es to O rd er in g Inform atio n, add ed So ld eri ng Temp er ature to 1 4 4/10 Abs ol ute M axi mu m Ratin gs , cor re cted C ondi ti ons for Di ffere nti al N onl in ear it y in 1, 2, 8, 13 4 E le ctri cal C har acter is ti cs, cor re cted A0 in P in D escri pt i on, cor re cted Fig ur es 12 and 13 5 X A M / 7 1 4 5 X A M Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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