19-1316; Rev 1; 12/97 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface _______________General Description ____________________________Features M The MAX5154/MAX5155 low-power, serial, voltage-out- '12-Bit Dual DAC with Internal Gain of +2V/V A put, dual 12-bit digital-to-analog converters (DACs) 'Rail-to-Rail Output Swing X consume only 500µA from a single +5V (MAX5154) or '12µs Settling Time +3V (MAX5155) supply. These devices feature Rail-to- 5 Rail® output swing and are available in a space-saving 'Single-Supply Operation: +5V (MAX5154) 1 16-pin QSOP package. To maximize the dynamic +3V (MAX5155) 5 range, the DAC output amplifiers are configured with an ' Low Quiescent Current: 500µA (normal operation) 4 internal gain of +2V/V. 2µA (shutdown mode) / The 3-wire serial interface is SPI™/QSPI™ and 'SPI/QSPI and Microwire Compatible M Microwire™ compatible. Each DAC has a double- 'Available in Space-Saving 16-Pin QSOP Package A buffered input organized as an input register followed 'Power-On Reset Clears Registers and DACs by a DAC register, which allows the input and DAC reg- X to Zero isters to be updated independently or simultaneously with a 16-bit serial word. Additional features include 'Adjustable Output Offset 5 1 programmable shutdown (2µA), hardware-shutdown lockout (PDL), a separate reference voltage input for ______________Ordering Information 5 each DAC that accepts AC and DC signals, and an 5 active-low clear input (CL) that resets all registers and INL PART TEMP. RANGE PIN-PACKAGE DACs to zero. These devices provide a programmable (LSB) logic pin for added functionality, and a serial-data out- MAX5154ACPE 0°C to +70°C 16 Plastic DIP ±1/2 put pin for daisy chaining. MAX5154BCPE 0°C to +70°C 16 Plastic DIP ±1 MAX5154ACEE 0°C to +70°C 16 QSOP ±1/2 ________________________Applications MAX5154BCEE 0°C to +70°C 16 QSOP ±1 Industrial Process Control Remote Industrial Controls Ordering Information continued at end of data sheet. Digital Offset and Gain Microprocessor- Adjustment Controlled Systems Pin Configuration appears at end of data sheet. Motion Control Automatic Test Equipment (ATE) _________________________________________________________Functional Diagram DOUT CL PDL DGND AGND VDD REFA OSA DECODE R CONTROL R INPUT DAC OUTA REG A REG A DAC A OSB 16-BIT SHIFT R REGISTER MAX5154 MAX5155 R SR CONTROL INPUT DAC OUTB LOGIC DAC B REG B REG B OUTPUT CS DIN SCLK UPO REFB Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468.

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 ABSOLUTE MAXIMUM RATINGS 5 VDDto AGND............................................................-0.3V to +6V Continuous Power Dissipation (TA= +70°C) 1 VDDto DGND...........................................................-0.3V to +6V Plastic DIP (derate 10.5mW/°C above +70°C)...........842mW 5 AGND to DGND..................................................................±0.3V QSOP (derate 8.30mW/°C above +70°C)...................667mW OSA, OSB to AGND........................(AGND - 4V) to (VDD+ 0.3V) CERDIP (derate 10.00mW/°C above +70°C)..............800mW X REF_, OUT_ to AGND.................................-0.3V to (VDD+ 0.3V) Operating Temperature Ranges A Digital Inputs (SCLK, DIN, CS,CL, PDL) MAX515_ _C_ E.................................................0°C to +70°C to DGND............................................................(-0.3V to +6V) MAX515_ _E_ E..............................................-40C°to +85°C M Digital Outputs (DOUT, UPO) MAX515_ _MJE.............................................-55°C to +125°C to DGND................................................-0.3V to (VDD+ 0.3V) Storage Temperature Range.............................-65°C to +150°C / 4 Maximum Current into Any Pin.........................................±20mA Lead Temperature (soldering, 10sec).............................+300°C 5 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to 1 absolute maximum rating conditions for extended periods may affect device reliability. 5 ELECTRICAL CHARACTERISTICS—MAX5154 X (VDD= +5V ±10%, VREFA= VREFB= 2.048V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are A at TA= +25°C (OS_ tied to AGND for a gain of +2V/V).) M PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Bits MAX5154A ±1/2 Integral Nonlinearity INL (Note 1) LSB MAX5154B ±1 Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB Offset Error Vos Code = 6 ±6 mV Offset Tempco TCVos Normalized to 2.048V 4 ppm/°C Gain Error -0.2 ±3 LSB Gain-Error Tempco Normalized to 2.048V 4 ppm/°C RVDejDecPtoiowne Rr-aStuiopply PSRR 4.5V ≤VDD≤5.5V 20 260 µV/V REFERENCE INPUT Reference Input Range REF 0 VDD- 1.4 V Reference Input Resistance RREF Minimum with code 1554 hex 14 20 kΩ MULTIPLYING-MODE PERFORMANCE Input code = 1FFE hex, Reference 3dB Bandwidth 300 kHz VREF_= 0.67Vp-p at 2.5VDC Input code = 0000 hex, Reference Feedthrough -82 dB VREF_= (VDD- 1.4Vp-p) at 1kHz Signal-to-Noise plus Input code = 1FFE hex, SINAD 75 dB Distortion Ratio VREF_= 1Vp-p at 1.25VDC, f = 25kHz DIGITAL INPUTS Input High Voltage VIH CL, PDL, CS, DIN, SCLK 3 V Input Low Voltage VIL CL, PDL, CS, DIN, SCLK 0.8 V Input Hysteresis VHYS 200 mV Input Leakage Current IIN VIN= 0V to VDD 0.001 ±1 µA Input Capacitance CIN 8 pF 2 _______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX5154 (continued) M (VDD= +5V ±10%, VREFA= VREFB= 2.048V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are A at TA= +25°C (OS_ tied to AGND for a gain of +2V/V).) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5 DIGITAL OUTPUTS (DOUT, UPO) 1 Output High Voltage VOH ISOURCE= 2mA VDD- 0.5 V 5 Output Low Voltage VOL ISINK= 2mA 0.13 0.40 V 4 DYNAMIC PERFORMANCE / Voltage Output Slew Rate SR 0.75 V/µs M Output Settling Time To 1/2LSB of full-scale, VSTEP= 4V 15 µs A Output Voltage Swing Rail-to-rail (Note 2) 0 to VDD V X OSA or OSB Input Resistance ROS_ 24 34 kΩ 5 Time Required to Exit Shutdown 25 µs 1 Digital Feedthrough CS= VDD, fDIN= 100kHz, VSCLK= 5Vp-p 5 nV-s 5 Digital Crosstalk 5 nV-s 5 POWER SUPPLIES Positive Supply Voltage VDD 4.5 5.5 V Power-Supply Current IDD (Note 3) 0.5 0.65 mA Power-Supply Current IDD(SHDN) (Note 3) 2 10 µA in Shutdown Reference Current in Shutdown 0 ±1 µA TIMING CHARACTERISTICS SCLK Clock Period tCP (Note 4) 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CSFall to SCLK Rise tCSS 40 ns Setup Time SCLK Rise to CSRise tCSH 0 ns Hold Time SDI Setup Time tDS 40 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT tDO1 CLOAD= 200pF 80 ns Valid Propagation Delay SCLK Fall to DOUT tDO2 CLOAD= 200pF 80 ns Valid Propagation Delay SCLK Rise to CSFall Delay tCS0 10 ns CSRise to SCLK Rise Hold tCS1 40 ns CSPulse Width High tCSW 100 ns Note 1: Accuracy is specified from code 6 to code 4095. Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD- 50mV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either VDDor DGND, code = 0000 hex, RL= ∞. Note 4: SCLK minimum clock period includes the rise and fall times. _______________________________________________________________________________________ 3

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 ELECTRICAL CHARACTERISTICS—MAX5155 5 (VDD= +2.7V to +3.6V, VREFA= VREFB= 1.25V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values 1 are at TA= +25°C (OS_ pins tied to AGND for a gain of +2V/V).) 5 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X STATIC PERFORMANCE A Resolution 12 Bits M MAX5155A ±1 Integral Nonlinearity INL (Note 5) LSB MAX5155B ±2 / 4 Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB 5 Offset Error Vos Code = 10 ±6 mV 1 Offset Tempco TCVos Normalized to 1.25V 6.5 ppm/°C 5 Gain Error -0.2 ±4 LSB X Gain-Error Tempco Normalized to 1.25V 6.5 ppm/°C A M RVDejDecPtoiowne Rr-aStuiopply PSRR 2.7V ≤VDD≤3.6V 40 320 µV/V REFERENCE INPUT (VREF) Reference Input Range REF 0 VDD- 1.4 V Reference Input Resistance RREF Minimum with code 1554 hex 14 20 kΩ MULTIPLYING-MODE PERFORMANCE Input code = 1FFE hex, Reference 3dB Bandwidth 300 kHz VREF_= 0.67Vp-p at 0.75VDC Input code = 0000 hex, Reference Feedthrough -82 dB VREF_= (VDD- 1.4)Vp-p at 1kHz Signal-to-Noise plus Input code = 1FFE hex, SINAD 73 dB Distortion Ratio VREF_= 1Vp-p at 1VDC, f = 15kHz DIGITAL INPUTS Input High Voltage VIH CL, PDL, CS, DIN, SCLK 2.2 V Input Low Voltage VIL CL, PDL, CS, DIN, SCLK 0.8 V Input Hysteresis VHYS 200 mV Input Leakage Current IIN VIN= 0V to VDD 0 ±1 µA Input Capacitance CIN 8 pF DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage VOH ISOURCE= 2mA VDD- 0.5 V Output Low Voltage VOL ISINK= 2mA 0.13 0.4 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR 0.75 V/µs Output Settling Time To 1/2LSB of full-scale, VSTEP= 2.5V 15 µs Output Voltage Swing Rail-to-rail (Note 6) 0 to VDD V OSA or OSB Input Resistance ROS_ 24 34 kΩ Time Required for Valid 25 µs Operation after Shutdown Digital Feedthrough CS= VDD, fDIN= 100kHz, VSCLK= 3Vp-p 5 nV-s Digital Crosstalk 5 nV-s 4 _______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX5155 (continued) M (VDD= +2.7V to +3.6V, VREFA= VREFB= 1.25V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values A are at TA= +25°C (OS_ pins tied to AGND for a gain of +2V/V).) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5 POWER SUPPLIES 1 Positive Supply Voltage VDD 2.7 3.6 V 5 Power-Supply Current IDD (Note 7) 0.45 0.6 mA 4 Power-Supply Current in Shutdown IDD (SHDN) (Note 7) 1 8 µA /M Reference Current in Shutdown 0 ±1 µA A TIMING CHARACTERISTICS X SCLK Clock Period tCP (Note 4) 100 ns 5 SCLK Pulse Width High tCH 40 ns 1 SCLK Pulse Width Low tCL 40 ns 5 CSFall to SCLK Rise 5 tCSS 40 ns Setup Time SCLK Rise to CSRise Hold Time tCSH 0 ns SDI Setup Time tDS 50 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD= 200pF 120 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD= 200pF 120 ns SCLK Rise to CSFall Delay tCS0 10 ns CSRise to SCLK Rise Hold tCS1 40 ns CSPulse Width High tCSW 100 ns Note 5: Accuracy is specified from code 10 to code 4095. Note 6: Accuracy is better than 1LSB for VOUTgreater than 6mV and less than VDD- 80mV. Guaranteed by PSRR test at the end points. Note 7: Digital inputs are set to either VDDor DGND, code = 0000 hex, RL= ∞. _______________________________________________________________________________________ 5

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 __________________________________________Typical Operating Characteristics 5 (VDD= +5V, RL= 10kΩ, CL= 100pF, OS_ pins tied to AGND, TA= +25°C, unless otherwise noted.) 1 5 MAX5154 X REFERENCE VOLTAGE INPUT TOTAL HARMONIC DISTORTION FREQUENCY RESPONSE SUPPLY CURRENT vs. TEMPERATURE PLUS NOISE vs. FREQUENCY A X5154/M RELATIVE OUTPUT (dB) ---111----24806240 MAX5154/5155toc01 mSUPPLY CURRENT (A) 556675050000000 CCOODDEE == 10F0F0E0 ((HHEEXX)) MAX5154/5155 toc02 THD + NOISE (dB) ----36540000 VCROEDF E= =1 V1FpF-pE @(H E2X.5)VDC MAX5154/5155 toc03 A -16 -70 M -18 CVORDEFE = = 0 1.6F7FVE p(-HpE @X) 2.5VDC 450 RVRL E=F ¥= 2.048V -20 400 -80 1 370 740 1110 1480 1850 -55 -35 -15 5 25 45 65 85 105 125 1 10 100 FREQUENCY (kHz) TEMPERATURE (°C) FREQUENCY (kHz) SHUTDOWN CURRENT FULL-SCALE ERROR vs. RESISTIVE LOAD REFERENCE FEEDTHROUGH AT 1kHz vs. TEMPERATURE FULL-SCALE ERROR (LSB)----100000......0752250050550 VREF = 2.048V MAX5154/5155 toc04 RELATIVE OUTPUT (dB) ---111-----1290867500000000 VCROEDF E= 3=. 60V00p0-p ( H@E X1).88VDC MAX5154/5155 toc05 mSHUTDOWN CURRENT (A) 23456 VREF = 1V MAX5154/5155 toc06 -130 1 -1.25 -140 -1.50 -150 0 0.1 1 10 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -55 -35 -15 5 25 45 65 85 105 125 RL (kW ) FREQUENCY (kHz) TEMPERATURE (°C) OUTPUT FFT PLOT DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME 0 MAX5154/5155 toc08 MAX5154/5155 toc09 B) ---312000 VfC =RO E1DFk E=H =z2 .14F5FVEp (-Hp E@X) 1.225VDC MAX5154/5155 toc07 5CVS/div 5CVS/div d UT ( -40 NOTE: RELATIVE TO FULL-SCALE P UT -50 O TIVE -60 OUT_ OUT_ ELA -70 1V/div 1V/div R -80 -90 -100 0.5 1.6 2.7 3.8 4.9 6.0 2m s/div 2m s/div FREQUENCY (kHz) VREF = 2.048V VREF = 2.048V 6 _______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface _____________________________Typical Operating Characteristics (continued) M (VDD= +3V, RL= 10kΩ, CL= 100pF, OS_pins tied to AGND, TA= +25°C, unless otherwise noted.) A X MAX5155 REFERENCE VOLTAGE INPUT TOTAL HARMONIC DISTORTION 5 FREQUENCY RESPONSE SUPPLY CURRENT vs. TEMPERATURE PLUS NOISE vs. FREQUENCY 1 0 560 -30 RELATIVE OUTPUT (dB) ---111----2480624 MAX5154/5155 toc10 mSUPPLY CURRENT (A) 544550864200000 RVRL E=F ¥= 1V CCOODDEE == 10F0F0E0 ((HHEEXX)) MAX5154/5155 toc11 THD + NOISE (dB) ---654000 VCROEDF E= =1 V1FpF-pE @(H E1XV)DC MAX5154/5155 toc12 54/MAX5 440 -16 -70 1 VREF = 0.67Vp-p @ 0.75VDC 420 -18 5 CODE = 1FFE -20 400 -80 5 1 320 640 960 1280 1600 -55 -35 -15 5 25 45 65 85 105 125 1 10 100 FREQUENCY (kHz) TEMPERATURE (°C) FREQUENCY (kHz) SHUTDOWN CURRENT FULL-SCALE ERROR vs. RESISTIVE LOAD REFERENCE FEEDTHROUGH AT 1kHz vs. TEMPERATURE 0.25 -50 3.0 ULL-SCALE ERROR (LSB)---000...5720055 VREF = 1.25V MAX5154/5155 toc13 RELATIVE OUTPUT (dB) ---111----12908670000000 VCROEDF E= 1=. 60V00p0-p ( H@E X0).88VDC MAX5154/5155 toc14 mHUTDOWN CURRENT (A) 1212222.......6082486 RVRL E=F ¥= 1V MAX5154/5155 toc15 F S -130 1.4 -1.00 -140 1.2 -1.25 -150 1.0 0.1 1 10 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -55 -35 -15 5 25 45 65 85 105 125 RL (kW ) FREQUENCY (kHz) TEMPERATURE (°C) OUTPUT FFT PLOT DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME 0 MAX5154/5155 toc17 MAX5154/5155 toc18 dB) ---312000 VfC =RO E1DFk E=H =z1 .14FVFpE- p(H @EX 0).75VDC MAX5154/5155toc16 2CVS/div C2VS/div T ( U -40 P T OU -50 E TIV -60 A REL -70 OUT_ OUT_ 500mV/div 500mV/div -80 -90 -100 0.5 1.6 2.7 3.8 4.9 6.0 2m s/div 2m s/div FREQUENCY (kHz) VREF = 1.25V VREF = 1.25V _______________________________________________________________________________________ 7

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 _____________________________Typical Operating Characteristics (continued) 5 (VDD= +5V (MAX5154), VDD= +3V (MAX5155), RL= 10kΩ, CL= 100pF, OS_ pins tied to AGND, unless otherwise noted.) 1 5 MAX5154/MAX5155 X MAX5154 MAX5155 A SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE 4/M A) 00..5650 CODE = 1FFE (HEX) MAX5154/5155toc19 A) 00..5650 CODE = 1FFE (HEX) MAX5154/5155toc20 5 T (m T (m N N 1 E E R R 5 CUR 0.50 CUR 0.50 X PLY CODE = OOOO (HEX) PLY CODE = OOOO (HEX) P P U U S S A 0.45 0.45 M 0.40 0.40 4.50 4.75 5.00 5.25 5.50 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) MAX5154 MAJOR-CARRY TRANSITION MAX5154/5155 toc21 CS 2V/div OUT_ 50mV/div AC COUPLED 5m s/div TRANSITION FROM 1000 (HEX) TO 0FFE (HEX) MAX5154 MAX5154 ANALOG CROSSTALK DIGITAL FEEDTHROUGH MAX5154/5155 toc22 O5VU/TdAiv MAX5154/5155 toc23 S5VC/LdKiv OUTA OUTB 500m V/div 200m V/div AC COUPLED AC COUPLED 250m s/div 2.5m s/div VREF = 2.048V, GAIN = +2V/V, CODE = 1FFE HEX 8 _______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface _____________________Pin Description M OS_ R A PIN NAME FUNCTION X 1 AGND Analog Ground R 5 2 OUTA DAC A Output Voltage R R R OUT_ 1 3 OSA DAC A Offset Adjustment 5 2R 2R 2R 2R 2R 4 4 REFA Reference for DAC A D0 D9 D10 D11 / M Active-Low Clear Input. Resets all reg- 5 CL isters to zero. DAC outputs go to 0V. A 6 CS Chip-Select Input REF_ X AGND 7 DIN Serial-Data Input 5 1 8 SCLK Serial Clock Input SHOWN FOR ALL 1s ON DAC 5 9 DGND Digital Ground Figure 1. Simplified DAC Circuit Diagram 5 10 DOUT Serial-Data Output VOUT= (VREFx NB / 4096) x 2 11 UPO User-Programmable Output where NB is the numeric value of the DAC’s binary input code (0 to 4095) and VREFis the reference voltage. Power-Down Lockout. The device can- 12 PDL not be powered down when PDLis low. The reference input impedance ranges from 14kΩ (1554 hex) to several giga ohms (with an input code of 0000 13 REFB Reference for DAC B hex). The reference input capacitance is code dependent 14 OSB DAC B Offset Adjustment and typically ranges from 15pF with an input code of all zeros to 50pF with a full-scale input code. 15 OUTB DAC B Output Voltage Output Amplifier 16 VDD Positive Power Supply The output amplifiers on the MAX5154/MAX5155 have internal resistors that provide for a gain of +2V/V when _______________Detailed Description OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers The MAX5154/MAX5155 dual, 12-bit, voltage-output have a typical slew rate of 0.75V/µs and settle to DACs are easily configured with a 3-wire serial inter- 1/2LSB within 15µs, with a load of 10kΩ in parallel with face. These devices include a 16-bit data-in/data-out 100pF. Loads less than 2kΩdegrade performance. shift register, and each DAC has a double-buffered input composed of an input register and a DAC register The OS_ pin can be used to produce an adjustable off- (see Functional Diagram). In addition, trimmed internal set voltage at the output. For instance, to achieve a 1V resistors produce an internal gain of +2V/V that maxi- offset, apply -1V to the OS_ pin to produce an output mizes output voltage swing. The amplifier’s offset-adjust range from 1V to (1V + VREF x 2). Note that the DAC’s pin allows for a DC shift in the DAC’s output. output range is still limited by the maximum output volt- age specification. Both DACs use an inverted R-2R ladder network that pro- duces a weighted voltage proportional to the input volt- Power-Down Mode age value. Each DAC has its own reference input to The MAX5154/MAX5155 feature a software-program- facilitate independent full-scale values. Figure 1 depicts a mable shutdown mode that reduces the typical supply simplified circuit diagram of one of the two DACs. current to 2µA. The two DACs can be shutdown inde- pendently, or simultaneously using the appropriate pro- Reference Inputs gramming command. Enter shutdown mode by writing The reference inputs accept both AC and DC values the appropriate input-control word (Table 1). In shut- with a voltage range extending from 0V to (VDD- 1.4V). down mode, the reference inputs and amplifier out- Determine the output voltage using the following equa- puts become high impedance, and the serial tion (OS_ = AGND): interface remains active. Data in the input registers is _______________________________________________________________________________________ 9

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 Table 1. Serial-Interface Programming Commands 5 16-BIT SERIAL WORD 1 5 FUNCTION D11.......................D0 A0 C1 C0 S0 X (MSB) (LSB) A 0 0 1 12-bit DAC data 0 Load input register A; DAC registers are unchanged. M 1 0 1 12-bit DAC data 0 Load input register B; DAC registers are unchanged. / 4 0 1 0 12-bit DAC data 0 Load input register A; all DAC registers are updated. 5 1 1 0 12-bit DAC data 0 Load input register B; all DAC registers are updated. 1 5 Load all DAC registers from the shift register 0 1 1 12-bit DAC data 0 (start up both DACs with new data.). X A 1 0 0 xxxxxxxxxxxx 0 Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). M 1 1 1 xxxxxxxxxxxx 0 Shut down both DACs (provided PDL= 1). Update DAC register A from input register A 0 0 0 0 0 1 x xxxxxxxx 0 (start up DAC A with data previously stored in input register A). Update DAC register B from input register B 0 0 0 1 0 1 x xxxxxxxx 0 (start up DAC B with data previously stored in input register B). 0 0 0 1 1 0 x xxxxxxxx 0 Shut down DAC A (provided PDL= 1). 0 0 0 1 1 1 x xxxxxxxx 0 Shut down DAC B (provided PDL= 1). 0 0 0 0 1 0 x xxxxxxxx 0 UPO goes low (default). 0 0 0 0 1 1 x xxxxxxxx 0 UPO goes high. 0 0 0 1 0 0 1 xxxxxxxx 0 Mode 1, DOUT clocked out on SCLK’s rising edge. 0 0 0 1 0 0 0 xxxxxxxx 0 Mode 0, DOUT clocked out on SCLK’s falling edge (default). 0 0 0 0 0 0 x xxxxxxxx 0 No operation (NOP). x = Don’t care Note:D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub bit, always zero. saved, allowing the MAX5154/MAX5155 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previ- SCLK SK ous condition or by updating the DAC with new infor- mation. When returning to normal operation (exiting shutdown), wait 20µs for output stabilization. MICROWIRE MAX5154 DIN SO PORT Serial Interface MAX5155 The MAX5154/MAX5155 3-wire serial interface is com- patible with both Microwire (Figure 2) and SPI/QSPI CS I/O (Figure 3) serial-interface standards. The 16-bit serial input word consists of an address bit, two control bits, 12 bits of data (MSB to LSB), and one sub bit as shown in Figure 4. The address and control bits determine the Figure 2. Connections for Microwire MAX5154/ MAX5155’s response, as outlined in Table 1. 10 ______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface The MAX5154/MAX5155’s digital inputs are double M +5V buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), A updating the DAC register(s) from the input register(s), X or updating the input and DAC registers concurrently. 5 The address and control bits allow the DACs to act SS independently. 1 5 Send the 16-bit data as one 16-bit word (QSPI) or two DIN MOSI 8-bit packets (SPI, Microwire), with CS low during this 4 SPI/QSPI period. The address and control bits determine which / MAX5154 SCLK SCK PORT register will be updated, and the state of the registers M MAX5155 when exiting shutdown. The 3-bit address/control deter- A mines the following: X CS I/O • registers to be updated 5 • clock edge on which data is to be clocked out via 1 the serial-data output (DOUT) CPOL = 0,CPHA = 0 5 • state of the user-programmable logic output 5 Figure 3. Connections for SPI/QSPI • configuration of the device after shutdown. The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to MSB...................................................................................LSB receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the 16 Bits of Serial Data register on the rising edge of SCLK. As CS goes high, SUB data is latched into the input and/or DAC registers Address Bits Control Bits MSB...DataBits...LSB BIT depending on the address and control bits. The maxi- mum clock frequency guaranteed for proper operation A0 C1, C0 D11.......................D0 S0 is 10MHz. Figure 6 depicts a more detailed timing dia- 1 Address/2 Control Bits 12 Data Bits 0 gram of the serial interface. Figure 4. Serial-Data Format CS COMMAND EXECUTED SCLK 1 8 9 16 DIN A0 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S0 Figure 5. Serial-Interface Timing Diagram ______________________________________________________________________________________ 11

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 5 CS tCSW 1 5 tCSO tCSS tCL tCH tCP tCSH tCS1 X SCLK A tDS tDH M DIN / 4 5 Figure 6. Detailed Serial-Interface Timing Diagram 1 5 X A SCLK SCLK SCLK M MAX5154 MAX5154 MAX5154 MAX5155 MAX5155 MAX5155 DIN DOUT DIN DOUT DIN DOUT CS CS CS TO OTHER SERIAL DEVICES Figure 7. Daisy Chaining MAX5154/MAX5155s DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS CS MAX5154 MAX5154 MAX5154 MAX5155 MAX5155 MAX5155 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5154/MAX5155s Sharing a Common DIN Line 12 ______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface Serial-Data Output M The serial-data output, DOUT, is the internal shift regis- +5V/+3V OS_ ter’s output. DOUT allows for daisy chaining of devices REF_ A and data readback. The MAX5154/MAX5155 can be X VDD programmed to shift data out of DOUT on SCLK’s falling edge (Mode 0) or on the rising edge (Mode 1). MAX5154 R 5 MAX5155 1 Mode 0 provides a lag of 16 clock cycles, which main- tains compatibility with SPI/QSPI and Microwire inter- R 5 faces. In Mode 1, the output data lags 15.5 clock DAC_ OUT_ 4 cycles. On power-up, the device defaults to Mode 0. / M AGND DGND User-Programmable Logic Output (UPO) A UPO allows an external device to be controlled through GAIN = +2V/V the serial interface (Table 1), thereby reducing the X number of microcontroller I/O pins required. On power- 5 up, UPO is low. Figure 9. Unipolar Output Circuit (Rail-to-Rail) 1 Power-Down Lockout Input (PPDDLL) 5 +5V/+3V OS_ The power-down lockout pin (PDL) disables software 5 REF_ shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output VDD VOS set to the state prior to shutdown. PDL can also be MAX5154 R used to asynchronously wake up the device. MAX5155 Daisy Chaining Devices R Any number of MAX5154/MAX5155s can be daisy DAC _ OUT_ chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). AGND DGND Since the MAX5154/MAX5155’s DOUT pin has an inter- nal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the digital output VOHand VOL Figure 10. Setting OS_ for Output Offset specifications in the Electrical Characteristics. Table 2. Unipolar Code Table (Gain = +2) Figure 8 shows an alternate method of connecting sev- eral MAX5154/MAX5155s. In this configuration, the DAC CONTENTS data bus is common to all devices; data is not shifted ANALOG OUTPUT MSB LSB through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select (cid:230) 4095(cid:246) input (CS) is required for each IC. 1111 1111 1111 (0) +VREF Ł(cid:231) 4096ł(cid:247) x 2 __________Applications Information (cid:230) 2049(cid:246) 1000 0000 0001 (0) +V (cid:231) (cid:247) x 2 Unipolar Output REF Ł 4096ł Figure 9 shows the MAX5154/MAX5155 configured for (cid:230) 2048(cid:246) unipolar, rail-to-rail operation with a gain of +2V/V. The 1000 0000 0000 (0) +V (cid:231) (cid:247) x 2 = V REF Ł 4096ł REF MAX5154 can produce a 0V to 4.096V output with 2.048V reference (Figure 9), while the MAX5155 can (cid:230) 2047(cid:246) produce a range of 0V to 2.5V with a 1.25V reference. 0111 1111 1111 (0) +VREF Ł(cid:231) 4096ł(cid:247) x 2 Table 2 lists the unipolar output codes. An offset to the oOuSt_p,u at sc ashno bwen ainc hFiiegvuered 1b0y. Bcoy nanpepcltyiningg aV OvSo_lt a=g e-1 Vto, 0000 0000 0001 (0) +VREF (cid:230)Ł(cid:231) 40196(cid:246)ł(cid:247) x 2 the output values will range between 1V and (1V + 0000 0000 0000 (0) 0V VREFx 2). Note: ( ) are for the sub bit. ______________________________________________________________________________________ 13

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 Table 3. Bipolar Code Table +5V/ 5 +3V 1 DAC CONTENTS +5V/+3V MSB LSB ANALOG OUTPUT AC 26k 5 MAX495 REFERENCE X (cid:230) 2047(cid:246) INPUT 1111 1111 1 111 (0) +V (cid:231) (cid:247) A REF Ł 2048ł M 1000 0000 0 001 (0) +V (cid:230)(cid:231) 1 (cid:246)(cid:247) 500mVp-p 10k REF VDD R OS_ REF Ł 2048ł / 4 R 1000 0000 0 000 (0) 0V 5 1 (cid:230) 1 (cid:246) DAC_ OUT_ 0111 1111 1 111 (0) -V (cid:231) (cid:247) 5 REF Ł 2048ł X (cid:230) 2047(cid:246) MAX5154 0000 0000 0 001 (0) -V (cid:231) (cid:247) MAX5155 A REF Ł 2048ł AGND DGND M (cid:230) 2048(cid:246) 0000 0000 0 000 (0) -V (cid:231) (cid:247) = -V REF Ł 2048ł REF Figure 12. AC Reference Input Circuit Note:( ) are for the sub bit. V+ REF_ +5V/+3V 10k 10k REF_ +5V/+3V PHOTODIODE OS_ OS_ VDD VDD R R V+ MAX5154 V+ MAX5154 MAX5155 MAX5155 R OUT_ VOUT R 10k VOUT m P DAC _ DAC _ OUT_ DIN V- AGND DGND DGND AGND 10k V- RPULLDOWN Figure 13. Digital Calibration Figure 11. Bipolar Output Circuit Bipolar Output ing a sinusoidal input to REF_, where the AC signal is The MAX5154/MAX5155 can be configured for a bipo- offset before being applied to the reference input. lar output, as shown in Figure 11. The output voltage is Harmonic Distortion and Noise given by the equation (OS_ = AGND): The total harmonic distortion plus noise (THD+N) is typ- VOUT= VREF[((2 x NB) / 4096) - 1] ically less than -78dB at full scale with a 1Vp-p input where NB represents the numeric value of the DAC’s swing at 5kHz. The typical -3dB frequency is 300kHz binary input code. Table 3 shows digital codes and the for both devices, as shown in the Typical Operating corresponding output voltage for Figure 11’s circuit. Characteristics. Using an AC Reference Digital Calibration and In applications where the reference has an AC signal Threshold Selection component, the MAX5154/MAX5155 have multiplying Figure 13 shows the MAX5154/MAX5155 in a digital capabilities within the reference input voltage range calibration application. With a bright light value applied specifications. Figure 12 shows a technique for apply- to the photodiode (on), the DAC is digitally ramped until 14 ______________________________________________________________________________________

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface M VDD OSA A X MAX5154 R MAX5155 5 VIN REFA R R1 1 OUTA 5 CS INPUT DAC SHIFT REG A REG A DACA R2 4 SCLK REGISTER / DIN IRNEPGU BT RDEAGC B DACB OUTB R3 VOUT M A REFB R4 VREF R X [ ] [ ] R VOUT = GAIN – OFFSET 5 OSB = [( V IN 2 N A ) ( R 2 ) ( 1 + R 4 )] [( V R E F 2 N B ) ( R 4 )] 1 4096 R1+R2 R3 4096 R3 5 5 NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. AGND DGND NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB. Figure 14. Digital Control of Gain and Offset it trips the comparator. The microprocessor (µP) stores Power-Supply Considerations this “high” calibration value. Repeat the process with a On power-up, the input and DAC registers clear (set to dim light (off) to obtain the dark current calibration. zero code). For rated performance, VREF_ should be at The µP then programs the DAC to set an output voltage least 1.4V below VDD. Bypass the power supply with a at the midpoint of the two calibrated values. 4.7µF capacitor in parallel with a 0.1µF capacitor to Applications include tachometers, motion sensing, AGND. Minimize lead lengths to reduce lead inductance. automatic readers, and liquid clarity analysis. Grounding and Layout Considerations Digital Control of Gain and Offset Digital and AC transient signals on AGND can create The two DACs can be used to control the offset and noise at the output. Connect AGND to the highest quality gain for curve-fitting nonlinear functions, such as trans- ground available. Use proper grounding techniques, ducer linearization or analog compression/expansion such as a multilayer board with a low-inductance ground applications. The input signal is used as the reference plane. Carefully lay out the traces between channels to for the gain-adjust DAC, whose output is summed with reduce AC cross-coupling and crosstalk. Wire-wrapped the output from the offset-adjust DAC. The relative boards and sockets are not recommended. If noise weight of each DAC output is adjusted by R1, R2, R3, becomes an issue, shielding may be required. and R4 (Figure 14). ______________________________________________________________________________________ 15

Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 5 __________________Pin Configuration _Ordering Information (continued) 5 1 TOP VIEW PART TEMP. RANGE PIN-PACKAGE INL (LSB) 5 AGND 1 16 VDD MAX5154AEPE -40°C to +85°C 16 Plastic DIP ±1/2 X OUTA 2 15 OUTB MAX5154BEPE -40°C to +85°C 16 Plastic DIP ±1 A OSA 3 14 OSB MAX5154AEEE -40°C to +85°C 16 QSOP ±1/2 M REFA 4 MAX5154 13 REFB MAX5154BEEE -40°C to +85°C 16 QSOP ±1 MAX5155 / CL 5 12 PDL MAX5154BMJE -55°C to +125°C 16 CERDIP* ±1 4 MAX5155ACPE 0°C to +70°C 16 Plastic DIP ±1 5 CS 6 11 UPO MAX5155BCPE 0°C to +70°C 16 Plastic DIP ±2 1 DIN 7 10 DOUT MAX5155ACEE 0°C to +70°C 16 QSOP ±1 5 SCLK 8 9 DGND MAX5155BCEE 0°C to +70°C 16 QSOP ±2 X MAX5155AEPE -40°C to +85°C 16 Plastic DIP ±1 DIP/QSOP A MAX5155BEPE -40°C to +85°C 16 Plastic DIP ±2 M MAX5155AEEE -40°C to +85°C 16 QSOP ±1 MAX5155BEEE -40°C to +85°C 16 QSOP ±2 ___________________Chip Information MAX5155BMJE -55°C to +125°C 16 CERDIP* ±2 TRANSISTOR COUNT: 3053 *Contact factory for availability. SUBSTRATE CONNECTED TO AGND ________________________________________________________Package Information QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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