19-0352; Rev 2; 7/02 Microprocessor Programmable Universal Active Filters General Description Features M The MAX260/MAX261/MAX262 CMOS dual second- (cid:2) Filter Design Software Available A order universal switched-capacitor active filters allow microprocessor control of precise filter functions. No (cid:2) Microprocessor Interface X external components are required for a variety of band- (cid:2) 64-Step Center Frequency Control 2 pass, lowpass, highpass, notch, and allpass configura- 6 tions. Each device contains two second-order filter (cid:2) 128-Step Q Control 0 sections that place center frequency, Q, and filter oper- (cid:2) Independent Q and f0Programming / ating mode under programmed control. M (cid:2) Guaranteed Clock to f0Ratio-1% (A grade) An input clock, along with a 6-bit f0 program input, A determine the filter's center or corner frequency without (cid:2) 75kHz f0Range (MAX262) affecting other filter parameters. The filter Q is also pro- X (cid:2) Single +5V and ±5V Operation grammed independently. Separate clock inputs for 2 each filter section operate with either a crystal, RC net- 6 work, or external clock generator. Ordering Information 1 The MAX260 has offset and DC specifications superior to the MAX261 and MAX262 and a center frequency PART TEMP RANGE PACKAGE AC C U R A C Y /M (f0) range of 7.5kHz. The MAX261 handles center fre- MAX260ACNG 0°C to +70°C Plastic DIP 1% A quencies to 57kHz, while the MAX262 extends the cen- MAX260BCNG 0°C to +70°C Plastic DIP 2% ter frequency range to 140kHz by employing lower X MAX260AENG -40°C to +85°C Plastic DIP 1% clock-to-f0ratios. All devices are available in 24-pin DIP 2 and small outline packages in commercial, extended, MAX260BENG -40°C to +85°C Plastic DIP 2% 6 and military temperature ranges. MAX260ACWG 0°C to +70°C Wide SO 1% 2 Applications MAX260BCWG 0°C to +70°C Wide SO 2% MAX260AMRG -55°C to +125°C CERDIP 1% µP-Tuned Filters MAX260BMRG -55°C to +125°C CERDIP 2% Anti-Aliasing Filters *All devices—24-pin packages 0.3in-wide packages Digital Signal Processing Ordering Information continued at end of data sheet. Adaptive Filters Signal Analysis Pin Configurations Phase-Locked Loops Functional Diagram TOP VIEW BPA 1 24 LPA BPA 1 24 LPA INPUT OUTPUT N.C. 2 23 INB OP OUT 2 23 INB IN LP HP BP IN LP HP BP HPA 3 22 LPB HPA 3 22 LPB +5V V+ FILATER FILBTER NI.NCA. 45 MAX260 2210 BDP0B OPI NINA 45 MAX261 2210 BHPPBB MAX262 D1 6 19 OSC OUT D1 6 19 D0 A3 7 18 GND A3 7 18 OSC OUT GND CLK OUT 8 17 V- CLK OUT 8 17 GND V+ 9 16 WR V+ 9 16 V- MAX260 -5V V- MAX261 A2 10 15 A0 A2 10 15 WR MAX262 CLKA 11 14 HPB CLKA 11 14 A0 CLKA OSC CLKOUT CLKB CLKB 12 13 A1 CLKB 12 13 A1 PROGRAM INPUTS CRYSTAL FOURTH-ORDER BANDPASS FILTER ________________________________________________________________Maxim Integrated Products 1 For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Microprocessor Programmable Universal Active Filters 2 ABSOLUTE MAXIMUM RATINGS 6 Total Supply Voltage (V+to V-) .............................................15V Operating Temperature Ranges 2 Input Voltage, any pin ..........................(V-- 0.3V) to (V++ 0.3V) MAX260/MAX261/MAX262XCXG .......................0°C to +70°C Input Current, any pin ......................................................±50mA MAX260/MAX261/MAX262XEXG .....................-40°C to +85°C X Power Dissipation MAX260/MAX261/MAX262XMXG ..................-55°C to +125°C A Plastic DIP (derate 8.33mW/°C above 70°C) ...............660mW Storage Temperature Range.............................-65°C to +160°C CERDIP (derate 12.5mW/°C above 70°C) .................1000mW Lead Temperature (Soldering, 10s) ................................+300°C M Wide SO (derate 11.8mW/°C above 70°C) ..................944mW / 1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to 6 absolute maximum rating conditions for extended periods may affect device reliability. 2 X A ELECTRICAL CHARACTERISTICS M (V+ = +5V, V- = -5V, CLKA = CLKB = ±5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0 = 199.49 for 0/ MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA= +25°C, unless otherwise noted.) 6 PARAMETER CONDITIONS MIN TYP MAX UNITS 2 f0 Center Frequency Range See Table 1 X Maximum Clock Frequency See Table 1 A MAX260A ±0.2 ±1.0 M MAX260B ±0.2 ±2.0 fCLK/f0 Ratio Error (Note 1) TA = TMIN to TMAX % MAX261/MAX262A ±0.2 ±1.0 MAX261/MAX262B ±0.2 ±2.0 f0 Temperature Coefficient -5 ppm/°C Q = 8 MAX260A ±1 ±6 Q = 8 MAX260B ±1 ±10 Q = 32 MAX260A ±2 ±10 Q = 32 MAX260B ±2 ±15 Q = 64 MAX260A ±4 ±20 Q Accuracy (deviation from ideal TA = TMIN to Q = 64 MAX260B ±4 ±25 % continuous filter) (Note 2) TMAX Q = 8 MAX261/MAX262A ±1 ±6 Q = 8 MAX261/MAX262B ±1 ±10 Q = 32 MAX261/MAX262A ±2 ±10 Q = 32 MAX261/MAX262B ±2 ±15 Q = 64 MAX261/MAX262A ±4 ±20 Q = 64 MAX261/MAX262B ±4 ±25 Q Temperature Coefficient ±20 ppm/°C MAX260 ±0.1 ±0.3 DC Lowpass Gain Accuracy dB MAX261/MAX262 ±0.1 ±0.5 MAX260 -5 Lowpass (at D.C.) Gain Temperature Coefficient MAX261/MAX262 -5 ppm/°C Bandpass (at f0) MAX260/MAX261/MAX262 +20 2 _______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters ELECTRICAL CHARACTERISTICS (continued) M (V+ = +5V, V- = -5V, CLKA = CLKB = ±5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0 = 199.49 for A MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA= +25°C, unless otherwise noted.) X PARAMETER CONDITIONS MIN TYP MAX UNITS 2 MAX260A ±0.05 ±0.25 6 MAX260B ±0.15 ±0.45 0 TA = TMIN to TMAX, Q = 4 MAX261A ±0.40 ±1.00 / Mode 1 MAX261B ±0.80 ±1.60 M MAX262A ±0.40 ±1.20 A Offset Voltage At Filter MAX262B ±0.80 ±1.60 X V Outputs—LP, BP, HP (Note 3) MAX260A ±0.075 ±0.30 2 MAX260B ±0.075 ±0.50 6 MAX261A ±0.50 ±1.10 Mode 3 1 MAX261B ±0.90 ±1.60 / M MAX262A ±0.50 ±1.30 MAX262B ±0.90 ±1.60 A Offset Voltage Temperature fCLK/f0 = 100.53, Q = 4 X ±0.75 mV/°C Coefficient TA = TMIN to TMAX 2 Clock Feedthrough ±4 mV 6 Crosstalk -70 dB 2 Q = 1, 2nd-Order, LP/BP See Typ. Oper. Char. Wideband Noise 4th-Order LP (Figure 26) 90 µVRMS 4th-Order BP (Figure 24) (Note 4) 100 Harmonic Distortion at f0 Q = 4, VIN = 1.5VP-P -67 dB Supply Voltage Range TA = TMIN to TMAX ±2.37 ±5 ±6.3 V MAX260 15 20 TA = TMIN to TMAX Power Supply Current (Note 5) MAX261 16 20 mA CMOS Level Logic Inputs MAX262 16 20 Q0A - Q6A = all 0, Shutdown Supply Current 1.5 mA CMOS Level Logic Inputs (Note 5) INTERNAL AMPLIFIERS Output Signal Swing TA = TMIN to TMAX, 10kΩ load (Note 6) ±4.75 V Source 50 Output Signal Circuit Current mA Sink 2 Power Supply Rejection Ratio 0Hz to 10kHz -70 dB Gain Bandwidth Product 2.5 MHz Slew Rate 6 V/µs _______________________________________________________________________________________ 3

Microprocessor Programmable Universal Active Filters 2 ELECTRICAL CHARACTERISTICS (for V± = ±2.5V ±5%) 6 (V+= +2.37V, V-= -2.37V, CLKA= CLKB= ±2.5V 250kHz for the MAX260 and 1MHz for the MAX261/MAX262, fCLK/f0= 199.49 for 2 MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA= +25°C, unless otherwise noted.) X PARAMETER CONDITIONS MIN TYP MAX UNITS A f0 Center Frequency Range (Note 7) Maximum Clock Frequency (Note 7) M fCLK/f0 Ratio Error MAX26XA ±0.1 1 / Q = 8 % 1 (Notes 1, 8) MAX26XB ±0.1 2 6 Q = 8 MAX260A ±2 ±6 2 fCLK/f0 = 199.49 MAX260B ±2 ±10 X Q Accuracy (deviation from ideal MAX261A ±2 ±6 continuous filter) fCLK/f0 = 199.49 % A MAX261B ±2 ±10 (Notes 2, 8) M MAX262A ±2 ±6 fCLK/f0 = 139.80 MAX262B ±2 ±10 / 0 Output Signal Swing All Outputs (Note 6) ±2 V 6 Power Supply Current CMOS Level Logic Inputs (Note 5) 7 mA 2 Shutdown Current CMOS Level Logic Inputs (Note 5) 0.35 mA X Note 1: fCLK/f0accuracy is tested at 199.49 on the MAX260/MAX261, and at 139.8 on the MAX262. A Note 2: Q accuracy tested at Q = 8, 32, and 64. Q of 32 and 64 tested at 1/2 stated clock frequency. M Note 3: The offset voltage is specified for the entire filter. Offset is virtually independent of Q and fCLK/f0ratio setting. The test clock frequency for mode 3 is 175kHz for the MAX260 and 750kHz for the MAX261/MAX262. Note 4: Output noise is measured with an RC output smoothing filter at 4 ✕ f0to remove clock feedthrough. Note 5: TTL logic levels are: HIGH = 2.4V, LOW = 0.8V. CMOS logic levels are: HIGH = 5V, LOW = 0V. Power supply current is typi- cally 4mA higher with TTL logic and clock input levels. Note 6: On the MAX260 only, the HP output signal swing is typically 0.75V less than the LP or BP outputs. Note 7: At ±2.5V supplies, the f0range and maximum clock frequency are typically 75% of values listed in Table 1. Note 8: fCLK/f0and Q accuracy are a function of the accuracy of internal capacitor ratios. No increase in error is expected at ±2.5V as compared to ±5V; however, these parameters are only tested to the extent indicated by the MIN or MAX limits. INTERFACE SPECIFICATIONS (Note 9) (V+= +5V, V+= -5V, TA= +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS WR Pulse Width tWR 250 150 ns Address Setup tAS 25 ns Address Hold tAH 0 ns Data Setup tDS 100 50 ns Data Hold tDH 10 0 ns WR, D0, D1, A0–A3, CLKA, CLKB Logic Input High VIH 2.4 V TA =TMIN to TMAX WR, D0, D1, A0–A3, CLKA, CLKB Logic Input Low VIL 0.8 V TA =TMIN to TMAX WR, D0, D1, A0–A3, CLKB 10 Input Leakage Current IIN CLKA 6 60 µA TA =TMIN to TMAX Input Capacitance CIN WR, D0, D1, A0–A3, CLKA, CLKB 15 pF Note 9: Interface timing specifications are guaranteed by design and are not subject to test. 4 _______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters Pin Description M PIN PIN A MAX261/ NAME FUNCTION MAX261/ NAME FUNCTION X MAX260 MAX260 MAX262 MAX262 2 9 9 V+ Positive supply voltage 5, 23 5, 23 INA, INB Filter inputs 6 17 16 V- Negative supply voltage 1, 21 1, 21 BPA, BPB Bandpass outputs 0 Analog Ground. Connect 24, 22 24, 22 LPA, LPB Lowpass outputs /M to the system ground for Highpass/notch/allpass dual supply operation or 3, 14 3, 20 HPA, HPB outputs A 18 17 GND mid-supply for single sup- 16 15 WR Write enable input X ply operation. GND should be well bypassed in single 15, 13, 14, 13, A0, A1, Address inputs for f0 and 2 10, 7 10, 7 A2, A3 Q input data locations supply applications. 6 Input to the oscillator and 20, 6 19, 6 D0, D1 Data inputs for f0 and Q 1 programming clock input to section A. / 11 11 CLKA This clock is internally Outpu t of uncomm i t ted M divided by 2. op amp on MA X2 61/ 2 OP OUT A MA X 262 only . Pi n 2 is a no- Clock input to filter B. This connect on the MA X2 60. X 12 12 CLKB clock is internally divided by 2. Invert i ng in pu t of uncom- 2 mi tted op am p on M AX 261/ Cl ock outp ut for cry stal 6 8 8 CLK OUT MA X2 62 onl y (n oni nvert i ng and R-C oscil l a tor ope r ati on 4 OP IN 2 in pu t i s in tern all y connected Connects to crystal or R-C to g ro und) . Pi n 4 is a no- 19 18 OSC OUT for self-clocked operation connect on the MA X 260. _______________________________________________________________________________________ 5

Microprocessor Programmable Universal Active Filters 2 Typical Operating Characteristics 6 (TA = +25°C, unless otherwise noted.) 2 Q ERROR vs. CLOCK FREQUENCY X MAX260 IDD vs. POWER SUPPLY VOLTAGE IDD vs. CLOCK FREQUENCY /MA 2300 ±2QfC55 L=°VK C8/f0 (cid:4) N = 0 MODE 4 MAX260/61/62 toc01 2205 C2C5LO°KNC TFRROEQL P= I5N0S0 (K5HVz, 0V) MAX260/61/62 toc02 112980 CLOCK C(2L.O4VC,K 0 (.85VV), 0V) MAX260/61/62 toc03 X261 Q ERROR (%) 100 MODES 2 & 3 MODE 1 I (mA)DD 15 CLOCKS (5V, 0V) I (mA)DD 1176 ±C255O°VNCTROL PINS (5V, 0V)CLOCK (5V, -5V) CLOCKS (5V, -5V) 15 A 10 -10 14 M -20 5 13 0/ 0.2 0.4 0.6 0.8 1.0 1.2 1.4 5 6 7 8 9 10 11 12 0.5 1.5 2.5 3.5 CLOCK FREQUENCY (MHz) V+ TO V- (V) CLOCK FREQUENCY (MHz) 6 2 Q ERROR vs. CLOCK FREQUENCY FCLK/F0 ERROR vs. CLOCK FREQUENCY OUTPUT SIGNAL SWING MAX261/MAX262 MAX261/MAX262 vs. CLOCK FREQUENCY X MA %) 112260 ±QTfCAf5 0L= V=K 8 2(cid:4)5° CN = 0 MODE 3 MAX260/61/62 toc04 R (%)--000...4202 ±QTA5 = V= 8 25°C MODES 2M, 3ODES 1, 4 MAX260/61/62 toc05 UT SWING (V) 7658 MAX261/MAX262 ALL MODES MAX260/61/62 toc06 Q ERROR ( 48 MODE 2 F/F ERROCLK0--00..86 fCf0LK(cid:4) N = 0 TO PEAK, OUTP 43 MAX260 MODE 4 ±2Q55 =°V C8 -1.0 AK 2 fCLK/f0(cid:4) N = 0 0 PE MODES 1, 4 -1.2 1 MAX260 MODES 1, 2, 3 -4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.0 1.5 2.0 2.5 3.0 3.5 0.2 0.6 1.0 1.4 1.8 2.2 2.8 3.0 CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz) Wideband RMS Noise(db ref. to 2.47VRMS, 7VP-P)±5V Supplies Noise Spectral Distribution Q = 1 Q = 8 Q = 64 (MAX261, fCLK= 1MHz, dB ref. to 2.47VRMS, MODE 7VP-P) LP BP HP/AP/N LP BP HP/AP/N LP BP HP/AP/N MEASUREMENT 1 -84 -90 -84 -80 -82 -85 -72 -73 -85 Q = 1 Q = 8 Q = 64 1/2 BANDWIDTH 2626 2 -88 -90 -88 -84 -82 -84 -77 -73 -76 XX Wideband -84 -80 -72 AA 3 -84 -90 -88 -80 -82 -82 -73 -73 -74 MM 3kHz -87 -87 -86 4 -83 -89 -84 -79 -81 -85 -71 -73 -85 C Message 1 -87 -89 -86 -81 -81 -86 -73 -73 -86 -93 -93 -93 0 Weighted 6 2 -89 -88 -85 -83 -80 -82 -75 -72 -74 2 X A 3 -87 -88 -85 -80 -82 -80 -71 -72 -72 M 4 -87 -88 -86 -81 -81 -86 -71 -72 -86 Note 1: fCLK= 1MHz for MAX261/MAX262, fCLK= 350kHz for MAX260 Note 2: fCLK/f0ratio programmed at N = 63 (see Table 2) Note 3: Clock feedthrough is removed with an RC lowpass ar 4f0, ie., R = 3.9kΩ, C = 2000pF for MAX261. 6 _______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters M S-H N/HP/AP A SCN = SWITCH-CAPACITOR NETWORK SAMPLE-HOLD X MAX260 ONLY S1 2 SCN 6 BP - 0 IN SCN - + Σ ∫ ∫ LP /M + - A S1 S2 S3 S2 X 2 6 MODE SCN SELECT 1 / S3 M M0 M1 SCN A Q0–Q6 F0–F5 X (TABLE 3) (TABLE 2) 2 6 Figure 1. Filter Block Diagram (One Second-Order Section) 2 Introduction ance at the expense of high-end f0 and signal band- width. The N/HP/AP outputs of the MAX260 are internal- Each MAX260/MAX261/MAX262 contains two second- ly sample-and-held as a result of its auto-zero order switched-capacitor active filters. Figure 1 shows operation. Signal swing at this output is somewhat the filter's state variable topology, employed with two reduced as a result (MAX260 only). See Table 1 for cascaded integrators and one summing amplifier. The bandwidth comparisons of the three filters. MAX261 and MAX262 also contain an uncommitted amplifier. On-chip switches and capacitors provide Maxim also provides design programs that aid in con- feedback to-control each filter section's f0 and Q. verting filter response specifications into the f0 and Q Internal capacitor ratios are primarily responsible for program codes used by the MAX260 series devices. the accuracy of these parameters. Although these This software also precompensates f0 and Q when low switched-capacitor networks (SCN) are in fact sampled sample rates are used. systems, their behavior very closely matches that of It is important to note that, in all MAX260 series filters, continuous filters, such as RC active filters. The ratio of the filter's internal sample rate is one half the input the clock frequency to the filter center frequency clock rate (CLKA or CLKB) due to an internal division (fCLK/f0) is kept large so that ideal second-order state- by two. All clock-related data, tables, and other dis- variable response is maintained. cussions in this data sheet refer to the frequency at the The MAX262 uses a lower range of sampling (fCLK/f0) CLKAor CLKBinput, i.e., twice the internal sample rate, ratios than the MAX260 or MAX261 to allow higher unless specifically stated otherwise. operating f0 frequencies and signal bandwidths. These Quick Look Design Procedure reduced sample rates result in somewhat more devia- tion from ideal continuous filter parameters than with The MAX260, MAX261, and MAX262, with Maxim's filter the MAX260/MAX261. However, these differences can design software, greatly simplify the design procedures be compensated using Figure 20 (see Application for many active filters. Most designs can be realized Hints) or Maxim's filter design software. using a three-step process described in this section. If the design software is not used, or if the filter complexi- The MAX260 employs auto-zero circuitry not included ty is beyond the scope of this section, refer to the in the MAX261 or MAX262. This provides improved DC remainder of this data sheet for more detailed applica- characteristics, and improved low-frequency perform- tions and design information. _______________________________________________________________________________________ 7

Microprocessor Programmable Universal Active Filters 2 100 AB$ = "FILTER A" : GOSUB 150 : REM GET DATA FOR SECTION A 6 110 ADD = 0 : GOSUB 220 : REM WRITE DATA TO THE PRINTER PORT 2 120 AB$ = "FILTER B" : GOSUB 150 : REM GET DATA FOR B X 130 ADD = 32 : GOSUB 220 : REM WRITE DATA TO PRINTER PORT 140 GOTO 100 A 150 PRINT "MODE (1 to 4, see Table 5) "; AB$; : INPUT M 160 IF M<1 OR M>4 THEN GOTO 150 M 170 PRINT "CLOCK RATIO (0 to 63, N of Table 2) "; AB$; : INPUT F 180 IF F<0 OR F>63 THEN GOTO 170 1/ 190 PRINT "Q (0 to 127, N of Table 3) "; AB$; : INPUT Q 200 IF Q<0 OR Q>127 THEN GOTO 190 ELSE : PRINT 6 210 RETURN 2 220 LPRINT CHR$(ADD+M-1); : ADD = ADD+4 230 FOR I = 1 TO 3 X 240 X = (ADD + (F - 4*INT(F/4))) : LPRINT CHR$(X); 250 F=INT(F/4) : ADD = ADD + 4 A 260 NEXT I M 270 FOR I = 1 TO 4 280 X=(ADD + (Q - 4*INT(Q/4))) : LPRINT CHR$(X); / 290 Q=I(Q/4) :: ADD = ADD + 4 0 300 NEX T I 6 310 RETURN 2 X WR 16(15) 1 25 5 2 A IN INA 20(19) 3 24 D0 23 M 24 LPA 4 22 6 5 D1 21 3 6 HPA 20 15(14) 7 A0 19 1 BPA MMAAXX226610* A1 13 18 23 MAX262* INB 10 11 A2 22 LPB 12 DB-25 MALE PLUG 7 (BACK VIEW) A3 (20)14 HPB 11 CLKA 21 BPB 12 CLKB OUT V+ GND V- 9 18(17) 17(16) CLK IN 0.1µF 0.1µF TTL (SEE FIGURE 4) +5V -5V *PIN NUMBERS IN ( ) ARE FOR MAX261/MAX262 Figure 2. Basic Program and Hardware Connections to Parallel Printer Port for “Quick Look” Using a PC Step 1—Filter Design quency response and calculates the pole/zero (f0) and Start with the program “PZ” to determine what type of Q values for each second-order section. Each filter is needed. This helps determine the type MAX260/MAX261/MAX262 contains two second-order (Butterworth, Chebyshev, etc.) and the number of poles sections, and devices can be cascaded for higher for the optimum choice. The program also plots the fre- order filters. 8 _______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters Step 2—Generate Programming Program PR.BAS Allows a MAX260/MAX261/MAX262 M Coefficients to be programmed through a personal computer. The Starting with the f0and Q values obtained in Step 1, use mode, f0, and Q of each section are typed in, and the A the program “MPP” to generate the digital coefficients proper codes are sent to the filter through the comput- X that program each second-order section's f0and Q. The er’s parallel printer port. This program is also provided 2 program displays values for “N” (“N = _ for f0” and “N = in Figure 2. 6 _ for Q”). N is the decimal equivalent of the binary code Other design programs are also included for use with that sets the filter section’s f0 or Q. These are the same other Maxim filter products. 0 “N”s that are listed in Tables 2 and 3. / Other Filter Products M An input clock frequency and filter mode must also be selected in this step; however, if a specific-clock rate is Maxim has developed a number of other filter products A not selected, “GEN” picks one. With regard to mode in addition to the MAX260, MAX261, and MAX262. X selection, mode 1 is the most convenient choice for PIN-PROGRAMMABLE ACTIVE FILTERS—A dual sec- 2 most bandpass and lowpass filters. Exceptions are ond-order universal filter that needs no external compo- elliptic bandpass and lowpass filters, which require nents. A microprocessor interface is not required. 6 mode 3. Highpass filters also use mode 3, while allpass 1 filters use mode 4. For further information regarding MAX263 0.4Hz to 30kHz f0range / these filter modes, see the Filter Operating Modes sec- MAX264 1Hz to 75kHz f0range M tion. RESISTOR AND PIN-PROGRAMMABLE FILTERS—A A Step 3—Loading the Filter dual second-order universal filter where f0 adjustment X When the N values for the f0 and Q of each second- beyond pin-programmable resolution employs external 2 order filter section are determined, the filter can then be resistors. 6 programmed and operated. What follows is a con- MAX265 0.4Hz to 30kHz f0 range. Includes two venient method of programming the filter and evalu- uncommitted op amps. 2 ating a design if a PC is available. MAX266 1Hz to 75kHz f0 range. Includes two un- A short BASIC program loads data into the MAX260/ committed op amps. MAX261/MAX262 through the PC's parallel printer port. MF10 Industry Standard, Resistor Programmed Only The program asks for the filter mode, as well as the N values for the f0 and Q of each section. These coeffi- PIN-PROGRAMMABLE BANDPASS FILTERS—A cients are then loaded into the filter in the form of ASCII dual second-order bandpass that needs no external characters. This program can be used with or without components. A microprocessor interface is not Maxim's other filter design software. The program and required. the appropriate hardware connections for a Centronics- type printer port are shown in Figure 2. MAX267 0.4Hz to 30kHz f0range MAX268 1Hz to 75kHz f0range Filter Design Software PROGRAMMABLE ANTI-ALIAS FILTER—A program- Maxim provides software programs to help speed the mable dual second-order continuous (not switched) transition from frequency response design require- lowpass filter. No clock noise is generated. Designed ments to working hardware. A series of programs are for use as an anti-alias filter in front of, or as a smooth- available, including: ing filter following, any sampled filter or system. Program PZ. Given the requirements, such as center MAX270 1kHz to 25kHz Cutoff Frequency Range frequency, Q, passband ripple, and stopband attenua- tion, PZ calculates the pole frequencies, Q's, zeros, 5th-ORDER LOW PASS FILTER—Features zero offset and the number of stages needed. and drift errors for designs requiring high DC accuracy. Program MPP. For programmed filters, MPP computes MAX280, LT1062 0.1Hz to 20kHz Cutoff Frequency the input codes to use and describes the expected Range performance of the design. Program FR. When a design of one or more stages is completed, FR checks the final cascaded assembly. The output frequency response can be compared with that expected from PZ. _______________________________________________________________________________________ 9

Microprocessor Programmable Universal Active Filters 2 Table 1. Typical Clock and Center Frequency Limits 6 2 PART Q MODE fCLK f0 PART Q MODE fCLK f0 X 1 1 1Hz–400kHz 0.01Hz–4.0kHz 8 3 40Hz–1.7MHz 0.4Hz–17kHz 1 2 1Hz–425kHz 0.01Hz–6.0kHz 8 4 40Hz–2.7MHz 0.4Hz–27kHz A 1 3 1Hz–500kHz 0.01Hz–5.0kHz 64 1 40Hz–2.0MHz 0.4Hz–20kHz M MAX261 1 4 1Hz–400kHz 0.01Hz–4.0kHz 90 2 40Hz–1.2MHz 0.4Hz–18kHz 1/ 8 1 1Hz–500kHz 0.01Hz–5.0kHz 64 3 40Hz–1.2MHz 0.4Hz–12kHz 6 8 2 1Hz–700kHz 0.01Hz–10.0kH 64 4 40Hz–2.0MHz 0.4Hz–20kHz MAX260 2 8 3 1Hz–700kHz 0.01Hz–5.0kHz 1 1 40Hz–4.0MHz 1.0Hz–100kHz X 8 4 1Hz–600kHz 0.01Hz–4.0kHz 1 2 40Hz–4.0MHz 1.4Hz–140kHz A 64 1 1Hz–750kHz 0.01Hz–7.5kHz 1 3 40Hz–4.0MHz 1.0Hz–100kHz 90 2 1Hz–500kHz 0.01Hz–7.0kHz 1 4 40Hz–4.0MHz 1.0Hz–100kHz M 64 3 1Hz–400kHz 0.01Hz–4.0kHz 8 1 40Hz–2.5MHz 1.0Hz–60kHz / 0 64 4 1Hz–750kHz 0.01Hz–7.5kHz 6 2 40Hz–1.4MHz 1.4Hz–50kHz MAX262 6 1 1 40Hz–4.0MHz 0.4Hz–40kHz 8 3 40Hz–1.4MHz 1.0Hz–35kHz 2 1 2 40Hz–4.0MHz 0.5Hz–57kHz 8 4 40Hz–2.5MHz 1.0Hz–60kHz X 1 3 40Hz–4.0MHz 0.4Hz–40kHz 64 1 40Hz–1.5MHz 1.0Hz–37kHz MAX261 A 1 4 40Hz–4.0MHz 0.4Hz–40kHz 90 2 40Hz–0.9MHz 1.4Hz–32kHz M 8 1 40Hz–2.7MHz 0.4Hz–27kHz 64 3 40Hz–0.9MHz 1.0Hz–22kHz 8 2 40Hz–2.1MHz 0.5Hz–30kHz 64 4 40Hz–1.5MHz 1.0Hz–37kHz INA N/HP/APA BPA LPA INB N/HP/APB BPB LPB V+ ∫ ∫ ∫ ∫ V- MODE f0 Q CK MODE f0 Q CK GND 2 6 7 2 6 7 A PROGRAM MEMORY ÷2 B PROGRAM MEMORY ÷2 MODE, f0, Q MODE, f0, Q MAX261/MAX262 ONLY 15 15 - + INTERFACE LOGIC 2 4 D0, D1 A0–A3 WR CLKA OSC OUT CLK OUT CLKB OP IN OP OUT Figure 3. MAX260/MAX261/MAX262 Block Diagram 10 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters Table 2. fCLK/f0 Program Selection Table M fCLK/f0 RATIO A PROGRAM CODE MAX260/MAX261 MAX262 X MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 N F5 F4 F3 F2 F1 F0 2 100.53 71.09 40.84 28.88 0 0 0 0 0 0 0 6 102.10 72.20 42.41 29.99 1 0 0 0 0 0 1 0 103.67 73.31 43.98 31.10 2 0 0 0 0 1 0 105.24 74.42 45.55 32.21 3 0 0 0 0 1 1 /M 106.81 75.53 47.12 33.32 4 0 0 0 1 0 0 108.38 76.64 48.69 34.43 5 0 0 0 1 0 1 A 109.96 77.75 50.27 35.54 6 0 0 0 1 1 0 X 111.53 78.86 51.84 36.65 7 0 0 0 1 1 1 2 113.10 79.97 53.41 37.76 8 0 0 1 0 0 0 6 114.67 81.08 54.98 38.87 9 0 0 1 0 0 1 1 116.24 82.19 56.55 39.99 10 0 0 1 0 1 0 117.81 83.30 58.12 41.10 11 0 0 1 0 1 1 / M 119.38 84.42 59.69 42.21 12 0 0 1 1 0 0 120.95 85.53 61.26 43.32 13 0 0 1 1 0 1 A 122.52 86.64 62.83 44.43 14 0 0 1 1 1 0 X 124.09 87.75 64.40 45.54 15 0 0 1 1 1 1 2 125.66 88.86 65.97 46.65 16 0 1 0 0 0 0 6 127.23 89.97 67.54 47.76 17 0 1 0 0 0 1 128.81 91.80 69.12 48.87 18 0 1 0 0 1 0 2 130.38 92.19 70.69 49.98 19 0 1 0 0 1 1 131.95 93.30 72.26 51.10 20 0 1 0 1 0 0 133.52 94.41 73.83 52.20 21 0 1 0 1 0 1 135.08 95.52 75.40 53.31 22 0 1 0 1 1 0 136.66 96.63 76.97 54.43 23 0 1 0 1 1 1 138.23 97.74 78.53 55.54 24 0 1 1 0 0 0 139.80 98.86 80.11 56.65 25 0 1 1 0 0 1 141.37 99.97 81.68 57.76 26 0 1 1 0 1 0 142.94 101.08 83.25 58.87 27 0 1 1 0 1 1 14.4.51 102.89 84.82 59.98 28 0 1 1 1 0 0 146.08 103.30 86.39 61.09 29 0 1 1 1 0 1 147.65 104.41 87.96 62.20 30 0 1 1 1 1 0 149.23 105.52 89.54 63.31 31 0 1 1 1 1 1 150.80 106.63 91.11 64.42 32 1 0 0 0 0 0 152.37 107.74 92.68 65.53 33 1 0 0 0 0 1 153.98 108.85 94.25 66.64 34 1 0 0 0 1 0 155.51 109.96 95.82 67.75 35 1 0 0 0 1 1 157.08 111.07 97.39 68.86 36 1 0 0 1 0 0 158.65 112.18 98.96 69.98 37 1 0 0 1 0 1 160.22 113.29 100.53 71.09 38 1 0 0 1 1 0 161.79 114.41 102.10 72.20 39 1 0 0 1 1 1 163.36 115.52 102.67 73.31 40 1 0 1 0 0 0 164.93 116.63 105.24 74.42 41 1 0 1 0 0 1 166.50 117.74 106.81 75.53 42 1 0 1 0 1 0 168.08 118.85 108.38 76.64 43 1 0 1 0 1 1 169.65 119.96 109.96 77.75 44 1 0 1 1 0 0 171.22 121.07 111.53 78.86 45 1 0 1 1 0 1 ______________________________________________________________________________________ 11

Microprocessor Programmable Universal Active Filters 2 Table 2. fCLK/f0 Program Selection Table (continued) 6 fCLK/f0 RATIO 2 PROGRAM CODE MAX260/MAX261 MAX262 X MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 N F5 F4 F3 F2 F1 F0 A 172.79 122.18 113.10 79.97 46 1 0 1 1 1 0 M 174.36 123.29 114.66 81.08 47 1 0 1 1 1 1 175.93 124.40 11624 82.19 48 1 1 0 0 0 0 / 177.50 125.51 117.81 83.30 49 1 1 0 0 0 1 1 179.07 126.62 119.38 84.41 50 1 1 0 0 1 0 6 180.64 127.73 120.95 85.53 51 1 1 0 0 1 1 2 182.21 128.84 122.52 86.64 52 1 1 0 1 0 0 X 183.78 129.96 124.09 87.75 53 1 1 0 1 0 1 A 185.35 131.07 125.66 88.86 54 1 1 0 1 1 0 186.92 132.18 127.23 89.97 55 1 1 0 1 1 1 M 188.49 133.29 128.81 91.08 56 1 1 1 0 0 0 / 190.07 134.40 130.38 92.19 57 1 1 1 0 0 1 0 191.64 135.51 131.95 93.30 58 1 1 1 0 1 0 6 193.21 136.62 133.52 94.41 59 1 1 1 0 1 1 2 194.78 137.73 135.09 95.52 60 1 1 1 1 0 0 X 196.35 138.84 136.66 96.63 61 1 1 1 1 0 1 A 197.92 139.95 138.23 97.74 62 1 1 1 1 1 0 199.49 141.06 139.80 98.85 63 1 1 1 1 1 1 M Note 1: For the MAX260/MAX261, fCLK/f0= (64 + N)π / 2 in modes 1, 3, and 4, where N varies from 0 to 63. Note 2: For the MAX262, fCLK/f0= (26 s N)π / 2 in modes 1, 3, and 4, where N varies 0 to 63. Note 3: In mode 2, all fCLK/f0ratios are divided by √2. The functions are then: MAX260/MAX261 fCLK/f0= 1.11072 (64 + N), MAX262 fCLK/f0= 1.11072 (26 + N) Detailed Description The duty cycle of the clock at CLKA and CLKB is unim- portant because the input is internally divided by 2 to f0 and Q Programming generate the sampling clock for each filter section. It is Figure 3 shows a block diagram of the MAX260. Each important to note that this internal division also halves second-order filter section has its own clock input and the sample rate when considering aliasing and other independent f0 and Q control. The actual center fre- sampled system phenomenon. quency is a function of the filter's clock rate, 6-bit f0 control word (see Table 2), and operating mode. The Q Microprocessor Interface of each section is also set by a separate programmed f0, Q, and mode-selection data are stored in internal input (see Table 3). This way, each half of a MAX260/ program memory. The memory contents are updated MAX261/MAX262 is tuned independently so that com- by writing to addresses selected by A0–A3. D0, and D1 plex filter polynomials can be realized. Equations that are the data inputs. A map of the memory locations is convert program code numbers to fCLK/f0and Q values shown in Table 4. Data is stored in the selected are listed in the notes beneath Tables 2 and 3. address on the rising edge of WR. Address and data inputs are TTL and CMOS compatible when the filter is Oscillator and Clock Inputs powered from ±5V. With other power supply voltages, The clock circuitry of the MAX260/MAX261/MAX262 CMOS logic levels should be used. Interface timing is can operate with a crystal, resistor-capacitor (RC) net- shown in Figure 5. Note: Clock inputs CLKA and CLKB work, or an external clock generator as shown in Figure have no relation to the digital interface. They control the 4. If an RC oscillator is used, the clock rate, fCLK, nomi- switched-capacitor filter sample rate only. nally equals 0.45/RC. Some noise may be generated on the filter outputs by transitions at the logic inputs. If this is objectionable, 12 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters Table 3. Q Program Selection Table M PROGRAMMED Q PROGRAM CODE PROGRAMMED Q PROGRAM CODE A MODES MODE MODES MODE X N Q6 Q5 Q4 Q3 Q2 Q1 Q0 N Q6 Q5 Q4 Q3 Q2 Q1 Q0 1,3,4 2 1,3,4 2 2 0.500* 0.707* 0* 0 0 0 0 0 0 0 0.615 0.870 24 0 0 1 1 0 0 0 6 0.504 0.713 1 0 0 0 0 0 0 1 0.621 0.879 25 0 0 1 1 0 0 1 0 0.508 0.718 2 0 0 0 0 0 1 0 0.627 0.887 26 0 0 1 1 0 1 0 / M 0.512 0.724 3 0 0 0 0 0 1 1 0.634 0.896 27 0 0 1 1 0 1 1 A 0.516 0.730 4 0 0 0 0 1 0 0 0.640 0.905 28 0 0 1 1 1 0 0 0.520 0.736 5 0 0 0 0 1 0 1 0.646 0.914 29 0 0 1 1 1 0 1 X 0.525 0.742 6 0 0 0 0 1 1 0 0.653 0.924 30 0 0 1 1 1 1 0 2 0.529 0.748 7 0 0 0 0 1 1 1 0.660 0.933 31 0 0 1 1 1 1 1 6 0.533 0.754 8 0 0 0 1 0 0 0 0.667 0.943 32 0 1 0 0 0 0 0 1 0.538 0.761 9 0 0 0 1 0 0 1 0.674 0.953 33 0 1 0 0 0 0 1 /M 0.542 0.767 10 0 0 0 1 0 1 0 0.681 0.963 34 0 1 0 0 0 1 0 A 0.547 0.774 11 0 0 0 1 0 1 1 0.688 0.973 35 0 1 0 0 0 1 1 X 0.552 0.780 12 0 0 0 1 1 0 0 0.696 0.984 36 0 1 0 0 1 0 0 0.556 0.787 13 0 0 0 1 1 0 1 0.703 0.995 37 0 1 0 0 1 0 1 2 6 0.561 0.794 14 0 0 0 1 1 1 0 0.711 1.01 38 0 1 0 0 1 1 0 2 0.566 0.801 15 0 0 0 1 1 1 1 0.719 1.02 39 0 1 0 0 1 1 1 0.571 0.808 16 0 0 1 0 0 0 0 0.727 1.03 40 0 1 0 1 0 0 0 0.577 0.815 17 0 0 1 0 0 0 1 0.736 1.04 41 0 1 0 1 0 0 1 0.582 0.823 18 0 0 1 0 0 1 0 0.744 1.05 42 0 1 0 1 0 1 0 0.587 0.830 19 0 0 1 0 0 1 1 0.753 1.06 43 0 1 0 1 0 1 1 0.593 0.838 20 0 0 1 0 1 0 0 0.762 1.08 44 0 1 0 1 1 0 0 0.598 0.646 21 0 0 1 0 1 0 1 0.771 1.09 45 0 1 0 1 1 0 1 0.604 0.854 22 0 0 1 0 1 1 0 0.780 1.10 46 0 1 0 1 1 1 0 0.609 0.862 23 0 0 1 0 1 1 1 0.790 1.12 47 0 1 0 1 1 1 1 Note 4: * Writing all 0s into Q0A–Q6A on Filter A activates a low-power shutdown mode. BOTH filter sections are deactivated. Therefore, this Q value is only achievable in filter B. ______________________________________________________________________________________ 13

Microprocessor Programmable Universal Active Filters 2 Table 3. Q Program Selection Table (continued) 6 PROGRAMMED Q PROGRAM CODE PROGRAMMED Q PROGRAM CODE 2 MODES MODE MODES MODE X N Q6 Q5 Q4 Q3 Q2 Q1 Q0 N Q6 Q5 Q4 Q3 Q2 Q1 Q0 1,3,4 2 1,3,4 2 A 0.800 1.13 48 0 1 1 0 0 0 0 1.60 2.26 88 1 0 1 1 0 0 0 M 0.810 1.15 49 0 1 1 0 0 0 1 1.64 2.32 89 1 0 1 1 0 0 1 0.821 1.16 50 0 1 1 0 0 1 0 1.68 2.40 90 1 0 1 1 0 1 0 / 0.831 1.18 51 0 1 1 0 0 1 1 1.73 2.45 91 1 0 1 1 0 1 1 1 0.842 1.19 52 0 1 1 0 1 0 0 1.78 2.51 92 1 0 1 1 1 0 0 6 0.853 1.21 53 0 1 1 0 1 0 1 1.83 2.59 93 1 0 1 1 1 0 1 2 0.865 1.22 54 0 1 1 0 1 1 0 1.88 2.66 94 1 0 1 1 1 1 0 X 0.877 1.24 55 0 1 1 0 1 1 1 1.94 2.74 95 1 0 1 1 1 1 1 A 0.889 1.26 56 0 1 1 1 0 0 0 2.00 2.83 96 1 1 0 0 0 0 0 0.901 1.27 57 0 1 1 1 0 0 1 2.06 2.92 97 1 1 0 0 0 0 1 M 0.914 1.29 58 0 1 1 1 0 1 0 2.13 3.02 98 1 1 0 0 0 1 0 / 0.928 1.31 59 0 1 1 1 0 1 1 2.21 3.12 99 1 1 0 0 0 1 1 0 0.941 1.33 60 0 1 1 1 1 0 0 2.29 3.23 100 1 1 0 0 1 0 0 6 0.955 1.35 61 0 1 1 1 1 0 1 2.37 3.35 101 1 1 0 0 1 0 1 2 0.969 1.37 62 0 1 1 1 1 1 0 2.46 3.48 102 1 1 0 0 1 1 0 X 0.985 1.39 63 0 1 1 1 1 1 1 2.56 3.62 103 1 1 0 0 1 1 1 A 1.00 1.41 64 1 0 0 0 0 0 0 2.67 3.77 104 1 1 0 1 0 0 0 1.02 1.44 65 1 0 0 0 0 0 1 2.78 3.96 105 1 1 0 1 0 0 1 M 1.03 1.46 66 1 0 0 0 0 1 0 2.91 4.11 106 1 1 0 1 0 1 0 1.05 1.48 67 1 0 0 0 0 1 1 3.05 4.31 107 1 1 0 1 0 1 1 1.07 1.51 68 1 0 0 0 1 0 0 3.20 4.53 108 1 1 0 1 1 0 0 1.08 1.53 69 1 0 0 0 1 0 1 3.37 4.76 109 1 1 0 1 1 0 1 1.10 1.56 70 1 0 0 0 1 1 0 3.56 5.03 110 1 1 0 1 1 1 0 1.12 1.59 71 1 0 0 0 1 1 1 3.76 5.32 111 1 1 0 1 1 1 1 1.14 1.62 72 1 0 0 1 0 0 0 4.00 5.66 112 1 1 1 0 0 0 0 1.16 1.65 73 1 0 0 1 0 0 1 4.27 6.03 113 1 1 1 0 0 0 1 1.19 1.68 74 1 0 0 1 0 1 0 4.57 6.46 114 1 1 1 0 0 1 0 1.21 1.71 75 1 0 0 1 0 1 1 4.92 6.96 115 1 1 1 0 0 1 1 1.23 1.74 76 1 0 0 1 1 0 0 5.33 7.54 116 1 1 1 0 1 0 0 1.25 1.77 77 1 0 0 1 1 0 1 5.82 8.23 117 1 1 1 0 1 0 1 1.28 1.81 78 1 0 0 1 1 1 0 6.40 9.05 118 1 1 1 0 1 1 0 1.31 1.85 79 1 0 0 1 1 1 1 7.11 10.1 119 1 1 1 0 1 1 1 1.33 1.89 80 1 0 1 0 0 0 0 8.00 11.3 120 1 1 1 1 0 0 0 1.36 1.93 81 1 0 1 0 0 0 1 9.14 12.9 121 1 1 1 1 0 0 1 1.39 1.97 82 1 0 1 0 0 1 0 10.7 15.1 122 1 1 1 1 0 1 0 1.42 2.01 83 1 0 1 0 0 1 1 12.8 18.1 123 1 1 1 1 0 1 1 1.45 2.06 84 1 0 1 0 1 0 0 16.0 22.6 124 1 1 1 1 1 0 0 1.49 2.10 85 1 0 1 0 1 0 1 21.3 30.2 125 1 1 1 1 1 0 1 1.52 2.16 86 1 0 1 0 1 1 0 32.0 45.3 126 1 1 1 1 1 1 0 1.56 2.21 87 1 0 1 0 1 1 1 64.0 90.5 127 1 1 1 1 1 1 1 Notes 5) In modes 1, 3, and 4: Q = 64 / (128 - N) 6) In mode 2, the listed Q values are those of mode 1 multiplied by √2. Then Q = 90.51 / (128 - N) 14 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters Table 4. Program Address Locations M DATA BIT ADDRESS A FILTER A LOCATION FILTER B D0 D1 A3 A2 A1 A0 X FILTER A 2 M0A M1A 0 0 0 0 0 CLKA OOSUCT COLUKT CLKB F0A F1A 0 0 0 1 1 60 11 19(18)* 8 12 F2A F3A 0 0 1 0 2 F4A F5A 0 0 1 1 3 /M CRYSTAL Q0A Q1A 0 1 0 0 4 *OSC OUT IS PIN 18 ON MAX261/MAX262 Q2A Q3A 0 1 0 1 5 A Q4A Q5A 0 1 1 0 6 X FILTER A Q6A 0 1 1 1 7 FILTER B FILTER B 2 6 M0B M1B 1 0 0 0 8 CLKA OOSUCT COLUKT CLKB FF02BB FF13BB 11 00 01 10 190 1/M 11 19(18)* 8 12 0.45 F4B F5B 1 0 1 1 11 R C fCLK = RC Q0B Q1B 1 1 0 0 12 A Q2B Q3B 1 1 0 1 13 X Q4B Q5B 1 1 1 0 14 FILTER A 2 FILTER B Q6B 1 1 1 1 15 6 Note: Writing 0 into Q0A–Q6A (address locations 4–7) on filter 2 A activates shutdown mode. BOTH filter sections deactivate. CLKA OOSUCT COLUKT CLKB 11 12 N.C. N.C. EXTERNAL CLOCK IN tAS tAH (ANY DUTY CYCLE) A0–A3 VALID ADDRESS Figure 4. Clock Input Connections tWR WR the digital lines should be buffered from the device by logic gates as shown in Figure 6. tDS tDH Shutdown Mode D0, D1 VALID DATA The MAX260/MAX261/MAX262 enters a shutdown/ standby mode when all zeroes are written to the Q SEE INTERFACE SPECIFICATIONS FOR TIMING LIMITS addresses of filter A (Q0A–Q6A). When shut down, power consumption with ±5V supplies typically drops Figure 5. Interface Timing to 10mW. When reactivating the filter after shutdown, allow 2ms to return to full operation. Filter Operating Modes inputs M0 and M1 (see Tables 4 and 5). These modes use no external components. A fifth mode, 3A, makes There are several ways in which the summing amplifier use of an additional op amp (included in the MAX261 and integrators in each MAX260/MAX261/MAX262 filter and MAX262) and external resistors, but uses the same section can be configured. The four most versatile internal configuration and is selected with the same interconnections (modes) are selected by writing to programming code, as mode 3. ______________________________________________________________________________________ 15

Microprocessor Programmable Universal Active Filters 2 +5V -5V MODE 1 6 2 OCTAL D FLIP-FLOP 74HC374 20 SCN N BP X A A0 3 1D VCC 1Q 2 A0 V+ V- IN SCN - + Σ- ∫ ∫ LP M + 4 5 - A1 2D 2Q A1 / 1 6 A2 7 3D 3Q 6 A2 MAX260 MAX261 SCN 2 A3 8 4D 4Q 9 A3 MAX262 X 13 12 SCN = SWITCHED-CAPACITOR NETWORK A D1 5D 5Q D1 Figure 7. Filter Mode 1: Second-Order Bandpass, Lowpass, M D2 14 6D 6Q 15 D2 and Notch / OC GND CK 0 different modes if desired. The f0, fN (notch), Q, and 1 10 11 6 various output gains in each case are shown in Table 5. WR WR 2 GND Filter Mode Selection X -5V MODE 1 (Figure 7) is useful when implementing allpole A lowpass and bandpass filters such as Butterworth, Figure 6. Buffering/Latching Logic Inputs Chebyshev, Basset, etc. It can also be used for notch M filters, but only second-order notches because the rela- Figures 7 through 11 show symbolic representations of tive pole and zero locations are fixed. Higher order the MAX260 filter modes. Only one second-order sec- notch filters require more latitude in f0 and 1N, which is tion is shown in each case. The A and B sections of why they are more easily implemented with mode 3A. one MAX260/MAX261/MAX262 can be programmed for Table 5. Filter Modes for Second-Order Functions M1, FILTER HON1 HON2 MODE M0 FUNCTIONS f0 Q fN HOLP HOBP (f ➝ 0) (f ➝ fCLK/4) OTHER 1 0, 0 LP, BP, N f0 -1 -Q -1 -1 2 0, 1 LP, BP, N f0√2 -0.5 -Q/√2 -0.5 -1 3 1, 0 LP, BP, HP E 2 E 3 -1 -Q HOHP = -1 L L E TAB E TAB f0 RRHL -1 -Q +RRGL +RRGH HOHP = -1 E E S S HOAP = -1 4 1, 1 LP, BP, AP -2 -2Q fZ = f0, QZ = Q Notes: f0= Center Frequency HON1= Notch Gain as f approaches DC fN= Notch Frequency HON2= Notch Gain as f approaches fCLK/4 HOLP = Lowpass Gain at DC HOAP= Allpass Gain HOBP= Bandpass Gain at f0 fz, Qz= f and Q of Complex Pole Pair HOHP= Highpass Gain as f approaches fCLK/4 16 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters M MODE 2 MODE 3A RG A SCN N BP RH - N X IN - RL + 2 SCN - + Σ ∫ ∫ LP 6 + 0 - SCN HP / BP M IN - SCN SCN - + Σ ∫ ∫ LP A + - X SCN 2 Figure 8. Filter Mode 2: Second-Order Bandpass, Lowpass, 6 SCN and Notch 1 SCN / M MODE 3 SCN = SWITCHED-CAPACITOR NETWORK A SCN HP BP Figure 10. Filter Mode 3a: Second-Order Bandpass, Lowpass, X Highpass, and Notch. For elliptic LP, BP, HP, and Notch, the N 2 IN - SCN - + Σ LP output is used. 6 ∫ ∫ + 2 - MODE 3 (Figure 9) is the only mode that produces high-pass filters. The maximum clock frequency is somewhat less than with mode 1 (see Table 1). SCN MODE 3A (Figure 10) uses a separate op amp to sum the highpass and lowpass outputs of mode 3, creating SCN a separate notch output. This output allows the notch to be set independently of f0 by adjusting the op amp’s SCN = SWITCHED-CAPACITOR NETWORK feedback resistor ratio (RH, RL). RH, RL, and RG are Figure 9. Filter Mode 3: Second-Order Bandpass, Lowpass, external resistors. Because the notch can be indepen- and Highpass dently set, mode 3A is also useful when designing pole-zero filters such as elliptics. Mode 1, along with mode 4, supports the highest clock MODE 4 (Figure 11) is the only mode that provides an frequencies (see Table 1) because the input summing allpass output. This is useful when implementing group amplifier is outside the filter’s resonant loop (Figure 7). delay equalization. In addition to this, mode 4 can also The gain of the lowpass and notch outputs is 1, while be used in all pole lowpass and bandpass filters. Along the bandpass gain at the center frequency is Q. For with mode 1, it is the fastest operating mode for the fil- bandpass gains other than Q, the filter input or output ter, although the gains are different than in mode 1. can be scaled by a resistive divider or op amp. When the allpass function is used, note that some MODE 2 (Figure 8) is used for all-pole lowpass and amplitude peaking occurs (approximately 0.3dB when bandpass filters. Key advantages compared to mode 1 Q = 8) at f0. Also note that f0and Q sampling errors are are higher available Qs (see Table 3) and lower output highest in mode 4 (see Figure 20). noise. Mode 2’s available fCLK/f0 ratios are √2 less than with mode 1 (see Table 2), so a wider overall range of f0s can be selected from a single clock when both modes are used together. This is demonstrated in the Wide Passband Chebyshev Bandpass design example. ______________________________________________________________________________________ 17

Microprocessor Programmable Universal Active Filters 2 BANDPASS OUTPUT MODE 4 6 2 X SCN AP BP HOBP MA IN SCN - + Σ- ∫ ∫ LP GAIN (V/V) 0.707 HOBP + / - 1 6 fL fO fH 2 SCN f(LOG SCALE) X A SCN = SWITCHED-CAPACITOR NETWORK Q = fH f−O fL, fO = fLfH /M Faingdu rAel l1p1a.s sFilter Mode 4: Second-Order Bandpass, Lowpass, fL = fO 2−Q1 + 21Q2+ 1 0   Description of Filter Functions 6    1  1 2  2 BANDPASS(Figure 12) fH = fO 2Q + 2Q + 1 X For all pole bandpass and lowpass filters (Butterworth,   A Bessel, Chebyshev) use mode 1 if possible. If appropri- M ate fCLK/f0 or Q values are not available in mode 1, Figure 12. Second-Order Bandpass Characteristics mode 2 provides a selection that is closer to the required values. Mode 1, however, has the highest bandwidth (see Table 1). For pole-zero filters, such as elliptics, see mode 3A. s2 G(s) = H G(s) = HOBPs2 + ss(ω(ωo / /Q Q)) + ω 2 OHPs2+ s(ωo / Q) + ωo2 o o HOHP= Highpass output gain as f approaches fCLK/4 HOBP= Bandpass output gain at ω= ωo f0= ω0 / 2π f0= ω0 / 2π= The center frequency of the complex NOTCH(Figure 15) pole pair. Input-output phase shift is -180°at f0. Mode 3A is recommended for multi-pole notch filters. In Q = The quality factor of the complex pole pair. second-order filters, mode 1 can also be used. The Also the ratio of f0to -3dB bandwidth of the advantages of mode 1 are higher bandwidth, com- second-order bandpass response. pared to mode 3 (higher fN can be implemented), and LOWPASSSee bandpass text. (Figure 13) no need for external components as required in mode 3A. ω 2 G(s) = HOLPs2 + s(ωo o/ Q) + ωo2 G(s) = HON2 s2 + ωn2 s2 + s(ω / Q) + ω 2 HOLP= Lowpass output gain at DC o o f0= ω0 / 2π HON2= Notch output gain as f approaches fCLK/4 HIGHPASS(Figure 14) HON1= Notch output gain as f approaches DC Mode 3 is the only mode with a highpass output. It fn= ωn / 2π works for all pole filter types such as Butterworth, ALLPASS Bessel and Chebyshev. Use mode 3A for filters Mode 4 is the only configuration in which an allpass employing both poles and zeros, such as elliptics. function can be realized. 18 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters M LOWPASS OUTPUT HIGHPASS OUTPUT A HOP HOP X HOLP HOHP N (V/V) 0.707 HOLP N (V/V)0.707 HOHP 26 GAI GAI 0 / M fP fC fC fP A f(LOG SCALE) f(LOG SCALE) X   f = f X 1 − 1  + 1 − 1 2+ 1 f = f X  1 − 1  + 1 − 1 2+ 1 26 C O  2Q2  2Q2 C O   2Q2  2Q2    1 fp = fO 1 − 2Q12 fp = fO 1 − 2Q12 /M H = H X 1 1 A OP OLP 1 1 − 1 HOP = HOHP X 1 1 X Q 4Q2 Q 1 − 4Q2 2 6 Figure 13. Second-Order Lowpass Characteristics Figure 14. Second-Order Highpass Characteristics 2 G(s) = H s2 − s(ωo / Q) + ωo2 OAP s2 + s(ωo / Q) + ωo2 HON2 HON1 HOAP= Allpass output gain for DC < f < fCLK / 4 V) f0= ω0 / 2π N (V/ AI Filter Design Procedure G The procedure for most filter designs is to first convert HON the required frequency response specifications to f0s and Qs for the appropriate number of second-order fN f(LOG SCALE) sections that implement the filter. This can be done by using design equations or tables in available liter- Figure 15. Second-Order Notch Characteristics ature, or can be conveniently calculated using Maxim's filter design software. Once the f0s and Qs have been Table 6. Cascading Identical Bandpass found, the next step is to turn them into the digital pro- gram coefficients required by the MAX260/MAX261/ Filter Sections MAX262. An operating mode and clock frequency (or TOTAL SECTIONS TOTAL B.W. TOTAL Q clock/center frequency ratio) must also be selected. 1 1.000 B 1.00 Q Next, if the sample rate (fCLK/2) is low enough to cause significant errors, the selected f0s and Qs should be 2 0.644 B 1.55 Q corrected to account for sampling effects by using 3 0.510 B 1.96 Q Figure 20 or Maxim's design software. In most cases, 4 0.435 B 2.30 Q the sampling errors are small enough to require no cor- 5 0.386 B 2.60 Q rection, i.e., less than 1%. In any case, with or without correction, the required f0s and Qs can then be select- Note:B = individual stage bandwidth, Q = individual ed from Tables 2 and 3. Maxim's filter design software stage Q. ______________________________________________________________________________________ 19

Microprocessor Programmable Universal Active Filters 2 can also perform this last step. The desired f0s and Qs Application Hints are stated, and the appropriate digital coefficients are 6 supplied. Power Supplies 2 The MAX260/MAX261/MAX262 can be operated with a X Cascading Filters variety of power supply configurations, including +5V to A In some designs, such as very narrow band filters, sev- +12V single supply or ±2.5V to ±5V dual supplies. eral second-order sections with identical center fre- When a single supply is used, V- is connected to sys- M quency can be cascaded. The total Q of the resultant tem ground and the filter's GND pin should be biased / filter is: at V+/2. The input signal is then either capacitively cou- 1 Q pled to the filter input or biased to V+/2. Figure 16 6 Total QT = ( ) shows circuit connections for single-supply operation. 21/N − 1 2 When power supplies other than ±5V are used, CMOS X input logic levels (HIGH = V+, LOW = GND or V-) are A Q is the Q of each individual filter section, and N is the required for WR, D0, D1, A0–A3, OLKA, and CLKB. number of sections. In Table 6, the total Q and band- With ±5V supplies, either TTL or CMOS levels can be M width are listed for up to five identical second-order used. Note, however, that power consumption at ±5V is / sections. B is the bandwidth of each section. reduced if CLKA and CLKB are driven with ±5V, rather 0 In high-order bandpass filters, stages with different f0s than TTL or 0 to 5V levels. Operation with +5V or ±2.5V 6 and Qs are also often cascaded. When this happens, power lowers power consumption, but also reduces 2 the overall filter gain at the bandpass center frequency bandwidth by approximately 25% compared to +12V or is not simply the product of the individual gains ±5V supplies. X because f0, the frequency where each sections gain is Best performance is achieved if V+and V-are bypassed A specified, is different for each second-order section. to ground with 4.7µF electrolytic (Tantalum is preferred.) M The gain of each section at the cascaded filter's center and 0.1µF ceramic capacitors. These should be located frequency must be determined to obtain the total gain. as close to the supply pins as possible. The lead length For all-pole filters the gain, H(f0), as each second-order of the bypass capacitors should be shortest at the V+ section's f0 is divided by an adjustment factor, G, to and V- pins. When using a single supply, V+ and GND obtain that section's gain, H(f0BP), at the overall center should be bypassed to V-as shown in Figure 16. frequency: Output Swing and Clipping H1(f0BP) = H(f01) / G1= Section 1’s Gain at f0BP MAX260/MAX261/MAX262 outputs are designed to drive 10kΩ loads. For the MAX261 and MAX262, all fil- Q1(F12− 1)2+ (F1 / Q1)21/2 ter outputs swing to within 0.15V of each supply rail G1 = with a 10kΩ load. In the MAX260 only, an internal sam- F 1 ple-hold circuit reduces voltage swing at the N/HP/AP where F1= f01 / fOBP output compared to LP and BR. N/HP/AP, therefore, swings to within 1V (10kΩ load) of either rail on the G1, Q1, and f01 are the gain adjustment factor, Q, and MAX260. f0 for the first of the cascaded second-order sections. The gain of the other sections (2, 3, etc.) at f0BP is To ensure that the outputs are not driven beyond their determined the same way. The overall gain is: maximum range (output clipping), the peak amplitude H(f0Bp) = H1(f0BP) x H2(f0BP) x etc. response, individual section gains (HOBP, HOLP, HOHP), input signal level, and filter offset voltages must For cascaded filters with zeros (fZ) such as elliptics, the be carefully considered. It is especially important to gain adjustment factor for each stage is: check unused outputs for clipping (i.e., the lowpass output in a bandpass hookup), because overload at Q1FZ12− F12(F12− 1)2+ (F1 / Q1)21/2 any filter stage severely distorts the overall response. G = The maximum signal swing with ±4.75V supplies and a 1 F12FZ12− 1 1.0V filter offset is approximately ±3.5V. For example, lets assume a fourth-order lowpass filter is where F1Z= fz1 / f0BP, and F1is the same as above. being implemented with a Q of 2 using mode 1. With a single 5V supply (i.e., ±2.5V with respect to chip GND) the maximum output signal is ±2V (w.r.t. GND). Since in 20 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters M 10kΩ A 10kΩ + VIN 0V X - 2 SEE 5V NOTE 2.5kΩ 6 7.5kΩ 0V 0 TO V+ /M CMOS WR INA VIN ANY DC LOGIC A0–A3 OR A LEVELS D0, D1 INB X TO GND PIN MAX260 5V 2 MAX261 VIN 6 MAX262 V+ +5V 0V 1 4.7kΩ / M GND A 4.7kΩ X 4.7µF 0.1µF 4.7µF 0.1µF 2 V- 6 2 NOTE: OP-AMP LEVEL SHIFT CIRCUIT HAS A GAIN OF 0.5 FROM V*. Figure 16. Power Supply and Input Connections for Single Supply Operation mode 1 the maximum signal is 0 times the input signal, Input Impedance the input should not exceed ±(2/Q)V, or ±1V in this case. The input to each filter is the switched capacitor circuit shown in Figure 18. In the MAX260, the input capacitor Clock Feedthrough and Noise charges to the input voltage VIN during the first half Typical wideband noise for MAX260 series devices is clock cycle. During the second half-cycle, its charge is 0.5mVP-P from DC to 100kHz. The noise is virtually transferred to the feedback capacitor. The resultant independent of clock frequency. In multistage filters, input impedance can be approximated by: the section with the highest Q should be placed first for lower output noise. RIN= 1 / (CINfCLK / 2) = 2 / (CINfCLK). The output waveform of the MAX260 series and other CIN is around 12pF, hence, for a clock frequency of switched capacitor filters appears as a sampled signal 500kHz, RIN = 333kΩ. The input also has about 5pF of fixed capacitance to ground. with stepping or “staircasing” of the output waveform occurring at the internal sample rate (fCLK/2). This step- The MAX261/MAX262 input structure is shown in Figure ping, if objectionable, can be removed by adding a sin- 19. Here CA = 12pF and CB = 0.016pF and only CB is gle-pole AC filter. With no input signal, clock-related switched, so the input resistance is 750 times larger feedthrough is approximately 8mVP-P. This can also be compared to the MAX260 (RIN = 250MΩ). The attenuated with an RC-smoothing filter as shown with MAX261/MAX262 have a fixed capacitance of approxi- the MAX261 in Figure 17. mately 5pF to ground. Some noise also can be generated at the filter outputs f0 and Q at Low Sample Rates by transitions at the logic inputs. If this is objectionable, When low fCLK/f0 ratios and low Q settings are select- the digital lines should be buffered from the device by ed, deviation from ideal continuous filter response can logic gates as shown in Figure 6. be noticeable in some designs. This is due to interac- tion between Q and f0 at low fCLK/f0 ratios and Qs. The data in Figure 20 quantifies these differences. Since the ______________________________________________________________________________________ 21

Microprocessor Programmable Universal Active Filters 2 errors are predictable, the graphs can be used to cor- 6 rect the selected f0 and Q so that the actual realized parameters are on target. These predicted errors are 2 not unique to MAX260 series devices and, in fact, A 1V/DIV X OV occur with all types of sampled filters. Consequently, A these corrections can be applied to other switched B 5mV/DIV M capacitor filters. In the majority of cases, the errors are OV not significant, i.e., less than 1%, and correction is not / needed. However, the MAX262 does employ a lower C mV/DIV 1 range of fCLK/f0ratios than the MAX260 or MAX261 and OV 6 is more prone to sampling errors, as the tables show. 2 Maxim's filter design software applies the previous cor- X rections automatically as a function of desired fCLK/f0, 1µs/div A and Q. Therefore, Figure 20 should not be used when Maxim's software determines f0 and Q. This results in TRACE B M overcompensation of the sampling errors since the cor- R, 10kΩ / rection factors are then counted twice. INA BPA TRACE C 0 The data plotted in Figure 20 applies for modes 1 and MAX261 C, 1000pF 6 2 3ob. tWainheedn furosmin gth Fei ggurarep h2 0sh foourl dm boed em u4l,t ipthliee df 0bye r1ro.5r 500TkRHAzC TET AL CLKA X and the Q error should be multiplied by 3.0. In mode 2, A the value of fCLK/f0 should be multiplied by √2 and the programmed Q should be divided by √2 before using Figure 17. MAX261 Bandpass Output Clock Noise M the graphs. As with all sampled systems, frequency components of the input signal above one half the sampling rate are fCLK aliased. In particular, input signal components near the 2 sampling rate generate difference frequencies that VIN CFB often fall within the passband of the filter. Such aliased CIN signals, when they appear at the output, are indistin- ~5pF - guishable from real input information. For example, the 12pF + aliased output signal generated when a 99kHz wave- form is applied to a filter sampling at 100kHz (fCLK = 200kHz) is 1kHz. This waveform is an attenuated ver- 2 sion of the output that would result from a true 1kHz RIN = CIN fCLK input. Remember that, with the MAX260 series filters, the nyquist rate (one half the sample rate) is in fact Figure 18. MAX260 Input Model fCLK/4, because fCLKis internally divided by two. A simple, passive RC lowpass input filter is usually suf- ficient to remove input frequencies that can cause fCLK aliasing. In many cases, the input signal itself may be 2 band limited and require no special anti-alias filtering. CB CFB The wideband MAX262 uses lower fCLK/f0 ratios than 0.016pF the MAX260/MAX261 and, for this reason, is more likely VIN - to require input filtering than the MAX260 or MAX281. + ~5pF Trimming DC Offset The DC offset voltage at the LP or notch output can be CA 12pF adjusted with the circuit in Figure 21. This circuit also 2 uses the input op amp to implement a single-pole anti- RIN = 750 CA fCLK alias filter. Note that the total offset is generally less in multistage filters than when only one section is used, Figure 19. MAX261/MAX262 Input Model 22 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters since each offset is typical negative and each section M inverts. When the HP or BP outputs are used, the offset fO ERROR vs. fCLK/fO RATIO (MODE 1, 3) can be removed with capacitor coupling. 20 A Design Examples 18 fM0 OERDREO 2R: MISU PLLTOIPTLTYE DIC FLKOIRO MBYO √D2ES a n1d AND 3 X 16 DIVIDE Q BY √2 BEFORE USING GRAPH 2 Fourth-Order Chebyshev Bandpass Filter 14 MODE 4: MUTIPLY fO ERROR BY 1.5 6 Ffoigrmur ea 2f2o usrhtohw-osr dbeorth C hhaelvbeyss hoef va MbaAnXd2p6a0s csa sficltaedr.e dTh teo R (%) 12 Q = 0.512 0 desired parameters are: ERROO 180 QQ = =0 .05.15212 /M Center frequency (f0) = 1kHz f 6 Q = 0.512Q = 0.512 A Q = 0.512 Pass bandwidth = 200Hz 4 X Stop bandwidth = 600Hz 2 2 Max passband ripple = 0.5dB 0 40 60 80 100 120 140 160 180 200 6 Min stopband attenuation = 15dB fCLK/fO RATIO 1 From the previous parameters, the order (number of / poles) and the f0 and Q of each section can be deter- Q ERROR vs. fCLK/fO RATIO M mined. Such a derivation is beyond the scope of this -7 A data sheet; however, there are a number of sources Q ERROR IS PLOTTED FOR MODES 1 AND 3 that provide design data for this procedure. These -6 MODE 2: MULTIPLY fCLK/fO BY √2 and X DIVIDE Q BY √2 BEFORE USING GRAPH include look-up tables, design texts, and computer pro- MODE 4: MUTIPLY Q ERROR BY 1.5 2 -5 gvirdaem sc.o Dmepsrieghne snosfitvwea rseo ilsu taiovnasila fbolre mfroomst Mpaoxpiumla tro fpilrteo-r R (%) -4 Q =Q 0 =.5 0.6 62 configurations. The A and B section parameters for the O RR Q = 0.83 above filter are: Q E -3 Q = 1.21 Q = 3.05 f0A= 904Hz f0B= 1106Hz -2 Q = 7.11 QA= 7.05 QB= 7.05 -1 To implement this filter, both halves operate in mode 1 and use the same clock. See Tables 2 and 3. The pro- 0 40 60 80 100 120 140 160 180 200 grammed parameters are: fCLK/fO RATIO CLKA= CLKB= 150kHz fCLK/f0A =166.50 (Mode 1, N = 42), actual f0A= 902.4Hz Figure 20. Sampling Errors in fCLK/f0and Q at Low fCLK/f0and Q Settings fCLK/f0B = 136.66 (Mode 1, N = 23), actual f0B = 1099.7Hz QA= QB= 7.11 (Mode 1, N = 119) C1 Sampling errors are very small at this fCLK/f0 ratio, so the actual realized Q is very close to 7.05 (see Figure R2 100kΩ 20 or program MPP in the Filter Design Software sec- VIN tion). Often the realized Q is not exactly the target value R3 270kΩ R1 100kΩ at high Qs because programming resolution lowers as +5V - TO FILTER Q increases. This does not affect most filter designs, + INPUT since three-digit Q accuracy is practically never 100kΩ GAIN = -R1/R2 1 roef q1u0ir.e Tdh, ea nodve ara Qll friletesro lgutaioinn aotf f10 iiss p16ro.4vVid/eVd o ur p2 4to.3 dQBs -5V OTRFIFMSET fLP = 2πR1C2 (see the Cascading Filters section). If another gain is NOTE: OP AMP INCLUDED WITH MAX261/MAX262 required, amplification or attenuation must be added at the input, output, or between stages. Figure 21. Circuit for DC Offset Adjustment ______________________________________________________________________________________ 23

Microprocessor Programmable Universal Active Filters 2 40 -180 30 6 2 GAIN X 15 -90 15 A ES) M GAIN (dB) -10 0 SE (DEGRE GAIN (dB) 0 / PHASE HA 1 P -35 90 -15 6 2 X -60 180 -30 200 500 1K 2K 5K 10K 20K 1K 2K 5K 10K 20K 50K 100K A FREQUENCY (Hz) FREQUENCY (Hz) M Figure 23. MAX261 Fourth-Order Chebyshev Bandpass Using VIN VOUT / Coefficients of Figure 22 0 5 1 23 21 6 INA BPA INB BPB 2 From the previous parameters, we use either lookup X tables, design texts, or Maxim's filter design programs A MAX260 to generate the order (number of poles), and the f0and Q of each second-order section. The A and B parame- M CLKA CLKB WR, AX, DX ters are: 11 12 f0A= 639Hz f0B= 1564Hz QA= 2.01 QB= 2.01 To implement this filter, section A operates in mode 1 PROGRAM CLK and section B uses mode 2 to provide a wider overall range of fCLK/f0 ratios. This way, one clock frequency CLKA,B MODE fOA fOB QA QB can drive both sections A and B. See Tables 2 and 3. 150kHz 1 N = 42 N = 23 N = 119 N = 119 CLKA= CLKB= 120kHz Figure 22. Fourth-Order Chebyshev Bandpass Filter fCLK/f0A= 188.49 (Mode 1, N = 56), actual f0A= 636.6Hz fCLK/f0B= 76.64 (Mode 2, N = 5), actual f0B= 156.5Hz In Figure 23, a series of response curves are shown for QA = 2.000 (Mode 1, N = 96), QB = 2.01 (Mode 2, N = the previous configuration using a MAX261 with clock 83) frequencies ranging from 750kHz to 4MHz (f0 from The overall passband gain at f0 is 0.64V/V or 500Hz to 30kHz). Note that the rightmost curve shows -3.9dB. about 2dB of gain peaking compared to the lower fre- quency curves, indicating the upper limit of usable filter High-Frequency Chebyshev Bandpass accuracy at this Q (see Table 1). The same Chebyshev response shape shown in Figure 24 is implemented at higher frequencies with a Wide Passband Chebyshev Bandpass MAX262 in Figure 25. The curves show plots for center In this example (Figure 24), the desired parameters frequencies of 15.6kHz, 31.3kHz, and 47kHz. Not only are: is this faster than the MAX260 implementation, but Center frequency (f0) = 1kHz mode 1 can be used in both halves of the MAX262 for this filter because the range of available fCLK/f0ratios is Pass bandwidth = 1kHz wider with the MAX262 than the MAX260. Stop bandwidth = 3kHz Max passband ripple = 1dB Min stopband attenuation = 20dB 24 ______________________________________________________________________________________

Microprocessor Programmable Universal Active Filters M 10 -180 0 fO = 15.6kHz A fCLK = 1MHz X -10 GAIN -10 -90 2 S) GAIN (dB) -30 0 SE (DEGREE GAIN (dB) --2300 60/ HA fO = 31.3kHz M P fCLK = 2MHz -50 PHASE 90 -40 A fO = 47kHz fCLK = 3MHz X -70 180 -50 100 200 500 1K 2K 5K 10K 1K 2K 5K 10K 20K 50K 100K 2 FREQUENCY (Hz) FREQUENCY (Hz) 6 VIN VOUT 1 VIN VOUT 5 1 23 21 / 5 1 23 21 M INA BPA INB BPB INA BPA INB BPB A X MAX262 MAX260 2 6 CLKA CLKB WR, AX, DX CLKA CLKB WR, AX, DX 2 11 12 11 12 PROGRAM PROGRAM CLK CLK CLKA,B MODEA MODEB fOA fOB QA QB CLKA,B MODE fOA fOB QA QB 120kHz 1 2 N = 56 N = 5 N = 96 N = 83 1 to 3MHz 1 N = 38 N = 0 N = 96 N = 96 Figure 24. Wide Passband Chebyshev Bandpass Filter Figure 25. High-Frequency Chebyshev Bandpass Filter Fourth-Order Butterworth Lowpass CLKA= CLKB= 400kHz Figure 26 shows a fourth-order Butterworth lowpass fCLK/f0A= 135.08 (N = 22), f0B= 2961Hz with a cutoff frequency of 3kHz. Sections A and B of a (-1.3% correction) MAX260 are cascaded. The f0 and Q parameters for each section are: fCLK/f0B= 139.80 (N = 25), f0A= 2861Hz (-4.6% correction) f0A= 3kHz f0B= 3kHz QA= 1.306 (N = 79, Q resolution prevents +0.5% QA= 1.307 QB= 0.541 correction) Mode 1 and a 400kHz clock are used. Because of low QB= 0.547 (N = 11 +1.1% correction) Q values, the sampling errors of Figure 20 begin to look Measured wideband noise for this filter is 123µV RMS. significant in this case. From the graphs, using fCLK/f0 If mode 2 were used, the noise would be 87µV RMS. ratio near 133, f0A is about 4% high, f0B is 1.5% high, For lower noise with either mode, the first section QA is -1.2% low, and QB is -0.5% low. If these errors should have the highest Q (section A in this example). are not a problem, the corrections can be ignored. They are included here for best possible accuracy: ______________________________________________________________________________________ 25

Microprocessor Programmable Universal Active Filters 2 Ordering Information (continued) Chip Topography 6 PART TEMP RANGE PACKAGE AC C U R A C Y 2 0.128in X MAX261ACNG 0°C to +70°C Plastic DIP 1% 3.251mm MAX261BCNG 0°C to +70°C Plastic DIP 2% A HPA(OP OUT) M MAX261AENG -40°C to +85°C Plastic DIP 1% N.C.(HPA) N.C.(HPB) MAX261BENG -40°C to +85°C Plastic DIP 2% BPALPA INB LPBBPB / MAX261ACWG 0°C to +70°C Wide SO 1% 1 6 MAX261BCWG 0°C to +70°C Wide SO 2% N.C.(OP IN) 2 MAX261AMRG -55°C to +125°C CERDIP 1% INDA1 X MAX261BMRG -55°C to +125°C CERDIP 2% D0 A3 MAX262ACNG 0°C to +70°C Plastic DIP 1% A MAX262BCNG 0°C to +70°C Plastic DIP 2% M MAX262AENG -40°C to +85°C Plastic DIP 1% 0.199in / 0 MAX2G2BENG -40°C to +85°C Plastic DIP 2% (5.055mm) 6 MAX262ACWG 0°C to +70°C Wide SO 1% 2 MAX262BCWG 0°C to +70°C Wide SO 2% X MAX262AMRG -55°C to +125°C CERDIP 1% A MAX262BMRG -55°C to +125°C CERDIP 2% CLK OUT OSC OUT M *All devices—24-pin packages 0.3in-wide packages GND V+ A2 A1 A0WR V- CLKA CLKB HPB(N.C.) NOTE: LABELS IN PARENTHESES ( ) ARE FOR MAX261/MAX262 ONLY Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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