128Mb 3V Embedded Parallel NOR Flash Features Parallel NOR Flash Embedded Memory M29W128GH, M29W128GL Features • V /WP# pin protection PP – Protects first or last block regardless of block • Supply voltage protection settings – VCC = 2.7–3.6V (program, erase, read) • Software protection – VCCQ = 1.65–3.6V (I/O buffers) – Volatile protection – VPPH = 12V for fast program (optional) – Nonvolatile protection • Asynchronous random/page read – Password protection – Page size: 8 words or 16 bytes • Extended memory block – Page access: 25, 30ns – 128-word (256-byte) memory block for perma- – Random access: 60ns1, 70, 80ns nent, secure identification • Fast program commands: 32-word (64-byte) write • Common flash interface buffer – 64-bit security code • Enhanced buffered program commands: 256-word • Low power consumption: Standby and automatic • Program time mode – 16µs per byte/word TYP • Minimum 100,00 PROGRAM/ERASE cycles per – Chip program time: 5s with VPPH and 8s without block VPPH • RoHS compliant packages • Memory organization – 56-pin TSOP (N) 14mm x 20mm – Uniform blocks: 128 main blocks, 128-Kbytes or – 64-ball TBGA (ZA) 10mm x 13mm 64-Kwords each – 64-ball FBGA (ZS) 11mm x 13mm • Program/erase controller • Electronic signature – Embedded byte/word program algorithms – Manufacturer code: 0020h • Program/erase suspend and resume capability – M29W128GH uniform, last block protected by – Read from any block during a PROGRAM SUS- V /WP#: 227Eh + 2221h + 2201h PP PEND operation – M29W128GL uniform, first block protected by – Read or program another block during an ERASE V /WP#: 227Eh + 2221h + 2200h PP SUSPEND operation • Automotive device grade temperature • Unlock bypass, block erase, chip erase, write to buf- – –40°C to +125°C (automotive grade certified) fer, enhanced buffer program commands – Fast buffered/batch programming Note: 1. The 60ns device is available upon customer – Fast block/chip erase request. CCMTD-1725822587-2335 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

128Mb 3V Embedded Parallel NOR Flash Features Part Numbering Information Available with extended memory block prelocked by Micron. Devices are shipped from the factory with memory content bits erased to 1. For available options, such as packages or high/low protection, or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specifica- tion comparison by device type is available at www.micron.com/products. Contact the factory for devices not found. Table 1: Part Number Information Part Number Category Category Details Notes Device type M29 Operating voltage W = V = 2.7– 3.6V CC Device function 128GH = 128Mb (x8/x16) page, uniform block Flash memory, highest block protected by V /WP# PP 128GL = 128Mb (x8/x16) page, uniform block Flash memory, lowest block protected by V /WP# PP Speed 70 = 70ns 1 60 = 60ns 1, 2 7A = 70ns 1, 3 Package N = 56-pin TSOP, 14mm x 20mm ZA = 64-ball TBGA, 10mm x 13mm, 1mm pitch ZS = 64-ball Fortified BGA, 11mm x 13mm, 1mm pitch Temperature range 1 = 0 to 70°C 6 = –40°C to +85°C (IT) 3 = –40°C to +125°C (IT) Shipping options E = RoHS-compliant package, standard packing F = RoHS-compliant package, tape and reel packing Notes: 1. 80ns if VCCQ = 1.65V to VCC. 2. The 60ns device is available upon customer request. 3. Automotive qualified, available only with option 6. Qualified and characterized according to AEC Q100 and Q003 or equivalent; advanced screening according to AEC Q001 and Q002 or equivalent. CCMTD-1725822587-2335 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Features Contents Important Notes and Warnings ......................................................................................................................... 7 General Description ......................................................................................................................................... 7 Signal Assignments ........................................................................................................................................... 9 Signal Descriptions ......................................................................................................................................... 11 Memory Organization .................................................................................................................................... 12 Uniform Block Memory Map – 128Mb Density ............................................................................................. 12 Bus Operations ............................................................................................................................................... 13 Read .......................................................................................................................................................... 13 Write .......................................................................................................................................................... 13 Standby and Automatic Standby ................................................................................................................. 13 Output Disable ........................................................................................................................................... 14 Reset .......................................................................................................................................................... 14 Status Register ................................................................................................................................................ 15 Lock Register .................................................................................................................................................. 20 Standard Command Definitions – Address-Data Cycles .................................................................................... 23 READ Operations ........................................................................................................................................... 25 READ/RESET Command ............................................................................................................................ 25 READ CFI Command .................................................................................................................................. 25 AUTO SELECT Operations .............................................................................................................................. 26 AUTO SELECT Command ........................................................................................................................... 26 Bypass Operations .......................................................................................................................................... 29 UNLOCK BYPASS Command ...................................................................................................................... 29 UNLOCK BYPASS RESET Command ............................................................................................................ 29 Program Operations ....................................................................................................................................... 30 PROGRAM Command ................................................................................................................................ 30 UNLOCK BYPASS PROGRAM Command ..................................................................................................... 30 WRITE TO BUFFER PROGRAM Command .................................................................................................. 30 UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 33 WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 33 BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 33 PROGRAM SUSPEND Command ................................................................................................................ 33 PROGRAM RESUME Command .................................................................................................................. 34 ENHANCED BUFFERED PROGRAM Command ........................................................................................... 34 UNLOCK BYPASS ENHANCED BUFFERED PROGRAM Command ............................................................... 35 ENHANCED BUFFERED PROGRAM CONFIRM Command .......................................................................... 35 Erase Operations ............................................................................................................................................ 38 CHIP ERASE Command .............................................................................................................................. 38 UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 38 BLOCK ERASE Command ........................................................................................................................... 38 UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 39 ERASE SUSPEND Command ....................................................................................................................... 39 ERASE RESUME Command ........................................................................................................................ 40 Block Protection Command Definitions – Address-Data Cycles ........................................................................ 41 Protection Operations .................................................................................................................................... 44 LOCK REGISTER Commands ...................................................................................................................... 44 PASSWORD PROTECTION Commands ....................................................................................................... 44 NONVOLATILE PROTECTION Commands .................................................................................................. 44 NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 46 VOLATILE PROTECTION Commands .......................................................................................................... 46 EXTENDED MEMORY BLOCK Commands .................................................................................................. 46 CCMTD-1725822587-2335 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Features EXIT PROTECTION Command .................................................................................................................... 47 Device Protection ........................................................................................................................................... 48 Hardware Protection .................................................................................................................................. 48 Software Protection .................................................................................................................................... 48 Volatile Protection Mode ............................................................................................................................. 49 Nonvolatile Protection Mode ...................................................................................................................... 49 Password Protection Mode .......................................................................................................................... 50 Common Flash Interface ................................................................................................................................ 51 Power-Up and Reset Characteristics ................................................................................................................ 55 Absolute Ratings and Operating Conditions ..................................................................................................... 58 DC Characteristics .......................................................................................................................................... 60 Read AC Characteristics .................................................................................................................................. 62 Write AC Characteristics ................................................................................................................................. 65 Accelerated Program, Data Polling/Toggle AC Characteristics ........................................................................... 72 Program/Erase Characteristics ........................................................................................................................ 74 Package Dimensions ....................................................................................................................................... 75 Revision History ............................................................................................................................................. 78 Rev. C – 05/18 ............................................................................................................................................. 78 Rev. B – 05/15 ............................................................................................................................................. 78 Rev. A – 07/13 ............................................................................................................................................. 78 CCMTD-1725822587-2335 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Features List of Figures Figure 1: 128 Logic Diagram ............................................................................................................................ 8 Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 9 Figure 3: 64-Ball Fortified BGA and 64-Ball TBGA ........................................................................................... 10 Figure 4: Data Polling Flowchart .................................................................................................................... 17 Figure 5: Toggle Bit Flowchart ........................................................................................................................ 18 Figure 6: Status Register Polling Flowchart ..................................................................................................... 19 Figure 7: Lock Register Program Flowchart ..................................................................................................... 21 Figure 8: WRITE TO BUFFER PROGRAM Flowchart ........................................................................................ 32 Figure 9: ENHANCED BUFFERED PROGRAM Flowchart ................................................................................ 36 Figure 10: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 45 Figure 11: Software Protection Scheme .......................................................................................................... 50 Figure 12: Power-Up Timing .......................................................................................................................... 55 Figure 13: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 56 Figure 14: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 57 Figure 15: AC Measurement Load Circuit ....................................................................................................... 59 Figure 16: AC Measurement I/O Waveform ..................................................................................................... 59 Figure 17: Random Read AC Timing (8-Bit Mode) ........................................................................................... 63 Figure 18: Random Read AC Timing (16-Bit Mode) ......................................................................................... 63 Figure 19: BYTE Transition AC Timing ............................................................................................................ 64 Figure 20: Page Read AC Timing (16-Bit Mode) ............................................................................................... 64 Figure 21: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 66 Figure 22: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 67 Figure 23: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 69 Figure 24: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 70 Figure 25: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 71 Figure 26: Accelerated Program AC Timing ..................................................................................................... 72 Figure 27: Data Polling AC Timing .................................................................................................................. 73 Figure 28: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 73 Figure 29: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 75 Figure 30: 64-Ball TBGA – 10mm x 13mm ....................................................................................................... 76 Figure 31: 64-Ball FBGA – 11mm x 13mm ....................................................................................................... 77 CCMTD-1725822587-2335 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Features List of Tables Table 1: Part Number Information ................................................................................................................... 2 Table 2: Signal Descriptions ........................................................................................................................... 11 Table 3: x8 and x16 Blocks[127:0] ................................................................................................................... 12 Table 4: Bus Operations ................................................................................................................................. 13 Table 5: Status Register Bit Definitions ........................................................................................................... 15 Table 6: Operations and Corresponding Bit Settings ........................................................................................ 16 Table 7: Lock Register Bit Definitions ............................................................................................................. 20 Table 8: Block Protection Status ..................................................................................................................... 20 Table 9: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ............................................. 23 Table 10: Read Electronic Signature ............................................................................................................... 26 Table 11: Block Protection ............................................................................................................................. 28 Table 12: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 41 Table 13: Extended Memory Block Address and Data ...................................................................................... 46 Table 14: V /WP# Functions ......................................................................................................................... 48 PP Table 15: Query Structure Overview ............................................................................................................... 51 Table 16: CFI Query Identification String ........................................................................................................ 51 Table 17: CFI Query System Interface Information .......................................................................................... 52 Table 18: Device Geometry Definition ............................................................................................................ 52 Table 19: Primary Algorithm-Specific Extended Query Table ........................................................................... 53 Table 20: Security Code Area .......................................................................................................................... 54 Table 21: Power-Up Wait Timing Specifications .............................................................................................. 55 Table 22: Reset AC Characteristics .................................................................................................................. 56 Table 23: Absolute Maximum/Minimum Ratings ............................................................................................ 58 Table 24: Operating and AC Measurment Conditions ...................................................................................... 58 Table 25: Input/Output Capacitance .............................................................................................................. 59 Table 26: DC Current Characteristics .............................................................................................................. 60 Table 27: DC Voltage Characteristics .............................................................................................................. 61 Table 28: Read AC Characteristics .................................................................................................................. 62 Table 29: WE#-Controlled Write AC Characteristics ......................................................................................... 65 Table 30: CE#-Controlled Write AC Characteristics ......................................................................................... 68 Table 31: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 72 Table 32: Program/Erase Characteristics ........................................................................................................ 74 CCMTD-1725822587-2335 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu- ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib- utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non- automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con- ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in- demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo- nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ- mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi- cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en- vironmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. General Description The M29W is an asynchronous, uniform block, parallel NOR Flash memory device man- ufactured on 90nm single-level cell (SLC) technology. READ, ERASE, and PROGRAM op- erations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. CCMTD-1725822587-2335 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash General Description The main memory array is divided into uniform blocks that can be erased independent- ly so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identi- fied. The command set required to control the device is consistent with JEDEC stand- ards. CE#, OE#, and WE# control the bus operation of the device and enable a simple con- nection to most microprocessors, often without additional logic. The M29W supports asynchronous random read and page read from all blocks of the array. It features a write to buffer program capability that improves throughput by pro- gramming a buffer of 32 words in one command sequence. Also, in x16 mode, the en- hanced buffered program capability improves throughput by programming 256 words in one command sequence. The device V /WP# signal enables faster programming. PP The device contains a 128-word (x16) and 256-byte (x8) extended memory block. The user can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification. Figure 1: 128 Logic Diagram V V V /WP# CC CCQ PP 15 A[22:0] DQ[14:0] WE# DQ15/A-1 CE# OE# RY/BY# RST# BYTE# V SS CCMTD-1725822587-2335 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Signal Assignments Signal Assignments Figure 2: 56-Pin TSOP (Top View) RFU 1 56 RFU A22 2 55 RFU A15 3 54 A16 A14 4 53 BYTE# A13 5 52 VSS A12 6 51 DQ15/A-1 A11 7 50 DQ7 A10 8 49 DQ14 A9 9 48 DQ6 A8 10 47 DQ13 A19 11 46 DQ5 A20 12 45 DQ12 WE# 13 44 DQ4 RST# 14 43 VCC A21 15 42 DQ11 VPP/WP# 16 41 DQ3 RY/BY# 17 40 DQ10 A18 18 39 DQ2 A17 19 38 DQ9 A7 20 37 DQ1 A6 21 36 DQ8 A5 22 35 DQ0 A4 23 34 OE# A3 24 33 VSS A2 25 32 CE# A1 26 31 A0 RFU 27 30 RFU RFU 28 29 VCCQ Notes: 1. A22 = A[MAX]. 2. A-1 is the least significant address bit in x8 mode. CCMTD-1725822587-2335 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Signal Assignments Figure 3: 64-Ball Fortified BGA and 64-Ball TBGA 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A RFU A3 A7 RY/BY# WE# A9 A13 RFU RFU A13 A9 WE# RY/BY# A7 A3 RFU B B RFU A4 A17 V /WP#RST# A8 A12 A22 A22 A12 A8 RST#V /WP# A17 A4 RFU PP PP C C RFU A2 A6 A18 A21 A10 A14 RFU RFU A14 A10 A21 A18 A6 A2 RFU D D RFU A1 A5 A20 A19 A11 A15 V V A15 A11 A19 A20 A5 A1 RFU CCQ CCQ E E RFU A0 D0 D2 D5 D7 A16 V V A16 D7 D5 D2 D0 A0 RFU SS SS F F V CE# D8 D10 D12 D14 BYTE# RFU RFU BYTE# D14 D12 D10 D8 CE# V CCQ CCQ G G RFU OE# D9 D11 V D13 D15/A-1 RFU RFU D15/A-1 D13 V D11 D9 OE# RFU CC CC H H RFU V D1 D3 D4 D6 V RFU RFU V D6 D4 D3 D1 V RFU SS SS SS SS Top view – ball side down Bottom view – ball side up Notes: 1. A[22] = A[MAX]. 2. A-1 is the least significant address bit in x8 mode. CCMTD-1725822587-2335 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for this device fami- ly. All signals listed may not be supported on this device. See Signal Assignments for in- formation specific to this device. Table 2: Signal Descriptions Name Type Description A[MAX:0] Input Address: Selects the cells in the array to access during READ operations. During WRITE oper- ations, they control the commands sent to the command interface of the program/erase con- troller. CE# Input Chip enable: Activates the device, enabling READ and WRITE operations to be performed. When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z. OE# Input Output enable: Controls the bus READ operation. WE# Input Write enable: Controls the bus WRITE operation of the command interface. V /WP# Input V /Write Protect: Provides WRITE PROTECT function and V function. These functions PP PP PPH protect the lowest or highest block and enable the device to enter unlock bypass mode, re- spectively. (Refer to Hardware Protection and Bypass Operations for details.) BYTE# Input Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is LOW, the device is in x8 mode; when HIGH, the device is in x16 mode. RST# Input Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details. DQ[7:0] I/O Data I/O: Outputs the data stored at the selected address during a READ operation. During WRITE operations, they represent the commands sent to the command interface of the inter- nal state machine. DQ[14:8] I/O Data I/O: Outputs the data stored at the selected address during a READ operation when BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE operations, these bits are not used. When reading the status register, these bits should be ig- nored. DQ15/A-1 I/O Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8 mode). RY/BY# Output Ready busy: Open-drain output that can be used to identify when the device is performing a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. After a hard- ware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET AC Specifications for more details). The use of an open-drain output enables the RY/BY# pins from several devices to be connec- ted to a single pull-up resistor to V . A low value will then indicate that one ( CCQ or more) of the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V V . OL CCMTD-1725822587-2335 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Memory Organization Table 2: Signal Descriptions (Continued) Name Type Description V Supply Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations. CC The command interface is disabled when V <= V . This prevents WRITE operations from CC LKO accidentally damaging the data during power-up, power-down, and power surges. If the pro- gram/erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid. A 0.1μF capacitor should be connected between V and V to decouple the current surges CC SS from the power supply. The PCB track widths must be sufficient to carry the currents required during PROGRAM and ERASE operations (see DC Characteristics). V Supply I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be CCQ powered independently from V . CC V Supply Ground: All V pins must be connected to the system ground. SS SS RFU – Reserved for future use: RFUs should be not connected. Memory Organization Uniform Block Memory Map – 128Mb Density Table 3: x8 and x16 Blocks[127:0] Block Address Range (x8) Block Address Range (x16) Block Size Start End Size Start End 127 128KB 0FE 0000h 0FF FFFFh 64KW 07F 0000h 07F FFFFh ⋮ ⋮ ⋮ ⋮ ⋮ 63 07E 0000h 07F FFFFh 03F 0000h 03F FFFFh ⋮ ⋮ ⋮ ⋮ ⋮ 0 000 0000h 001 FFFFh 000 0000h 000 FFFFh Note: 1. The main memory array is divided into 128KB or 64KW uniform blocks. CCMTD-1725822587-2335 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Bus Operations Bus Operations Table 4: Bus Operations Notes 1 and 2 apply to entire table 8-Bit Mode 16-Bit Mode A[MAX:0], DQ15/A-1, Operation CE# OE# WE# RST# V /WP# DQ15/A-1 DQ[14:8] DQ[7:0] A[MAX:0] DQ[14:0] PP READ L L H H X Cell address High-Z Data output Cell address Data output WRITE L H L H X3 Command High-Z Data input4 Command Data input4 address address STANDBY H X X H X X High-Z High-Z X High-Z OUTPUT L H H H X X High-Z High-Z X High-Z DISABLE RESET X X X L X X High-Z High-Z X High-Z Notes: 1. Typical glitches of less than 5ns on CE#, WE#, and RST# are ignored by the device and do not affect bus operations. 2. H = Logic level HIGH (V ); L = Logic level LOW (V ); X = HIGH or LOW. IH IL 3. If WP# is LOW, then the highest or the lowest block remains protected, depending on line item. 4. Data input is required when issuing a command sequence or when performing data polling or block protection. Read Bus READ operations read from the memory cells, registers, or CFI space. To accelerate the READ operation, the memory array can be read in page mode where data is inter- nally read and stored in a page buffer. The page size is 8 words (16 bytes) and is addressed by address inputs A[2:0] in x16 bus mode and A[2:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI area do not support page read mode. A valid READ operation requires setting the appropriate address on the address inputs, taking CE# and OE# LOW, and holding WE# HIGH. Data I/O signals output the value. Write Bus WRITE operations write to the command interface. A valid WRITE operation re- quires setting the appropriate address on the address inputs. These are latched by the command interface on the falling edge of CE# or WE#, whichever occurs last. Values on data I/O signals are latched by the command interface on the rising edge of CE# or WE#, whichever occurs first. OE# must remain HIGH during the entire operation. Standby and Automatic Standby When the device is in read mode, driving CE# HIGH places the device in standby mode and drives data I/Os to High-Z. Supply current is reduced to standby (I ) by holding CC2 CE# within V ±0.3V. CC CCMTD-1725822587-2335 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Bus Operations During PROGRAM or ERASE operations, the device continues to use the program/erase supply current (I ) until the operation completes. CC3 Automatic standby enables low power consumption during read mode. When CMOS levels (V ± 0.3 V) drive the bus, and following a READ operation and a period of inac- CC tivity specified in DC Characteristics, the memory enters automatic standby as internal supply current is reduced to I . Data I/O signals still output data if a READ operation CC2 is in progress. Depending on load circuits connected with data bus, V can have a CCQ null consumption when the memory enters automatic standby. Output Disable Data I/Os are High-Z when OE# is HIGH. Reset During reset mode, the device is deselected, and outputs are High-Z. The device is in reset mode when RST# is LOW. Power consumption is reduced to standby level inde- pendently from CE#, OE#, or WE# inputs. CCMTD-1725822587-2335 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Status Register Status Register Table 5: Status Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes DQ7 Data polling 0 or 1, depending on Monitors whether the program/erase controller has successful- 2, 3, 4 bit operations ly completed its operation, or has responded to an ERASE SUS- PEND operation. DQ6 Toggle bit Toggles: 0 to 1; 1 to 0; Monitors whether the program/erase controller has successful- 3, 4, 5 and so on ly completed its operations, or has responded to an ERASE SUSPEND operation. During a PROGRAM/ERASE operation, DQ6 toggles from 0 to 1, 1 to 0, and so on, with each succes- sive READ operation from any address. DQ5 Error bit 0 = Success Identifies errors detected by the program/erase controller. DQ5 4, 6 1 = Failure is set to 1 when a PROGRAM, BLOCK ERASE, or CHIP ERASE op- eration fails to write the correct data to the memory. DQ3 Erase timer 0 = Erase not in progress Identifies the start of program/erase controller operation dur- 4 bit 1 = Erase in progress ing a BLOCK ERASE command. Before the program/erase con- troller starts, this bit set to 0, and additional blocks to be erased can be written to the command interface. DQ2 Alternative Toggles: 0 to 1; 1 to 0; Monitors the program/erase controller during ERASE opera- 3, 4 toggle bit and so on tions. During CHIP ERASE, BLOCK ERASE, and ERASE SUSPEND operations, DQ2 toggles from 0 to 1, 1 to 0, and so on, with each successive READ operation from addresses within the blocks being erased. DQ1 Buffered 1 = Abort Indicates a BUFFER PROGRAM operation abort. The BUFFERED program PROGRAM ABORT and RESET command must be issued to re- abort bit turn the device to read mode (see WRITE TO BUFFER PRO- GRAM command). Notes: 1. The status register can be read during PROGRAM, ERASE, or ERASE SUSPEND operations; the READ operation outputs data on DQ[7:0]. 2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being programmed. For a READ operation from the address previously programmed success- fully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks to be erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon successful completion of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE operation in progress, DQ7 outputs 0; upon either operation's successful completion, DQ7 outputs 1. 3. After successful completion of a PROGRAM or ERASE operation, the device returns to read mode. 4. During erase suspend mode, READ operations to addresses within blocks not being erased output memory array data as if in read mode. A protected block is treated the same as a block not being erased. See the Toggle Flowchart for more information. 5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being erased. The toggling stops when the program/erase controller has suspended the ERASE operation. See the Toggle Flowchart for more information. 6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent command. CCMTD-1725822587-2335 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Status Register Table 6: Operations and Corresponding Bit Settings Note 1 applies to entire table Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# Notes PROGRAM Any address DQ7# Toggle 0 – No toggle 0 0 2 PROGRAM during Any address DQ7# Toggle 0 – – – 0 ERASE SUSPEND BUFFERED Any address DQ7# Toggle 0 – – 1 0 2 PROGRAM ABORT PROGRAM error Any address DQ7# Toggle 1 – – – High-Z CHIP ERASE Any address 0 Toggle 0 1 Toggle – 0 BLOCK ERASE Erasing block 0 Toggle 0 0 Toggle – 0 before time-out Non-erasing block 0 Toggle 0 0 No toggle – 0 BLOCK ERASE Erasing block 0 Toggle 0 1 Toggle – 0 Non-erasing block 0 Toggle 0 1 No toggle – 0 ERASE SUSPEND Erasing block 1 No toggle 0 – Toggle – High-Z Non-erasing block Outputs memory array data as if in read mode – High-Z BLOCK ERASE Good block 0 Toggle 1 1 No toggle – High-Z error address Faulty block 0 Toggle 1 1 Toggle – High-Z address Notes: 1. Unspecified data bits should be ignored. 2. DQ7# for buffer program is related to the last address location loaded. CCMTD-1725822587-2335 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Status Register Figure 4: Data Polling Flowchart Start Read DQ7, DQ5, and DQ1 at valid address1 Yes DQ7 = Data No No No DQ1 = 1 DQ5 = 1 Yes Yes Read DQ7 at valid address Yes DQ7 = Data No Failure 2 Success Notes: 1. Valid address is the address being programmed or an address within the block being erased. 2. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF- FER PROGRAM ABORT operation. CCMTD-1725822587-2335 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Status Register Figure 5: Toggle Bit Flowchart Start Read DQ6 at valid address Read DQ6, DQ5, and DQ1 at valid address No DQ6 = Toggle Yes No No DQ1 = 1 DQ5 = 1 Yes Yes Read DQ6 (twice) at valid address No DQ6 = Toggle Yes Failure1 Success Note: 1. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF- FER PROGRAM ABORT operation. CCMTD-1725822587-2335 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Status Register Figure 6: Status Register Polling Flowchart Start Read 1 Yes Yes Yes DQ7 = Valid data Read 2 Read 3 PROGRAM operation Read 3 correct data? No No No PROGRAM operation Yes DQ5 = 1 Read 2 failure No DQ6 = Toggling Yes Device error Read 3 Read2.DQ6 = Read3.DQ6 No DQ6 = Toggling Yes Timeout failure DQ2 = Toggling Yes Erase/suspend mode Read1.DQ6 = Read2.DQ6 Read2.DQ2 = Read3.DQ2 No No ERASE operation PROGRAM operation Device busy: Repolling complete complete Yes Yes WRITE TO BUFFER WRITE TO BUFFER DQ1 = 1 PROGRAM PROGRAM abort No No Device busy: Repolling CCMTD-1725822587-2335 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Lock Register Lock Register Table 7: Lock Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes DQ2 Password 0 = Password protection Places the device permanently in password protection mode. 2 protection mode enabled mode lock bit 1 = Password protection mode disabled (Default) DQ1 Nonvolatile 0 = Nonvolatile protection Places the device in nonvolatile protection mode with pass- 2 protection mode enabled with pass- word protection mode permanently disabled. When shipped mode lock bit word protection mode from the factory, the device will operate in nonvolatile protec- permanently disabled tion mode, and the memory blocks are unprotected. 1 = Nonvolatile protection mode enabled (Default) DQ0 Extended 0 = Protected If the device is shipped with the extended memory block un- memory 1 = Unprotected (Default) locked, the block can be protected by setting this bit to 0. The block extended memory block protection status can be read in auto protection bit select mode by issuing an AUTO SELECT command. Notes: 1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved and are set to a default value of 1. 2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot both be programmed to 0. Any attempt to program one while the other is programmed causes the operation to abort, and the device returns to read mode. The device is ship- ped from the factory with the default setting. Table 8: Block Protection Status Nonvolatile Nonvolatile Volatile Block Protection Bit Protection Protection Protection Lock Bit1 Bit2 Bit3 Status Block Protection Status 1 1 1 00h Block unprotected; nonvolatile protection bit changeable. 1 1 0 01h Block protected by volatile protection bit; nonvolatile protec- tion bit changeable. 1 0 1 01h Block protected by nonvolatile protection bit; nonvolatile protection bit changeable. 1 0 0 01h Block protected by nonvolatile protection bit and volatile protection bit; nonvolatile protection bit changeable. 0 1 1 00h Block unprotected; nonvolatile protection bit unchangeable. 0 1 0 01h Block protected by volatile protection bit; nonvolatile protec- tion bit unchangeable. 0 0 1 01h Block protected by nonvolatile protection bit; nonvolatile protection bit unchangeable. CCMTD-1725822587-2335 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Lock Register Table 8: Block Protection Status (Continued) Nonvolatile Nonvolatile Volatile Block Protection Bit Protection Protection Protection Lock Bit1 Bit2 Bit3 Status Block Protection Status 0 0 0 01h Block protected by nonvolatile protection bit and volatile protection bit; nonvolatile protection bit unchangeable. Notes: 1. Nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked. 2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. Figure 7: Lock Register Program Flowchart Start Enter LOCK REGISTER command set Address/data (unlock) cycle 1 Address/data (unlock) cycle 2 Address/data cycle 3 PROGRAM LOCK REGISTER Address/data cycle 1 Address/data cycle 2 Polling algorithm Yes Done? No No DQ5 = 1 Yes Success: Failure: EXIT PROTECTION command set READ/RESET (Returns to device read mode) (Returns device to read mode) Address/data cycle 1 Address/data cycle 2 Notes: 1. Each lock register bit can be programmed only once. CCMTD-1725822587-2335 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Lock Register 2. See the Block Protection Command Definitions table for address-data cycle details. CCMTD-1725822587-2335 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Standard Command Definitions – Address-Data Cycles Standard Command Definitions – Address-Data Cycles Table 9: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit Note 1 applies to entire table Address and Data Cycles Command and Bus 1st 2nd 3rd 4th 5th 6th Code/Subcode Size A D A D A D A D A D A D Notes READ and AUTO SELECT Operations READ/RESET (F0h) x8 X F0 AAA AA 555 55 X F0 x16 X F0 555 AA 2AA 55 X F0 READ CFI (98h) x8 AA 98 x16 55 AUTO SELECT (90h) x8 AAA AA 555 55 AAA 90 Note Note 2, 3, 4 x16 555 2AA 555 2 2 BYPASS Operations UNLOCK BYPASS (20h) x8 AAA AA 555 55 AAA 20 x16 555 2AA 555 UNLOCK BYPASS x8 X 90 X 00 RESET (90h/00h) x16 PROGRAM Operations PROGRAM (A0h) x8 AAA AA 555 55 AAA A0 PA PD x16 555 2AA 555 UNLOCK BYPASS x8 X A0 PA PD 5 PROGRAM (A0h) x16 WRITE TO BUFFER x8 AAA AA 555 55 BAd 25 BAd N PA PD 6, 7, 8 PROGRAM (25h) x16 555 2AA UNLOCK BYPASS x8 BAd 25 BAd N PA PD 5 WRITE TO BUFFER x16 PROGRAM (25h) WRITE TO BUFFER x8 BAd 29 PROGRAM CONFIRM x16 (29h) BUFFERED PROGRAM x8 AAA AA 555 55 AAA F0 ABORT and RESET (F0h) x16 555 2AA 555 ENHANCED x8 NA 9 BUFFERED x16 555 AA 2AA 55 555 33 BAd Data PROGRAM (33h) (00) UNLOCK BYPASS x8 NA 10 ENHANCED x16 BAd 33 BAd Data BAd Data BUFFERED PROGRAM (00) (01) (33h) CCMTD-1725822587-2335 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Standard Command Definitions – Address-Data Cycles Table 9: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued) Note 1 applies to entire table Address and Data Cycles Command and Bus 1st 2nd 3rd 4th 5th 6th Code/Subcode Size A D A D A D A D A D A D Notes ENHANCED x8 NA BUFFERED x16 BAd 29 PROGRAM CONFIRM (00) (29h) ENHANCED x8 NA BUFFERED x16 555 AA 2AA 55 555 F0 PROGRAM ABORT (F0h) PROGRAM SUSPEND x8 X B0 (B0h) x16 PROGRAM RESUME x8 X 30 (30h) x16 ERASE Operations CHIP ERASE (80/10h) x8 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 x16 555 2AA 555 555 2AA 555 UNLOCK BYPASS x8 X 80 X 10 5 CHIP ERASE (80/10h) x16 BLOCK ERASE (80/30h) x8 AAA AA 555 55 AAA 80 AAA AA 555 55 BAd 30 11 x16 555 2AA 555 555 2AA UNLOCK BYPASS x8 X 80 BAd 30 5 BLOCK ERASE (80/30h) x16 ERASE SUSPEND (B0h) x8 X B0 x16 ERASE RESUME (30h) x8 X 30 x16 Notes: 1. A = Address; D = Data; X = "Don't Care"; BAd = Any address in the block; N = Number of bytes to be programmed; PA = Program address; PD = Program data; Gray shading = Not applicable. All values in the table are hexadecimal. Some commands require both a com- mand code and subcode. 2. These cells represent READ cycles (versus WRITE cycles for the others). 3. AUTO SELECT enables the device to read the manufacturer code, device code, block pro- tection status, and extended memory block protection indicator. 4. AUTO SELECT addresses and data are specified in the Electronic Signature table and the Extended Memory Block Protection table. 5. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are unnecessary. 6. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM 3rd and 4th cycles. 7. WRITE TO BUFFER PROGRAM operation: maximum cycles = 68(x8) and 36 (x16). UNLOCK BYPASS WRITE TO BUFFER PROGRAM operation: maximum cycles = 66 (x8), 34 (x16). CCMTD-1725822587-2335 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash READ Operations WRITE TO BUFFER PROGRAM operation: N + 1 = bytes to be programmed; maximum buffer size = 64 bytes (x8) and 32 words (x16). 8. For x8, A[MAX:5] address pins should remain unchanged while A[4:0] and A-1 pins are used to select a byte within the N + 1 byte page. For x16, A[MAX:5] address pins should remain unchanged while A[4:0] pins are used to select a word within the N + 1 word page. 9. The following is content for address-data cycles 258 through 259: BAd (FE) - Data; BAd (FF) - Data. 10. The following is content for address-data cycles 256 through 257: BAd (FE) - Data; BAd (FF) - Data. 11. BLOCK ERASE address cycles can extend beyond six address-data cycles, depending on the number of blocks to erase. READ Operations READ/RESET Command The READ/RESET (F0h) command returns the device to read mode and resets the errors in the status register. One or three bus WRITE operations can be used to issue the READ/RESET command. To return the device to read mode, this command can be issued between bus WRITE cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET com- mand is issued during the timeout of a BLOCK ERASE operation, the device requires up to 10μs to abort, during which time no valid data can be read. READ CFI Command The READ CFI (98h) command puts the device in read CFI mode and is valid only when the device is in read array or auto select mode. One bus WRITE cycle is required to issue the command. Once in read CFI mode, bus READ operations will output data from the CFI memory area. A READ/RESET command must be issued to return the device to the previous mode (read array or auto select ). A second READ/RESET command is required to put the device in read array mode from auto select mode. CCMTD-1725822587-2335 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash AUTO SELECT Operations AUTO SELECT Operations AUTO SELECT Command At power-up or after a hardware reset, the device is in read mode. It can then be put in auto select mode by issuing an AUTO SELECT (90h) command or by applying V to A9. ID Auto select mode enables the following device information to be read: • Electronic signature, which includes manufacturer and device code information, as shown in the Electronic Signature table. • Block protection, which includes the block protection status and extended memory block protection indicator, as shown in the Block Protection table. Electronic signature or block protection information is read by executing a READ opera- tion with control signals and addresses set, as shown in the Read Electronic Signature table or the Block Protection table, respectively. Auto select mode can be used by the programming equipment to automatically match a device with the application code to be programmed. Three consecutive bus WRITE operations are required to issue an AUTO SELECT com- mand. The device remains in auto select mode until a READ/RESET or READ CFI com- mand is issued. The device cannot enter auto select mode when a PROGRAM or ERASE operation is in progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUS- PEND command. To enter auto select mode by appling V to A9, see the Read Electronic Signature table ID and the Block Protection table. Auto select mode is exited by performing a reset. The device returns to read mode un- less it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND command, in which case it returns to erase or program suspend mode. Table 10: Read Electronic Signature Note 1 applies to entire table READ Cycle Manufacturer Signal Code Device Code 1 Device Code 3 Device Code 3 Notes CE# L L L L OE# L L L L WE# H H H H Address Input, 8-Bit and 16-Bit A[MAX:10] X X X X A9 V V V V 2 ID ID ID ID A8 X X X X A[7:5] L L L L A4 X X X X A[3:1] L L H H CCMTD-1725822587-2335 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash AUTO SELECT Operations Table 10: Read Electronic Signature (Continued) Note 1 applies to entire table READ Cycle Manufacturer Signal Code Device Code 1 Device Code 3 Device Code 3 Notes A0 L H L H Address Input, 8-Bit Only DQ[15]/A-1 X X X X Data I/O, 8-Bit Only DQ[14:8] X X X X DQ[7:0] 20h 7Eh 21h XX Data I/O, 16-Bit Only DQ[15]/A-1, and DQ[14:0] 0020h 227Eh 2221h XXXX Notes: 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 2. When using the AUTO SELECT command to enter auto select mode, applying V to A9 is ID not required. A9 can be either V or V . IL IH 3. XX = 01h for M29W128GH and 00h for M29W128GL. 4. XXXX = 2201h for M29W128GH and 2200h for M29W128GL. CCMTD-1725822587-2335 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash AUTO SELECT Operations Table 11: Block Protection Note 1 applies to entire table READ Cycle Extended Memory Extended Memory Block Block Block Protection Signal Verify Indicator (GL) Verify Indicator (GH) Status Indicator Notes CE# L L L OE# L L L WE# H H H Address Input, 8-Bit and 16-Bit A[MAX:16] X X Block base address A[15:10] X X X A9 V V V 2 ID ID ID A8 X X X A[7:5] L L L A4 X X X A[3:2] L L L A1 H H H A0 H H L Address Input, 8-Bit Only DQ[15]/A-1 X X X Data I/O, 8-Bit Only DQ[14:8] X X X DQ[7:0] 89h 99h 01h 3, 5 09h 19h 00h 4, 6 Data I/O, 16-Bit Only DQ[15]/A-1, and DQ[14:0] 0089h 0099h 0001h 3, 5 0009h 0019h 0000h 4, 6 Notes: 1. Read cycle output to DQ7 = Extended memory block protection indicator; GH = High block protection; GL = Low block protection; BPS = Block protection status; H = Logic level HIGH (V ); L = Logic level LOW (V ); X = HIGH or LOW. IH IL 2. When using the AUTO SELECT command to enter auto select mode, applying V to A9 is ID not required. A9 can be either V or V . IL IH 3. Extended memory blocks are Micron-prelocked (permanent). 4. Extended memory blocks are customer-lockable. 5. Block protection status = protected: 01h (in x8 mode) is output on DQ[7:0]. 6. Block protection status = unprotected: 00h (in x8 mode) is output on DQ[7:0]. CCMTD-1725822587-2335 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Bypass Operations Bypass Operations UNLOCK BYPASS Command The UNLOCK BYPASS (20h) command is used to place the device in unlock bypass mode. Three bus WRITE operations are required to issue the UNLOCK BYPASS com- mand. When the device enters unlock bypass mode, the two initial UNLOCK cycles required for a standard PROGRAM or ERASE operation are not needed, thus enabling faster total program or erase time. The UNLOCK BYPASS command is used in conjunction with UNLOCK BYPASS PRO- GRAM or UNLOCK BYPASS ERASE commands to program or erase the device faster than with standard PROGRAM or ERASE commands. Using these commands can save considerable time when the cycle time to the device is long. When in unlock bypass mode, only the following commands are valid: • The UNLOCK BYPASS PROGRAM command can be issued to program addresses within the device. • The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or more memory blocks. • The UNLOCK BYPASS CHIP ERASE command can be issued to erase the whole mem- ory array. • The UNLOCK BYPASS WRITE TO BUFFER PROGRAM and UNLOCK BYPASS EN- HANCED WRITE TO BUFFER PROGRAM commands can be issued to speed up the programming operation. • The UNLOCK BYPASS RESET command can be issued to return the device to read mode. In unlock bypass mode, the device can be read as if in read mode. In addition to the UNLOCK BYPASS command, when V /WP# is raised to V , the de- PP PPH vice automatically enters unlock bypass mode. When V /WP# returns to V or V , the PP IH IL device is no longer in unlock bypass mode, and normal operation resumes. The transi- tions from V to V and from V to V must be slower than tVHVPP. (See the Accel- IH PPH PPH IH erated Program, Data Polling/Toggle AC Characteristics.) Note: Micron recommends entering and exiting unlock bypass mode using the ENTER UNLOCK BYPASS and UNLOCK BYPASS RESET commands rather than raising V /WP# PP to V . V /WP# should never be raised to V from any mode except read mode; oth- PPH PP PPH erwise, the device may be left in an indeterminate state. V /WP# should not remain at PP V for than 80 hours cumulative. PPH UNLOCK BYPASS RESET Command The UNLOCK BYPASS RESET (90/00h) command is used to return to read/reset mode from unlock bypass mode. Two bus WRITE operations are required to issue the UN- LOCK BYPASS RESET command. The READ/RESET command does not exit from un- lock bypass mode. CCMTD-1725822587-2335 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations Program Operations PROGRAM Command The PROGRAM (A0h) command can be used to program a value to one address in the memory array. The command requires four bus WRITE operations, and the final WRITE operation latches the address and data in the internal state machine and starts the pro- gram/erase controller. After programming has started, bus READ operations output the status register content. Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND command and a PROGRAM RESUME command, respectively. If the address falls in a protected block, the PROGRAM command is ignored, and the data remains unchanged. The status register is not read, and no error condition is given. After the PROGRAM operation has completed, the device returns to read mode, unless an error has occurred. When an error occurs, bus READ operations to the device contin- ue to output the status register. A READ/RESET command must be issued to reset the error condition and return the device to read mode. The PROGRAM command cannot change a bit set to 0 back to 1, and an attempt to do so is masked during a PROGRAM operation. Instead, an ERASE command must be used to set all bits in one memory block or in the entire memory from 0 to 1. The PROGRAM operation is aborted by performing a reset or by powering-down the de- vice. In this case, data integrity cannot be ensured, and it is recommended that the words or bytes that were aborted be reprogrammed. UNLOCK BYPASS PROGRAM Command When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h) command can be used to program one address in the memory array. The command re- quires two bus WRITE operations instead of four required by a standard PROGRAM command; the final WRITE operation latches the address and data and starts the pro- gram/erase controller (The standard PROGRAM command requires four bus WRITE op- erations). The PROGRAM operation using the UNLOCK BYPASS PROGRAM command behaves identically to the PROGRAM operation using the PROGRAM command. The operation cannot be aborted. A bus READ operation to the memory outputs the status register. WRITE TO BUFFER PROGRAM Command The WRITE TO BUFFER PROGRAM (25h) command makes use of the 32-word program buffer to speed up programming. A maximum of 32 words can be loaded into the pro- gram buffer. The WRITE TO BUFFER PROGRAM command dramatically reduces system programming time compared to the standard non-buffered PROGRAM command. When issuing a WRITE TO BUFFER PROGRAM command, V /WP# can be either held PP HIGH or raised to V . Also, it can be held LOW if the block is not the lowest or highest PPH block, depending on the part number. The following successive steps are required to is- sue the WRITE TO BUFFER PROGRAM command: First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE TO BUFFER PROGRAM command. The set-up code can be addressed to any location CCMTD-1725822587-2335 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words/ bytes to be programmed. Value n is written to the same block address, where n + 1 is the number of words/bytes to be programmed. Value n + 1 must not exceed the size of the program buffer, or the operation will abort. A fifth cycle loads the first address and data to be programmed. Last, n bus WRITE cycles load the address and data for each word/ byte into the program buffer. Addresses must lie within the range from the start address +1 to the start address + (n - 1). Optimum programming performance and lower power usage are achieved by aligning the starting address at the beginning of a 32-word boundary. Any buffer size smaller than 32 words is allowed within a 32-word boundary, while all addresses used in the op- eration must lie within the 32-word boundary. In addition, any crossing boundary buf- fer program will result in a program abort. To program the content of the program buffer, this command must be followed by a WRITE TO BUFFER PROGRAM CONFIRM command. If an address is written several times during a WRITE TO BUFFER PROGRAM operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort the WRITE TO BUFFER PROGRAM command. The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a WRITE TO BUFFER PROGRAM operation. The WRITE BUFFER PROGRAM command should not be used to change a bit set to 0 back to 1, and an attempt to do so is masked during the operation. Rather than the WRITE BUFFER PROGRAM command, the ERASE command should be used to set memory bits from 0 to 1. CCMTD-1725822587-2335 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations Figure 8: WRITE TO BUFFER PROGRAM Flowchart Start WRITE TO BUFFER WRITE TO BUFFER command, confirm, block address block address Read data polling Write n,1 register (DQ1, DQ5, block address First three cycles of the DQ7) at last loaded WRITE TO BUFFER address PROGRAM command Write buffer data, start address Yes DQ7 = Data X = n No No No Yes DQ1 = 1 DQ5 = 1 X = 0 Yes Yes No Check data polling register (DQ5, DQ7) Abort Yes Write to a different at last loaded address WRITE TO BUFFER block address No Yes WRITE TO BUFFER DQ7 = Data4 Write next data,3 and PROGRAM program address pair aborted2 No Fail or X = X - 1 abort5 End Notes: 1. n + 1 is the number of addresses to be programmed. 2. The BUFFERED PROGRAM ABORT and RESET command must be issued to return the de- vice to read mode. 3. When the block address is specified, any address in the selected block address space is acceptable. However, when loading program buffer address with data, all addresses must fall within the selected program buffer page. 4. DQ7 must be checked because DQ5 and DQ7 may change simultaneously. 5. If this flowchart location is reached because DQ5 = 1, then the WRITE TO BUFFER PRO- GRAM command failed. If this flowchart location is reached because DQ1 = 1, then the WRITE TO BUFFER PROGRAM command aborted. In both cases, the appropriate RESET command must be issued to return the device to read mode: A RESET command if the operation failed; a WRITE TO BUFFER PROGRAM ABORT AND RESET command if the op- eration aborted. 6. See the Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit table for details about the WRITE TO BUFFER PROGRAM command sequence. CCMTD-1725822587-2335 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER (25h) command can be used to program the device in fast program mode. The com- mand requires two bus WRITE operations fewer than the standard WRITE TO BUFFER PROGRAM command. The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command behaves the same way as the WRITE TO BUFFER PROGRAM command: the operation cannot be aborted, and a bus READ operation to the memory outputs the status register. The WRITE TO BUFFER PROGRAM CONFIRM command is used to confirm an UN- LOCK BYPASS WRITE TO BUFFER PROGRAM command and to program the n + 1 words/bytes loaded in the program buffer by this command. WRITE TO BUFFER PROGRAM CONFIRM Command The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a WRITE TO BUFFER PROGRAM command and to program the n + 1 words/bytes loaded in the program buffer by this command. BUFFERED PROGRAM ABORT AND RESET Command A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to abort the WRITE TO BUFFER PROGRAM and ENHANCED BUFFERED PROGRAM operations and reset the device in read mode. The buffer programming sequence can be aborted in the following ways: • Load a value that is greater than the page buffer size during the number of locations to program in the WRITE TO BUFFER PROGRAM command. • Write to an address in a different block than the one specified during the WRITE BUF- FER LOAD command. • Write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. • Write data other than the CONFIRM command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location loaded), DQ6 = toggle, and DQ5 = 0 (all of which are status register bits). A BUFFERED PROGRAM ABORT and RESET command sequence must be written to reset the device for the next operation. Note: The full three-cycle BUFFERED PROGRAM ABORT and RESET command se- quence is required when using buffer programming features in unlock bypass mode. PROGRAM SUSPEND Command The PROGRAM SUSPEND (B0h) command can be used to interrupt a program opera- tion so that data can be read from any block. When the PROGRAM SUSPEND command is issued during a program operation, the device suspends the operation within the pro- gram suspend latency time and updates the status register bits. After the program operation has been suspended, data can be read from any address. However, data is invalid when read from an address where a program operation has been suspended. CCMTD-1725822587-2335 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations The PROGRAM SUSPEND command may also be issued during a PROGRAM operation while an erase is suspended. In this case, data may be read from any address not in erase suspend or program suspend mode. To read from the extended memory block area (one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK command sequences must be issued. The system may also issue the AUTO SELECT command sequence when the device is in program suspend mode. The system can read as many auto select codes as required. When the device exits auto select mode, the device reverts to program suspend mode and is ready for another valid operation. The PROGRAM SUSPEND operation is aborted by performing a device reset or power- down. In this case, data integrity cannot be ensured, and it is recommended that the words or bytes that were aborted be reprogrammed. PROGRAM RESUME Command The PROGRAM RESUME (30h) command must be issued to exit a program suspend mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 status bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME command is issued, subsequent PROGRAM RESUME commands are ignored. Another PROGRAM SUSPEND command can be issued after the device has resumed program- ming. ENHANCED BUFFERED PROGRAM Command The ENHANCED BUFFERED PROGRAM command (x16 only) makes use of a 256-word write buffer to speed up programming. Each write buffer has the same A22-A8 address- es. This command dramatically reduces system programming time compared to both the standard non-buffered PROGRAM command and the WRITE TO BUFFER com- mand. When issuing the ENHANCED BUFFERED PROGRAM command, the V /WP pin can PP be held HIGH or raised to V (see Program/Erase Characteristics). The following suc- PPH cessive steps are required to issue the ENHANCED BUFFERED PROGRAM command: The ENHANCED BUFFERED PROGRAM command begins with two unlock cycles, fol- lowed by one bus write cycle that sets up the command. The setup code can be ad- dressed to any location within the targeted block. Next, another bus write cycle loads the first address and data to be programmed. There a total of 256 address and data load- ing cycles. To program the content of the write buffer, the ENHANCED BUFFERED PROGRAM command must be followed by an ENHANCED BUFFERED PROGRAM CONFIRM command. The command ends with an internal enhanced buffered program confirm cycle. Address/data cycles must be loaded in an increasing address order, from A[7:0] = 00000000 to A[7:0] = 11111111 until all 256 words are loaded. Invalid address combina- tions or the incorrect sequence of bus WRITE cycles will abort the WRITE TO BUFFER PROGRAM command. The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a WRITE TO BUFFER PROGRAM operation. An external 12V supply can be used to improve programming efficiency. CCMTD-1725822587-2335 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations When reprogramming data in a portion of memory already programmed (changing programmed data from '0' to '1') operation failure can be detected by a logical OR be- tween the previous and the current value. UNLOCK BYPASS ENHANCED BUFFERED PROGRAM Command The UNLOCK BYPASS ENHANCED BUFFERED PROGRAM command can be used to program the memory in fast program mode. The command requires two less address/ data loading cycles than the standard ENHANCED BUFFERED PROGRAM command. Otherwise, the two operations behave identically. The operation cannot be aborted and a READ operation to the memory outputs the status register. The ENHANCED BUF- FERED PROGRAM CONFIRM command confirms the command and programs the 256 words loaded in the buffer. ENHANCED BUFFERED PROGRAM CONFIRM Command The ENHANCED BUFFERED PROGRAM CONFIRM command is used to confirm the two ENHANCED BUFFERED PROGRAM CONFIRM commands and to program the 256 words loaded in the buffer. CCMTD-1725822587-2335 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations Figure 9: ENHANCED BUFFERED PROGRAM Flowchart Start ENHANCED BUFFERED First cycle of the PROGRAM command, ENHANCED BUFFERED PROGRAM ENHANCED block address command BUFFERED PROGRAM command set Write buffer data, start address (00), Read DQ6 at X=255 valid address Yes Read X = 0 DQ5 and DQ6 at valid address No Abort WRITE Yes Write to a different DQ6= No TO BUFFER block address toggle No Yes ENHANCED BUFFERED No p rWogrritaem n aedxtd dreastsa p, a(2)ir PROGRAM aborted (1) DQ5=1 Yes Write next data, (2) Read DQ6 program address pair twice at valid address X = X-1 DQ6 = No toggle Yes ENHANCED BUFFERED 258th WRITE cycle of the PROGRAM confirm, ENHANCED BUFFERED PROGRAM Fail block address command Read status register (DQ1, DQ5, DQ7) at last loaded address Yes DQ7 = Data No No No DQ1 = 1 DQ5 = 1 Yes Yes Check status register las(tD lQoa5d, eDdQ a7d) darte ss New Yes Program? No Yes Exit ENHANCED DQ7 (=3 )Data BUFFERED PROGRAM command set No Fail or Abort(4) End Notes: 1. The BUFFERED PROGRAM ABORT AND RESET command must be issued to return the de- vice to read mode. CCMTD-1725822587-2335 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program Operations 2. When the block address is specified, all addresses in the selected block address space must be issued starting from 00h. Furthermore, when loading the write buffer address with data, data program addresses must be consecutive. 3. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 4. If this flowchart location is reached because DQ5 = 1, then the ENHANCED WRITE TO BUFFER PROGRAM command failed. If this flowchart location is reached because DQ1 = 1, then the ENHANCED WRITE TO BUFFER PROGRAM command aborted. In both cases, the appropriate RESET command must be issued to return the device to read mode: A RESET command if the operation failed; a WRITE TO BUFFER PROGRAM ABORT AND RE- SET command if the operation aborted. CCMTD-1725822587-2335 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Erase Operations Erase Operations CHIP ERASE Command The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations are required to issue the command and start the program/erase controller. Protected blocks are not erased. If all blocks are protected, the CHIP ERASE operation appears to start, but will terminate within approximately100μs, leaving the data un- changed. No error is reported when protected blocks are not erased. During the CHIP ERASE operation, the device ignores all other commands, including ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations dur- ing CHIP ERASE output the status register on the data I/Os. (See the Status Register sec- tion for more details.) After the CHIP ERASE operation completes, the device returns to read mode, unless an error has occurred. If an error occurs, the device will continue to output the status regis- ter. A READ/RESET command must be issued to reset the error condition and return to read mode. The CHIP ERASE command sets all of the bits in unprotected blocks of the device to 1. All previous data is lost. The operation is aborted by performing a reset or by powering-down the device. In this case, data integrity cannot be ensured, and the entire chip should be erased again. UNLOCK BYPASS CHIP ERASE Command When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h) command can be used to erase all memory blocks at one time. The command requires only two bus WRITE operations instead of six using the standard CHIP ERASE com- mand. The final bus WRITE operation starts the program/erase controller. The UNLOCK BYPASS CHIP ERASE command behaves the same way as the CHIP ERASE command: the operation cannot be aborted, and a bus READ operation to the memory outputs the status register. BLOCK ERASE Command The BLOCK ERASE (80/30h) command erases a list of one or more blocks. It sets all of the bits in the unprotected selected blocks to 1. All previous data in the selected blocks is lost. Six bus WRITE operations are required to select the first block in the list. Each addition- al block in the list can be selected by repeating the sixth bus WRITE operation using the address of the additional block. After the command sequence is written, a block erase timeout occurs. During the timeout period, additional block addresses and BLOCK ERASE commands can be written. After the program/erase controller has started, it is not possible to select any more blocks. Each additional block must therefore be selected within the timeout period of the last block. The timeout timer restarts when an addi- tional block is selected. After the sixth bus WRITE operation, a bus READ operation out- puts the status register. (See the WE#-Controlled Program waveforms for details on how to identify if the program/erase controller has started the BLOCK ERASE operation.) CCMTD-1725822587-2335 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Erase Operations After the BLOCK ERASE operation completes, the device returns to read mode, unless an error has occurred. If an error occurs, bus READ operations will continue to output the status register. A READ/RESET command must be issued to reset the error condi- tion and return to read mode. If any selected blocks are protected, they are ignored, and all the other selected blocks are erased. If all the selected blocks are protected, the BLOCK ERASE operation appears to start, but will terminate within approximately100μs, leaving the data unchanged. No error condition is given when protected blocks are not erased. During the BLOCK ERASE operation, the device ignores all commands except the ERASE SUSPEND command and the READ/RESET command, which is accepted only during the timeout period. The operation is aborted by performing a reset or powering- down the device. In this case, data integrity cannot be ensured, and the aborted blocks should be erased again. UNLOCK BYPASS BLOCK ERASE Command When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE (80/30h) command can be used to erase one or more memory blocks at a time. The command requires two bus WRITE operations instead of six using the standard BLOCK ERASE command. The final bus WRITE operation latches the address of the block and starts the program/erase controller. To erase multiple blocks (after the first two bus WRITE operations have selected the first block in the list), each additional block in the list can be selected by repeating the sec- ond bus WRITE operation using the address of the additional block. The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK ERASE command: the operation cannot be aborted, and a bus READ operation to the memory outputs the status register. (See the BLOCK ERASE Command section for de- tails.) ERASE SUSPEND Command The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE opera- tion. One bus WRITE operation is required to issue the command. The block address is "Don't Care." The program/erase controller suspends the ERASE operation within the erase suspend latency time of the ERASE SUSPEND command being issued. However, when the ERASE SUSPEND command is written during the block erase timeout, the device im- mediately terminates the timeout period and suspends the ERASE operation. After the program/erase controller has stopped, the device operates in read mode, and the erase is suspended. During an ERASE SUSPEND operation, it is possible to read and execute PROGRAM op- erations or WRITE TO BUFFER PROGRAM operations in blocks that are not suspended. Both READ and PROGRAM operations behave normally on these blocks. Reading from blocks that are suspended will output the status register. If any attempt is made to pro- gram in a protected block or in the suspended block, the PROGRAM command is ignor- ed, and the data remains unchanged. In this case, the status register is not read, and no error condition is given. CCMTD-1725822587-2335 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Erase Operations It is also possible to issue AUTO SELECT and UNLOCK BYPASS commands during an ERASE SUSPEND operation. The READ/RESET command must be issued to return the device to read array mode before the RESUME command will be accepted. During an ERASE SUSPEND operation, a bus READ operation to the extended memory block will output the extended memory block data. After the device enters extended memory block mode, the EXIT EXTENDED MEMORY BLOCK command must be issued before the ERASE operation can be resumed. An ERASE SUSPEND command is ignored if it is written during a CHIP ERASE opera- tion. If the ERASE SUSPEND operation is aborted by performing a device reset or power- down, data integrity cannot be ensured, and the suspended blocks should be erased again. ERASE RESUME Command The ERASE RESUME (30h) command restarts the program/erase controller after an ERASE SUSPEND operation. The device must be in read array mode before the RESUME command will be accepted. An erase can be suspended and resumed more than once. CCMTD-1725822587-2335 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Block Protection Command Definitions – Address-Data Cycles Block Protection Command Definitions – Address-Data Cycles Table 12: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit Notes 1 and 2 apply to entire table Address and Data Cycles Command and Bus 1st 2nd 3rd 4th nth Code/Subcode Size A D A D A D A D … A D Notes LOCK REGISTER Commands ENTER LOCK REGISTER x8 AAA AA 555 55 AAA 40 3 COMMAND SET (40h) x16 555 AA 2AA 55 555 PROGRAM LOCK REGISTER x8 X A0 X Data 5 (A0h) x16 READ LOCK REGISTER x8 X Data 4, 5, 6 x16 PASSWORD PROTECTION Commands ENTER PASSWORD x8 AAA AA 555 55 AAA 60 3 PROTECTION COMMAND x16 555 AA 2AA 55 555 SET (60h) PROGRAM PASSWORD x8 X A0 PWAn PWDn 7 (A0h) x16 READ PASSWORD x8 00 PWD0 01 PWD1 02 PWD2 03 PWD3 … 07 PWD7 4, 6, 8, x16 00 PWD0 01 PWD1 02 PWD2 03 PWD3 9 UNLOCK PASSWORD x8 00 25 00 03 00 PWD0 01 PWD1 … 00 29 8, 10 (25h/03) x16 NONVOLATILE PROTECTION Commands ENTER NONVOLATILE x8 AAA AA 555 55 AAA C0 3 PROTECTION COMMAND x16 555 AA 2AA 55 555 SET (C0h) PROGRAM NONVOLATILE x8 X A0 BAd 00 PROTECTION BIT (A0h) x16 READ NONVOLATILE x8 BAd READ(0) 4, 6, PROTECTION BIT STATUS x16 11 CLEAR ALL NONVOLATILE x8 X 80 00 30 12 PROTECTION BITS (80/30h) x16 NONVOLATILE PROTECTION BIT LOCK BIT Commands ENTER NONVOLATILE x8 AAA AA 555 55 AAA 50 3 PROTECTION BIT LOCK BIT x16 555 AA 2AA 55 555 COMMAND SET (50h) PROGRAM NONVOLATILE x8 X A0 X 00 11 PROTECTION BIT LOCK BIT x16 (A0h) CCMTD-1725822587-2335 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Block Protection Command Definitions – Address-Data Cycles Table 12: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued) Notes 1 and 2 apply to entire table Address and Data Cycles Command and Bus 1st 2nd 3rd 4th nth Code/Subcode Size A D A D A D A D … A D Notes READ NONVOLATILE x8 X READ(0) 4, 6, PROTECTION BIT LOCK BIT x16 11 STATUS VOLATILE PROTECTION Commands ENTER VOLATILE x8 AAA AA 555 55 AAA E0 3 PROTECTION COMMAND x16 555 AA 2AA 55 555 SET (E0h) PROGRAM VOLATILE x8 X A0 BAd 00 PROTECTION BIT (A0h) x16 READ VOLATILE x8 BAd READ(0) 4, 6, PROTECTION BIT STATUS x16 11 CLEAR VOLATILE x8 X A0 BAd 01 PROTECTION BIT (A0h) x16 EXTENDED MEMORY BLOCK Commands ENTER EXTENDED x8 AAA AA 555 55 AAA 88 3 MEMORY BLOCK (88h) x16 555 AA 2AA 55 555 EXIT EXTENDED x8 AAA AA 555 55 AAA 90 X 00 MEMORY BLOCK (90/00h) x16 555 AA 2AA 55 555 EXIT PROTECTION Commands EXIT PROTECTION x8 X 90 X 00 3 COMMAND SET (90/00h) x16 Notes: 1. Key: A = Address and D = Data; X = "Don’t Care;" BAd = any address in the block; PWDn = password bytes 0 to 7; PWAn = password address, n = 0 to 7; Gray = not applicable. All values in the table are hexadecimal. 2. DQ[15:8] are "Don’t Care" during UNLOCK and COMMAND cycles. A[MAX:16] are "Don’t Care" during UNLOCK and COMMAND cycles, unless an address is required. 3. The ENTER command sequence must be issued prior to any operation. It disables READ and WRITE operations from and to block 0. READ and WRITE operations from and to any other block are allowed. Also, when an ENTER COMMAND SET command is issued, an EXIT PROTECTION COMMAND SET command must be issued to return the device to READ mode. 4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven LOW and data is read according to a specified address. 5. Data = Lock register content. 6. All address cycles shown for this command are READ cycles. 7. Only one portion of the password can be programmed or read by each PROGRAM PASS- WORD command. 8. Each portion of the password can be entered or read in any order as long as the entire 64-bit password is entered or read. CCMTD-1725822587-2335 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Block Protection Command Definitions – Address-Data Cycles 9. For the x8 READ PASSWORD command, the nth (and final) address cycle equals the 8th address cycle. From the 5th to the 8th address cycle, the values for each address and da- ta pair continue the pattern shown in the table as follows: for x8, address and data = 04 and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7. 10. For the x8 UNLOCK PASSWORD command, the nth (and final) address cycle equals the 11th address cycle. From the 5th to the 10th address cycle, the values for each address and data pair continue the pattern shown in the table as follows: address and data = 02 and PWD2; 03 and PWD3; 04 and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7. For the x16 UNLOCK PASSWORD command, the nth (and final) address cycle equals the 7th address cycle. For the 5th and 6th address cycles, the values for the address and data pair continue the pattern shown in the table as follows: address and data = 02 and PWD2; 03 and PWD3. 11. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00; Unprotected state= 01. 12. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile pro- tection bits before erasure. This prevents over-erasure of previously cleared nonvolatile protection bits. CCMTD-1725822587-2335 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Protection Operations Protection Operations Blocks can be protected individually against accidental PROGRAM, ERASE, or READ op- erations on both 8-bit and 16-bit configurations. The block protection scheme is shown in the Software Protection Scheme figure. Memory block and extended memory block protection is configured through the lock register. LOCK REGISTER Commands The ENTER LOCK REGISTER COMMAND SET (40h) command enables execution of all READ or PROGRAM LOCK REGISTER commands. PROGRAM LOCK REGISTER (A0h) configures the lock register, and READ LOCK REGISTER reads/confirms programmed data. PASSWORD PROTECTION Commands The ENTER PASSWORD PROTECTION COMMAND SET (60h) command enables execu- tion of password protection commands. PROGRAM PASSWORD (A0h) programs the 64- bit password used in the password protection mode. To program the 64-bit password in 8-bit mode, the complete command sequence must be entered eight times at eight con- secutive addresses selected by A[1:0] plus DQ15/A-1; in 16-bit mode, the command se- quence must be entered four times at four consecutive addresses selected by A[1:0]. By default, all password bits are set to 1. The password can be checked by issuing a READ PASSWORD command. READ PASSWORD verifies the password used in password protection mode. To verify the 64-bit password in 8-bit mode, the complete command sequence must be entered eight times at eight consecutive addresses selected by A[1:0] plus DQ15/A-1. In 16-bit mode, the command sequence must be entered four times at four consecutive address- es selected by A[1:0]. If the password mode lock bit is programmed, and a user attempts to read the password, the device outputs FFh. UNLOCK PASSWORD (25/03h) clears the nonvolatile protection bit lock bit, allowing the nonvolatile protection bits to be modified. UNLOCK PASSWORD must be issued with the correct password and requires a 1μs delay between successive UNLOCK PASS- WORD commands. The delay helps prevent password intruders from trying all possible 64-bit combinations. If the delay does not occur, the latest command is ignored. After a valid 64-bit password is entered, approximately 1μs is required to unlock the device. NONVOLATILE PROTECTION Commands The ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command enables nonvolatile protection mode commands to be issued to the device. A block can be pro- tected from PROGRAM or ERASE operations using a PROGRAM NONVOLATILE PRO- TECTION BIT (A0h) command, along with the block address. This command sets the nonvolatile protection bit to 0 for a given block. The status of a nonvolatile protection bit for a given block or group of blocks can be read using a READ NONVOLATILE MODIFY PROTECTION BIT command, along with the block address. The nonvolatile protection bits are erased simultaneously using a CLEAR ALL NONVOLATILE PROTECTION BITS (80/30h) command. No specific block address is required. If the nonvolatile protection bit lock bit is set to 0, the command fails. CCMTD-1725822587-2335 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Protection Operations Figure 10: Program/Erase Nonvolatile Protection Bit Algorithm Start ENTER NONVOLATILE PROTECTION command set PROGRAM NONVOLATILE PROTECTION BIT Addr = BAd Read byte twice Addr = BAd No DQ6 = Toggle Yes No DQ5 = 1 Wait 500µs Yes Read byte twice Addr = BAd No Read byte twice DQ6 = Toggle Addr = BAd Yes DQ0 = No 1 (erase) 0 (program) Yes Fail Reset Pass EXIT PROTECTION command set CCMTD-1725822587-2335 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Protection Operations NONVOLATILE PROTECTION BIT LOCK BIT Commands After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h) command has been issued, the commands that allow the nonvolatile protection bit lock bit to be set can be issued to the device. The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection bits and preventing them from being modified. The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to read the status of the nonvolatile protection bit lock bit. VOLATILE PROTECTION Commands After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been issued, commands related to the volatile protection mode can be issued to the device. The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a vola- tile protection bit to 0 for a given block. If the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (See the Block Protection Status table.) The status of a volatile protection bit for a given block can be read by issuing a READ VOLATILE PROTECTION BIT STATUS command along with the block address. The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1) the volatile protection bit for a given block. If the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (See the Block Protection Status table.) EXTENDED MEMORY BLOCK Commands The device has one extra 128-word extended memory block that can be accessed only by the ENTER EXTENDED MEMORY BLOCK (88h) command. The extended memory block is 128 words (x16) or 256 bytes (x8). It is used as a security block to provide a per- manent 128-bit security identification number or to store additional information. The device can be shipped with the extended memory block prelocked permanently by Mi- cron, including the 128-bit security identification number. Or, the device can be ship- ped with the extended memory block unlocked, enabling customers to permanently program and lock it. (See Lock Register, the AUTO SELECT command, and the Block Protection table.) Table 13: Extended Memory Block Address and Data Address Data x8 x16 Micron-Prelocked Customer-Lockable 000000h–0000FFh 000000h–00007Fh Secure ID number Determined by customer After the ENTER EXTENDED MEMORY BLOCK command has been issued, the device enters the extended memory block mode. All bus READ or PROGRAM operations are conducted on the extended memory block, and the extended memory block is ad- dressed using the addresses occupied by block 0 in the other operating modes. (See the Memory Map table.) CCMTD-1725822587-2335 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Protection Operations In extended memory block mode, ERASE, CHIP ERASE, ERASE SUSPEND, and ERASE RESUME commands are not allowed. The extended memory block cannot be erased, and each bit of the extended memory block can only be programmed once. The extended memory block is protected from further modification by programming lock register bit 0. Once invoked, this protection cannot be undone. The device remains in extended memory block mode until the EXIT EXTENDED MEM- ORY BLOCK (90/00h) command is issued, which returns the device to read mode, or until power is removed from the device. After a power-up sequence or hardware reset, the device will revert to reading memory blocks in the main array. EXIT PROTECTION Command The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock register, password protection, nonvolatile protection, volatile protection, and nonvola- tile protection bit lock bit command set modes and return the device to read mode. CCMTD-1725822587-2335 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Device Protection Device Protection Hardware Protection The V /WP# function provides a hardware method of protecting the highest or lowest PP block. When V /WP# is LOW, PROGRAM and ERASE operations on either of these PP blocks is ignored to provide protection. When V /WP# is HIGH, the device reverts to PP the previous protection status for the highest or lowest block. PROGRAM and ERASE operations can modify the data in this block unless the block is protected using block protection. When V /WP# protect is raised to V , the device automatically enters the unlock by- PP PPH pass mode, and command execution time is faster. This must never be done from any mode except read mode; otherwise, the device might be left in an indeterminate state. A 0.1μF capacitor should be connected between V /WP# and the V ground pin to de- PP SS couple the current surges from the power supply. The PCB track widths must be suffi- cient to carry the currents required during unlock bypass program. When V /WP# returns to HIGH or LOW, normal operation resumes. When operations PP execute in unlock bypass mode, the device draws I from the pin to supply the pro- PP gramming circuits. Transitions from HIGH to V and from V to LOW must be slow- PPH PPH er than tVHVPP. Note: Micron highly recommends driving V /WP# HIGH or LOW. If a system needs to PP float V /WP#, without a pull-up/pull-down resistor and no capacitor, then an internal PP pull-up resistor is enabled. Table 14: V /WP# Functions PP V /WP# Settings Function PP V Highest (29WxxxGH) or lowest (29WxxxGL) block is protected. IL V Highest or lowest block is unprotected unless software protection is activated. IH V Unlock bypass mode supplies current necessary to speed up PROGRAM execution time. PPH Software Protection Software protection includes volatile, nonvolatile, and password protection as well as password access. The device is shipped with all blocks unprotected. On first use, the de- vice defaults to the nonvolatile protection mode but can be activated in either the non- volatile protection or password protection mode. The desired protection mode is activated by setting either the nonvolatile protection mode lock bit or the password protection mode lock bit of the lock register. (See the Lock Register section.) Both bits are one-time-programmable and nonvolatile; there- fore, after the protection mode has been activated, it cannot be changed, and the device is set permanently to operate in the selected protection mode. It is recommended that the desired software protection mode be activated when first programming the device. For the lowest and highest blocks, a higher level of block protection can be achieved by locking the blocks using nonvolatile protection mode and holding V /WP# LOW. PP CCMTD-1725822587-2335 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Device Protection Blocks with volatile protection and nonvolatile protection can coexist within the memo- ry array. If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. The block protection status can be read by performing a read electronic signature or by issuing an AUTO SELECT command. (See the Block Protection table.) Refer to the Block Protection Status table and the Software Protection Scheme figure for details on the block protection scheme. Refer to the Protection Operations section for a description of the command sets. Volatile Protection Mode Volatile protection enables the software application to protect blocks against inadver- tent change and can be disabled when changes are needed. Volatile protection bits are unique for each block and can be individually modified. Volatile protection bits control the protection scheme only for unprotected blocks whose nonvolatile protection bits are cleared to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT or CLEAR VOLATILE PROTECTION BIT command sets to 0 or clears to 1 the volatile protection bits and pla- ces the associated blocks in the protected (0) or unprotected (1) state, respectively. The volatile protection bit can be set or cleared as often as needed. When the device is first shipped, or after a power-up or hardware reset, the volatile pro- tection bits default to 1 (unprotected). Nonvolatile Protection Mode A nonvolatile protection bit is assigned to each block. Each of these bits can be set for protection individually by issuing a PROGRAM NONVOLATILE PROTECTION BIT com- mand. Also, each device has one global volatile bit called the nonvolatile protection bit lock bit; it can be set to protect all nonvolatile protection bits at once. This global bit must be set to 0 only after all nonvolatile protection bits are configured to the desired settings. When set to 0, the nonvolatile protection bit lock bit prevents changes to the state of the nonvolatile protection bits. When cleared to 1, the nonvolatile protection bits can be set and cleared using the PROGRAM NONVOLATILE PROTECTION BIT and CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively. No software command unlocks the nonvolatile protection bit lock bit unless the device is in password protection mode; in nonvolatile protection mode, the nonvolatile protec- tion bit lock bit can be cleared only by taking the device through a hardware reset or power-up. Nonvolatile protection bits cannot be cleared individually; they must be cleared all at once using a CLEAR ALL NONVOLATILE PROTECTION BITS command. They will re- main set through a hardware reset or a power-down/power-up sequence. If one of the nonvolatile protection bits needs to be cleared (unprotected), additional steps are required. First, the nonvolatile protection bit lock bit must be cleared to 1, us- ing either a power-cycle or hardware reset. Then, the nonvolatile protection bits can be changed to reflect the desired settings. Finally, the nonvolatile protection bit lock bit must be set to 0 to lock the nonvolatile protection bits. The device now will operate nor- mally. To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT command should be executed early in the boot code, and the boot code should be pro- tected by holding V /WP# LOW. PP CCMTD-1725822587-2335 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Device Protection Nonvolatile protection bits and volatile protection bits have the same function when V /WP# is HIGH or when V /WP# is at the voltage for program acceleration (V ). PP PP PPH Password Protection Mode Password protection mode provides a higher level of security than the nonvolatile pro- tection mode by requiring a 64-bit password to unlock the nonvolatile protection bit lock bit. In addition to this password requirement, the nonvolatile protection bit lock bit is set to 0 after power-up and reset to maintain the device in password protection mode. Executing the UNLOCK PASSWORD command by entering the correct password clears the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to be modified. If the password provided is incorrect, the nonvolatile protection bit lock bit remains locked, and the state of the nonvolatile protection bits cannot be modified. To place the device in password protection mode, the following two steps are required: First, before activating the password protection mode, a 64-bit password must be set and the setting verified. Password verification is allowed only before the password pro- tection mode is activated. Next, password protection mode is activated by program- ming the password protection mode lock bit to 0. This operation is irreversible. After the bit is programmed, it cannot be erased, the device remains permanently in password protection mode, and the 64-bit password can be neither retrieved nor reprogrammed. In addition, all commands to the address where the password is stored are disabled. Note: There is no means to verify the password after password protection mode is ena- bled. If the password is lost after enabling the password protection mode, there is no way to clear the nonvolatile protection bit lock bit. Figure 11: Software Protection Scheme Volatile protection bit Nonvolatile protection bit 1 = unprotected 1 = unprotected (default) 0 = protected 0 = protected (Default setting depends on the product order option) Volatile Nonvolatile protection protection Array block Nonvolatile protection bit lock bit (volatile) 1 = unlocked (default, after power-up or hardware reset) 0 = locked Nonvolatile protection Password protection mode mode Notes: 1. Volatile protection bits are programmed and cleared individually. Nonvolatile protection bits are programmed individually and cleared collectively. 2. Once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by taking the device through a power-up or hardware reset. CCMTD-1725822587-2335 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Common Flash Interface Common Flash Interface The common Flash interface (CFI) is a JEDEC-approved, standardized data structure that can be read from the Flash memory device. It allows a system's software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. The system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. When the READ CFI command is issued, the device enters CFI query mode and the data structure is read from memory. The following tables show the addresses (A-1, A[7:0]) used to retrieve the data. The query data is always presented on the lowest order data outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0. Table 15: Query Structure Overview Note 1 applies to the entire table Address x16 x8 Subsection Name Description 10h 20h CFI query identification string Command set ID and algorithm data offset 1Bh 36h System interface information Device timing and voltage information 27h 4Eh Device geometry definition Flash device layout 40h 80h Primary algorithm-specific extended query table Additional information specific to the primary al- gorithm (optional) 61h C2h Security code area 64-bit unique device number Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8] are set to 0. Table 16: CFI Query Identification String Note 1 applies to the entire table Address x16 x8 Data Description Value 10h 20h 0051h Query unique ASCII string "QRY" "Q" 11h 22h 0052h "R" 12h 24h 0059h "Y" 13h 26h 0002h Primary algorithm command set and control interface ID code 16-bit ID Spansion 14h 28h 0000h code defining a specific algorithm compatible 15h 2Ah 0040h Address for primary algorithm extended query table (see the Primary Algo- P = 40h 16h 2Ch 0000h rithm-Specific Extended Query Table) 17h 2Eh 0000h Alternate vendor command set and control interface ID code second ven- – 18h 30h 0000h dor-specified algorithm supported 19h 32h 0000h Address for alternate algorithm extended query table – 1Ah 34h 0000h Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8] are set to 0. CCMTD-1725822587-2335 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Common Flash Interface Table 17: CFI Query System Interface Information Note 1 applies to the entire table Address x16 x8 Data Description Value 1Bh 36h 0027h V logic supply minimum program/erase voltage 2.7V CC Bits[7:4] BCD value in volts Bits[3:0] BCD value in 100mV 1Ch 38h 0036h V logic supply maximum program/erase voltage 3.6V CC Bits[7:4] BCD value in volts Bits[3:0] BCD value in 100mV 1Dh 3Ah 00B5h V (programming) supply minimum program/erase voltage 11.5V PPH Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 1Eh 3Ch 00C5h V (programming) supply maximum program/erase voltage 12.5V PPH Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 1Fh 3Eh 0004h Typical timeout for single byte/word program = 2nμs 16µs 20h 40h 0004h Typical timeout for maximum size buffer program = 2nμs 16µs 21h 42h 0009h Typical timeout per individual block erase = 2nms 0.5s 22h 44h 0010h Typical timeout for full chip erase = 2nms 40s 23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 200µs 24h 48h 0004h Maximum timeout for buffer program = 2n times typical 200µs 25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 2.3s 26h 4Ch 0004h Maximum timeout for chip erase = 2n times typical 400s Note: 1. The values in this table are valid for both packages. Table 18: Device Geometry Definition Address x16 x8 Data Description Value 27h 4Eh 0018h Device size = 2n in number of bytes 16MB 28h 50h 0002h Flash device interface code description x8, x16 29h 52h 0000h asynchronous 2Ah 54h 0006h Maximum number of bytes in multi-byte program or page = 64B 2Bh 56h 0000h 2n 2Ch 58h 0001h Number of erase block regions. It specifies the number of 1 regions containing contiguous erase blocks of the same size. 2Dh 5Ah 007Fh Erase block region 1 information 128 block 2Eh 5Ch 0000h Number of identical-size erase blocks = 007Fh + 1 2Fh 5Eh 0000h Erase block region 1 information 128KB 30h 60h 0002h Block size in region 1 = 0200h × 256 bytes CCMTD-1725822587-2335 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Common Flash Interface Table 18: Device Geometry Definition (Continued) Address x16 x8 Data Description Value 31h 62h 0000h Erase block region 2 information 0 32h 64h 0000h 33h 66h 0000h 34h 68h 0000h 35h 6Ah 0000h Erase block region 3 information 0 36h 6Ch 0000h 37h 6Eh 0000h 38h 70h 0000h 39h 72h 0000h Erase block region 4 information 0 3Ah 74h 0000h 3Bh 76h 0000h 3Ch 78h 0000h Table 19: Primary Algorithm-Specific Extended Query Table Note 1 applies to the entire table Address x16 x8 Data Description Value 40h 80h 0050h Primary algorithm extended query table unique ASCII string “PRI” "P" 41h 82h 0052h "R" 42h 84h 0049h "I" 43h 86h 0031h Major version number, ASCII "1" 44h 88h 0033h Minor version number, ASCII "3" 45h 8Ah 000Dh Address sensitive unlock (bits[1:0]): Yes 00 = Required 90nm 01 = Not required Silicon revision number (bits[7:2]) 46h 8Ch 0002h Erase suspend: 2 00 = Not supported 01 = Read only 02 = Read and write 47h 8Eh 0001h Block protection: 1 00 = Not supported x = Number of blocks per group 48h 90h 0000h Temporary block unprotect: 00 00 = Not supported 01 = Supported 49h 92h 0008h Block protect/unprotect: 06 06 = M29W128GH/M29W128GL 4Ah 94h 0000h Simultaneous operations: – Not supported CCMTD-1725822587-2335 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Common Flash Interface Table 19: Primary Algorithm-Specific Extended Query Table (Continued) Note 1 applies to the entire table Address x16 x8 Data Description Value 4Bh 96h 0000h Burst mode: 00 00 = Not supported 01 = Supported 4Ch 98h 0002h Page mode: 02 00 = Not supported 02 = 8-word page 4Dh 9Ah 00B5h V supply minimum program/erase voltage: 11.5V PPH Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 4Eh 9Ch 00C5h V supply maximum program/erase voltage: 12.5V PPH Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 4Fh 9Eh 00xxh Top/bottom boot block flag: Uniform + xx = 04h: M29W128GL, first block protected by V /WP# V /WP# protect- PP PP xx = 05h: M29W128GH, last block protected by V /WP# ing highest or PP lowest block 50h A0h 0001h Program suspend: 01 00 = Not supported 01 = Supported Note: 1. The values in this table are valid for both packages. Table 20: Security Code Area Address x16 x8 Data Description 61h C3h, C2h XXXX 64-bit unique device number 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX CCMTD-1725822587-2335 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Power-Up and Reset Characteristics Power-Up and Reset Characteristics Table 21: Power-Up Wait Timing Specifications 70ns or 60ns1 80ns Parameter Symbol Min Min Unit Notes V HIGH to CE# LOW tVCHEL 55 µs 2 CC V HIGH to CE# LOW tVCQHEL 55 µs 2 CCQ V HIGH to WE# LOW tVCHWL 500 µs CC V HIGH to WE# LOW tVCQHWL 500 µs CCQ Notes: 1. Only available upon customer request. 2. V and V ramps must be synchronized during power-up. CC CCQ Figure 12: Power-Up Timing tVCHEL V CC V CCQ tVCQHEL CE# WE# tVCHWL tVCQHWL CCMTD-1725822587-2335 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Power-Up and Reset Characteristics Table 22: Reset AC Characteristics Symbol 60ns1, 70ns, 80ns Condition/Parameter Legacy JEDEC Min Max Unit Notes RST# LOW to read mode during program or tREADY tPLRH – 50 µs 2 erase RST# pulse width tRP tPLPH 10 – µs RST# HIGH to WE# LOW, CE# LOW, OE# LOW tRH tPHEL, 50 – ns 2 tPHGL, tPHWL RST# LOW to standby mode during read mode tRPD – 10 – µs RST# LOW to standby mode during program or 50 – µs erase RB# HIGH to WE# LOW, CE# LOW, OE# LOW tRB tRHEL, 0 – ns 2 tRHGL, tRHWL Notes: 1. Only available upon customer request. 2. Sampled only; not 100% tested. Figure 13: Reset AC Timing – No PROGRAM/ERASE Operation in Progress RY/BY# CE#, OE#, WE# tRH RST# tRP CCMTD-1725822587-2335 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Power-Up and Reset Characteristics Figure 14: Reset AC Timing During PROGRAM/ERASE Operation tREADY RY/BY# tRB CE#, OE#, WE# tRH RST# tRP CCMTD-1725822587-2335 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Absolute Ratings and Operating Conditions Absolute Ratings and Operating Conditions Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. Exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. Table 23: Absolute Maximum/Minimum Ratings Parameter Symbol Min Max Unit Notes Temperature under bias T –50 125 °C BIAS Storage temperature T –65 150 °C STG Input/output voltage V –0.6 V + 0.6 V 1, 2 IO CC Supply voltage V –0.6 4 V CC Input/output supply voltage V –0.6 4 V CCQ Identification voltage V –0.6 13.5 V ID Program voltage V –0.6 13.5 V 3 PPH Notes: 1. Minimum voltage may undershoot to −2V during transition and for less than 20ns dur- ing transitions. 2. Maximum voltage may overshoot to V + 2V during transition and for less than 20ns CC during transitions. 3. V must not remain at 12V for more than a total of 80 hours. PPH Table 24: Operating and AC Measurment Conditions 70ns or 60ns1 80ns Parameter Symbol Min Max Min Max Unit Supply voltage V 2.7 3.6 2.7 3.6 V CC Input/output supply voltage V 2.7 3.6 1.65 3.6 V CCQ Ambient operating temperature (range 1) T 0 70 0 70 °C A1 Ambient operating temperature (range 3) T –40 125 –40 125 °C A3 Ambient operating temperature (range 6) T –40 85 –40 85 °C A6 Load capacitance C 30 30 pF L Input rise and fall times – – 10 – 10 ns Input pulse voltages – 0 to V 0 to V V CCQ CCQ Input/output timing reference voltages – V /2 V /2 V CCQ CCQ Note: 1. Only available upon customer request. CCMTD-1725822587-2335 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Absolute Ratings and Operating Conditions Figure 15: AC Measurement Load Circuit V CCQ V V PP CC 25kΩ Device under test CL 0.1µF 25kΩ 0.1µF Note: 1. CL includes jig capacitance. Figure 16: AC Measurement I/O Waveform V CCQ V /2 CCQ 0V Table 25: Input/Output Capacitance Sampled only, not 100% tested. Parameter Symbol Test Condition Min Max Unit Input capacitance C V = 0V – 6 pF IN IN Output capacitance C V = 0V – 12 pF OUT OUT CCMTD-1725822587-2335 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash DC Characteristics DC Characteristics Table 26: DC Current Characteristics Parameter Symbol Conditions Min Typ Max Unit Notes Input leakage current I 0V ≤ V ≤ V – – ±1 µA 1 LI IN CC Output leakage current I 0V ≤ V ≤ V – – ±1 µA LO OUT CC V read Random read I CE# = V , OE# = V , – – 10 mA CC CC1 IL IH current f = 6 MHz Page read CE# = V , OE# = V , – – 15 mA IL IH f = 10 MHz V standby Grade 6 I CE# = V ±0.2V – – 100 µA 2 CC CC2 CCQ current Grade 3 – – 200 µA 2 V program/erase current I Program/ V /WP# = V – – 20 mA 3 CC CC3 PP IL erase or V IH controller V /WP# = – – 20 mA PP active V PPH V program Read or standby I V /WP# ≤ V – 1 5 µA PP PP1 PP CC current (pro- Standby gram) Reset I RST# = V ±0.2V – 1 5 µA PP2 SS PROGRAM opera- I V /WP# = 12V ±5% – 1 10 mA PP3 PP tion V /WP# = V – 1 5 µA PP CC ongoing V program ERASE operation I V /WP# = 12V ±5% – 3 10 mA PP PP4 PP current (erase) ongoing V /WP# = V – 1 5 µA PP CC Notes: 1. The maximum input leakage current is ±5µA on the VPP/WP# pin. 2. When the bus is inactive for tAVQV +30ns or more, the memory enters automatic stand- by. 3. Sampled only; not 100% tested. CCMTD-1725822587-2335 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash DC Characteristics Table 27: DC Voltage Characteristics Parameter Symbol Conditions Min Typ Max Unit Notes Input LOW voltage V V ≥ 2.7V –0.5 – 0.3V V IL CC CCQ Input HIGH voltage V V ≥ 2.7V 0.7V – V + 0.4 V IH CC CCQ CCQ Output LOW voltage V I = 100µA, – – 0.15V V OL OL CCQ V = V , CC CC,min V = V CCQ CCQ,min Output HIGH voltage V I = 100µA, 0.85V – – V OH OH CCQ V = V , CC CC,min V = V CCQ CCQ,min Identification voltage V – 11.5 – 12.5 V ID Voltage for V /WP# program V – 11.4 – 12.6 V PP PPH acceleration Program/erase lockout supply V – 1.8 – 2.5 V 1 LKO voltage Note: 1. Sampled only; not 100% tested. CCMTD-1725822587-2335 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Read AC Characteristics Read AC Characteristics Table 28: Read AC Characteristics Symbol 80ns 60ns 1 70ns V = 1.65V CCQ V = V V = V to V CCQ CC CCQ CC CC Parameter Legacy JEDEC Condition Min Max Min Max Min Max Unit Notes Address valid to next ad- tRC tAVAV CE# = V , 60 – 70 – 80 – ns IL dress valid OE# = V IL Address valid to output val- tACC tAVQV CE# = V , – 60 – 70 – 80 ns IL id OE# = V IL Address valid to output val- tPAGE tAVQV1 CE# = V , – 25 – 25 – 30 ns IL id (page) OE# = V IL CE# LOW to output transi- tLZ tELQX OE# = V 0 – 0 – 0 – ns 2 IL tion CE# LOW to output valid tE tELQV OE# = V – 60 – 70 – 80 ns IL OE# LOW to output transi- tOLZ tGLQX CE# = V 0 – 0 – 0 – ns 2 IL tion OE# LOW to output valid tOE tGLQV CE# = V – 25 – 25 – 30 ns IL CE# HIGH to output High-Z tHZ tEHQZ OE# = V – 20 – 20 – 30 ns 2 IL OE# HIGH to output High-Z tDF tGHQZ CE# = V – 20 – 20 – 20 ns 2 IL CE#, OE#, or address transi- tOH tEHQX, – 0 – 0 – 0 – ns tion to output transition tGHQX, tAXQX CE# to BYTE# LOW tELFL tELBL – – 5 – 5 – 5 ns CE# to BYTE# HIGH tELFH tELBH – – 5 – 5 – 5 ns BYTE# LOW to output HIgh- tFLQZ tBLQZ – – 25 – 25 – 25 ns Z BYTE# HIGH to output valid tFHQV tBHQV – – 30 – 30 – 30 ns Notes: 1. Only available upon customer request. 2. Sampled only; not 100% tested. CCMTD-1725822587-2335 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Read AC Characteristics Figure 17: Random Read AC Timing (8-Bit Mode) A[22:0]/A-1 Valid Valid tACC tOH CE# tHZ tOE OE# tE tDF DQ[15A-1, 14:0] High-Z Note: 1. BYTE# = VIL Figure 18: Random Read AC Timing (16-Bit Mode) A[22:0] Valid Valid tACC tOH CE# tHZ tOE OE# tE tDF DQ[7:0] High-Z Note: 1. BYTE# = VIH CCMTD-1725822587-2335 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Read AC Characteristics Figure 19: BYTE Transition AC Timing A[MAX:0] Valid A–1 Valid tACC tOH BYTE# tFHQV DQ[7:0] Data out tBLQX DQ[15:8] High-Z Data out tFLQZ Note: 1. CE# and OE# = VIL Figure 20: Page Read AC Timing (16-Bit Mode) A[22:3] Valid A[2:0] Valid Valid Valid Valid Valid Valid Valid tACC CE# tE tOH tHZ OE# tOE tPAGE tOH tDF DQ[15:0] DQ[15A-1] Valid Valid Valid Valid Valid Valid Valid CCMTD-1725822587-2335 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Write AC Characteristics Table 29: WE#-Controlled Write AC Characteristics 80ns 60ns 1 70ns V = 1.65V CCQ Parameter Symbol V = V V = V to V Unit Notes CCQ CC CCQ CC CC Legacy JEDEC Min Max Min Max Min Max Address valid to next address tWC tAVAV 65 – 70 – 80 – ns valid CE# LOW to WE# LOW tCS tELWL 0 – 0 – 0 – ns WE# LOW to WE# HIGH tWP tWLWH 35 – 35 – 35 – ns Input valid to WE# HIGH tDS tDVWH 45 – 45 – 45 – ns 2 WE# HIGH to input transition tDH tWHDX 0 – 0 – 0 – ns WE# HIGH to CE# HIGH tCH tWHEH 0 – 0 – 0 – ns WE# HIGH to WE# LOW tWPH tWHWL 30 – 30 – 30 – ns Address valid to WE# LOW tAS tAVWL 0 – 0 – 0 – ns WE# LOW to address transi- tAH tWLAX 45 – 45 – 45 – ns tion OE# HIGH to WE# LOW – tGHWL 0 – 0 – 0 – ns WE# HIGH to OE# LOW tOEH tWHGL 0 – 0 – 0 – ns Program/erase valid to tBUSY tWHRL – 30 – 30 – 30 ns 2 RY/BY# LOW V HIGH to CE# LOW tVCS tVCHEL 50 – 50 – 50 – µs CC Notes: 1. Only available upon customer request. 2. Sampled only; not 100% tested. CCMTD-1725822587-2335 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 21: WE#-Controlled Program AC Timing (8-Bit Mode) 3rd cycle 4th cycle Data polling READ cycle tWC tWC A[22:0]/A-1 AAAh PA PA tAS tAH tCS tCH tE CE# tGHWL tOE OE# tWP tWPH WE# tWHWH1 tDF tOH tDS DQ[7:0] AOh PD DQ7# D D OUT OUT tDH Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO- GRAM command is followed by checking of the status register data polling bit and by a READ operation that outputs the data (D ) programmed by the previous PROGRAM OUT command. 2. PA is the address of the memory location to be programmed. PD is the data to be pro- grammed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]). 4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. CCMTD-1725822587-2335 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 22: WE#-Controlled Program AC Timing (16-Bit Mode) 3rd cycle 4th cycle Data polling READ cycle tWC tWC A[22:0] 555h PA PA tAS tAH tCS tCH tE CE# tGHWL tOE OE# tWP tWPH WE# tWHWH1 tDF tOH tDS DQ[14:0] AOh PD DQ7# D D DQ[15]-A1 OUT OUT tDH Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO- GRAM command is followed by checking of the status register data polling bit and by a READ operation that outputs the data (D ) programmed by the previous PROGRAM OUT command. 2. PA is the address of the memory location to be programmed. PD is the data to be pro- grammed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]). 4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. CCMTD-1725822587-2335 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Table 30: CE#-Controlled Write AC Characteristics 80ns 60ns1 70ns V = 1.65V to CCQ Symbol V = V V = V V CCQ CC CCQ CC CC Parameter Legacy JEDEC Min Max Min Max Min Max Unit Address valid to next address valid tWC tAVAV 65 – 70 – 80 – ns WE# LOW to CE# LOW tWS tWLEL 0 – 0 – 0 – ns CE# LOW to CE# HIGH tCP tELEH 35 – 35 – 35 – ns Input valid to CE# HIGH tDS tDVEH 45 – 45 – 45 – ns CE# HIGH to input transition tDH tEHDX 0 – 0 – 0 – ns CE# HIGH to WE# HIGH tWH tEHWH 0 – 0 – 0 – ns CE# HIGH to CE# LOW tCPH tEHEL 30 – 30 – 30 – ns Address valid to CE# LOW tAS tAVEL 0 – 0 – 0 – ns CE# LOW to address transition tAH tELAX 45 – 45 – 45 – ns OE# HIGH to CE# LOW – tGHEL 0 – 0 – 0 – ns Note: 1. Only available upon customer request. CCMTD-1725822587-2335 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 23: CE#-Controlled Program AC Timing (8-Bit Mode) 3rd cycle 4th cycle Data polling tWC A[22:0]/A-1 AAAh PA PA tAS tAH tWS tWH WE# tGHEL OE# tCP tCPH CE# tWHWH1 tDS DQ[7:0] AOh PD DQ7# D OUT tDH Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO- GRAM command is followed by checking of the status register data polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be pro- grammed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]). 4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. CCMTD-1725822587-2335 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 24: CE#-Controlled Program AC Timing (16-Bit Mode) 3rd cycle 4th cycle Data polling tWC A[22:0] 555h PA PA tAS tAH tWS tWH WE# tGHEL OE# tCP tCPH CE# tWHWH1 tDS DQ[14:0]/A-1 AOh PD DQ7# D OUT tDH Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO- GRAM command is followed by checking of the status register data polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be pro- grammed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]). 4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. CCMTD-1725822587-2335 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Write AC Characteristics Figure 25: Chip/Block Erase AC Timing (8-Bit Mode) tWC A[22:0]/A-1 AAAh AAAh 555h AAAh AAAh 555h BAh1 tAS tAH tCS tCH CE# tGHWL OE# tWP tWPH WE# tDS DQ[7:0] AAh 55h 80h AAh 55h 10h/ 30h tDH Notes: 1. For a CHIP ERASE command, addresses and data are AAAh and 10h, respectively, while they are BAd and 30h for a BLOCK ERASE command. 2. BAd is the block address. 3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. CCMTD-1725822587-2335 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Accelerated Program, Data Polling/Toggle AC Characteristics Accelerated Program, Data Polling/Toggle AC Characteristics Table 31: Accelerated Program and Data Polling/Data Toggle AC Characteristics 60ns1, 70ns, Symbol 80ns Parameter Legacy JEDEC Min Max Unit V /WP# rising or falling time – tVHVPP 250 – ns PP Address setup time to OE# LOW during toggle bit poll- tASO tAXGL 10 – ns ing Address hold time from OE# during toggle bit polling tAHT tGHAX, tEHAX 10 – ns CE# HIGH during toggle bit polling tEPH tEHEL2 10 – ns Output hold time during data and toggle bit polling tOEH tWHGL2, tGHGL2 20 – ns Program/erase valid to RY/BY# LOW tBUSY tWHRL – 30 ns Note: 1. Only available upon customer request. Figure 26: Accelerated Program AC Timing V PPH V /WP# PP V or V IL IH tVHVPP tVHVPP CCMTD-1725822587-2335 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Accelerated Program, Data Polling/Toggle AC Characteristics Figure 27: Data Polling AC Timing tCH tE tHZ/tDF CE# tOE OE# tOEH WE# tWHWH1/tWHWH2 DQ7 DQ7 Data DQ7# High-Z Valid data DQ[6:0] DQ[6:0] DQ[6:0] Data High-Z Output flag Valid data tBUSY RY/BY# Notes: 1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed. 2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro- gram and Data Polling/Data Toggle AC Characteristics. Figure 28: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) A[22:0]/A-1 tAHT tASO CE# tOEH tAHT tAS WE# tOEH tEPH tOEH OE# tDH tOE tE DQ6/DQ2 Data Toggle Toggle Toggle Stop Output toggling valid tBUSY RY/BY# Notes: 1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops toggling when the CHIP ERASE or BLOCK ERASE command has completed. 2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro- gram and Data Polling/Data Toggle AC Characteristics. CCMTD-1725822587-2335 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Program/Erase Characteristics Program/Erase Characteristics Table 32: Program/Erase Characteristics Notes 1 and 2 apply to the entire table Parameter Min Typ Max Unit Notes Chip erase – 40 400 s 3 Block erase (128KB) – 0.5 2 s 4 Erase suspend latency time – 25 45 µs Block erase timeout 50 – – µs Byte program Single-byte program – 16 200 µs 3 Write to buffer program V /WP# = V – 51 200 µs 3 PP PPH (64 bytes at a time) V /WP# = V – 78 200 µs 3 PP IH Word program Single-word program – 16 200 µs 3 Write to buffer program V /WP# = V – 51 200 µs 3 PP PPH (32 words at a time) V /WP# = V – 78 200 µs 3 PP IH Chip program (byte by byte) – 270 800 s 3 Chip program (word by word) – 135 400 s 3 Chip program (write to buffer program) – 20 200 s 3, 5 Chip program (write to buffer program with V /WP# = V ) – 13 50 s 3, 5 PP PPH Chip program (enhanced buffered program) – 8 40 s 5 Chip program (enhanced buffered program with V /WP# = V ) – 5 25 s 5 PP PPH Program suspend latency time – 5 15 µs PROGRAM/ERASE cycles (per block) 100,000 – – cycles Data retention 20 – – years Notes: 1. Typical values measured at room temperature and nominal voltages and for not cycled devices. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and V after CC 100,000 PROGRAM/ERASE cycles. 4. Block erase polling cycle time (see Data polling AC waveforms figure). 5. Intrinsic program timing, that means without the time required to execute the bus cy- cles to load the PROGRAM commands. CCMTD-1725822587-2335 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Package Dimensions Package Dimensions Figure 29: 56-Pin TSOP – 14mm x 20mm 1.1 ±0.1 Pin A1 ID 1 56 0.5 TYP 14 ±0.1 56X 0.22 ±0.05 28 29 18.4 ±0.1 56X 0.1 ±0.05 20 ±0.2 Plating material composition: Ni/Pd/Au. Plastic package material: epoxy novolac. 0.1 A Package width and length include mold flash. 0.15 ±0.05 See Detail A 0.25 gage plane Seating plane (0.1 ±0.05) A 0.6 ±0.1 Detail A Notes: 1. All dimensions are in millimeters. 2. For the lead width value of 0.22 ±0.05, there is also a legacy value of 0.15 ±0.05. CCMTD-1725822587-2335 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Package Dimensions Figure 30: 64-Ball TBGA – 10mm x 13mm 10.00 ±0.10 1.50 TYP 7.00 TYP 3.00 TYP 0.50 TYP 7.00 TYP 0.50 TYP 13.00 ±0.10 0.10 MAX BALL "A1" 0.35 MIN/ 1.00 TYP 0.50 MAX 0.80 TYP -0.10 1.20 MAX 0.30 +0.05 Note: 1. All dimensions are in millimeters. CCMTD-1725822587-2335 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Package Dimensions Figure 31: 64-Ball FBGA – 11mm x 13mm 0.80 TYP Seating plane 0.10 64X Ball A1 ID 8 7 6 5 4 3 2 1 3.00 TYP A B C 13.00 ±0.10 D 7.00 TYP E F G H 1.00 TYP 0.60 ±0.05 1.00 1.40 MAX TYP 2.00 TYP 0.48 ±0.05 7.00 TYP 11.00 ±0.10 Note: 1. All dimensions are in millimeters. CCMTD-1725822587-2335 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.

128Mb 3V Embedded Parallel NOR Flash Revision History Revision History Rev. C – 05/18 • Added Important Notes and Warnings section for further clarification aligning to in- dustry standards Rev. B – 05/15 • Updated TSOP package Rev. A – 07/13 • Initial Micron brand release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. CCMTD-1725822587-2335 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. m29w_128mb.pdf - Rev. C 5/18 EN © 2012 Micron Technology, Inc. All rights reserved.