M28W640HCT M28W640HCB 64 Mbit (4 Mb x 16, boot block) 3 V supply Flash memory Features (cid:132) Supply voltage – V = 2.7V to 3.6V DD FBGA – V = 12V for fast program (optional) PP (cid:132) Access times: 70ns (cid:132) Asynchronous Page Read mode TFBGA48 (ZB) – Page width: 4words 6.39 x 10.5 mm – Page access: 25 ns – Random access: 70ns (cid:132) Programming time: – 10μs typical – Double Word Programming option – Quadruple Word Programming option (cid:132) Common Flash interface TSOP48 (N) 12 x 20 mm (cid:132) Memory blocks – Parameter blocks (top or bottom location) – Main blocks (cid:132) Packages (cid:132) Block locking – RoHS compliant – All blocks locked at power-up – Any combination of blocks can be locked – WP for block lock-down (cid:132) Security – 128 bit user programmable OTP cells – 64 bit unique device identifier (cid:132) Automatic standby mode (cid:132) Program and Erase Suspend (cid:132) 100,000 program/erase cycles per block (cid:132) Electronic signature – Manufacturer code: 20h – Top device code, M28W640HCT: 8848h – Bottom device code, M28W640HCB: 8849h November 2008 Rev 3 1/72 www.numonyx.com 1

Contents M28W640HCT, M28W640HCB Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DD 2.9 V program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PP 2.10 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SS 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.9 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/72

M28W640HCT, M28W640HCB Contents 4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.12 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.15 Block Lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Program/Erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Erase Suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 Erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4 Program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.5 V status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PP 6.6 Program Suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 Block Protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8 Reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3/72

Contents M28W640HCT, M28W640HCB Appendix C Flowcharts and pseudocodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Appendix D Command interface and Program/Erase controller state . . . . . . . 67 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4/72

M28W640HCT, M28W640HCB List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. Read electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Read block lock signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Program, Erase times and Program/Erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Block Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Protection status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. Read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 18. Write AC characteristics, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 19. Power-up and Reset AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 20. TSOP48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data. . . . . 42 Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, package mechanical data . . 43 Table 22. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 23. Top boot block addresses, M28W640HCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 24. Bottom boot block addresses, M28W640HCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 26. CFI query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 27. CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 28. Device geometry definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 29. Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 30. Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 31. Write state machine current/next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 32. Write state machine current/next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 33. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5/72

List of figures M28W640HCT, M28W640HCB List of figures Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. TFBGA connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Protection register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. AC measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 7. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 9. Page Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 10. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 11. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. Power-up and Reset AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 13. TSOP48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . . . . . 42 Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, bottom view package outline43 Figure 15. Program flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 16. Double Word Program flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 17. Quadruple Word Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 18. Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 19. Erase flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 20. Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 21. Locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 22. Protection Register Program flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . 66 6/72

M28W640HCT, M28W640HCB Description 1 Description The M28W640HCT and M28W640HCB are 64 Mbit (4 Mbit x 16) non-volatile Flash memories that can be erased electrically at block level and programmed in-system on a word-by-word basis using a 2.7V to 3.6V V supply. An optional 12V V power supply is DD PP provided to speed up customer programming. The devices feature an asymmetrical blocked architecture. They have an array of 135 blocks: 8 parameter blocks of 4 Kwords and 127 main blocks of 32 Kwords. The M28W640HCT has the parameter blocks at the top of the memory address space while the M28W640HCB locates the parameter blocks starting from the bottom. The memory maps are shown in Figure4: Block addresses. The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked- down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V ≤ V all blocks are protected PP PPLK against program or erase. All blocks are locked at power-up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 192-bit protection register to increase the protection of a system design. The protection register is divided into a 64-bit segment and a 128-bit segment. The 64-bit segment contains a unique device number written by Numonyx, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. Figure5, shows the protection register memory map. Program and Erase commands are written to the command interface of the memory. An on- chip Program/Erase controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (12×20mm) and TFBGA48 (6.39×10.5mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’). 7/72

Description M28W640HCT, M28W640HCB Figure 1. Logic diagram VDD VPP 22 16 A0-A21 DQ0-DQ15 W E M28W640HCT M28W640HCB G RP WP VSS AI09903b T able 1. Signal names Name Description Direction A0-A21 Address inputs Inputs DQ0-DQ15 Data input/output I/O E Chip Enable Input G Output Enable Input W Write Enable Input RP Reset Input WP Write Protect Input V Power supply Power supply DD V Optional supply voltage for fast program & erase Power supply PP V Ground Power supply SS NC Not connected internally – 8/72

M28W640HCT, M28W640HCB Description Figure 2. TSOP connections A15 1 48 A16 A14 VDD A13 VSS A12 DQ15 A11 DQ7 A10 DQ14 A9 DQ6 A8 DQ13 A21 DQ5 A20 DQ12 W DQ4 RP 12 M28W640HCT 37 VDD VPP 13 M28W640HCB 36 DQ11 WP DQ3 A19 DQ10 A18 DQ2 A17 DQ9 A7 DQ1 A6 DQ8 A5 DQ0 A4 G A3 VSS A2 E A1 24 25 A0 AI09904c 1. All V pins must be connected to the power supply. DD 2. All V pins must be connected to the ground. SS 9/72

Description M28W640HCT, M28W640HCB Figure 3. TFBGA connections (top view through package) 1 2 3 4 5 6 7 8 A A13 A11 A8 VPP WP A19 A7 A4 B A14 A10 W RP A18 A17 A5 A2 C A15 A12 A9 A21 A20 A6 A3 A1 D A16 DQ14 DQ5 DQ11 DQ2 DQ8 E A0 E VDD DQ15 DQ6 DQ12 DQ3 DQ9 DQ0 VSS F VSS DQ7 DQ13 DQ4 VDD DQ10 DQ1 G AI04380c 1. All V pins must be connected to the power supply. DD 2. All V pins must be connected to the ground. SS 10/72

M28W640HCT, M28W640HCB Description Figure 4. Block addresses M28W640HCT M28W640HCB Top boot block addresses Bottom boot block addresses 3FFFFF 3FFFFF 4 Kwords 32 Kwords 3FF000 3F8000 3F7FFF 32 Kwords Total of 8 4 Kword blocks 3F0000 Total of 127 3F8FFF 32 Kword blocks 4 Kwords 3F8000 3F7FFF 32 Kwords 3F0000 00FFFF 32 Kwords 008000 007FFF 4 Kwords Total of 127 007000 32 Kword blocks 00FFFF Total of 8 32 Kwords 4 Kword blocks 008000 007FFF 000FFF 32 Kwords 4 Kwords 000000 000000 AI09905b 1. Also see Appendix A, Tables 23 and 24 for a full listing of the block addresses. Figure 5. Protection register memory map PROTECTION REGISTER 8Ch User programmable OTP 85h 84h Unique device number 81h 80h Protection register lock 1 0 AI05520b 11/72

Signal descriptions M28W640HCT, M28W640HCB 2 Signal descriptions See Figure1: Logic diagram and Table1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A21) The Address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the internal state machine. 2.2 Data input/output (DQ0-DQ15) The Data I/O outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V andReset is at V the device is in active IL IH mode. When Chip Enable is at V the memory is deselected, the outputs are high IH impedance and the power consumption is reduced to the standby level. 2.4 Output Enable (G) The Output Enable controls data outputs during the bus read operation of the memory. 2.5 Write Enable (W) The Write Enable controls the bus write operation of the memory’s command interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. 2.6 Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V , the lock-down is enabled and the protection status of the block IL cannot be changed. When Write Protect is at V , the lock-down is disabled and the block IH can be locked or unlocked (refer to Table7: Read Protection Register and Lock Register). 12/72

M28W640HCT, M28W640HCB Signal descriptions 2.7 Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at V , the IL memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the locked state. When Reset is at V , the device is IH in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. 2.8 V supply voltage DD V provides the power supply to the internal core and the I/O pins of the memory device. It DD is the main power supply for all operations (read, program and erase). 2.9 V program supply voltage PP V is both a control input and a power supply pin. The two functions are selected by the PP voltage range applied to the pin. The supply voltage, V , and the program supply voltage, DD V , can be applied in any order. PP If V is kept in a low voltage range (0V to 3.6V) V is seen as a control input. In this case PP PP a voltage lower than V gives an absolute protection against program or erase, while PPLK V > V enables these functions (see Table15: DC characteristics, for the relevant PP PP1 values). V is only sampled at the beginning of a program or erase; a change in its value PP after the operation has started does not have any effect on program or erase, however for Double or Quadruple Word Program the results are uncertain. If V is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition V PP PP must be stable until the Program/Erase algorithm is completed (see Table17 and Table18). 2.10 V ground SS V is the reference for all voltage measurements. SS Note: Each device in a system should have V and V decoupled with a 0.1μF capacitor close DD PP to the pin. See Figure7: AC measurement load circuit. The PCB track widths should be sufficient to carry the required V program and erase currents. PP 13/72

Bus operations M28W640HCT, M28W640HCB 3 Bus operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table2: Bus operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Read Read bus operations are used to output the contents of the memory array, the Electronic Signature, the Status Register and the common Flash interface. Both Chip Enable and Output Enable must be at V in order to perform a read operation. The Chip Enable input IL should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Section4: Command interface). See Figure8: Read AC waveforms, and Table16: Read AC characteristics, for details of when the output becomes valid. Read operations of the memory array can be performed in asynchronous page mode, which provides a fast access time. Data is internally read and stored in a page buffer. The page has a size of 4words and is addressed by A0-A1 address inputs. Read operations of the electronic signature, the Status Register, the command Flash interface, the Block Protection status, the Configuration Register status and the security code are performed as asynchronous read cycles (Random Read). Both Chip Enable, E, and Output Enable, G, must be at V in order to read the output of the memory (see Figure9: Page Read AC IL waveforms). Read mode is the default state of the device when exiting reset or after power-up. 3.2 Write Bus write operations write commands to the memory or latch input data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V with Output IL Enable at V . Commands, input data and addresses are latched on the rising edge of Write IH Enable or Chip Enable, whichever occurs first. See Figure9 and Figure11, Write AC waveforms, and Table17 and Table18, Write AC characteristics, for details of the timing requirements. 3.3 Output Disable The data outputs are high impedance when the Output Enable is at V . IH 3.4 Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable is at V and the device is in IH read mode. The power consumption is reduced to the standby level and the outputs are set 14/72

M28W640HCT, M28W640HCB Bus operations to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V during a program or erase operation, the device enters Standby IH mode when finished. 3.5 Automatic Standby Automatic standby provides a low power consumption state during Read mode. Following a read operation, the device enters automatic standby after 150ns of bus inactivity even if Chip Enable is Low, V , and the supply current is reduced to I . The data inputs/outputs IL DD1 will still output data if a bus read operation is in progress. 3.6 Reset During Reset mode when Output Enable is Low, V , the memory is deselected and the IL outputs are high impedance. The memory is in Reset mode when Reset is at V . The power IL consumption is reduced to the standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V during a program or erase, this SS operation is aborted and the memory content is no longer valid. T able 2. Bus operations(1) Operation E G W RP WP V DQ0-DQ15 PP Bus Read V V V V X Don't care Data output IL IL IH IH Bus Write V V V V X V or V Data input IL IH IL IH DD PPH Output Disable V V V V X Don't care Hi-Z IL IH IH IH Standby V X X V X Don't care Hi-Z IH IH Reset X X X V X Don't care Hi-Z IL 1. X = V or V , V = 12V ± 5%. IL IH PPH 15/72

Command interface M28W640HCT, M28W640HCB 4 Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. An internal Program/Erase controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase controller provides a Status Register whose output may be read at any time to monitor the progress of the operation, or the Program/Erase states. See Table3: Command codes, for a summary of the commands and see Appendix D, Table31: Write state machine current/next, for a summary of the command interface. The command interface is reset to Read mode when power is first applied, when exiting from reset or whenever V is lower than V . Command sequences must be followed DD LKO exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table4: Commands, in conjunction with the text descriptions below. 4.1 Read Memory Array command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. 4.2 Read Status Register command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register’s contents. Subsequent bus read operations read the Status Register at any address, until another command is issued. See Table11: Status Register bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a program/erase operation. Any read attempt during a program/erase operation will automatically output the content of the Status Register. 4.3 Read Electronic Signature command The Read Electronic Signature command reads the manufacturer and device codes and the Block Locking Status, or the Protection Register. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the manufacturer code, the device code, the Block Lock and Lock-Down Status, or the Protection and Lock Register. See Tables 5, 6 and 7 for the valid address. 16/72

M28W640HCT, M28W640HCB Command interface T able 3. Command codes Hex code Command 01h Block Lock confirm 10h Program 20h Erase 2Fh Block Lock-down confirm 30h Double Word Program 40h Program 50h Clear Status Register 56h Quadruple Word Program 60h Block Lock, Block Unlock, Block Lock-down 70h Read Status Register 90h Read Electronic Signature 98h Read CFI Query B0h Program/Erase Suspend C0h Protection Register Program D0h Program/Erase Resume, Block Unlock confirm FFh Read Memory Array 4.4 Read CFI Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent bus read operations read from the common Flash interface memory area. See Appendix B: Common Flash interface (CFI), tables 25, 26, 27, 28, 29 and 30 for details on the information contained in the common Flash interface memory area. 4.5 Block Erase command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command: (cid:132) The first bus cycle sets up the Erase command (cid:132) The second latches the block address in the internal state machine and starts the Program/Erase controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. 17/72

Command interface M28W640HCT, M28W640HCB Erase aborts if Reset turns to V . As data integrity cannot be guaranteed when the erase IL operation is aborted, the block must be erased again. During erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table8: Program, Erase times and Program/Erase endurance cycles. See Appendix C, Figure19: Erase flowchart and pseudocode, for a suggested flowchart for using the Erase command. 4.6 Program command The memory array can be programmed word-by-word. Two bus write cycles are required to issue the Program command: (cid:132) The first bus cycle sets up the Program command. (cid:132) The second latches the address and the data to be written and starts the Program/Erase controller. During program operations the memory will accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table8: Program, Erase times and Program/Erase endurance cycles. Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the IL program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure15: Program flowchart and pseudocode, for the flowchart for using the Program command. 4.7 Double Word Program command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when V is not at V . PP PPH Three bus write cycles are necessary to issue the Double Word Program command: (cid:132) The first bus cycle sets up the Double Word Program command (cid:132) The second bus cycle latches the address and the data of the first word to be written (cid:132) The third bus cycle latches the address and the data of the second word to be written and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the IL program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure16: Double Word Program flowchart and pseudocode for the flowchart for using the Double Word Program command. 18/72

M28W640HCT, M28W640HCB Command interface 4.8 Quadruple Word Program command This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. Programming should not be attempted when V is not at V . PP PPH Five bus write cycles are necessary to issue the Quadruple Word Program command: (cid:132) The first bus cycle sets up the Quadruple Word Program command. (cid:132) The second bus cycle latches the address and the data of the first word to be written (cid:132) The third bus cycle latches the address and the data of the second word to be written (cid:132) The fourth bus cycle latches the address and the data of the third word to be written (cid:132) The fifth bus cycle latches the address and the data of the fourth word to be written and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the IL program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure17: Quadruple Word Program flowchart and pseudocode, for the flowchart for using the Quadruple Word Program command. 4.9 Clear Status Register command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. 4.10 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a program or erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the command interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, Block Lock-down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V . Program/Erase is aborted if Reset turns to V . IH IL See Appendix C, Figure18: Program Suspend & Resume flowchart and pseudocode, and Figure20: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Suspend command. 19/72

Command interface M28W640HCT, M28W640HCB 4.11 Program/Erase Resume command The Program/Erase Resume command can be used to restart the Program/Erase controller after a program/erase suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent bus read operations read the Status Register. See Appendix C, Figure18: Program Suspend & Resume flowchart and pseudocode, and Figure20: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Resume command. 4.12 Protection Register Program command The Protection Register Program command is used to program the 128 bit user one-time- programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protection Register Program command: (cid:132) The first bus cycle sets up the Protection Register Program command (cid:132) The second latches the address and the data to be written to the Protection Register and starts the Program/Erase controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure5: Protection register memory map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. 4.13 Block Lock command The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command: (cid:132) The first bus cycle sets up the Block Lock command (cid:132) The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table10 shows the protection status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power- down/power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation. 20/72

M28W640HCT, M28W640HCB Command interface 4.14 Block Unlock command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command: (cid:132) The first bus cycle sets up the Block Unlock command (cid:132) The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table10 shows the protection status after issuing a Block Unlock command. Refer to the Section5: Block locking, for a detailed explanation. 4.15 Block Lock-down command A locked block cannot be programmed or erased, or have its protection status changed when WP is Low, V . When WP is High, V the Lock-down function is disabled and the IL IH, locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-down command: (cid:132) The first bus cycle sets up the Block Lock command (cid:132) The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table10 shows the protection status after issuing a Block Lock-down command. Refer to the Section5: Block locking for a detailed explanation. 21/72

Command interface M28W640HCT, M28W640HCB Table 4. C ommands(1) Bus write operations s e Commands cl 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle y C Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data Read Memory 1+ Write X FFh Read RA RD Array Read Status 1+ Write X 70h Read X SRD Register Read Electronic 1+ Write X 90h Read SA(2) IDh Signature Read CFI 1+ Write X 98h Read QA QD Query Erase 2 Write X 20h Write BA D0h 40h or Program 2 Write X Write PA PD 10h Double Word 3 Write X 30h Write PA1 PD1 Write PA2 PD2 Program(3) Quadruple Word 5 Write X 56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4 Program(4) Clear Status 1 Write X 50h Register Program/Erase 1 Write X B0h Suspend Program/Erase 1 Write X D0h Resume Block Lock 2 Write X 60h Write BA 01h Block Unlock 2 Write X 60h Write BA D0h Block Lock- 2 Write X 60h Write BA 2Fh down Protection Register 2 Write X C0h Write PRA PRD Program 1. X = Don't care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (manufacturer and device code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data. 2. The signature addresses are listed in Tables 5, 6 and 7. 3. Program addresses 1 and 2 must be consecutive addresses differing only for A0. 4. Program addresses 1,2,3 and 4 must be consecutive addresses differing only for A0 and A1. 22/72

M28W640HCT, M28W640HCB Command interface T able 5. Read electronic signature(1) Code Device E G W A0 A1 A2-A7 A8-A21 DQ0-DQ7 DQ8-DQ15 Manufacturer V V V V V 0 Don't care 20h 00h code IL IL IH IL IL M28W640HCT V V V V V 0 Don't care 48h 88h IL IL IH IH IL Device code M28W640HCB V V V V V 0 Don't care 49h 88h IL IL IH IH IL 1. RP = V . IH T able 6. Read block lock signature Block status E G W A0 A1 A2-A7 A8-A11 A12-A21 DQ0 DQ1 DQ2-DQ15 Locked block V V V V V 0 Don't care Block address 1 0 00h IL IL IH IL IH Unlocked block V V V V V 0 Don't care Block address 0 0 00h IL IL IH IL IH Locked-down V V V V V 0 Don't care Block address X(1) 1 00h block IL IL IH IL IH 1. A locked-down block can be locked ‘DQ0 = 1’ or unlocked ‘DQ0 = 0’; see Section5: Block locking. Table 7. R ead Protection Register and Lock Register DQ3- DQ8- Word E G W A0-A7 A8-A21 DQ0 DQ1 DQ2 DQ7 DQ15 OTP Prot. Lock V V V 80h Don't care 0 0 00h 00h IL IL IH data Unique ID 0 V V V 81h Don't care ID data ID data ID data ID data ID data IL IL IH Unique ID 1 V V V 82h Don't care ID data ID data ID data ID data ID data IL IL IH Unique ID 2 V V V 83h Don't care ID data ID data ID data ID data ID data IL IL IH Unique ID 3 V V V 84h Don't care ID data ID data ID data ID data ID data IL IL IH OTP 0 V V V 85h Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 1 V V V 86h Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 2 V V V 87h Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 3 V V V 88h Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 4 V V V 89h Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 5 V V V 8Ah Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 6 V V V 8Bh Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH OTP 7 V V V 8Ch Don't care OTP data OTP data OTP data OTP data OTP data IL IL IH 23/72

Command interface M28W640HCT, M28W640HCB Table 8. P rogram, Erase times and Program/Erase endurance cycles M28W640HCT, M28W640HCB Parameter Test conditions Unit Min Typ Max Word Program V =V 10 200 μs PP DD Double Word Program V =12V±5% 10 200 μs PP Quadruple Word Program V =12V±5% 10 200 μs PP V =12V±5% 0.16/0.08(1) 5 s PP Main Block Program V = V 0.32 5 s PP DD V =12V±5% 0.02/0.01(1) 4 s PP Parameter Block Program V =V 0.04 4 s PP DD V =12V±5% 1 10 s PP Main Block Erase V =V 1 10 s PP DD V =12V±5% 0.4 10 s PP Parameter Block Erase V =V 0.4 10 s PP DD Program/Erase cycles (per block) 100,000 cycles 1. Typical time to program a main or parameter block using the Double Word Program and the Quadruple Word Program commands respectively. 24/72

M28W640HCT, M28W640HCB Block locking 5 Block locking The M28W640HCT and M28W640HCB feature an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection: (cid:132) Lock/unlock - this first level allows software-only control of block locking (cid:132) Lock-down - this second level requires hardware interaction before locking can be changed (cid:132) V ≤ V - the third level offers a complete hardware protection against program PP PPLK and erase on all blocks. The protection status of each block can be set to ‘Locked’, ‘Unlocked’, and ‘Lock-down’. Table10, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure21, shows a flowchart for the locking operations. 5.1 Reading a block’s lock status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-down. DQ1 indicates the Lock-down status and is set by the Lock-down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. 5.2 Locked state The default status of all blocks on power-up or after a hardware reset is ‘Locked’ (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The status of a locked block can be changed to ‘Unlocked’ or ‘Lock-down’ using the appropriate software commands. An unlocked block can be locked by issuing the Lock command. 5.3 Unlocked state Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. The status of an unlocked block can be changed to ‘Locked’ or ‘Locked-down’ using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. 25/72

Block locking M28W640HCT, M28W640HCB 5.4 Lock-down state Blocks that are Locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by issuing the Lock-down command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The Lock-down function is dependent on the WP input pin. When WP=0 (V ), the blocks in IL the Lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (V ) the Lock-down function is disabled (1,1,1) and Locked-down IH blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while WP remains High. When WP is Low, blocks that were previously Locked-down return to the Lock-down state (0,1,x) regardless of any changes made while WP was High. Device reset or power-down resets all blocks, including those in Lock-down or in a Locked state. 5.5 Locking operations during Erase Suspend Changes to block lock status can be performed during an Erase Suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the Lock Status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is Locked or Locked-down during an Erase Suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a Program Suspend. Refer to Appendix D, command interface and Program/Erase controller state, for detailed information on which commands are valid during Erase Suspend. T able 9. Block Lock status Item Address Data Block Lock configuration LOCK Block is Unlocked DQ0=0 xx002 Block is Locked DQ0=1 Block is Locked-down DQ1=1 26/72

M28W640HCT, M28W640HCB Block locking T able 10. Protection status Current Protection status(1) Next Protection status(1) (WP, DQ1, DQ0) (WP, DQ1, DQ0) After Block After Block After Block Program/Erase After WP Current state Lock Unlock Lock-down allowed transition command command command 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1(2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1(2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3) 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with A1 = V and A0 = V . IH IL 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110. IH 27/72

Status Register M28W640HCT, M28W640HCB 6 Status Register The Status Register provides information on the current or previous program or erase operation. The various bits convey information and errors on the operation. To read the Status Register the Read Status Register command can be issued, refer to Section4.2: Read Status Register command. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V . Either Chip Enable or Output Enable must be IH toggled to update the latched data. Bus read operations from any address always read the Status Register during program and erase operations. The bits in the Status Register are summarized in Table11: Status Register bits. Refer to Table11 in conjunction with the following text descriptions. 6.1 Program/Erase controller status (bit 7) The Program/Erase controller status bit indicates whether the Program/Erase controller is active or inactive. When the Program/Erase controller status bit is Low (set to ‘0’), the Program/Erase controller is active; when the bit is High (set to ‘1’), the Program/Erase controller is inactive, and the device is ready to process a new command. The Program/Erase controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase controller pauses. After the Program/Erase controller pauses the bit is High. During program, erase, operations the Program/Erase controller status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase controller completes the operation and the bit is High. After the Program/Erase controller completes its operation the Erase Status, Program Status, V Status and Block Lock Status bits should be tested for errors. PP 6.2 Erase Suspend status (bit 6) The Erase Suspend status bit indicates that an erase operation has been suspended or is going to be suspended. When the Erase Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase controller status bit is High (Program/Erase controller inactive). Bit 7 is set within 30μs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. 28/72

M28W640HCT, M28W640HCB Status Register 6.3 Erase status (bit 5) The Erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase status bit is High (set to ‘1’), the Program/Erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase controller status bit is High (Program/Erase controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 6.4 Program status (bit 4) The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Program/Erase controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase controller status bit is High (Program/Erase controller inactive). Once set High, the Program status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 6.5 V status (bit 3) PP The V status bit can be used to identify an invalid voltage on the V pin during program PP PP and erase operations. The V pin is only sampled at the beginning of a program or erase PP operation. Indeterminate results can occur if V becomes invalid during an operation. PP When the V status bit is Low (set to ‘0’), the voltage on the V pin was sampled at a valid PP PP voltage; when the V status bit is High (set to ‘1’), the V pin has a voltage that is below PP PP the V Lockout voltage, V , the memory is protected and program and erase PP PPLK operations cannot be performed. Once set High, the V status bit can only be reset Low by a Clear Status Register PP command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 6.6 Program Suspend status (bit 2) The Program Suspend status bit indicates that a program operation has been suspended. When the Program Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend status should only be considered valid when the Program/Erase controller status bit is High (Program/Erase controller inactive). Bit 2 is set within 5μs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. 29/72

Status Register M28W640HCT, M28W640HCB 6.7 Block Protection status (bit 1) The Block Protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a locked block. When the Block Protection status bit is High (set to ‘1’), a program or erase operation has been attempted on a locked block. Once set High, the Block Protection status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. 6.8 Reserved (bit 0) Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix C: Flowcharts and pseudocodes, for using the Status Register. T able 11. Status Register bits(1) Bit Name Logic level Definition '1' Ready 7 P/E.controller status '0' Busy '1' Suspended 6 Erase Suspend status '0' In progress or completed '1' Erase error 5 Erase status '0' Erase success '1' Program error 4 Program status '0' Program success '1' V invalid, abort PP 3 V status PP '0' V OK PP '1' Suspended 2 Program Suspend status '0' In progress or completed Program/Erase on protected Block, '1' abort 1 Block Protection status '0' No operation to protected blocks 0 Reserved 1. Logic level '1' is High, '0' is Low. 30/72

M28W640HCT, M28W640HCB Maximum ratings 7 Maximum ratings Stressing the device above the rating listed in Table12: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. T able 12. Absolute maximum ratings Value Symbol Parameter Unit Min Max T Ambient operating temperature – 40 85 °C A T Temperature under bias – 40 125 °C BIAS T Storage temperature – 55 155 °C STG V Input or output voltage – 0.6 V +0.6 V IO DD V Supply voltage – 0.6 4.1 V DD V Program voltage – 0.6 13 V PP 31/72

DC and AC parameters M28W640HCT, M28W640HCB 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table13: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. T able 13. Operating and AC measurement conditions M28W640HCT, M28W640HCB Parameter 70ns Units Min Max V supply voltage 2.7 3.6 V DD Ambient operating temperature –40 85 °C Load capacitance (C ) 50 pF L Input rise and fall times 5 ns Input pulse voltages 0 to V V DD Input and output timing reference voltages V /2 V DD Figure 6. AC measurement I/O waveform VDD VDD/2 0 V AI00610b Figure 7. AC measurement load circuit VDD VDD 25 kΩ DEVICE UNDER TEST CL 25 kΩ 0.1 µF CL includes JIG capacitance AI00609d 32/72

M28W640HCT, M28W640HCB DC and AC parameters T able 14. Capacitance(1) Symbol Parameter Test condition Min Max Unit C Input capacitance V = 0V 6 pF IN IN C Output capacitance V = 0V 12 pF OUT OUT 1. Sampled only, not 100% tested. 33/72

DC and AC parameters M28W640HCT, M28W640HCB Table 15. D C characteristics Symbol Parameter Test condition Min Typ Max Unit I Input Leakage current 0V≤V ≤V ±1 μA LI IN DD ILO Output Leakage current 0V≤VOUT≤VDD ±10 μA E=V , G=V , I Supply current (Read) SS IH 9 18 mA DD f=5MHz Supply current (Standby or Automatic E=V ±0.2V, I DD 15 50 μA DD1 Standby) RP=V ±0.2V DD I Supply current (Reset) RP=V ±0.2V 15 50 μA DD2 SS Program in progress 5 10 mA V =12V±5% PP I Supply current (Program) DD3 Program in progress 10 20 mA V =V PP DD Erase in progress 10 20 mA V =12V±5% PP I Supply current (Erase) DD4 Erase in progress 10 20 mA V =V PP DD E=V ±0.2V, I Supply current (Program/Erase Suspend) DD 15 50 μA DD5 Erase suspended I Program current (Read or Standby) V >V 400 μA PP PP DD I Program current (Read or Standby) V ≤V 1 5 μA PP1 PP DD I Program current (Reset) RP=V ±0.2V 1 5 μA PP2 SS Program in progress 1 10 mA V =12V±5% PP I Program current (Program) PP3 Program in progress 1 5 μA V =V PP DD Erase in progress 3 10 mA V = 12V ± 5% PP I Program Current (Erase) PP4 Erase in progress 1 5 μA V = V PP DD V Input Low voltage –0.5 0.4 V IL V Input High voltage 0.7V V +0.4 V IH DD DD I = 100μA, V Output Low voltage OL 0.1 V OL V = V min DD DD I = –100μA, V Output High voltage OH V –0.1 V OH V = V min DD DD DD Program voltage (program or erase V 2.7 3.6 V PP1 operations) Program voltage (program or erase V 11.4 12.6 V PPH operations) Program voltage (program and erase V 1 V PPLK lock-out) V supply voltage (Program and Erase V DD 2 V LKO lock-out) 34/72

M28W640HCT, M28W640HCB DC and AC parameters Figure 8. Read AC waveforms tAVAV A0-A21 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQV tGHQX tGLQX tGHQZ DQ0- VALID DQ15 OUTPUTS ADDR. VALID DATA VALID STANDBY ENABLED CHIP ENABLE AI04387 T able 16. Read AC characteristics M28W640HCT, M28W640HCB Symbol Alt Parameter 70ns Unit t t Address valid to Next Address Valid Min 70 ns AVAV RC t t Address valid to Random Output Valid Max 70 ns AVQV ACC t (1) t Address Transition to Output Transition Min 0 ns AXQX OH t (1) t Chip Enable High to Output Transition Min 0 ns EHQX OH t (1) t Chip Enable High to Output Hi-Z Max 20 ns EHQZ HZ t (2) t Chip Enable Low to Output Valid Max 70 ns ELQV CE t (1) t Chip Enable Low to Output Transition Min 0 ns ELQX LZ t (1) t Output Enable High to Output Transition Min 0 ns GHQX OH t (1) t Output Enable High to Output Hi-Z Max 20 ns GHQZ DF t (2) t Output Enable Low to Output Valid Max 20 ns GLQV OE t (1) t Output Enable Low to Output Transition Min 0 ns GLQX OLZ t t Page address Valid to Page Output Valid Max 25 ns AVQV1 PAGE t t Address Transition to Page Output Transition Min 0 ns AXQX1 OH 1. Sampled only, not 100% tested. 2. G may be delayed by up to t - t after the falling edge of E without increasing t . ELQV GLQV ELQV 35/72

DC and AC parameters M28W640HCT, M28W640HCB Figure 9. Page Read AC waveforms b 1 9 1 6 0 AI 1 X Z Z Q Q Q X H H A G E t t t D LI A D QX V LI H A G X V t Q H E t D LI D A LI V A V D 1 LI D V A D ALI VQ V ALI V tA V D LI V A Q V L G t D LI A V V Q L tE QV V A t 5 1 Q A21 A1 0-D 2- 0- Q A A E G D 36/72

M28W640HCT, M28W640HCB DC and AC parameters Figure 10. Write AC waveforms, Write Enable controlled 8 8 3 4 0 ER WPL VPL AI T V V S Q Q GI t t R E E STATUS R S REGISTREADPOLLING ATU 1st T V S Q L E E t S A R E R O X M HA OGRA tW WHGL WHEL R t t P A T D A N D AT tAVAV VALID H CMD or RM COMMDATA INPU W FIR V NO A O t H H C W W H H P P W V t t H X HE WL HD W H W t W t t H W L W D t N A M D M N O MA C M L O W C L P E U t H T- W E S V D t 5 1 Q A0-A21 E G W DQ0-D WP VPP 37/72

DC and AC parameters M28W640HCT, M28W640HCB T able 17. Write AC characteristics, Write Enable controlled M28W640HCT, M28W640HCB Symbol Alt Parameter 70ns Unit t t Write Cycle time Min 70 ns AVAV WC t t Address Valid to Write Enable High Min 45 ns AVWH AS t t Data Valid to Write Enable High Min 45 ns DVWH DS t t Chip Enable Low to Write Enable Low Min 0 ns ELWL CS t Chip Enable Low to Output Valid Min 70 ns ELQV t (1)(2) Output Valid to V Low Min 0 ns QVVPL PP t Output Valid to Write Protect Low Min 0 ns QVWPL t (1) t V High to Write Enable High Min 200 ns VPHWH VPS PP t t Write Enable High to Address Transition Min 0 ns WHAX AH t t Write Enable High to Data Transition Min 0 ns WHDX DH t t Write Enable High to Chip Enable High Min 0 ns WHEH CH t Write Enable High to Chip Enable Low Min 25 ns WHEL t Write Enable High to Output Enable Low Min 20 ns WHGL t t Write Enable High to Write Enable Low Min 25 ns WHWL WPH t t Write Enable Low to Write Enable High Min 45 ns WLWH WP t Write Protect High to Write Enable High Min 45 ns WPHWH 1. Sampled only, not 100% tested. 2. Applicable if V is seen as a logic input (V < 3.6V). PP PP 38/72

M28W640HCT, M28W640HCB DC and AC parameters Figure 11. Write AC waveforms, Chip Enable controlled 9 8 3 4 0 ER WPL VPL AI T V V S Q Q GI t t R E E STATUS R S REGISTREADPOLLING ATU 1st T V S Q L E E t S A R E R O X L M HA HG A E E R t t G O R P A T D A N D AT tAVAV VALID EH CMD or FIRM COMMR DATA INPU V NO A O t H H C E E H H P P W V t t H X W L D tEH tEHE tEH H E tEL ND A M D M DN O ANMA C P M L UO E R-C WL EP WU t H OT- E PE V S D t 5 1 Q 21 D A0-A W G E DQ0- WP VPP 39/72

DC and AC parameters M28W640HCT, M28W640HCB T able 18. Write AC characteristics, Chip Enable controlled M28W640HCT, M28W640HCB Symbol Alt Parameter 70ns Unit t t Write Cycle time Min 70 ns AVAV WC t t Address Valid to Chip Enable High Min 45 ns AVEH AS t t Data Valid to Chip Enable High Min 45 ns DVEH DS t t Chip Enable High to Address Transition Min 0 ns EHAX AH t t Chip Enable High to Data Transition Min 0 ns EHDX DH t t Chip Enable High to Chip Enable Low Min 25 ns EHEL CPH t Chip Enable High to Output Enable Low Min 25 ns EHGL t t Chip Enable High to Write Enable High Min 0 ns EHWH WH t t Chip Enable Low to Chip Enable High Min 45 ns ELEH CP t Chip Enable Low to Output Valid Min 70 ns ELQV t (1)(2) Output Valid to V Low Min 0 ns QVVPL PP t Data Valid to Write Protect Low Min 0 ns QVWPL t (1) t V High to Chip Enable High Min 200 ns VPHEH VPS PP t t Write Enable Low to Chip Enable Low Min 0 ns WLEL CS t Write Protect High to Chip Enable High Min 45 ns WPHEH 1. Sampled only, not 100% tested. 2. Applicable if V is seen as a logic input (V < 3.6V). PP PP 40/72

M28W640HCT, M28W640HCB DC and AC parameters Figure 12. Power-up and Reset AC waveforms W, E, G tPHWL tPHWL tPHEL tPHEL tPHGL tPHGL RP tVDHPH tPLPH VDD Power-up Reset AI03537c T able 19. Power-up and Reset AC characteristics M28W640HCT, M28W640HCB Symbol Parameter Test condition 70ns Unit During program and tPHWL Reset High to Write Enable Low, erase Min 50 μs t PHEL Chip Enable Low, Output Enable Low t PHGL others Min 30 ns t (1)(2) Reset Low to Reset High Min 100 ns PLPH t (3) Supply voltages High to Reset High Min 300 μs VDHPH 1. The device reset is possible but not guaranteed if t < 100ns. PLPH 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset. 41/72

Package mechanical M28W640HCT, M28W640HCB 9 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. RoHS compliant packages are lead-free. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 13. TSOP48 - 48 lead plastic thin small outline, 12 x 20mm, package outline 1 48 e D1 B L1 24 25 A2 A E1 E DIE A1 α L C CP TSOP-G 1. Drawing is not to scale. T able 20. TSOP48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1.20 0.047 A1 0.10 0.05 0.15 0.004 0.002 0.006 A2 1.00 0.95 1.05 0.039 0.037 0.041 B 0.22 0.17 0.27 0.009 0.007 0.011 C 0.10 0.21 0.004 0.008 CP 0.10 0.004 D1 12.00 11.90 12.10 0.472 0.468 0.476 E 20.00 19.80 20.20 0.787 0.779 0.795 E1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 – – 0.020 – – L 0.60 0.50 0.70 0.024 0.020 0.028 L1 0.80 0.031 α 3° 0° 5° 3° 0° 5° 42/72

M28W640HCT, M28W640HCB Package mechanical Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, bottom view package outline D D1 FD SD FE SE E E1 e BALL "A1" ddd e b A A2 A1 BGA-Z34 1. Drawing is not to scale. T able 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1.20 0.047 A1 0.26 0.010 A2 1.00 0.039 b 0.40 0.35 0.45 0.016 0.014 0.018 D 6.39 6.29 6.49 0.252 0.248 0.255 D1 5.250 – – 0.207 – – ddd 0.10 0.004 E 10.50 10.40 10.60 0.413 0.409 0.417 E1 3.75 – – 0.148 – – e 0.75 – – 0.029 – – FD 0.57 – – 0.022 – – FE 3.37 – – 0.133 – – SD 0.37 – – 0.015 – – SE 0.37 – – 0.015 – – 43/72

Ordering information M28W640HCT, M28W640HCB 10 Ordering information T able 22. Ordering information scheme Example: M28W640HCT 70 N 6 E Device type M28 Operating voltage W = V = 2.7V to 3.6V DD Device function 640HC = 64 Mbit (4Mbx16), boot block Array matrix T = top boot B = bottom boot Speed 70 = 70ns Package N = TSOP48: 12 x 20 mm ZB = TFBGA48: 6.39x 10.5mm, 0.75mm pitch Temperature range 6 = –40 to 85°C Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape & reel packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 44/72

M28W640HCT, M28W640HCB Block address tables Appendix A Block address tables T able 23. Top boot block addresses, M28W640HCT # Size (Kword) Address range 0 4 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 4 4 3FB000-3FBFFF 5 4 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 3F8000-3F8FFF 8 32 3F0000-3F7FFF 9 32 3E8000-3EFFFF 10 32 3E0000-3E7FFF 11 32 3D8000-3DFFFF 12 32 3D0000-3D7FFF 13 32 3C8000-3CFFFF 14 32 3C0000-3C7FFF 15 32 3B8000-3BFFFF 16 32 3B0000-3B7FFF 17 32 3A8000-3AFFFF 18 32 3A0000-3A7FFF 19 32 398000-39FFFF 20 32 390000-397FFF 21 32 388000-38FFFF 22 32 380000-387FFF 23 32 378000-37FFFF 24 32 370000-377FFF 25 32 368000-36FFFF 26 32 360000-367FFF 27 32 358000-35FFFF 28 32 350000-357FFF 29 32 348000-34FFFF 30 32 340000-347FFF 31 32 338000-33FFFF 45/72

Block address tables M28W640HCT, M28W640HCB Table 23. Top boot block addresses, M28W640HCT (continued) # Size (Kword) Address range 32 32 330000-337FFF 33 32 328000-32FFFF 34 32 320000-327FFF 35 32 318000-31FFFF 36 32 310000-317FFF 37 32 308000-30FFFF 38 32 300000-307FFF 39 32 2F8000-2FFFFF 40 32 2F0000-2F7FFF 41 32 2E8000-2EFFFF 42 32 2E0000-2E7FFF 43 32 2D8000-2DFFFF 44 32 2D0000-2D7FFF 45 32 2C8000-2CFFFF 46 32 2C0000-2C7FFF 47 32 2B8000-2BFFFF 48 32 2B0000-2B7FFF 49 32 2A8000-2AFFFF 50 32 2A0000-2A7FFF 51 32 298000-29FFFF 52 32 290000-297FFF 53 32 288000-28FFFF 54 32 280000-287FFF 55 32 278000-27FFFF 56 32 270000-277FFF 57 32 268000-26FFFF 58 32 260000-267FFF 59 32 258000-25FFFF 60 32 250000-257FFF 61 32 248000-24FFFF 62 32 240000-247FFF 63 32 238000-23FFFF 64 32 230000-237FFF 65 32 228000-22FFFF 66 32 220000-227FFF 46/72

M28W640HCT, M28W640HCB Block address tables Table 23. Top boot block addresses, M28W640HCT (continued) # Size (Kword) Address range 67 32 218000-21FFFF 68 32 210000-217FFF 69 32 208000-20FFFF 70 32 200000-207FFF 71 32 1F8000-1FFFFF 72 32 1F0000-1F7FFF 73 32 1E8000-1EFFFF 74 32 1E0000-1E7FFF 75 32 1D8000-1DFFFF 76 32 1D0000-1D7FFF 77 32 1C8000-1CFFFF 78 32 1C0000-1C7FFF 79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF 82 32 1A0000-1A7FFF 83 32 198000-19FFFF 84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF 100 32 110000-117FFF 101 32 108000-10FFFF 47/72

Block address tables M28W640HCT, M28W640HCB Table 23. Top boot block addresses, M28W640HCT (continued) # Size (Kword) Address range 102 32 100000-107FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF 111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF 116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF 119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF 124 32 050000-057FFF 125 32 048000-04FFFF 126 32 040000-047FFF 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF 130 32 020000-027FFF 131 32 018000-01FFFF 132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF 48/72

M28W640HCT, M28W640HCB Block address tables T able 24. Bottom boot block addresses, M28W640HCB # Size (Kword) Address range 134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 131 32 3E0000-3E7FFF 130 32 3D8000-3DFFFF 129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 32 3B0000-3B7FFF 124 32 3A8000-3AFFFF 123 32 3A0000-3A7FFF 122 32 398000-39FFFF 121 32 390000-397FFF 120 32 388000-38FFFF 119 32 380000-387FFF 118 32 378000-37FFFF 117 32 370000-377FFF 116 32 368000-36FFFF 115 32 360000-367FFF 114 32 358000-35FFFF 113 32 350000-357FFF 112 32 348000-34FFFF 111 32 340000-347FFF 110 32 338000-33FFFF 109 32 330000-337FFF 108 32 328000-32FFFF 107 32 320000-327FFF 106 32 318000-31FFFF 105 32 310000-317FFF 104 32 308000-30FFFF 103 32 300000-307FFF 102 32 2F8000-2FFFFF 101 32 2F0000-2F7FFF 100 32 2E8000-2EFFFF 49/72

Block address tables M28W640HCT, M28W640HCB Table 24. Bottom boot block addresses, M28W640HCB (continued) # Size (Kword) Address range 99 32 2E0000-2E7FFF 98 32 2D8000-2DFFFF 97 32 2D0000-2D7FFF 96 32 2C8000-2CFFFF 95 32 2C0000-2C7FFF 94 32 2B8000-2BFFFF 93 32 2B0000-2B7FFF 92 32 2A8000-2AFFFF 91 32 2A0000-2A7FFF 90 32 298000-29FFFF 89 32 290000-297FFF 88 32 288000-28FFFF 87 32 280000-287FFF 86 32 278000-27FFFF 85 32 270000-277FFF 84 32 268000-26FFFF 83 32 260000-267FFF 82 32 258000-25FFFF 81 32 250000-257FFF 80 32 248000-24FFFF 79 32 240000-247FFF 78 32 238000-23FFFF 77 32 230000-237FFF 76 32 228000-22FFFF 75 32 220000-227FFF 74 32 218000-21FFFF 73 32 210000-217FFF 72 32 208000-20FFFF 71 32 200000-207FFF 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF 50/72

M28W640HCT, M28W640HCB Block address tables Table 24. Bottom boot block addresses, M28W640HCB (continued) # Size (Kword) Address range 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF 57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 51/72

Block address tables M28W640HCT, M28W640HCB Table 24. Bottom boot block addresses, M28W640HCB (continued) # Size (Kword) Address range 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF 11 32 020000-027FFF 10 32 018000-01FFFF 9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF 4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF 52/72

M28W640HCT, M28W640HCB Common Flash interface (CFI) Appendix B Common Flash interface (CFI) The Common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 25, 26, 27, 28, 29 and 30 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table30: Security code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read command to return to Read mode. T able 25. Query structure overview(1) Offset Sub-section name Description 00h Reserved Reserved for algorithm-specific information 10h CFI Query identification string Command set ID and algorithm data offset 1Bh System interface information Device timing & voltage information 27h Device geometry definition Flash device layout Primary algorithm-specific extended query Additional information specific to the primary P table algorithm (optional) Alternate algorithm-specific extended query Additional information specific to the A table alternate algorithm (optional) 1. Query data are always presented on the lowest order data outputs. 53/72

Common Flash interface (CFI) M28W640HCT, M28W640HCB T able 26. CFI query identification string(1) Offset Data Description Value 00h 0020h Manufacturer code Numonyx 8848h Top 01h Device code 8849h Bottom 02h-0Fh reserved Reserved 10h 0051h ‘Q’ 11h 0052h Query unique ASCII string ‘QRY’ ‘R’ 12h 0059h ‘Y’ 13h 0003h Primary algorithm command set and control interface ID code 16 Intel 14h 0000h bit ID code defining a specific algorithm compatible 15h 0035h Address for primary algorithm extended query table (see Table28) P = 35h 16h 0000h 17h 0000h Alternate vendor command set and control interface ID code second vendor - specified algorithm supported (0000h means NA 18h 0000h none exists) 19h 0000h Address for Alternate algorithm extended query table NA 1Ah 0000h (0000h means none exists) 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 54/72

M28W640HCT, M28W640HCB Common Flash interface (CFI) T able 27. CFI query system interface information Offset Data Description Value V logic supply minimum program/erase or write voltage DD 1Bh 0027h bit 7 to 4BCD value in volts 2.7V bit 3 to 0BCD value in 100 mV V logic supply maximum Program/Erase or Write voltage DD 1Ch 0036h bit 7 to 4BCD value in volts 3.6V bit 3 to 0BCD value in 100 mV V [programming] supply minimum Program/Erase voltage PP 1Dh 00B4h bit 7 to 4HEX value in volts 11.4V bit 3 to 0BCD value in 100 mV V [programming] supply maximum Program/Erase voltage PP 1Eh 00C6h bit 7 to 4HEX value in volts 12.6V bit 3 to 0BCD value in 100 mV 1Fh 0004h Typical time-out per single word program = 2n μs 16μs 20h 0004h Typical time-out for Double/Quadruple Word Program = 2n μs 16μs 21h 000Ah Typical time-out per individual block erase = 2n ms 1s 22h 0000h Typical time-out for full chip erase = 2n ms NA 23h 0005h Maximum time-out for Word program = 2n times typical 512μs Maximum time-out for Double/Quadruple Word Program = 2n times 24h 0005h 512μs typical 25h 0003h Maximum time-out per individual block erase = 2n times typical 8s 26h 0000h Maximum time-out for chip erase = 2n times typical NA 55/72

Common Flash interface (CFI) M28W640HCT, M28W640HCB T able 28. Device geometry definition Offset Word Data Description Value Mode 27h 0017h Device size = 2n in number of bytes 8 Mbyte 28h 0001h x16 Flash device interface code description 29h 0000h Async. 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2n 8 2Bh 0000h Number of Erase block regions within the device. 2Ch 0002h It specifies the number of regions within the device containing 2 contiguous Erase blocks of the same size. 2Dh 007Eh Region 1 information 127 2Eh 0000h Number of identical-size erase block = 007Eh+1 T C 2Fh 0000h Region 1 information H 64 Kbyte 0 30h 0001h Block size in Region 1 = 0100h * 256 byte 4 6 W 31h 0007h Region 2 information 8 8 2 32h 0000h Number of identical-size erase block = 0007h+1 M 33h 0020h Region 2 information 8 Kbyte 34h 0000h Block size in region 2 = 0020h * 256 byte 2Dh 0007h Region 1 information 8 2Eh 0000h Number of identical-size erase block = 0007h+1 B C 2Fh 0020h Region 1 information H 8 Kbyte 0 30h 0000h Block size in region 1 = 0020h * 256 byte 4 6 W 31h 007Eh Region 2 information 8 127 2 32h 0000h Number of identical-size erase block = 007Eh=1 M 33h 0000h Region 2 information 64 Kbyte 34h 0001h Block size in region 2 = 0100h * 256 byte 56/72

M28W640HCT, M28W640HCB Common Flash interface (CFI) T able 29. Primary algorithm-specific extended query table Offset Data Description Value P = 35h(1) (P+0)h=35h 0050h ‘P’ (P+1)h=36h 0052h Primary algorithm extended query table unique ASCII string ‘PRI’ ‘R’ (P+2)h=37h 0049h ‘I’ (P+3)h=38h 0031h Major version number, ASCII ‘1’ (P+4)h=39h 0030h Minor version number, ASCII ‘0’ (P+5)h=3Ah 0066h Extended query table contents for primary algorithm. address (P+5)h contains less significant byte. (P+6)h=3Bh 0000h bit 0Chip Erase supported(1 = Yes, 0 = No) (P+7)h=3Ch 0000h bit 1Suspend Erase supported(1 = Yes, 0 = No) No bit 2Suspend Program supported(1 = Yes, 0 = No) Yes bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No) Yes bit 4Queued Erase supported(1 = Yes, 0 = No) No bit 5Instant individual block locking supported(1 = Yes, 0 = No) No (P+8)h=3Dh 0000h bit 6Protection bits supported(1 = Yes, 0 = No) Yes bit 7Page mode read supported(1 = Yes, 0 = No) Yes bit 8Synchronous read supported(1 = Yes, 0 = No) No bit 31 to 9Reserved; undefined bits are ‘0’ No Supported functions after Suspend Read Array, Read Status Register and CFI query are always (P+9)h=3Eh 0001h supported during erase or program operation bit 0Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1Reserved; undefined bits are ‘0’ Yes (P+A)h=3Fh 0003h Block Lock status Defines which bits in the block Status Register section of the query are implemented. Address (P+A)h contains less significant byte bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 (P+B)h=40h 0000h = No) Yes bit 1Block Lock Status Register Lock-down bit active (1 = Yes, 0 = Yes No) bit 15 to 2Reserved for future use; undefined bits are ‘0’ V logic supply optimum Program/Erase voltage (highest DD performance) (P+C)h=41h 0030h 3V bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV V supply optimum Program/Erase voltage PP (P+D)h=42h 00C0h bit 7 to 4HEX value in volts 12V bit 3 to 0BCD value in 100 mV Number of protection register fields in JEDEC ID space. (P+E)h=43h 0001h 01 "00h," indicates that 256 protection bytes are available 57/72

Common Flash interface (CFI) M28W640HCT, M28W640HCB Table 29. Primary algorithm-specific extended query table (continued) Offset Data Description Value P = 35h(1) (P+F)h=44h 0080h Protection field 1: protection description 80h This field describes user-available one-time-programmable (P+10)h=45h 0000h 00h (OTP) protection register bytes. Some are pre-programmed with (P+11)h=46h 0003h device unique serial numbers. Others are user programmable. 8 byte bits 0–15 point to the Protection Register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user- programmable. (P+12)h=47h 0004h 16 byte bit 0 to 7 Lock/bytes JEDEC-plane physical low address bit 8 to 15Lock/bytes JEDEC-plane physical high address bit 16 to 23 "n" such that 2n = factory pre-programmed bytes bit 24 to 31 "n" such that 2n = user programmable bytes (P+13)h=48h Reserved 1. See Table26, offset 15 for P pointer definition. T able 30. Security code area Offset Data Description 80h 00XX Protection Register Lock 81h XXXX 82h XXXX 64 bits: unique device number 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 128 bits: user programmable OTP 89h XXXX 8Ah XXXX 8Bh XXXX 8Ch XXXX 58/72

M28W640HCT, M28W640HCB Flowcharts and pseudocodes Appendix C Flowcharts and pseudocodes Figure 15. Program flowchart and pseudocode Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ Write Address writeToFlash (addressToProgram, dataToProgram) ; & Data /*Memory enters read status state after the Program Command*/ do { Read Status status_register=readFlash (any_address) ; Register /* E or G must be toggled*/ NO b7 = 1 } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ; YES NO Program if (status_register.b4==1) /*program error */ b4 = 0 Error (1, 2) error_handler ( ) ; YES NO Program to Protected if (status_register.b1==1) /*program to protect block error */ b1 = 0 Block Error (1, 2) error_handler ( ) ; YES } End AI03538b 1. Status check of b1 (protected block), b3 (V invalid) and b4 (program error) can be made after each program operation or PP after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations. 59/72

Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 16. Double Word Program flowchart and pseudocode Start Write 30h double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; Write Address 1 writeToFlash (addressToProgram1, dataToProgram1) ; & Data 1 (3) /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after Write Address 2 the Program command*/ & Data 2 (3) do { status_register=readFlash (any_address) ; Read Status /* E or G must be toggled*/ Register NO b7 = 1 } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ; YES NO Program if (status_register.b4==1) /*program error */ b4 = 0 Error (1, 2) error_handler ( ) ; YES NO Program to Protected if (status_register.b1==1) /*program to protect block error */ b1 = 0 Block Error (1, 2) error_handler ( ) ; YES } End AI03539b 1. Status check of b1 (protected block), b3 (V invalid) and b4 (program error) can be made after each program operation or PP after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and address 2 must be consecutive addresses differing only for bit A0. 60/72

M28W640HCT, M28W640HCB Flowcharts and pseudocodes Figure 17. Quadruple Word Program flowchart and pseudocode Start quadruple_word_program_command (addressToProgram1, dataToProgram1, Write 56h addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { Write Address 1 writeToFlash (any_address, 0x56) ; & Data 1 (3) writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ Write Address 2 writeToFlash (addressToProgram2, dataToProgram2) ; & Data 2 (3) /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; Write Address 3 /*see note (3) */ & Data 3 (3) writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */ Write Address 4 /*Memory enters read status state after & Data 4 (3) the Program command*/ do { status_register=readFlash (any_address) ; Read Status /* E or G must be toggled*/ Register NO b7 = 1 } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ; YES NO Program if (status_register.b4==1) /*program error */ b4 = 0 Error (1, 2) error_handler ( ) ; YES NO Program to Protected if (status_register.b1==1) /*program to protect block error */ b1 = 0 Block Error (1, 2) error_handler ( ) ; YES } End AI06233 1. Status check of b1 (protected block), b3 (V invalid) and b4 (program error) can be made after each program operation or PP after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to address 4 must be consecutive addresses differing only for bits A0 and A1. 61/72

Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 18. Program Suspend & Resume flowchart and pseudocode Start program_suspend_command ( ) { Write B0h writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; Read Status /* E or G must be toggled*/ Register NO b7 = 1 } while (status_register.b7== 0) ; YES NO b2 = 1 Program Complete if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; YES read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array Write FFh (as if program/erase suspend was not issued).*/ } Read data from else another address { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; Write D0h Write FFh /*write 0xD0 to resume program*/ } } Program Continues Read Data AI03540b 62/72

M28W640HCT, M28W640HCB Flowcharts and pseudocodes Figure 19. Erase flowchart and pseudocode Start erase_command ( blockToErase ) { Write 20h writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ Write Block /* Memory enters read status state after Address & D0h the Erase Command */ do { Read Status status_register=readFlash (any_address) ; Register /* E or G must be toggled*/ NO b7 = 1 } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1) error_handler ( ) ; YES if ( (status_register.b4==1) && (status_register.b5==1) ) YES Command b4, b5 = 1 /* command sequence error */ Sequence Error (1) error_handler ( ) ; NO if ( (status_register.b5==1) ) NO b5 = 0 Erase Error (1) /* erase error */ error_handler ( ) ; YES NO Erase to Protected if (status_register.b1==1) /*program to protect block error */ b1 = 0 Block Error (1) error_handler ( ) ; YES } End AI03541b 1. If an error is found, the Status Register must be cleared before further program/erase operations. 63/72

Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 20. Erase Suspend & Resume flowchart and pseudocode Start erase_suspend_command ( ) { Write B0h writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h do { Read Status status_register=readFlash (any_address) ; Register /* E or G must be toggled*/ NO b7 = 1 } while (status_register.b7== 0) ; YES NO b6 = 1 Erase Complete if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ; YES read_data ( ) ; Write FFh /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock } else { writeToFlash (any_address, 0xFF) ; read_program_data ( ); Write D0h Write FFh /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } } Erase Continues Read Data AI03542b 64/72

M28W640HCT, M28W640HCB Flowcharts and pseudocodes Figure 21. Locking operations flowchart and pseudocode Start locking_operation_command (address, lock_operation) { Write 60h writeToFlash (any_address, 0x60) ; /*configuration setup*/ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; Write else if (lock_operation==UNLOCK) /*to unprotect the block*/ 01h, D0h or 2Fh writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; Write 90h writeToFlash (any_address, 0x90) ; Read Block Lock States if (readFlash (address) ! = locking_state_expected) Locking NO error_handler () ; change confirmed? /*Check the locking state (see Read Block Signature table )*/ YES writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ Write FFh } End AI04364 65/72

Flowcharts and pseudocodes M28W640HCT, M28W640HCB Figure 22. Protection Register Program flowchart and pseudocode Start protection_register_program_command (addressToProgram, dataToProgram) {: Write C0h writeToFlash (any_address, 0xC0) ; Write Address writeToFlash (addressToProgram, dataToProgram) ; & Data /*Memory enters read status state after the Program Command*/ do { Read Status status_register=readFlash (any_address) ; Register /* E or G must be toggled*/ NO b7 = 1 } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ; YES NO Program if (status_register.b4==1) /*program error */ b4 = 0 Error (1, 2) error_handler ( ) ; YES NO Program to Protected if (status_register.b1==1) /*program to protect block error */ b1 = 0 Block Error (1, 2) error_handler ( ) ; YES } End AI04381 1. Status check of b1 (protected block), b3 (V invalid) and b4 (program error) can be made after each program operation or PP after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase controller operations. 66/72

M28W640HCT, M28W640HCB Command interface and Program/Erase controller state Appendix D Command interface and Program/Erase controller state Table 31. W . rite state machine current/next(1) Command input (and next state) SR Current Data when bit Read Program Erase Erase Prog/Ers Prog/Ers Read Clear state Read 7 Array Setup Setup Confirm Suspend Resume Status Status (FFh) (10/40h) (20h) (D0h) (B0h) (D0h) (70h) (50h) Read Ers. Read Read Read Array ‘1’ Array Prog.Setup Read Array Array Setup Sts. Array Read Read Program Erase Read Read ‘1’ Status Read Array Status Array Setup Setup Status Array Read Electronic Read Program Erase Read Read ‘1’ Read Array Elect.Sg. signature Array Setup Setup Status Array Read CFI Read Program Erase Read Read ‘1’ CFI Read Array Query Array Setup Setup Status Array Lock Lock Cmd Lock Lock Command Lock Setup ‘1’ Status Lock Command Error (complete) Error (complete) Error Lock Cmd Read Program Erase Read Read ‘1’ Status Read Array Error Array Setup Setup Status Array Lock Read Program Erase Read Read ‘1’ Status Read Array (complete) Array Setup Setup Status Array Prot. Prog. ‘1’ Status Protection Register Program Setup Prot. Prog. ‘0’ Status Protection Register Program continue (continue) Prot. Prog. Read Program Erase Read Read ‘1’ Status Read Array (complete) Array Setup Setup Status Array Prog. ‘1’ Status Program Setup Program Prog. Sus ‘0’ Status Program (continue) Program (continue) (continue) Read Sts Prog. Prog. Prog. Prog. Sus Prog. Sus Sus Program Suspend to Program Program Sus Sus ‘1’ Status Read Status Read Read Array (continue) (continue) Read Read Array Array Sts Array Prog. Prog. Prog. Prog. Sus Prog. Sus Sus Program Suspend to Program Program Sus Sus ‘1’ Array Read Read Array Read Read Array (continue) (continue) Read Read Array Array Sts Array Prog. Prog. Prog. Prog. Sus Prog. Sus Electronic Sus Program Suspend to Program Program Sus Sus Read ‘1’ Read signature Read Read Array (continue) (continue) Read Read Elect.Sg. Array Array Sts Array 67/72

Command interface and Program/Erase controller state M28W640HCT, M28W640HCB Table 31. Write state machine current/next(1) (continued) Command input (and next state) SR Current Data when bit Read Program Erase Erase Prog/Ers Prog/Ers Read Clear state Read 7 Array Setup Setup Confirm Suspend Resume Status Status (FFh) (10/40h) (20h) (D0h) (B0h) (D0h) (70h) (50h) Prog. Prog. Prog. Prog. Sus Prog. Sus Sus Program Suspend to Program Program Sus Sus ‘1’ CFI Read Read CFI Read Read Array (continue) (continue) Read Read Array Array Sts Array Program Read Program Erase Read Read ‘1’ Status Read Array (complete) Array Setup Setup Status Array Erase Erase Erase Erase Erase ‘1’ Status Erase Command Error Setup (continue) CmdError (continue) Command Error Erase Read Program Erase Read Read ‘1’ Status Read Array Cmd.Error Array Setup Setup Status Array Erase Erase Sus ‘0’ Status Erase (continue) Erase (continue) (continue) Read Sts Erase Erase Erase Erase Erase Sus Erase Sus Sus Program Sus Erase Erase Sus Sus ‘1’ Status Read Read Sts Read Setup Read (continue) (continue) Read Read Array Array Array Sts Array Erase Erase Erase Erase Erase Sus Erase Sus Sus Program Sus Erase Erase Sus Sus ‘1’ Array Read Read Array Read Setup Read (continue) (continue) Read Read Array Array Array Sts Array Erase Erase Erase Erase Erase Sus Erase Sus Electronic Sus Program Sus Erase Erase Sus Sus Read ‘1’ Read Signature Read Setup Read (continue) (continue) Read Read Elect.Sg. Array Array Array Sts Array Erase Erase Erase Erase Erase Sus Erase Sus Sus Program Sus Erase Erase Sus Sus ‘1’ CFI Read Read CFI Read Setup Read (continue) (continue) Read Read Array Array Array Sts Array Erase Read Program Erase Read Read ‘1’ Status Read Array (complete) Array Setup Setup Status Array 1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend. 68/72

M28W640HCT, M28W640HCB Command interface and Program/Erase controller state Table 32. W . rite state machine current/next(1) Command input (and next state) Current Read Read CFI Lock Lock Down Unlock state Lock Setup Prot. Prog. Elect.Sg. Query Confirm Confirm Confirm (60h) Setup (C0h) (90h) (98h) (01h) (2Fh) (D0h) Read Read CFI Prot. Prog. Read Array Lock Setup Read Array Elect.Sg. Query Setup Read Read CFI Prot. Prog. Read Status Lock Setup Read Array Elect.Sg. Query Setup Read Read Read CFI Prot. Prog. Lock Setup Read Array Elect.Sg. Elect.Sg. Query Setup Read CFI Read Read CFI Prot. Prog. Lock Setup Read Array Query Elect.Sg. Query Setup Lock Setup Lock Command Error Lock (complete) Lock Cmd Read Read CFI Prot. Prog. Lock Setup Read Array Error Elect.Sg. Query Setup Lock Read Read CFI Prot. Prog. Lock Setup Read Array (complete) Elect.Sg. Query Setup Prot. Prog. Protection Register Program Setup Prot. Prog. Protection Register Program (continue) (continue) Prot. Prog. Read Read CFI Prot. Prog. Lock Setup Read Array (complete) Elect.Sg. Query Setup Prog. Setup Program Program Program (continue) (continue) Prog. Prog. Prog. Suspend Suspend Program Suspend Program Suspend Read Array Read Read CFI (continue) Read Status Elect.Sg. Query Prog. Prog. Prog. Suspend Suspend Program Suspend Program Suspend Read Array Read Read CFI (continue) Read Array Elect.Sg. Query Prog. Prog. Prog. Suspend Suspend Suspend Program Program Suspend Read Array Read Read Read CFI (continue) Elect.Sg. Elect.Sg. Query Prog. Prog. Prog. Suspend Suspend Program Suspend Program Suspend Read Array Read Read CFI (continue) Read CFI Elect.Sg. Query Program Read Read Prot. Prog. Lock Setup Read Array (complete) Elect.Sg. CFIQuery Setup 69/72

Command interface and Program/Erase controller state M28W640HCT, M28W640HCB Table 32. Write state machine current/next(1) (continued) Command input (and next state) Current Read Read CFI Lock Lock Down Unlock state Lock Setup Prot. Prog. Elect.Sg. Query Confirm Confirm Confirm (60h) Setup (C0h) (90h) (98h) (01h) (2Fh) (D0h) Erase Erase Setup Erase Command Error (continue) Erase Read Read CFI Prot. Prog. Lock Setup Read Array Cmd.Error Elect.Sg. Query Setup Erase Erase (continue) (continue) Erase Erase Erase Suspend Suspend Erase Suspend Lock Setup Erase Suspend Read Array Read Read CFI (continue) Read Ststus Elect.Sg. Query Erase Erase Erase Suspend Suspend Erase Suspend Lock Setup Erase Suspend Read Array Read Read CFI (continue) Read Array Elect.Sg. Query Erase Erase Erase Suspend Suspend Suspend Erase Lock Setup Erase Suspend Read Array Read Read Read CFI (continue) Elect.Sg. Elect.Sg. Query Erase Erase Erase Suspend Suspend Suspend Erase Lock Setup Erase Suspend Read Array Read CFI Read Read CFI (continue) Query Elect.Sg. Query Erase Read Read CFI Prot. Prog. Lock Setup Read Array (complete) Elect.Sg. Query Setup 1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection. 70/72

M28W640HCT, M28W640HCB Revision history 11 Revision history T able 33. Document revision history Date Version Changes 29-Jan-2008 1 Initial release. 20-Mar-2008 2 Applied Numonyx branding. Changed title page to remove “preliminary” status. 06-Nov-2008 3 Corrected minimum voltage for V in Table 15.: DC characteristics IH 71/72

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