LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 Negative Voltage Hot Swap Controllers FEATURES DESCRIPTION n Allows Safe Board Insertion and Removal from a The LTC®4252 negative voltage Hot SwapTM controller Live –48V Backplane allows a board to be safely inserted and removed from a n Floating Topology Permits Very High Voltage Operation live backplane. Output current is controlled by three stages n Current Limit With Circuit Breaker Timer of current limiting: a timed circuit breaker, active current n Fast Response Time Limits Peak Fault Current limiting and a fast feedforward path that limits peak current n Programmable Soft-Start Current Limit under worst-case catastrophic fault conditions. n Programmable Timer with Drain Voltage Adjustable undervoltage and overvoltage detectors dis- Accelerated Response connect the load whenever the input supply exceeds the n ±1% Undervoltage/Overvoltage Threshold (LTC4252C) desired operating range. The LTC4252’s supply input is n Improved Ruggedness Shunt Regulator shunt regulated, allowing safe operation with very high ■ Adjustable Undervoltage/Overvoltage Protection supply voltages. A multifunction timer delays initial start- ■ LTC4252B-1/LTC4252C-1: Latch Off After Fault up and controls the circuit breaker’s response time. The ■ LTC4252B-2/LTC4252C-2: Automatic Retry After Fault circuit breaker’s response time is accelerated by sensing ■ Available in 8-Pin and 10-Pin MSOP Packages excessive MOSFET drain voltage, keeping the MOSFET APPLICATIONS within its safe operating area (SOA). An adjustable soft- start circuit controls MOSFET inrush current at start-up. n Hot Board Insertion The LTC4252-2 provides automatic retry after a fault. The n Electronic Circuit Breaker LTC4252C-1/LTC4252C-2 feature tight ±1% undervoltage/ n –48V Distributed Power Systems overvoltage threshold accuracy. The LTC4252 is available n Negative Power Supply Control in either an 8-pin or 10-pin MSOP. n Central Office Switching n High Availability Servers The LTC4252B and LTC4252C improve the ruggedness n ATCA of the shunt regulator in the LTC4252 and LTC4252A. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Start-Up Behavior –48V/2.5A Hot Swap Controller –48RTN RIN + CL GATE 3× 1.8k IN SERIES 100µF 5V/DIV 1/4W EACH –48RTN DDIDNZ†13B** 1CµINF R5.31k LOAD (SHORT PIN) R1 VIN EN SENSE 4012%k LTC4252B-1 * VOUT 2.5A/DIV OV PWRGD RD 1M UV DRAIN 32.R42k TIMER GATE QIR1F530S 20VV/ODUIVT 1% C0.T33µF SS VEE SENSE RC RS C1 CSS 10Ω 0.02Ω 10nF 68nF CC PWRGD 18nF 10V/DIV –48V* M0C207 †RECOMMENDED FOR HARSH ENVIRONMENTS 4252B12 TA01 1ms/DIV 4252B12 TA01a **DIODES, INC 4252b12f 1

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 ABSOLUTE MAXIMUM RATINGS All Voltages Referred to V (Note 1) EE Current into V (100µs Pulse) .............................100mA Operating Temperature Range IN V , DRAIN Pin Minimum Voltage ........................ –0.3V LTC4252BC-1/LTC4252BC-2 IN Input/Output Pins LTC4252CC-1/LTC4252CC-2 ....................0°C to 70°C (Except SENSE and DRAIN) Voltage ..........–0.3V to 16V LTC4252BI-1/LTC4252BI-2 SENSE Pin Voltage .................................... –0.6V to 16V LTC4252CI-1/LTC4252CI-2 ................. –40°C to 85°C Current Out of SENSE Pin (20µs Pulse) .......... –200mA Storage Temperature Range ..................–65°C to 150°C Current into DRAIN Pin (100µs Pulse) ...................20mA Lead Temperature (Soldering, 10 sec) ...................300°C Maximum Junction Temperature ..........................125°C PIN CONFIGURATION TOP VIEW TOP VIEW VIN 1 8TIMER PWRVGIDN 12 190 TUIVMER SS 2 7UV/OV SS 3 8 OV SENSE 3 6DRAIN SENSE 4 7 DRAIN VEE 4 5GATE VEE 5 6 GATE MS8 PACKAGE MS PACKAGE 8-LEAD PLASTIC MSOP 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W TJMAX = 125°C, θJA = 160°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4252BCMS8-1#PBF LTC4252BCMS8-1#TRPBF LTGDX 8-Lead Plastic MSOP 0°C to 70°C LTC4252BCMS8-2#PBF LTC4252BCMS8-2#TRPBF LTGDZ 8-Lead Plastic MSOP 0°C to 70°C LTC4252BIMS8-1#PBF LTC4252BIMS8-1#TRPBF LTGDX 8-Lead Plastic MSOP –40°C to 85°C LTC4252BIMS8-2#PBF LTC4252BIMS8-2#TRPBF LTGDZ 8-Lead Plastic MSOP –40°C to 85°C LTC4252BCMS-1#PBF LTC4252BCMS-1#TRPBF LTGDY 10-Lead Plastic MSOP 0°C to 70°C LTC4252BCMS-2#PBF LTC4252BCMS-2#TRPBF LTGFB 10-Lead Plastic MSOP 0°C to 70°C LTC4252BIMS-1#PBF LTC4252BIMS-1#TRPBF LTGDY 10-Lead Plastic MSOP –40°C to 85°C LTC4252BIMS-2#PBF LTC4252BIMS-2#TRPBF LTGFB 10-Lead Plastic MSOP –40°C to 85°C LTC4252CCMS-1#PBF LTC4252CCMS-1#TRPBF LTGFC 10-Lead Plastic MSOP 0°C to 70°C LTC4252CCMS-2#PBF LTC4252CCMS-2#TRPBF LTGFD 10-Lead Plastic MSOP 0°C to 70°C LTC4252CIMS-1#PBF LTC4252CIMS-1#TRPBF LTGFC 10-Lead Plastic MSOP –40°C to 85°C LTC4252CIMS-2#PBF LTC4252CIMS-2#TRPBF LTGFD 10-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4252b12f 2

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 2) A LTC4252B-1/-2 LTC4252C-1/-2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V V – V Zener Voltage I = 2mA l 11.5 13 14.5 11.5 13 14.5 V Z IN EE IN r V – V Zener Dynamic Impedance I = 2mA to 30mA 5 5 Ω Z IN EE IN I V Supply Current UV = OV = 4V, V = (V – 0.3V) ● 0.8 2 0.9 2 mA IN IN IN Z V V Undervoltage Lockout Coming Out of UVLO (Rising V ) ● 9.2 11.5 9 10 V LKO IN IN V V Undervoltage Lockout Hysteresis 1 0.5 V LKH IN V Circuit Breaker Current Limit Voltage V = (V – V ) ● 40 50 60 45 50 55 mV CB CB SENSE EE V Analog Current Limit Voltage V = (V – V ), ● 80 100 120 mV ACL ACL SENSE EE SS = Open or 2.2V V / Analog Current Limit Voltage/ V = (V – V ), ● 1.05 1.20 1.38 V/V ACL ACL SENSE EE V Circuit Breaker Voltage SS = Open or 1.4V CB V Fast Current Limit Voltage V = (V – V ) ● 150 200 300 150 200 300 mV FCL FCL SENSE EE V SS Voltage After End of SS Timing Cycle 2.2 1.4 V SS R SS Output Impedance 100 50 kΩ SS I SS Pin Current UV = OV = 4V, V = V , 22 28 µA SS SENSE EE V = 0V (Sourcing) SS UV = OV = 0V, V = V , 28 28 mA SENSE EE V = 2V (Sinking) SS V Analog Current Limit Offset Voltage 10 10 mV OS V +V / Ratio (V + V ) to SS Voltage 0.05 0.05 V/V ACL OS ACL OS V SS I GATE Pin Output Current UV = OV = 4V, V = V , ● 40 58 80 40 58 80 µA GATE SENSE EE V = 0V (Sourcing) GATE UV = OV = 4V, V – V = 0.15V, 17 17 mA SENSE EE V = 3V (Sinking) GATE UV = OV = 4V, V – V = 0.3V, 190 190 mA SENSE EE V = 1V (Sinking) GATE V External MOSFET Gate Drive V – V , I = 2mA ● 10 12 V 10 12 V V GATE GATE EE IN Z Z V Gate High Threshold V = V – V , I = 2mA, 2.8 2.8 V GATEH GATEH IN GATE IN for PWRGD Status (MS Only) V Gate Low Threshold (Before Gate Ramp-Up) 0.5 0.5 V GATEL V UV Pin Threshold HIGH ● 3.075 3.225 3.375 V UVHI V UV Pin Threshold LOW ● 2.775 2.925 3.075 V UVLO V UV Pin Threshold Low-to-High Transition ● 3.05 3.08 3.11 V UV V UV Pin Hysteresis (● for LTC4252C Only) ● 300 292 324 356 mV UVHST V OV Pin Threshold HIGH ● 5.85 6.15 6.45 V OVHI V OV Pin Threshold LOW ● 5.25 5.55 5.85 V OVLO V OV Pin Threshold Low-to-High Transition ● 5.04 5.09 5.14 V OV V OV Pin Hysteresis (● for LTC4252C Only) ● 600 82 102 122 mV OVHST I SENSE Pin Input Current UV = OV = 4V, V = 50mV ● –15 –30 –15 –30 µA SENSE SENSE I UV, OV Pin Input Current UV = OV = 4V ● ±0.1 ±1 ±0.1 ±1 µA INP V TIMER Pin Voltage High Threshold 4 4 V TMRH V TIMER Pin Voltage Low Threshold 1 1 V TMRL 4252b12f 3

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 2) A LTC4252B-1/-2 LTC4252C-1/-2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS I TIMER Pin Current Timer On (Initial Cycle/Latchoff/ 5.8 5.8 µA TMR Shutdown Cooling, Sourcing), V = 2V TMR Timer Off (Initial Cycle, Sinking), 28 28 mA V = 2V TMR Timer On (Circuit Breaker, Sourcing, 230 230 µA I = 0µA), V = 2V DRN TMR Timer On (Circuit Breaker, Sourcing, 630 630 µA I = 50µA), V = 2V DRN TMR Timer Off (Circuit Breaker/ 5.8 5.8 µA Shutdown Cooling, Sinking), V = 2V TMR ∆I / [(I at I = 50µA) – (I at I = Timer On (Circuit Breaker with 8 8 µA/µA TMRACC TMR DRN TMR DRN ∆I 0µA)]/∆I I = 50µA) DRN DRN DRN V DRAIN Pin Voltage Low Threshold For PWRGD Status (MS Only) 2.385 2.385 V DRNL I DRAIN Leakage Current V = 5V (4V for LTC4252C) ±0.1 ±1 ±0.1 ±1 µA DRNL DRAIN V DRAIN Pin Clamp Voltage I = 50µA 7 6 V DRNCL DRN V PWRGD Output Low Voltage I = 1.6mA (MS Only) ● 0.2 0.4 0.2 0.4 V PGL PG I = 5mA (MS Only) ● 1.1 1.1 V PG I PWRGD Pull-Up Current V = 0V (Sourcing) (MS Only) ● 40 58 80 40 58 80 µA PGH PWRGD t SS Default Ramp Period SS Pin Floating, V Ramps from 180 µs SS SS 0.2V to 2V SS Pin Floating, V Ramps from 230 µs SS 0.1V to 0.9V t UV Low to Gate Low 0.4 0.4 µs PLLUG t OV High to Gate Low 0.4 0.4 µs PHLOG Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 2: All currents into device pins are positive; all currents out of device may cause permanent damage to the device. Exposure to any Absolute pins are negative. All voltages are referenced to V unless otherwise EE Maximum Rating condition for extended periods may affect device specified. reliability and lifetime. 4252b12f 4

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS V vs Temperature r vs Temperature I vs Temperature Z Z IN 14.5 10 2000 IIN = 2mA IIN = 2mA VIN = (VZ – 0.3V) 1800 9 14.0 1600 8 1400 7 13.5 1200 V (V)Z13.0 r(Ω)Z 6 I (µA)IN1080000 5 600 4 12.5 400 3 200 12.0 2 0 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G01 4252B12 G02 4252B12 G03 Undervoltage Lockout V Undervoltage Lockout Hysteresis LKO I vs V vs Temperature V vs Temperature IN IN LKH 1000 12.0 1.5 11.5 1.3 100 11.0 10.5 A) V) V) 1.1 I (mIN 10 V (LKO109..05 V (LKH0.9 1 125°C 9.0 85°C 0.7 25°C 8.5 –40°C 0.1 8.0 0.5 0 2 4 6 8 10 12 14 16 18 20 22 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 95 105 125 VIN (V) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G04 4252B12 G05 4252B12 G06 Circuit Breaker Current Limit Analog Current Limit Voltage Fast Current Limit Voltage V FCL Voltage V vs Temperature V vs Temperature vs Temperature CB ACL 60 120 300 58 115 275 56 110 54 250 105 mV) 52 mV) mV) V (CB 5408 V (ACL10905 V (FCL225 200 46 90 44 175 85 42 40 80 150 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G07 4252B12 G08 4252B12 G09 4252b12f 5

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS V vs Temperature R vs Temperature I (Sinking) vs Temperature SS SS SS 2.40 110 45 UV = OV = VSENSE = VEE 2.35 108 40 IIN = 2mA 106 VSS = 2V 35 2.30 104 30 V (V)SS 22..2250 R (kΩ)SS11009208 I (mA)SS 2205 2.15 15 96 2.10 10 94 2.05 92 5 2.00 90 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G10 4252B12 G11 4252B12 G12 V vs Temperature (V + V )/V vs Temperature I (Sourcing) vs Temperature OS ACL OS SS GATE 11.0 0.060 70 UV/0V = 4V 10.8 0.058 TIMER = 0V 65 VSENSE = VEE 10.6 0.056 VGATE = 0V 10.4 V/V)0.054 60 V)10.2 V (SS0.052 A) V (mOS109..08 + V)/OS00..005408 I (GATE 55 CL 50 9.6 VA0.046 ( 9.4 0.044 45 9.2 0.042 9.0 0.040 40 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (C) 4252B12 G13 4252B12 G14 4252B12 G15 I (ACL, Sinking) I (FCL, Sinking) GATE GATE vs Temperature vs Temperature V vs Temperature GATE 30 400 14.5 UV/0V = 4V UV/0V = 4V UV/0V = 4V TIMER = 0V 350 TIMER = 0V 14.0 TIMER = 0V 25 VSENSE – VEE = 0.15V VSENSE – VEE = 0.3V VSENSE = VEE VGATE = 3V 300 VGATE = 1V 13.5 20 13.0 250 (mA)GATE 15 (mA)GATE200 V (V)GATE1122..50 I I 150 10 11.5 100 11.0 5 50 10.5 0 0 10.0 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G16 4252B12 G17 4252B12 G18 4252b12f 6

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS V vs Temperature V vs Temperature UV Threshold vs Temperature GATEH GATEL 3.6 0.8 3.375 VGATEH = VIN – VGATE, UV/0V = 4V 3.4 IIN = 2mA 0.7 TIMER = 0V (MS ONLY) GATE THRESHOLD 3.275 3.2 0.6 BEFORE RAMP-UP VUVH V)3.175 V (V)GATEH322...086 V (V)GATEL 000...543 THRESHOLD (3.075 VUV V 2.975 U VUVL 2.4 0.2 2.875 2.2 0.1 2.0 0 2.775 –55 –35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G19 4252B12 G20 4252B12 G21 OV Threshold vs Temperature I vs Temperature I vs (V – V ) SENSE SENSE SENSE EE 6.45 –10 0.01 –12 6.25 VOVH –14 0.1 6.05 V) –16 V THRESHOLD (555...864555 VOVL I (A)SENSE–––122802 –I (mA)SENSE 11.00 O –24 5.25 UV/0V = 4V UV/0V = 4V VOV –26 TIMER = 0V 100 TIMER = 0V 5.05 –28 GATE = HIGH GATE = HIGH VSENSE – VEE = 50mV TA = 25°C 4.85 –30 1000 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TEMPERATURE (°C) TEMPERATURE (°C) (VSENSE – VEE) (V) 4252B12 G22 4252B12 G23 4252B12 G24 TIMER Threshold I (Initial Cycle, Sourcing) I (Initial Cycle, Sinking) TMR TMR vs Temperature vs Temperature vs Temperature 5.0 10 50 TIMER = 2V TIMER = 2V 4.5 9 VTMRH 45 4.0 8 D (V) 3.5 7 40 SHOL 3.0 µA) 6 mA) 35 HRE 2.5 (MR 5 (MR 30 R T 2.0 IT 4 IT 25 E M 1.5 3 TI VTMRL 20 1.0 2 0.5 1 15 0 0 10 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G25 4252B12 G26 4252B12 G27 4252b12f 7

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS I (Circuit Breaker, Sourcing) I (Circuit Breaker, I = 50µA, I (Cooling Cycle, Sinking) TMR TMR DRN TMR vs Temperature Sourcing) vs Temperature vs Temperature 280 690 10 TIMER = 2V TIMER = 2V TIMER = 2V IDRN = 0µA 670 IDRN = 50µA 9 260 8 650 7 I (µA)TMR224200 I (µA)TMR661300 I (A)TMR 654 590 3 200 2 570 1 180 550 0 –55–35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G28 4252B12 G29 4252B12 G30 I vs I ∆I /∆I vs Temperature I vs V TMR DRN TMRACC DRN DRN DRAIN 10 9.0 100 TIMER ON IIN = 2mA 8.8 (CIRCUIT BREAKING, 8.6 IDRN = 50µA) 10 µA) 8.4 1 A/ I (mA)TMR 1 /I (µRACCDRN887...208 I (mA)DRN00.0.11 M ∆IT7.6 0.001 125°C 7.4 85°C 0.0001 7.2 25°C –40°C 0.1 7.0 0.00001 0.001 0.01 0.1 1 10 –55 –35 –15 5 25 45 65 85 105 125 0 2 4 6 8 10 12 14 16 IDRN (mA) TEMPERATURE (°C) VDRAIN (V) 4252B12 G31 4252B12 G32 4252B12 G33 V vs Temperature V vs Temperature V vs Temperature DRNL DRNCL PGL 2.60 8.0 3.0 FOR PWRGD STATUS (MS ONLY) IDRN = 50µA (MS ONLY) 7.8 2.55 2.5 7.6 2.50 7.4 2.45 2.0 IPG = 10mA V (V)DRNL 22..4305 V (V)DRNCL776...208 V (V)PGL1.5 6.6 1.0 IPG = 5mA 2.30 6.4 0.5 2.25 6.2 IPG = 1.6mA 2.20 6.0 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G34 4252B12 G35 4252B12 G36 4252b12f 8

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL PERFORMANCE CHARACTERISTICS t and t PLLUG PHLOG I vs Temperature t vs Temperature vs Temperature PGH SS 62 220 0.8 VPWRGD = 0V SS PIN FLOATING, 61 (MS ONLY) 210 VSS RAMPS FROM 0.2V TO 2V 0.7 0.6 60 200 0.5 I (µA)PGH 5598 t (µs)SS119800 DELAY (µs) 00..43 tPLLUtGPHLOG 57 170 0.2 56 160 0.1 55 150 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55–35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252B12 G37 TEMPERATURE (°C) TEMPERATURE (°C) 4252B12 G38 4252B12 G39 PIN FUNCTIONS (MS/MS8) V (Pin 1/Pin 1): Positive Supply Input. Connect this GATE pin is held low until SS exceeds 20 • V = 0.2V. IN OS pin to the positive side of the supply through a dropping SS is internally shunted by a 100k resistor (R ) which SS resistor. A shunt regulator clamps V at 13V. An internal limits the SS pin voltage to 2.2V (50k resistor and 1.4V IN undervoltage lockout (UVLO) circuit holds GATE low until for the LTC4252C). This corresponds to an analog current the V pin is greater than V , overriding UV and OV. If limit SENSE voltage of 100mV (60mV for the LTC4252C). If IN LKO UV is high, OV is low and V comes out of UVLO, TIMER the SS capacitor is omitted, the SS pin ramps up in about IN starts an initial timing cycle before initiating a GATE ramp- 180µs. The SS pin is pulled low under any of the following up. If V drops below approximately 8.2V, GATE pulls conditions: in UVLO, in an undervoltage condition, in an IN low immediately. overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. PWRGD (Pin 2/Not Available): Power Good Status Output (MS only). At start-up, PWRGD latches low if DRAIN is SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense below 2.385V and GATE is within 2.8V of V . PWRGD Pin. Load current is monitored by a sense resistor R con- IN S status is reset by UV, V (UVLO) or a circuit breaker nected betweenSENSE and V , and controlled in three IN EE fault timeout. This pin is internally pulled high by a 58µA steps.If SENSE exceeds V (50mV), the circuit breaker CB current source. comparator activates a (230µA + 8 • I ) TIMER pull-up DRN current. If SENSE exceeds V , the analog current limit SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp ACL amplifier pulls GATE down to regulate the MOSFET current inrush current during start up, thereby effecting control at V /R . In the event of a catastrophic short-circuit, over di/dt. A 20x attenuated version of the SS pin voltage ACL S SENSE may overshoot. If SENSE reaches V (200mV), is presented to the current limit amplifier. This attenuated FCL the fast current limit comparator pulls GATE low with a voltage limits the MOSFET’s drain current through the sense strong pull-down. To disable the circuit breaker and cur- resistor during the soft-start current limiting. At the begin- rent limit functions, connect SENSEto V . ning of a start-up cycle, the SS capacitor (C ) is ramped EE SS by a 22µA (28µA for the LTC4252C) current source. The 4252b12f 9

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 PIN FUNCTIONS (MS/MS8) V (Pin 5/Pin 4): Negative Supply Voltage Input. Connect UV (Pin 9/Pin 7): Undervoltage Input. The active low thresh- EE this pin to the negative side of the power supply. old at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V, PWRGD pulls high, both GATE and TIMER GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output. pull low. If UV rises above 3.225V, this initiates an initial This pin is pulled high by a 58µA current source. GATE is timing cycle followed by GATE start-up. The LTC4252C pulled low by invalid conditions at V (UVLO), UV, OV, or IN UV pin is set at 3.08V with 324mV hysteresis. If UV < a circuit breaker fault timeout. GATE is actively servoed to 2.756V, PWRGD pulls high, both GATE and TIMER pull control the fault current as measured at SENSE. A compen- low. If UV rises above 3.08V, this initiates an initial timing sation capacitor at GATE stabilizes this loop. A comparator cycle followed by GATE start-up. The internal UVLO at V monitors GATE to ensure that it is low before allowing an IN always overrides UV. A low at UV resets an internal fault initial timing cycle, GATE ramp-up after an overvoltage latch. A 1nF to 10nF capacitor at UV prevents transients event or restart after a current limit fault. During GATE and switching noise from affecting the UV thresholds and start-up, a second comparator detects if GATE is within prevents glitches at the GATE pin. 2.8V of V before PWRGD is set (MS package only). IN TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to DRAIN (Pin 7/Pin 6): Drain Sense Input. Connecting an generate an initial timing delay at start-up and to delay external resistor, R ,between this pin and the MOSFET’s D shutdown in the event of an output overload (circuit drain (V ) allows voltage sensing below 6.15V (5V for OUT breaker fault). TIMER starts an initial timing cycle when LTC4252C) and current feedback to TIMER. A comparator the following conditions are met: UV is high, OV is low, V detects if DRAIN is below 2.385V and together with the IN clears UVLO, TIMER pin is low, GATE is lower than V , GATE high comparator sets the PWRGD flag. If V is GATEL OUT SS < 0.2V, and V – V < V . A pull-up current above V , DRAIN clamps at approximately V . SENSE EE CB DRNCL DRNCL of 5.8µA then charges C , generating a time delay. If C The current through R is internally multiplied by 8 and T T D charges to V (4V), the timing cycle terminates, TIMER added to TIMER’s 230µA pull-up current during a circuit TMRH quickly pulls low and GATE is activated. breaker fault cycle. This reduces the fault time and MOS- FET heating. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 230µA pull-up current charging C . OV (Pin 8/Pin 7): Overvoltage Input. The active high thresh- T If DRAIN is approximately 7V (6V for LTC4252C) during old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV this cycle, the timer pull-up has an additional current > 6.15V, GATE pulls low. When OV returns below 5.55V, of 8 • I . If SENSE drops below 50mV before TIMER GATE start-up begins without an initial timing cycle. The DRN reaches 4V, a 5.8µA pull-down current slowly discharges LTC4252C OV pin is set at 5.09V with 102mV hysteresis. the C . In the event that C eventually integrates up to the If OV > 5.09V, GATE pulls low. When OV returns below T T V threshold, the circuit breaker trips, GATE quickly 4.988V, GATE start-up begins without an initial timing TMRH pulls low and PWRGD pulls high. The LTC4252-1 TIMER cycle. If an overvoltage condition occurs in the middle of pin latches high with a 5.8µA pull-up source. This latched an initial timing cycle, the initial timing cycle is restarted fault is cleared by either pulling TIMER low with an external after the overvoltage condition goes away. An overvoltage device or by pulling UV below V . The LTC4252-2 starts condition does not reset the PWRGD flag. The internal UVLO UVLO a shutdown cooling cycle following an overcurrent fault. at V always overrides OV. A 1nF to 10nF capacitor at OV IN This cycle consists of 4 discharging ramps and 3 charging prevents transients and switching noise from affecting ramps. The charging and discharging currents are 5.8µA the OV thresholds and prevents glitches at the GATE pin. and TIMER ramps between its 1V and 4V thresholds. At the completion of a shutdown cooling cycle, the LTC4252-2 attempts a start-up cycle. 4252b12f 10

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 BLOCK DIAGRAM VIN – DRAIN + 2.385V VIN 6.15V 8× 1× VEE (5V) 1× 1× VIN 58µA VEE PWRGD ** VIN 6.15V – (5.09V) 58µA VEE OV * + GATE 2.8V UV * – (+) VEE – –+ VIN + 2.925V + (–) VIN (3.08V) 230µA VIN LOGIC – 4V – 5.8µA + + 0.5V TIMER + – FCL 200mV VEE 5.8µA 1V + – +– VEE VIN VEE 22µA (28µA) SS + 95k VOS = 10mV ACL (47.5k) –+ – RSS VEE 5k VEE + SENSE (2.5k) VEE CB 50mV – +– VEE 4252B12 BD VEE *OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE ** ONLY AVAILABLE IN THE MS PACKAGE FOR COMPONENTS, CURRENT AND VOLTAGE WITH TWO VALUES, VALUES IN PARENTHESES REFER TO THE LTC4252C. VALUES WITHOUT PARENTHESES REFER TO THE LTC4252B 4252b12f 11

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 OPERATION Hot Circuit Insertion Interlock Conditions When circuit boards are inserted into a live backplane, the A start-up sequence commences once these “interlock” supply bypass capacitors can draw huge transient currents conditions are met. from the power bus as they charge. The flow of current 1. The input voltage V exceeds V (UVLO). IN LKO damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4252 2. The voltage at UV > VUVHI. is designed to turn on a circuit board supply in a controlled 3. The voltage at OV < V . OVLO manner, allowing insertion or removal without glitches or 4. The (SENSE – V ) voltage is < 50mV (V ). connector damage. EE CB 5. The voltage at SS is < 0.2V (20 • V ). OS Initial Start-Up 6. The voltage on the TIMER capacitor (C ) is < 1V (V ). T TMRL The LTC4252 resides on a removable circuit board and 7. The voltage at GATE is < 0.5V (V ). controls the path between the connector and load or power GATEL conversion circuitry with an external MOSFET switch (see The first three conditions are continuously monitored and Figure 1). Both inrush control and short-circuit protection the latter four are checked prior to initial timing or GATE are provided by the MOSFET. ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in A detailed schematic for the LTC4252C is shown in Figure 2. the Applications Information, Timing Waveforms section. –48V and –48RTN receive power through the longest con- nector pins and are the first to connect when the board is TIMER begins the start-up sequence by sourcing 5.8µA inserted. The GATE pin holds the MOSFET off during this into C . If V , UV or OV falls out of range, the start-up T IN time. UV and OV determine whether or not the MOSFET cycle stops and TIMER discharges C to less than 1V, then T should be turned on based upon internal high accuracy waits until the aforementioned conditions are once again thresholds and an external divider. UV and OV do double met. If C successfully charges to 4V, TIMER pulls low T duty by also monitoring whether or not the connector is and both SS and GATE pins are released. GATE sources seated. The top of the divider detects –48RTN by way of 58µA (I ), charging the MOSFET gate and associated GATE a short connector pin that is the last to mate during the capacitance. The SS voltage ramp limits V to control SENSE insertion sequence. the inrush current. PWRGD pulls active low when GATE is within 2.8V of V and DRAIN is lower than V . IN DRNL PLUG-IN BOARD LONG LONG –48RTN –48RTN LTC4252 + +ISOLATED+ LOW DDZD1IN3+B** 3 × 1.8k1 I/N4W S EERARICEIHSN C1L0O0AµDF+ DC/DC CLOAD CONVERTER VCOIRLCTAUGITERY SHORT R1 CIN LONG MODULE 392k 1µF OV VIN –48V – – 1% UV LTC4252C-1 BACKPLANE C1 TIMER 4252B12 F01 10nF SS DRAIN Figure 1. Basic LTC4252 Hot Swap Topology CSS VEE SENSE GATE 30.R12k 68nF RD 1% C0.T68µF CC 1R0CΩ 1M 10nF LONG –48V RS Q1 4252B12 F02 **DIODES, INC 0.02Ω IRF530S † RECOMMENDED FOR HARSH ENVIRONMENTS Figure 2. –48V, 2.5A Hot Swap Controller 4252b12f 12

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 OPERATION Two modes of operation are possible during the time the Higher overloads are handled by an analog current limit MOSFET is first turning on, depending on the values of loop. If the drop across R reaches V , the current S ACL external components, MOSFET characteristics and nominal limiting loop servos the MOSFET gate and maintains a design current. One possibility is that the MOSFET will turn constant output current of V /R . In current limit mode, ACL S on gradually so that the inrush into the load capacitance V typically rises and this increases MOSFET heating. OUT remains a low value. The output will simply ramp to –48V If V > V , connecting an external resistor, R , OUT DRNCL D and the LTC4252 will fully enhance the MOSFET. A second between V and DRAIN allows the fault timing cycle to OUT possibility is that the load current exceeds the soft-start be shortened by accelerating the charging of the TIMER current limit threshold of [V (t)/20 – V ]/R . In this case capacitor. The TIMER pull-up current is increased by 8 • SS OS S the LTC4252 will ramp the output by sourcing soft-start I . Note that because SENSE > 50mV, TIMER charges DRN limited current into the load capacitance. If the soft-start C during this time and the LTC4252 will eventually shut T voltage is below 1.2V, the circuit breaker TIMER is held down. low. Above 1.2V, TIMER ramps up. It is important to set Low impedance failures on the load side of the LTC4252 the timer delay so that, regardless of which start-up mode coupled with 48V or more driving potential can produce is used, the TIMER ramp is less than one circuit breaker current slew rates well in excess of 50A/µs. Under these delay time. If this condition is not met, the LTC4252-1 may conditions, overshoot is inevitable. A fast SENSE com- shut down after one circuit breaker delay time whereas parator with a threshold of 200mV detects overshoot and the LTC4252-2 may continue to autoretry. pulls GATE low much harder and hence much faster than the weaker current limit loop. The V /R current limit Board Removal ACL S loop then takes over and servos the current as previously If the board is withdrawn from the card cage, the UV and described. As before, TIMER runs and shuts down the OV divider is the first to lose connection. This shuts off LTC4252 when C reaches 4V. T the MOSFET and commutates the flow of current in the If C reaches 4V, the LTC4252-1 latches off with a 5.8µA connector. When the power pins subsequently separate, T pull-up current source whereas the LTC4252-2 starts a there is no arcing. shutdown cooling cycle. The LTC4252-1 circuit breaker latch is reset by either pulling UV momentarily low or Current Control dropping the input voltage V below the internal UVLO IN Three levels of protection handle short-circuit and over- threshold or pulling TIMER momentarily low with a switch. load conditions. Load current is monitored by SENSE and The LTC4252-2 retries after its shutdown cooling cycle. resistor R . There are three distinct thresholds at SENSE: S Although short-circuits are the most obvious fault type, 50mV for a timed circuit breaker function; 100mV for an several operating conditions may invoke overcurrent analog current limit loop (60mV for the LTC4252C); and protection. Noise spikes from the backplane or load, input 200mV for a fast, feedforward comparator which limits steps caused by the connection of a second, higher voltage peak current in the event of a catastrophic short-circuit. supply, transient currents caused by faults on adjacent If, owing to an output overload, the voltage drop across R S circuit boards sharing the same power bus or the inser- exceeds 50mV, TIMER sources 230µA into C . C even- T T tion of non-hot-swappable products could cause higher tually charges to a 4V threshold and the LTC4252 shuts than anticipated input current and temporary detection off. If the overload goes away before C reaches 4V and T of an overcurrent condition. The action of TIMER and C T SENSE measures less than 50mV, C slowly discharges T rejects these events allowing the LTC4252 to “ride out” (5.8µA). In this way the LTC4252’s circuit breaker function temporary overloads and disturbances that could trip a responds to low duty cycle overloads and accounts for fast simple current comparator and, in some cases, blow a fuse. heating and slow cooling characteristics of the MOSFET. 4252b12f 13

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION SHUNT REGULATOR Kelvin terminal as illustrated in Figure 3, keeping trace lengths between V , C , D and V as short as possible. A fast responding shunt regulator clamps the V pin to 13V IN IN IN EE IN (VZ). Power is derived from –48RTN by an external current limiting resistor, R . A 1µF decoupling capacitor, C filters INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) IN IN supply transients and contributes a short delay at start-up. A hysteretic comparator, UVLO, monitors V for undervolt- IN To meet creepage requirements RIN may be split into two or age. The thresholds are defined by VLKO and its hysteresis, more series connected units. This introduces a wider total VLKH. When VIN rises above VLKO the chip is enabled; below spacing than is possible with a single component while at (VLKO – VLKH) it is disabled and GATE is pulled low. The the same time ballasting the potential across the gap under UVLO function at VIN should not be confused with the each resistor. The LTC4252 is fundamentally a low voltage UV/OV pin(s). These are completely separate functions. device that operates with –48V as its reference ground. To further protect against arc discharge into its pins, the area UV/OV COMPARATORS (LTC4252B) in and around the LTC4252 and all associated components An UV hysteretic comparator detects undervoltage condi- should be free of any other planes such as chassis ground, tions at the UV pin, with the following thresholds: return, or secondary-side power and ground planes. UV low-to-high (V ) = 3.225V V may be biased with additional current up to 30mA to UVHI IN accommodate external loading such as the PWRGD opto- UV high-to-low (V ) = 2.925V UVLO coupler shown in Figure 23. As an alternative to running An OV hysteretic comparator detects overvoltage condi- higher current, simply buffer V with an emitter follower IN tions at the OV pin, with the following thresholds: as shown in Figure 3. Another method shown in Figure 19 cascodes the PWRGD output. OV low-to-high (VOVHI) = 6.150V VIN is rated handle 30mA within the thermal limits of the OV high-to-low (VOVLO) = 5.550V package, and is tested to survive a 100µs, 100mA pulse. To The UV and OV trip point ratio is designed to match the protect V against damage from higher amplitude spikes, IN standard telecom operating range of 43V to 82V when con- clamp V to V with a 13V Zener diode. Star connect IN EE nected together as in the typical application. A divider (R1, V and all V -referred components to the sense resistor EE EE R2) is used to scale the supply voltage. Using R1 = 402k –48RTN RIN + 10k R4 CL 1/2W 22k 100µF Q2 † –48RTN 1 DDIDNZ13B** 1CµINF R5 LOAD (SHORT PIN) 2.2k R1 VIN EN 432k LTC4252B-1 1% 9 2 * UV PWRGD R2 8 7 RD 1M 4.75k OV DRAIN 1% 10 6 Q1 TIMER GATE IRF530S 381.R3%3k C102nF C33T0nF 3 SC6S8SnSF VEE5 SENSE 4 R10CCΩC R0.S02Ω 18nF –48V * M0C207 **DIODES, INC 4252B12 F03 Q2: MMBT5551LT1 †RECOMMENDED FOR HARSH ENVIRONMENTS Figure 3. –48V/2.5A Application with Different Input Operating Range 4252b12f 14

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION and R2 = 32.4k gives a typical operating range of 43.2V OV low-to-high (V ) = 5.09V OV to 82.5V. The undervoltage shutdown and overvoltage OV high-to-low (V – V ) = 4.988V OV OVHST recovery thresholds are then 39.2V and 74.4V. 1% divider resistors are recommended to preserve threshold accuracy. The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 71V when The R1-R2 divider values shown in the Typical Application connected together as in Figure 2. A divider (R1, R2) is set a standing current of slightly more than 100µA and used to scale the supply voltage. Using R1 = 390k and R2 define an impedance at UV/OV of 30kΩ. In most applica- = 30.1k gives a typical operating range of 43V to 71V. The tions, 30kΩ impedance coupled with 300mV UV hysteresis undervoltage shutdown and overvoltage recovery thresh- makes the LTC4252B insensitive to noise. If more noise olds are then 38.5V and 69.6V respectively. 1% divider immunity is desired, add a 1nF to 10nF filter capacitor resistors are recommended to preserve threshold accuracy. from UV/OV to V . EE The R1-R2 divider values shown in Figure 2 set a standing Separate UV and OV pins are available in the 10-pin MS current of slightly more than 100µA and define an impedance package and can be used for a different operating range at UV/OV of 28kΩ. In most applications, 28kΩ impedance such as 35.5V to 76V as shown in Figure 3. Other combi- coupled with 324mV UV hysteresis makes the LTC4252C nations are possible with different resistor arrangements. insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to V . EE UV/OV COMPARATORS (LTC4252C) The UV and OV pins can be used for a wider operat- A UV hysteretic comparator detects undervoltage condi- ing range such as 35.5V to 76V as shown in Figure 4. tions at the UV pin, with the following thresholds: Other combinations are possible with different resistor arrangements. UV low-to-high (V ) = 3.08V UV UV high-to-low (V – V ) = 2.756V UV UVHST UV/OV OPERATION An OV hysteretic comparator detects overvoltage condi- A low input to the UV comparator will reset the chip and pull tions at the OV pin, with the following thresholds: the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock –48RTN RIN + 10k R4 CL 1/2W 22k 100µF Q2 † –48RTN 1 DDIDNZ13B** 1CµINF R5 LOAD (SHORT PIN) 2.2k R1 VIN EN 464k LTC4252C-1 1% 9 2 * UV PWRGD R2 8 7 RD 1M 10k OV DRAIN 1% 10 6 Q1 TIMER GATE IRF530S 3R43k C0.T68µF 3 SS VEE SENSE 4 1% C2 CSS 5 R10CΩ R0.S02Ω 10nF 68nF CC 10nF –48V * M0C207 **DIODES, INC 4252B12 F04 † Q2: MMBT5551LT1 RECOMMENDED FOR HARSH ENVIRONMENTS Figure 4. –48V/2.5A Application with Wider Input Operating Range 4252b12f 15

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION conditions are met. A high-to-low transition in the UV 4) Low impedance switch; resets the TIMER capacitor comparator immediately shuts down the LTC4252, pulls after an initial timing delay, in UVLO, in UV and in OV the MOSFET gate low and resets the latched PWRGD high. during initial timing. Overvoltage conditions detected by the OV comparator For initial start-up, the 5.8µA pull-up is used. The low will also pull GATE low, thereby shutting down the load. impedance switch is turned off and the 5.8µA current However, it will not reset the circuit breaker TIMER, source is enabled when the interlock conditions are met. PWRGD flag or shutdown cooling timer. Returning the C charges to 4V in a time period given by: T supply voltage to an acceptable range restarts the GATE 4V•C pin if all the interlock conditions except TIMER are met. t= T (2) 5.8µA Only during the initial timing cycle does an OV condition reset the TIMER. When C reaches 4V (V ), the low impedance switch T TMRH turns on and discharges C . A GATE start-up cycle begins T DRAIN and both SS and GATE are released. Connecting an external resistor, R , to the dual function D DRAIN pin allows V sensing* without it being dam- CIRCUIT BREAKER TIMER OPERATION OUT aged by large voltage transients. Below 5V, negligible pin If the SENSE pin detects more than a 50mV drop across leakage allows a DRAIN low comparator to detect V OUT R , the TIMER pin charges C with (230µA + 8 • I ). If C S T DRN T less than 2.385V (V ). This condition, together with DRNL charges to 4V, the GATE pin pulls low and the LTC4252-1 the GATE low comparator, sets the PWRGD flag. latches off while the LTC4252-2 starts a shutdown cooling If V > V , the DRAIN pin is clamped at about cycle. The LTC4252-1 remains latched off until the UV OUT DRNCL V and the current flowing in R is given by: pin is momentarily pulsed low or TIMER is momentarily DRNCL D discharged low by an external switch or V dips below IN V -V I ≈ OUT DRNCL (1) UVLO and is then restored. The circuit breaker timeout DRN R period is given by: D This current is scaled up 8 times during a circuit breaker 4V•C fault and is added to the nominal 230µA TIMER current. t= T (3) 230µA+8•I This accelerates the fault TIMER pull-up when the MOS- DRN FET’s drain-source voltage exceeds V and effectively DRNCL If V < 5V, an internal PMOS device isolates any DRAIN OUT shortens the MOSFET heating duration. pin leakage current, making I = 0µA in Equation (3). DRN If V > V during the circuit breaker fault period, OUT DRNCL TIMER the charging of C accelerates by 8 • I of Equation (1). T DRN The operation of the TIMER pin is somewhat complex as Intermittent overloads may exceed the 50mV threshold at it handles several key functions. A capacitor C is used at SENSE, but, if their duration is sufficiently short, TIMER T TIMER to provide timing for the LTC4252. Four different will not reach 4V and the LTC4252 will not shut the external charging and discharging modes are available at TIMER: MOSFET off. To handle this situation, the TIMER discharges C slowly with a 5.8µA pull-down whenever the SENSE 1) A 5.8µA slow charge; initial timing and shutdown cool- T voltage is less than 50mV. Therefore, any intermittent ing delay. overload with V > 5V and an aggregate duty cycle of OUT 2) A (230µA + 8 • I ) fast charge; circuit breaker delay. DRN *VOUT as viewed by the MOSFET; i.e., VDS. 3) A 5.8µA slow discharge; circuit breaker “cool off” and shutdown cooling. 4252b12f 16

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION SOFT-START 10 IDRN = 0µA F) Soft-start limits the inrush current profile during GATE µ s/ E ( start-up. Unduly long soft-start intervals can exceed the M TI 1 MOSFET’s SOA rating if powering up into an active load. E S t 4 ON = If SS floats, an internal current source ramps SS from 0V ESP CT(µF) [(235.8 + 8 • IDRN) • D – 5.8] to 2.2V for the LTC4252B or 0V to 1.4V for the LTC4252C R D ZE 0.1 in about 230µs. Connecting an external capacitor CSS LI A from SS to ground modifies the ramp to approximate an M R O RC response of: N 0.01 0 20 40 60 80 100   t   – FAULT DUTY CYCLE (%) 4252B12 F05 V (t)≈V •1–e RSS•CSS  (6) SS SS   Figure 5. Circuit-Breaker Response Time     An internal resistive divider (95k/5k for the LTC4252B or 2.5% or more will eventually trip the circuit breaker and 47.5k/2.5k for the LTC4252C) scales V (t) down by 20 shut down the LTC4252. Figure 5 shows the circuit breaker SS times to give the analog current limit threshold: response time in seconds normalized to 1µF for I = DRN 0µA. The asymmetric charging and discharging of CT is V (t) V (t)= SS –V (7) a fair gauge of MOSFET heating. ACL OS 20 The normalized circuit response time is estimated by This allows the inrush current to be limited to V (t)/R . ACL S t 4 The offset voltage, V (10mV), ensures C is sufficiently = (4) OS SS C (µF) (235.8+8•I )•D–5.8 discharged and the ACL amplifier is in current limit before T  DRN  GATE start-up. SS is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an SHUTDOWN COOLING CYCLE overvoltage condition, during the initial timing cycle or For the LTC4252-1 (latchoff version), TIMER latches high when the circuit breaker fault times out. with a 5.8µA pull-up after the circuit breaker fault TIMER reaches 4V. For the LTC4252-2 (automatic retry ver- GATE sion), a shutdown cooling cycle begins if TIMER reaches the 4V threshold. TIMER starts with a 5.8µA pull-down GATE is pulled low to VEE under any of the following until it reaches the 1V threshold. Then, the 5.8µA pull-up conditions: in UVLO, in an undervoltage condition, in an turns back on until TIMER reaches the 4V threshold. Four overvoltage condition, during the initial timing cycle or 5.8µA pull-down cycles and three 5.8µA pull-up cycles when the circuit breaker fault times out. When GATE turns occur between the 1V and 4V thresholds, creating a time on, a 58µA current source charges the MOSFET gate and interval given by: any associated external capacitance. VIN limits the gate drive to no more than 14.5V. 7•3V•C tSHUTDOWN= 5.8µAT (5) Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit At the 1V threshold of the last pull-down cycle, a GATE pulls GATE low with practically no usable voltage at V ramp-up is attempted. IN 4252b12f 17

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION and eliminates current spikes at insertion. A large external SHORT-CIRCUIT OPERATION gate-source capacitor is thus unnecessary for the purpose Circuit behavior arising from a load side low impedance of compensating C . Instead, a smaller value (≥ 10nF) GD short is shown in Figure 6 for the LTC4252. Initially, the capacitor C is adequate. C also provides compensation C C current overshoots the fast current limit level of V = SENSE for the analog current limit loop. 200mV (Trace 2) as the GATE pin works to bring V under GS GATE has two comparators: the GATE low comparator control (Trace 3). The overshoot glitches the backplane looks for < 0.5V threshold prior to initial timing or a GATE in the negative direction and when the current is reduced start-up cycle; the GATE high comparator looks for < 2.8V to 100mV/R , the backplane responds by glitching in the S relative to V and, together with the DRAIN low compara- positive direction. IN tor, sets PWRGD status during GATE startup. TIMER commences charging C (Trace 4) while the analog T current limit loop maintains the fault current at 100mV/R , S SENSE which in this case is 5A (Trace 2). Note that the backplane The SENSE pin is monitored by the circuit breaker (CB) voltage (Trace 1) sags under load. Timer pull-up is ac- comparator, the analog current limit (ACL) amplifier and celerated by V . When C reaches 4V, GATE turns off, OUT T the fast current limit (FCL) comparator. Each of these three PWRGD pulls high, the load current drops to zero and the measures the potential of SENSE relative to V . When backplane rings up to over 100V. The transient associated EE SENSE exceeds 50mV, the CB comparator activates the with the GATE turn off can be controlled with a snubber to 230µA TIMER pull-up. At 100mV (60mV for the LTC4252C), reduce ringing and a transient voltage suppressor (such as the ACL amplifier servos the MOSFET current and, at Diodes Inc. SMAT70A) to clip off large spikes. The choice 200mV, the FCL comparator abruptly pulls GATE low in of RC for the snubber is usually done experimentally. The an attempt to bring the MOSFET current under control. If value of the snubber capacitor is usually chosen between any of these conditions persists long enough for TIMER 10 to 100 times the MOSFET C . The value of the snub- OSS to charge C to 4V (see Equation 3), the LTC4252 shuts ber resistor is typically between 3Ω to 100Ω. T down and pulls GATE low. If the SENSE pin encounters a voltage greater than VACL, SUPPLY RING OWING TO SUPPLY RING OWING TO CURRENT OVERSHOOT MOSFET TURN OFF the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the –48RTN MOSFET in normal operation, the ACL amplifier needs time 50V/DIV to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator ONSET OF OUTPUT SHORT-CIRCUIT SENSE takes over, quickly discharging the GATE pin to near V 200mV/DIV EE potential. FCL then releases and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is GATE FAST CURRENT LIMIT 10V/DIV to add a nonlinear response to the control loop in favor of reducing MOSFET current. ANALOG CURRENT LIMIT TIMER 5V/DIV Owing to inductive effects in the system, FCL typically over LATCH OFF CTIMER RAMP corrects the current limit loop and GATE undershoots. A 0.5ms/DIV 4252B12 F06 zero in the loop (resistor R in series with the gate capaci- C Figure 6. Output Short-Circuit Behavior of LTC4252 tor) helps the ACL amplifier to recover. 4252b12f 18

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION A low impedance short on one card may influence the To begin a design, first specify the required load current behavior of others sharing the same backplane. The initial and Ioad capacitance, I and C . The circuit breaker cur- L L glitch and backplane sag as seen in Figure 6 Trace 1, can rent trip point (V /R ) should be set to accommodate CB S rob charge from output capacitors on adjacent cards. the maximum load current. Note that maximum input When the faulty card shuts down, current flows in to current to a DC/DC converter is expected at V . SUPPLY(MIN) refresh the capacitors. If LTC4252s are used by the other R is given by: S cards, they respond by limiting the inrush current to a V CB(MIN) R = (8) wvaillul ree ocfh 1a0rg0em lVon/RgS b. eIff oCrTe i sC s itziemde cso orruetc.tly, the capacitors S IL(MAX) T where V = 40mV (45mV for LTC4252C) represents CB(MIN) the guaranteed minimum circuit breaker threshold. POWER GOOD, PWRGD During the initial charging process, the LTC4252B may PWRGD latches low if GATE charges up to within 2.8V of operate the MOSFET in current limit, forcing (V ) between V and DRAIN pulls below V during start-up. PWRGD ACL IN DRNL 80mV to 120mV (V is 54mV to 66mV for LTC4252C) is reset in UVLO, in a UV condition or if C charges up to ACL T across R . The minimum inrush current is given by: 4V. An overvoltage condition has no effect on PWRGD S status. A 58µA current pulls this pin high during reset. 80mV I = (9) Due to voltage transients between the power module and INRUSH(MIN) R PWRGD, optoisolation is recommended. This pin provides S sufficient drive for an opto-coupler. Figure 19 shows an Maximum short-circuit current limit is calculated using alternative NPN configuration with a limiting base resistor the maximum V . This gives ACL for the PWRGD interface. The module enable input should 120mV have protection from the negative input current. I = (10) SHORTCIRCUIT(MAX) R S MOSFET SELECTION The TIMER capacitor C must be selected based on the T slowest expected charging rate; otherwise TIMER might The external MOSFET switch must have adequate safe time out before the load capacitor is fully charged. A value operating area (SOA) to handle short-circuit conditions for C is calculated based on the maximum time it takes until TIMER times out. These considerations take prece- T the load capacitor to charge. That time is given by: dence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required C•V C •V L SUPPLY(MAX) current, but the opposite may not be true. Consult the tCL(CHARGE)= = (11) I I manufacturer’s MOSFET data sheet for safe operating INRUSH(MIN) area and effective transient thermal impedance curves. The maximum current flowing in the DRAIN pin is given by: MOSFET selection is a 3-step process by assuming the V –V SUPPLY(MAX) DRNCL absence of a soft-start capacitor. First, R is calculated I = (12) S DRN(MAX) R and then the time required to charge the load capacitance D is determined. This timing, along with the maximum short-circuit current and maximum input voltage defines an operating point that is checked against the MOSFET’s SOA curve. 4252b12f 19

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Approximating a linear charging rate as I drops from was appropriate. The ratio (R • C ) to t is DRN SS SS CL(CHARGE) I to zero, the I component in Equation (3) a good gauge as a large ratio may result in the time-out DRN(MAX) DRN can be approximated with 0.5 • I . Rearranging period expiring. This gauge is determined empirically with DRN(MAX) equation, TIMER capacitor C is given by: board level evaluation. T ( ) t • 230µA+4•I CL(CHARGE) DRN(MAX) SUMMARY OF DESIGN FLOW C = (13) T 4V To summarize the design flow, consider the application Returning to Equation (3), the TIMER period is calcu- shown in Figure 2 with the LTC4252C. It was designed lated and used in conjunction with V and for 80W. SUPPLY(MAX) I to check the SOA curves of a prospec- SHORTCIRCUIT(MAX) Calculate the maximum load current: 80W/43V = 1.86A; tive MOSFET. allowing for 83% converter efficiency, I = 2.2A. IN(MAX) As a numerical design example, consider a 30W load, Calculate R : from Equation (8) R = 20mΩ. S S which requires 1A input current at 36V. If V SUPPLY(MAX) = 72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS Calculate ISHORTCIRCUIT(MAX): from Equation (10) = 40mΩ; Equation (13) gives C = 441nF. To account for T 66mV errors in R , C , TIMER current (230µA), TIMER threshold I = =3.3A S T SHORTCIRCUIT(MAX) 20mΩ (4V), R , DRAIN current multiplier and DRAIN voltage D clamp (V ), the calculated value should be multiplied Select a MOSFET that can handle 3.3A at 71V: IRF530S. DRNCL by 1.5, giving the nearest standard value of C = 680nF. T Calculate C : from Equation (13) C = 322nF. Select T T If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A C  = 680nF, which gives the circuit breaker time-out T will flow in the MOSFET for 5.6ms as dictated by C  = 680nF period t = 5.6ms. T in Equation (3). The MOSFET must be selected based on Consult MOSFET SOA curves: the IRF530S can handle 3.3A this criterion. The IRF530S can handle 100V and 3A for at 100V for 8.2ms, so it is safe to use in this application. 10ms and is safe to use in this application. Calculate C : using Equations (14) and (15) select SS Computing the maximum soft-start capacitor value during C  = 68nF. SS soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the R C response. SS SS FREQUENCY COMPENSATION An overly conservative but simple approach begins with the maximum circuit breaker current, given by: The LTC4252C typical frequency compensation network for V the analog current limit loop is a series RC (10Ω) and CC CB(MAX) I = (14) connected to V . Figure 7 depicts the relationship between CB(MAX) EE R S the compensation capacitor C and the MOSFET’s C . C ISS where VCB(MAX) = 60mV (55mV for the LTC4252C). The line in Figure 7 is used to select a starting value for CC based upon the MOSFET’s C specification. Optimized From the SOA curves of a prospective MOSFET, determine ISS values for C are shown for several popular MOSFETs. the time allowed, t . C is given by: C SOA(MAX) SS Differences in the optimized value of C versus the starting t C SOA(MAX) C = (15) value are small. Nevertheless, compensation values should SS 0.916•RSS be verified by board level short-circuit testing. In the above example, 60mV/40mΩ gives 1.5A. t SOA(MAX) for the IRF530S is 40ms. From Equation (15), C = SS 437nF. Actual board evaluation showed that C = 100nF SS 4252b12f 20

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION 60 CURRENT FLOW CURRENT FLOW NTY100N10 FROM LOAD TO –48V BACKPLANE F) n (C 50 C E SENSE RESISTOR C AN 40 TRACK WIDTH W: CIT 0.03" PER AMP W A ON 1 OZ COPPER AP 30 C N TIO 20 IRF540S IRF3710 SA 4252B12 F08 N E MP 10 IRF530S O IRF740 C TO TO 0 0 2000 4000 6000 8000 SENSE VEE MOSFET CISS (pF) Figure 8. Making PCB Connections to the Sense Resistor 4252B12 F07 Figure 7. Recommended Compensation Capacitor C vs MOSFET C time point 1, the supply ramps up, together with UV/OV, C ISS V and DRAIN. V and PWRGD follow at a slower rate OUT IN as set by the V bypass capacitor. At time point 2, V As seen in Figure 6 previously, at the onset of a short- IN IN exceeds V and the internal logic checks for UV > V , circuit event, the input supply voltage can ring dramatically LKO UVHI OV < V , GATE < V , SENSE < V , SS < 20 • V owing to series inductance. If this voltage avalanches the OVLO GATEL CB OS and TIMER < V . If all conditions are met, an initial MOSFET, current continues to flow through the MOSFET TMRL timing cycle starts and the TIMER capacitor is charged to the output. The analog current limit loop cannot control by a 5.8µA current source pull-up. At time point 3, TIMER this current flow and therefore the loop undershoots. This reaches the V threshold and the initial timing cycle effect cannot be eliminated by frequency compensation. A TMRH terminates. The TIMER capacitor is quickly discharged. At Zener diode is required to clamp the input supply voltage time point 4, the V threshold is reached and the condi- and prevent MOSFET avalanche. TMRL tions of GATE < V , SENSE < V and SS < 20 • V GATEL CB OS must be satisfied before a GATE ramp-up cycle begins. SENSE RESISTOR CONSIDERATIONS SS ramps up as dictated by R • C (as in Equation 6); SS SS For proper circuit breaker operation, Kelvin-sense PCB GATE is held low by the analog current limit (ACL) ampli- connections between the sense resistor and the LTC4252’s fier until SS crosses 20 • V . Upon releasing GATE, 58µA OS V and SENSE pins are strongly recommended. The sources into the external MOSFET gate and compensation EE drawing in Figure 8 illustrates the correct way of making network. When the GATE voltage reaches the MOSFET’s connections between the LTC4252 and the sense resis- threshold, current begins flowing into the load capacitor tor. PCB layout should be balanced and symmetrical to at time point 5. At time point 6, load current reaches the minimize wiring errors. In addition, the PCB layout for the SS control level and the analog current limit loop activates. sense resistor should include good thermal management Between time points 6 and 8, the GATE voltage is servoed, techniques for optimal sense resistor power dissipation. the SENSE voltage is regulated at V (t) (Equation 7) and ACL soft-start limits the slew rate of the load current. If the SENSE voltage (V – V ) reaches the V threshold TIMING WAVEFORMS SENSE EE CB at time point 7, the circuit breaker TIMER activates. The System Power-Up TIMER capacitor, CT, is charged by a (230µA + 8 • IDRN) current pull-up. As the load capacitor nears full charge, Figure 9 details the timing waveforms for a typical power- load current begins to decline. up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At 4252b12f 21

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 56 7 891011 GND – VEE OR (–48RTN) – (–48V) UV/OV VIN VLKO VTMRH TIMER 5.8µA 230µA + 8 • IDRN 5.8µA VTMRL 5.8µA 58µA VIN – VGATEH GATE VGATEL 58µA 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VOUT VDRNCL DRAIN VDRNL PWRGD GATE 4252B12 F09 INITIAL TIMING START-UP Figure 9. System Power-Up Timing (All Waveforms Are Referenced to V ) EE At time point 8, the load current falls and the SENSE voltage makes contact through a short pin. This ensures the power drops below V (t). The analog current limit loop shuts connections are firmly established before the LTC4252 is ACL off and the GATE pin ramps further. At time point 9, the activated. At time point 1, the power pins make contact SENSE voltage drops below V , the fault TIMER cycle and V ramps through V . At time point 2, the UV/OV CB IN LKO ends, followed by a 5.8µA discharge cycle (cool off). The divider makes contact and its voltage exceeds V . In UVHI duration between time points 7 and 9 must be shorter than addition, the internal logic checks for OV < V , GATE OVHI one circuit breaker delay to avoid a fault time out during < V , SENSE < V , SS < 20 • V and TIMER < GATEL CB OS GATE ramp-up. When GATE ramps past the V thresh- V . If all conditions are met, an initial timing cycle GATEH TMRL old at time point 10, PWRGD pulls low. At time point 11, starts and the TIMER capacitor is charged by a 5.8µA GATE reaches its maximum voltage as determined by V . current source pull-up. At time point 3, TIMER reaches the IN V threshold and the initial timing cycle terminates. TMRH Live Insertion with Short Pin Control of UV/OV The TIMER capacitor is quickly discharged. At time point 4, the V threshold is reached and the conditions of In the example shown in Figure 10, power is delivered TMRL GATE < V , SENSE < V and SS < 20 • V must be through long connector pins whereas the UV/OV divider GATEL CB OS 4252b12f 22

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 56 7 891011 GND – VEE OR (–48RTN) – (–48V) UV/OV VUVHI VIN VLKO VTMRH 230µA + 8 • IDRN TIMER 5.8µA 5.8µA VTMRL 5.8µA GATE 58µA VIN – VGATEH VGATEL 58µA 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VOUT VDRNCL DRAIN VDRNL PWRGD GATE INITIAL TIMING START-UP 4252B12 F10 Figure 10. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to V ) EE satisfied before a GATE start-up cycle begins. SS ramps up V threshold at time point 7, the circuit breaker TIMER CB as dictated by R  • C ; GATE is held low by the analog activates. The TIMER capacitor, C , is charged by a (230µA SS SS T current limit amplifier until SS crosses 20 • V . Upon + 8 • I ) current pull-up. As the load capacitor nears full OS DRN releasing GATE, 58µA sources into the external MOSFET charge, load current begins to decline. At point 8, the load gate and compensation network. When the GATE voltage current falls and the SENSE voltage drops below V (t). ACL reaches the MOSFET’s threshold, current begins flowing The analog current limit loop shuts off and the GATE pin into the load capacitor at time point 5. At time point 6, ramps further. At time point 9, the SENSE voltage drops load current reaches the SS control level and the analog below V and the fault TIMER cycle ends, followed by a CB current limit loop activates. Between time points 6 and 8, 5.8µA discharge cycle (cool off). When GATE ramps past the GATE voltage is servoed, the SENSE voltage is regulated V threshold at time point 10, PWRGD pulls low. GATEH at V (t) and soft-start limits the slew rate of the load At time point 11, GATE reaches its maximum voltage as ACL current. If the SENSE voltage (V – V ) reaches the determined by V . SENSE EE IN 4252b12f 23

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Undervoltage Timing cycle starts. If the system bus voltage overshoots V OVHI as shown at time point 2, TIMER discharges. At time point In Figure 11 when UV pin drops below V (time point 1), UVLO 3, the supply voltage recovers and drops below the V the LTC4252 shuts down with TIMER, SS and GATE all OVLO threshold. The initial timing cycle restarts, followed by a pulling low. If current has been flowing, the SENSE pin GATE start-up cycle. voltage decreases to zero as GATE collapses. When UV recovers and clears V (time point 2), an initial timer UVHI Overvoltage Timing cycle begins followed by a GATE start-up cycle. During normal operation, if the OV pin exceeds V as OVHI V Undervoltage Lockout Timing shown at time point 1 of Figure 13, the TIMER and PWRGD IN status are unaffected. Nevertheless, SS and GATE pull down The V undervoltage lockout comparator, UVLO, has a IN and the load is disconnected. At time point 2, OV recovers similar timing behavior as the UV pin timing except it looks and drops below the V threshold. A GATE start-up for V < (V – V ) to shut down and V > V to OVLO IN LKO LKH IN LKO cycle begins. If the overvoltage glitch is long enough to start. In an undervoltage lockout condition, both UV and deplete the load capacitor, a full start-up cycle as shown OV comparators are held off. When V exits undervoltage IN between time points 4 through 7 may occur. lockout, the UV and OV comparators are enabled. Circuit Breaker Timing Undervoltage Timing with Overvoltage Glitch In Figure 14a, the TIMER capacitor charges at 230µA if In Figure 12, both UV and OV pins are connected together. the SENSE pin exceeds V but V is less than 5V. If When UV clears V (time point 1), an initial timing CB DRN UVHI the SENSE pin drops below V before TIMER reaches CB UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 56 7 891011 VUVHI UV VUVLO VTMRH 230µA + 8 • IDRN TIMER 5.8µA 5.8µA VTMRL 5.8µA 58µA VIN – VGATEH GATE VGATEL 58µA 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL PWRGD GATE INITIAL TIMING START-UP 4252B12 F11 Figure 11. Undervoltage Timing (All Waveforms Are Referenced to V ) EE 4252b12f 24

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 10 12 1 2 3 45 67 8 9 11 VOVHI VOVLO UV/OV VUVHI VTMRH TIMER 5.8µA 230µA + 8 • IDRN 5.8µA VTMRL 5.8µA 58µA GATE 58µA VIN – VGATEH VGATEL 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL PWRGD INITIAL TIMING STGARATT-EUP 4252B12 F12 Figure 12. Undervoltage Timing with an Overvoltage Glitch (All Waveforms Are Referenced to V ) EE OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 5 678 9 OV VOVHIVOVLO VTMRH TIMER 230µA + 8 • IDRN 5.8µA 5.8µA 58µA VIN – VGATEH GATE 58µA VGATEL 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB GATE 4252B12 F13 START-UP Figure 13. Overvoltage Timing (All Waveforms Are Referenced to V ) EE 4252b12f 25

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION CB TIMES OUT CB TIMES OUT 1 2 1 2 1 2 3 4 VTMRH VTMRH VTMRH 5.8µA TIMER 5.8µA TIMER TIMER 230µA + 8 • IDRN 230µA + 8 • IDRN 230µA + 8 • IDRN 230µA + 8 • IDRN GATE GATE GATE SS SS SS VACL VACL VACL SENSE VCB SENSE VCB SENSE VCB VOUT VOUT VOUT VDRNCL VDRNCL DRAIN DRAIN DRAIN PWRGD PWRGD PWRGD CB FAULT CB FAULT CB FAULT CB FAULT 4252B12 F14 (14a) Momentary Circuit-Breaker Fault (14b) Circuit-Breaker Time Out (14c) Multiple Circuit-Breaker Fault Figure 14. Circuit-Breaker Timing Behavior (All Waveforms Are Referenced to V ) EE the V threshold, TIMER is discharged by 5.8µA. In pole mechanical pushbutton switch, this may not be TMRH Figure 14b, when TIMER exceeds V , GATE pulls down feasible. A double pole, single throw pushbutton switch TMRH immediately and the LTC4252 shuts down. In Figure 14c, removes this restriction by connecting the second switch multiple momentary faults cause the TIMER capacitor to to the SS pin. With this method, both the SS and TIMER integrate and reach V . GATE pull down follows and the pins are released at the same time (see Figure 24). TMRH LTC4252 shuts down. During shutdown, the LTC4252-1 latches TIMER high with a 5.8µA pull-up current source; Shutdown Cooling Cycle (LTC4252-2) the LTC4252-2 activates a shutdown cooling cycle. Figure 16 shows the timer behavior of the LTC4252-2. At time point 2, TIMER exceeds V , GATE pulls down TMRH Resetting a Fault Latch (LTC4252-1) immediately and the LTC4252 shuts down. TIMER starts The latched circuit breaker fault of LTC4252-1 benefits a shutdown cooling cycle by discharging TIMER with from long cooling time. It is reset by pulling the UV pin 5.8µA to the V threshold. TIMER then charges with TMRL below V with a switch. Reset is also accomplished by 5.8µA to the V threshold. There are four 5.8µA UVLO TMRH pulling the V pin momentarily below (V – V ). A discharge phases and three 5.8µA charge phases in this IN LKO LKH third reset method involves pulling the TIMER pin below shutdown cooling cycle spanning time points 2 and 3. At V as shown in Figure 15. An initial timing cycle is time point 3, the LTC4252 automatic retry occurs with a TMRL skipped if TIMER is used for reset. An initial timing cycle start-up cycle. Good thermal management techniques are is generated if reset by the UV pin or the V pin. highly recommended; power and thermal dissipation must IN be carefully evaluated when implementing the automatic The duration of the TIMER reset pulse should be smaller retry scheme. than the time taken to reach 0.2V at SS pin. With a single 4252b12f 26

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION SWITCH RESETS LATCHED TIMER SWITCH RELEASES SS 1 234 5 678 9 5.8µA VTMRH TIMER 230µA + 8 • IDRN 5.8µA VTMRL 5.8µA 58µA GATE VIN – VGATEH 58µA VGATEL 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL PWRGD GATE START-UP 425212B F15 MOMENTARY DPST SWITCH RESET Figure 15. Pushbutton Reset of LTC4252-1’s Latched Fault (All Waveforms Are Referenced to V ) EE CIRCUIT BREAKER TIMES OUT RETRY 1 2 345 6 78910 230µA + T8I M• EIDRRN 5.8µA 5.8µA 5.8µA 5.8µA 5.8µA 5.8µA 5.8µAVTM2R3H0µA + 8 • IDRN 5.8µA 5.8µA VTMRL 58µA VIN – VGATEH GATE 58µA VGATEL 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VOUT VDRNCL DRAIN VDRNL PWRGD SHUTDOWN COOLING GATE 4252B12 F16 CB FAULT START-UP Figure 16. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms Are Referenced to V ) EE 4252b12f 27

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Analog Current Limit and Fast Current Limit shown in Figure 18a. If a soft-start capacitor, C , is con- SS nected to this SS pin, the soft-start response is modified In Figure 17a, when SENSE exceeds V , GATE is ACL from a linear ramp to an RC response (Equation 6), as regulated by the analog current limit amplifier loop. When shown in Figure 18b. This feature allows load current to SENSE drops below V , GATE is allowed to pull up. In ACL slowly ramp-up at GATE start-up. Soft-start is initiated at Figure 17b, when a severe fault occurs, SENSE exceeds time point 3 by a TIMER transition from V to V V and GATE immediately pulls down until the analog TMRH TMRL FCL (time points 1 to 2) or by the OV pin falling below the current amplifier establishes control. If the severe fault V threshold after an OV condition. When the SS pin causes V to exceed V , the DRAIN pin is clamped OVLO OUT DRNCL is below 0.2V, the analog current limit amplifier holds at V . I flows into the DRAIN pin and is multiplied DRNCL DRN GATE low. Above 0.2V, GATE is released and 58µA ramps by 8. This extra current is added to the TIMER pull-up up the compensation network and GATE capacitance at current of 230µA. This accelerated TIMER current of time point 4. Meanwhile, the SS pin voltage continues to [230µA+8 • I ] produces a shorter circuit breaker fault DRN ramp up. When GATE reaches the MOSFET’s threshold, delay. Careful selection of C , R and MOSFET can help T D the MOSFET begins to conduct. Due to the MOSFET’s high prevent SOA damage in a low impedance fault condition. g , the MOSFET current quickly reaches the soft-start m control value of V (t) (Equation 7). At time point 6, the Soft-Start ACL GATE voltage is controlled by the current limit amplifier. If the SS pin is not connected, this pin defaults to a linear The soft-start control voltage reaches the circuit breaker voltage ramp, from 0V to 2.2V in about 180µs (or 0V to voltage, V , at time point 7 and the circuit breaker TIMER CB 1.4V in 230µs for the LTC4252C) at GATE start-up, as activates. As the load capacitor nears full charge, load CB TIMES OUT 12 34 1 2 230µA + 8 • IDRN VTMRH 230µA + 8 • VIDTMRNRH TIMER 5.8µA TIMER 5.8µA GATE GATE SS SS VACL VFCL SENSE VCB SENSE VACL VCB VOUT VOUT VDRNCL DRAIN DRAIN 4252B12 F17 PWRGD PWRGD (17a) Analog Current Limit Fault (17b) Fast Current Limit Fault Figure 17. Current Limit Behavior (All Waveforms Are Referenced to V ) EE 4252b12f 28

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION END OF INTIAL TIMING CYCLE END OF INTIAL TIMING CYCLE 1234 567 7a 8 9 10 11 1234 56 7 8 9 10 11 VTMRH 230µA + 8 • IDRN VTMRH 230µA + 8 • IDRN 5.8µA 5.8µA TIMER TIMER VTMRL VTMRL 58µA 58µA GATE VIN – VGATEH GATE VIN – VGATEH VGS(th) VGS(th) 58µA 58µA 20 • (VACL + VOS) 20 • (VACL + VOS) SS 20 • (VCB + VOS) SS 20 • (VCB + VOS) 20 • VOS 20 • VOS VACL VACL SENSE SENSE VCB VCB VDRNCL VDRNCL DRAIN VDRNL DRAIN VDRNL PWRGD PWRGD 4252B12 F18 (18a) Without External C (18b) With External C SS SS Figure 18. Soft-Start Timing (All Waveforms Are Referenced to V ) EE current begins to decline below V (t). The current limit ACL R6 V loop shuts off and GATE releases at time point 8. At time = CB (16) R4 V point 9, the SENSE voltage falls below VCB and TIMER SUPPLY(MAX) deactivates. If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power Large values of CSS can cause premature circuit breaker limit is: time out as VACL(t) may exceed the VCB potential during ( )2 V +V the circuit breaker delay. The load capacitor is unable to SUPPLY(MIN) SUPPLY(MAX) POWER = achieve full charge in one GATE start-up cycle. A more MAX 4•V •V SUPPLY(MIN) SUPPLY(MAX) serious side effect of large C values is SOA duration (17) SS •POWER may be exceeded during soft-start into a low impedance SUPPLY(MIN) load. A soft-start voltage below V will not activate the =1.064•POWER CB SUPPLY(MIN) circuit breaker TIMER. when Power Limit Circuit Breaker V = 0.5 • (V + V ) = 57V. SUPPLY SUPPLY(MIN) SUPPLY(MAX) Figure 19 shows the LTC4252C-1 in a power limit circuit The peak power at the fault current limit occurs at the supply breaking application. The SENSE pin is modulated by the overvoltage threshold. The fault current limited power is: board supply voltage, V . The D1 Zener voltage, V SUPPLY Z POWER = is set to be the same as the low supply operating volt- FAULT asguep,p lVyS oUpPePrLYa(tMinIgN )v =o lt4a3gVe., IVf the goal is t=o 7h1aVv eg itvhine gh itghhe VSURPPLY •VACL–(VSUPPLY–VZ)•RR64 (18) SUPPLY(MAX) S same power at V , then resistors R4 and R6 are SUPPLY(MIN) selected using the ratio: 4252b12f 29

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION –48RTN R3×IN 1.8k R384.3k + 1C0L0µF 1/4W EACH DIN† 1CµINF R5 LOAD –48RTN DDZ13B** 100k (SHORT PIN) 1 39R21k VIN DBZ1V85C43 * VOUT EN 1% 9 LTC4252C-1 2 UV PWRGD 8 7 RD 1M OV DRAIN 10 6 Q1 TIMER GATE 30.R12k C0.T68µF 3 SS VEE SENSE 4 R6 27Ω IRF530S 1% C1 CSS 5 R10CΩ R0.S02Ω 10nF 68nF CC 10nF –48V 4252B12 F19 *FMMT493 **DIODES, INC † RECOMMENDED FOR HARSH ENVIRONMENTS Figure 19. Power Limit Circuit Breaking Application Circuit Breaker with Foldback Current Limit Capacitor C3 and resistor R4 prevent Q1 from momen- tarily turning on when the power pins first make contact. Figure 20 shows the LTC4252C in a foldback current Without C3 and R4, capacitor C2 pulls the gate of Q1 up limit application. When V is shorted to the –48V RTN OUT to a voltage roughly equal to V • C2/C before the supply, current flows through resistors R4 and R5. This EE GS(Q1) LTC4252C powers up. By placing capacitor C3 in parallel results in a voltage drop across R5 and a corresponding with the gate capacitance of Q1 and isolating them from reduction in voltage drop across the sense resistor, R , S C2 using resistor R4, the problem is solved. The value of as the ACL amplifier servos the sense voltage between C3 is given by: the SENSE and V pins to about 60mV. The short-circuit EE current through R reduces as the V voltage increases V S OUT SUPPLY(MAX) ( ) C3= • C2+C (20) during an output short-circuit condition. Without foldback GD(Q1) V current limiting resistor R5, the current is limited to 3A GS(TH),Q1 during analog current limit. With R5, the short-circuit C3 ≈ 35 • C2 for V = 71V SUPPLY(MAX) current is limited to 0.5A when V is shorted to 71V. OUT where V is the MOSFET’s minimum gate threshold GS(TH),Q1 Inrush Control Without a Sense Resistor and VSUPPLY(MAX) is the maximum operating input voltage. During Power-Up Diode-ORing Figure 21 shows the LTC4252C in an application where the Figure 22 shows the LTC4252B used as diode-oring with inrush current is controlled without a sense resistor during Hot Swap capability in a dual –48V power supply applica- power-up. This setup is suitable only for applications that tion. The conventional diode-OR method uses two high don’t require short-circuit protection from the LTC4252C. power diodes and heat sinks to contain the large heat Resistor R4 and capacitor C2 act as a feedback network dissipation of the diodes. With the LTC4252B controlling to accurately control the inrush current. The C2 capacitor the external FETs Q2 and Q3 in a diode-OR manner, the can be calculated with the following equation: small turn-on voltage across the fully enhanced Q2 and I •C C2= GATE L (19) Q3 reduces the power dissipation significantly. I INRUSH where I = 58µA and C is the total load capacitance. GATE L 4252b12f 30

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION –48RTN R3×IN 1.8k + CL 100µF 1/4W EACH LOAD –48RTN DDIDNZ†13B** 1CµINF R5.31k EN (SHORT PIN) 1 R1 392k VIN * 1% 8 LTC4252C-1 2 VOUT OV PWRGD 9 7 RD 1M UV DRAIN C1 R4 10nF 10 6 38.3k RG 10Ω Q1 TIMER GATE 301.R1%2k C0.T68µF 3 SCSSS VEE5 SENSE 4 R10CΩ R5 27Ω IR0R.SF0523Ω0S 68nF CC 10nF –48V 4252B12 F20 † *MOC207 **DIODES, INC RECOMMENDED FOR HARSH ENVIRONMENTS Figure 20. Circuit Breaker with Foldback Current Limit Application –48RTN R3×IN 1.8k + CL 100µF 1/4W EACH LOAD –48RTN 1 DDIDNZ†13B** 1CµINF R5.31k EN (SHORT PIN) R1 392k VIN * 1% 8 LTC4252C-1 2 VOUT OV PWRGD 9 7 RD 1M UV DRAIN C1 C2 10nF 10nF 100V R4 1k 10 6 1%RG 10Ω Q1 TIMER GATE IRF530S 30.R12k C0.T68µF 3 SS VEE SENSE 4 1% CSS 5 C3330nF 68nF 25V –48V 4252B12 F21 † *MOC207 **DIODES, INC RECOMMENDED FOR HARSH ENVIRONMENTS Figure 21. Inrush Control Without a Sense Resistor Application At power-up, Q5 and Q8 are held off low by the SS pin of rises as current flows into R5 and R8 through resistors the LTC4252B; resistors R5 and R8 pull the SENSE pin R3 and R6. The ACL amplifier of the LTC4252B servos closed to V . V is connected to the power supply with the sense voltage to about 100mV as the GATE voltage EE EE lower voltage through the body diodes Q2 or Q3 until Q2 regulates Q2 and Q3. Current flows into R4, Q4 and R7, or Q3 is turned on. This allows the LTC4252B to perform Q7 as Q2 and Q3 turn on. The respective node voltages at a start-up cycle and ramp up the SS and GATE voltage. the R3 and R4 connection and the R6 and R7 connection are always kept equal to their respective sense voltages As the SS voltage ramps up to 2.2V, it turns on Q5 and Q8 by the Q4 and Q2 V drop and the Q7 and Q3 V drop and pulls TIMER low through Q6 and Q9. The sense voltage DS DS assuming the Q5 and Q8 V drop is negligible. DS 4252b12f 31

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION Hot Swap SECTION –48RTN RIN1 3 × 1.8k IN SERIES 1/4W EACH LOAD 40R21k 1 DDIDNZ11†3B** C1µINFRD MODULE 7 UV/OV VIN DRAIN 6 1M C1 8 5 Q1 10nF TIMER GATE IRF530S R2 CT LTC4252B-1 1R0CΩ1 32.4k 0.33µF CC1 2 3 22nF SS VEE SENSE CSS 4 R0.S02Ω 68nF DIODE-OR CIRCUIT FOR CHANNEL A –48V A RIN2 3 × 1.8k IN SERIES 1/4W EACH 1 † DDIDNZ213B** 9 VIN 7 R3 CIN2 2 UV DRAIN 12k 1µF PWRGD Q5 R4 10 LTC4252B-2 4 FDV301N 150Ω TIMER SENSE Q6 3 Q4 SS BSS131 FDV301N 8 6 Q2 OV GATE VEE R5 RC2 IRF530S 5 560Ω 10µ CC2 22nF DIODE-OR CIRCUIT FOR CHANNEL B –48V B RIN3 3 × 1.8k IN SERIES 1/4W EACH 1 † DDIDNZ313B** 9 VIN 7 R6 CIN3 2 UV DRAIN 12k 1µF PWRGD Q8 R7 10 LTC4252B-2 4 FDV301N 150Ω TIMER SENSE Q9 3 Q7 SS BSS131 FDV301N 8 6 Q3 OV GATE VEE R8 RC3 IRF530S 5 560Ω 10Ω CC3 22nF † 4252B12 F22 **DIODES, INC RECOMMENDED FOR HARSH ENVIRONMENTS Figure 22. –48V/2.5A Diode-OR Application 4252b12f 32

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 APPLICATIONS INFORMATION The internal fault latches of the LTC4252B are disabled as the current flow. The sense voltage is lifted up and causes the TIMER pin is always held low by the SS voltage when the fast comparator of LTC4252B to trip and pull the GATE Q2 and Q3 are in analog current limit. low instantly. The channel A supply short will not cause Q3 of channel B diode-OR circuit to turn off. If both power supplies from channel A and B are exactly equal, then equal load current will flow through Q2 and Similarly, when the channel B supply is shorted to the Q3 to the load module via the Hot Swap section. –48V RTN (or GND), large current flows into Q7 momen- tarily and creates a voltage drop across R7, which in turn If the channel A supply is greater than the channel B by reduces the gate-to-source voltage of Q7, thus limiting more than 100mV, the sense voltage will rise above the the current flow. The increase in sense voltage will trip fast comparator trip threshold of 200mV, the GATE will the fast comparator of LTC4252B and pull the GATE low be pulled low and Q2 is turned off. The GATE ramps up instantly. The channel B supply short will not cause Q2 and regulates Q2 when the channel A supply is equal to of channel A diode-OR circuit to turn off. The load short the channel B supply. Likewise, if the channel B supply is at the output of Q1 is protected by the Hot Swap section. greater than channel A by more than 100mV, it trips the fast comparator and GATE is pulled low and Q3 is turned Using an EMI Filter Module off. The GATE ramps up and regulates Q3 when the channel B supply is equal to the channel A supply. Many applications place an EMI filter module in the power path to prevent switching noise of the module from being Resistors R4, R7 and external FETs Q4 and Q7 limit the injected back onto the power supply. A typical application current flow into Q5 and Q8 during their respective sup- using the Lucent FLTR100V10 filter module is shown in ply source short. When the channel A supply is shorted Figure 23. When using a filter, an opto-isolator is required to the –48V RTN (or GND), large current flows into Q4 to prevent common mode transients from destroying the momentarily and creates a voltage drop across R4, which PWRGD and ON/OFF pins. in turn reduces the gate-to-source voltage of Q4, limiting –48RTN (LONG PIN) RIN 3× 1.8k 1/4W –48RTN DIN† CIN R3 1 VIN+ VOUT+ 9 5V (SHORT PIN) 1 DDZ13B** 1µF 5.1k SENSE+ 8 39R21k VIN * 2 TRIM 7 1% 8 LTC4252C-1 2 ON/OFF + C6 OV PWRGD LUCENT 100µF 9 UV DRAIN 7 VIN+ VOUT+ JW050A1-E 16V C1 RD C2 C3 + C4 C5 10nF 10 TIMER GATE 6 1M Q1 1N4003 01.010µVF FLLTURC10E0NVT10 01.010µVF 110000µVF 01.010µVF SENSE– 6 30.R12k 3 SS SENSE 4 IRF530S VIN– VOUT– 4 VIN– VOUT– 5 1% CT VEE RC RS CASE CASE 0.68µF CSS 5 10CΩC 0.02Ω 3 68nF 10nF 4252B12 F23 –48V † *MOC207 **DIODES, INC RECOMMENDED FOR HARSH ENVIRONMENTS Figure 23. Typical Application Using a Filter Module 4252b12f 33

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 3.00 ± 0.102 0.42 ± 0.038 0.65 (.118 ± .004) 0.52 (.0165 ± .0015) (.0256) (NOTE 3) 8 7 6 5 (.0205) TYP BSC REF RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 4.90 ± 0.152 DETAIL “A” (.118 ± .004) 0.254 (.193 ± .006) (NOTE 4) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 0.53 ± 0.152 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 0.1016 ± 0.0508 (.009 – .015) (.004 ± .002) TYP 0.65 MSOP (MS8) 0307 REV F (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 4252b12f 34

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 3.00 ± 0.102 0.305 ± 0.038 0.50 (.118 ± .004) 0.497 ± 0.076 (.0120 ± .0015) (.0197) (NOTE 3) (.0196 ± .003) 10 9 8 76 TYP BSC REF RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 4.90 ± 0.152 DETAIL “A” (.193 ± .006) (.118 ± .004) 0.254 (NOTE 4) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) (.004 ± .002) 0.50 TYP (.0197) MSOP (MS) 0307 REV E NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 4252b12f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 35 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4252B-1/LTC4252B-2 LTC4252C-1/LTC4252C-2 TYPICAL APPLICATION –48RTN RIN + 21×/4 W5.1 EkA ICNH SERIES 100CµFL LOAD † CIN DIN 1µF DDZ13B** –48RTN 1 (SHORT PIN) R1 VIN VOUT 402k LTC4252B-1 RD 1% 7 6 1M UV/OV DRAIN R2 8 5 Q1 32.4k TIMER GATE IRF540S 1% C15T0nF 2 SS VEE SENSE 3 R3 RC RS C1 PUSH CSS 4 22Ω 10Ω 0.01Ω 10nF RESET 27nF CC 22nF –48V 4252B12 F24 † **DIODES, INC RECOMMENDED FOR HARSH ENVIRONMENTS Figure 24. –48V/5A Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to –80V LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers in SO-8 Supplies from 9V to 80V, Latched Off/Autoretry LTC1642 Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V LTC4214 Negative Voltage Hot Swap Controller Operates from –6V to –16V LTC4220 Dual Supply Hot Swap Controller ±2.2V to ±16.5V Operation LT4250 –48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from –20V to –80V LTC4251B/ –48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V LTC4251B-1/ LTC4251B-2 LTC4253B –48V Hot Swap Controller with Sequencer Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies from –15V 4252b12f 36 Linear Technology Corporation LT 0112 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2012