LTC3809-1 No R TM, Low Input SENSE Voltage, Synchronous DC/DC Controller with Output Tracking FEATURES DESCRIPTION n Programmable Output Voltage Tracking The LTC®3809-1 is a synchronous step-down switching n No Current Sense Resistor Required regulator controller that drives external complementary n Constant Frequency Current Mode Operation for power MOSFETs using few external components. The Excellent Line and Load Transient Response constant frequency current mode architecture with MOSFET n Wide VIN Range: 2.75V to 9.8V VDS sensing eliminates the need for a current sense resistor n Wide VOUT Range: 0.6V to VIN and improves effi ciency. n 0.6V ±1.5% Reference Optional Burst Mode operation provides high effi ciency n Low Dropout Operation: 100% Duty Cycle operation at light loads. 100% duty cycle provides low n Selectable Burst Mode®/Pulse-Skipping/Forced dropout operation, extending operating time in battery- Continuous Operation powered systems. Burst Mode is inhibited when the MODE n Auxiliary Winding Regulation pin is pulled low to reduce noise and RF interference. n Internal Soft-Start Circuitry n Selectable Maximum Peak Current Sense Threshold The LTC3809-1 allows either coincident or ratiometric n Output Overvoltage Protection output voltage tracking. Switching frequency is fi xed at n Micropower Shutdown: I = 9μA 550kHz. Fault protection is provided by an overvoltage Q n Tiny Thermally Enhanced Leadless (3mm × 3mm) comparator and a short-circuit current limit comparator. DFN and 10-lead MSOP Packages The LTC3809-1 is available in tiny footprint thermally APPLICATIONS enhanced DFN and 10-lead MSOP packages. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst n 1- or 2-Cell Lithium-Ion Powered Devices is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective n Notebook and Palmtop Computers, PDAs owners. Protected by U.S. Patents including 5481178, 5929620, 6580258, 6304066, n Portable Instruments 5847554, 6611131, 6498466. Other Patents pending. n Distributed DC Power Systems TYPICAL APPLICATION Effi ciency and Power Loss vs Load Current High Effi ciency, 550kHz Step-Down Converter 100 10k VIN EFFICIENCY 10μF 2.75V TO 9.8V VIN = 3.3V 90 1k VIN IPRG %) VIN = 5V VIN = 4.2V POW MODE TG Y ( 80 100 ER 59k 15k VFBLTC3809-1SW 2.2μH V22.AO5UVT FFICIENC 70 TLYOPSISC A(VLI NP O=W 4.E2RV) 10 LOSS (m 187k ITH BG 47μF E W) 470pF RUN 60 1 GND FIGURE 8 CIRCUIT VOUT = 2.5V 38091TA01 50 0.1 1 10 100 1k 10k LOAD CURRENT (mA) 38091TA02 38091fc 1

LTC3809-1 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (V ) ........................ –0.3V to 10V Storage Ambient Temperature Range IN RUN, TRACK/SS, MODE, DFN ....................................................–65°C to 125°C IPRG Voltages ...............................–0.3V to (V + 0.3V) MSOP ................................................–65°C to 150°C IN V , I Voltages ...................................... –0.3V to 2.4V Junction Temperature (Note 3) ............................ 125°C FB TH SW Voltage ......................... –2V to V + 1V (10V Max) Lead Temperature (Soldering, 10 sec) IN TG, BG Peak Output Current (<10μs) ......................... 1A MSOP Package .................................................300°C Operating Temperature Range (Note 2)....–40°C to 85°C PIN CONFIGURATION TOP VIEW TOP VIEW MODE 1 10 SW MODE 1 10 SW TRACK/SS 2 9 VIN TRACK/SS 2 9 VIN VFB 3 11 8 TG VFB 3 11 8 TG ITH 4 7 BG RIUTNH 45 76 BIPGRG RUN 5 6 IPRG MSE PACKAGE 10-LEAD PLASTIC MSOP DDPACKAGE 10-LEAD (3mm (cid:115) 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND TJMAX = 125°C, θJA = 43°C/W (MUST BE SOLDERED TO PCB) EXPOSED PAD (PIN 11) IS GND (MUST BE SOLDERED TO PCB) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3809EDD-1#PBF LTC3809EDD-1#TRPBF LBQZ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3809IDD-1#PBF LTC3809IDD-1#TRPBF LBQZ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3809EMSE-1#PBF LTC3809EMSE-1#TRPBF LTBQV 10-Lead Plastic MSOP –40°C to 85°C LTC3809IMSE-1#PBF LTC3809IMSE-1#TRPBF LTBQV 10-Lead Plastic MSOP –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3809EDD-1 LTC3809EDD-1#TR LBQZ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3809IDD-1 LTC3809IDD-1#TR LBQZ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3809EMSE-1 LTC3809EMSE-1#TR LTBQV 10-Lead Plastic MSOP –40°C to 85°C LTC3809IMSE-1 LTC3809IMSE-1#TR LTBQV 10-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 38091fc 2

LTC3809-1 ELECTRICAL CHARACTERISTICS The l indicates specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 4.2V unless otherwise noted. A IN PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops Input DC Supply Current (Note 4) Normal Operation 350 500 μA Sleep Mode 105 150 μA Shutdown RUN = 0V 9 20 μA UVLO V = UVLO Threshold –200mV 9 20 μA IN Undervoltage Lockout Threshold (UVLO) V Falling l 1.95 2.25 2.55 V IN V Rising l 2.15 2.45 2.75 V IN Shutdown Threshold of RUN Pin 0.8 1.1 1.4 V Start-Up Current Source TRACK/SS = 0V 0.65 1 1.35 μA Regulated Feedback Voltage (Note 5) l 0.591 0.6 0.609 V Output Voltage Line Regulation 2.75V < V < 9.8V (Note 5) 0.01 0.04 %/V IN Output Voltage Load Regulation I = 0.9V (Note 5) 0.1 0.5 % TH I = 1.7V –0.1 –0.5 % TH V Input Current (Note 5) 9 50 nA FB Overvoltage Protect Threshold Measured at V 0.66 0.68 0.7 V FB Overvoltage Protect Hysteresis 20 mV Auxiliary Feedback Threshold 0.325 0.4 0.475 V Top Gate (TG) Drive Rise Time C = 3000pF 40 ns L Top Gate (TG) Drive Fall Time C = 3000pF 40 ns L Bottom Gate (BG) Drive Rise Time C = 3000pF 50 ns L Bottom Gate (BG) Drive Fall Time C = 3000pF 40 ns L Maximum Current Sense Voltage (ΔV ) IPRG = Floating (Note 6) l 110 125 140 mV SENSE(MAX) (V – SW) IPRG = 0V (Note 6) l 70 85 100 mV IN IPRG = V (Note 6) l 185 204 223 mV IN Soft-Start Time (Internal) Time for V to Ramp from 0.05V to 0.55V 0.5 0.74 0.9 ms FB Oscillator Frequency 480 550 600 kHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: T is calculated from the ambient temperature TA and power J may cause permanent damage to the device. Exposure to any Absolute dissipation P according to the following formula: D Maximum Rating condition for extended periods may affect device T = T + (P • θ °C/W) J A D JA reliability and lifetime. Note 4: Dynamic supply current is higher due to gate charge being Note 2: The LTC3809E-1 is guaranteed to meet specifi ed performance delivered at the switching frequency. from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating range Note 5: The LTC3809-1 is tested in a feedback loop that servos I to TH are assured by design characterization, and correlation with statistical a specifi ed voltage and measures the resultant V voltage. FB process controls. The LTC3809I-1 is guaranteed to meet specifi ed Note 6: Peak current sense voltage is reduced dependent on duty cycle performance over the full –40°C to 85°C operating temperature range. to a percentage of value as shown in Figure 1. 38091fc 3

LTC3809-1 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A Maximum Current Sense Voltage Effi ciency vs Load Current Effi ciency vs Load Current vs I Pin Voltage TH 100 100 100 FIGURE 8 CIRCUIT VOUT = 2.5V FIGURE 8 CIRCUIT Burst Mode OPERATION 95 95 VIN = 5V, VOUT = 2.5V (ITH RISING) 80 Burst Mode OPERATION 90 VOUT = 3.3V 90 (ITHFALLING) Y (%) 85 VOUT = 1.2V Y (%) 8805 B(MUORDSET =M VOIDNE) MIT (%) 60 FMPOUORLDCSEEED S KCIOPNPTININGU OUS EFFICIENC 8705 VOUT = 1.8V EFFICIENC 7705 FC(MOORONCDTEIEND =U O0VU)S URRENT LI 2400 MODE 65 C 70 60 0 65 MODE = VIN 55 P(MUOLSDEE S=K 0I.P6PVI)NG VIN = 5V 60 50 –20 1 10 100 1k 10k 1 10 100 1k 10k 0.5 1 1.5 2 LOAD CURRENT (mA) LOAD CURRENT (mA) ITH VOLTAGE (V) 38091 G01 38091 G02 38091 G03 Load Step Load Step Load Step (Burst Mode Operation) (Forced Continuous Mode) (Pulse-Skipping Mode) VOUT VOUT VOUT 200mV/DIV 200mV/DIV 200mV/DIV AC COUPLED AC COUPLED AC COUPLED IL IL IL 2A/DIV 2A/DIV 2A/DIV 100μs/DIV 38091 G04 100μs/DIV 38091 G05 100μs/DIV 38091 G06 VIN = 3.3V VIN = 3.3V VIN = 3.3V VOUT = 1.8V VOUT = 1.8V VOUT = 1.8V ILOAD = 300mA TO 3A ILOAD = 300mA TO 3A ILOAD = 300mA TO 3A MODE = VIN MODE = 0V MODE = VFB FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT Start-Up with Internal Soft-Start Start-Up with External Soft-Start (TRACK/SS = V ) (C = 10nF) IN SS VOUT VOUT 1.8V 1.8V 500mV/DIV 500mV/DIV 200μs/DIV 38091 G07 1ms/DIV 38091 G08 VIN = 4.2V VIN = 4.2V RLOAD = 1 RLOAD = 1 FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT 38091fc 4

LTC3809-1 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A Start-Up with Coincident Tracking Start-Up with Coincident Tracking Start-Up with Ratiometric Tracking (V = 0V at 0s) (V = 0.8V at 0s) (V = 0V at 0s) OUT OUT OUT Vx Vx Vx 2.5V 2.5V 2.5V VOUT VOUT VOUT 1.8V 1.8V 1.8V 500mV/DIV 500mV/DIV 500mV/DIV 10ms/DIV 38091 G09 10ms/DIV 38091 G10 10ms/DIV 38091 G11 VIN = 4.2V VIN = 4.2V VIN = 4.2V RTA = 590 RTA = 590 RTA = 590 RTB = 1.18k RTB = 1.18k RTB = 1.69k FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT Regulated Feedback Voltage Undervoltage Lockout Threshold Shutdown (RUN) Threshold vs Temperature vs Temperature vs Temperature 0.606 2.55 1.20 2.50 0.604 VIN RISING V) 2.45 1.15 FEEDBACK VOLTAGE (000...665009028 INPUT VOLTAGE (V) 2222....42330505 VINFALLING RUN VOLTAGE (V) 11..0150 0.596 2.20 0.594 2.15 1.00 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 38091 G012 38091 G13 38091 G14 Maximum Current Sense TRACK/SS Start-Up Current Threshold vs Temperature vs Temperature mV)135 IPRG = FLOAT 1.04 TRACK/SS = 0V D ( A) HOL T (μ 1.02 S130 N E E R R H R T U E C 1.00 SENS125 T-UP CURRENT 120 K/SS STAR 0.98 M AC 0.96 U R M T XI A M115 0.94 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) 38091 G15 38091 G16 38091fc 5

LTC3809-1 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A Oscillator Frequency Oscillator Frequency Shutdown Quiescent Current vs Temperature vs Input Voltage vs Input Voltage 10 5 18 8 %) 4 16 NORMALIZED FREQUENCY (%) –––0644262 RMALIZED FREQUENCY SHIFT ( –––0322131 SHUTDOWN CURRENT (μA) 111842046 O –8 N –4 2 –10 –5 0 –60 –40 –20 0 20 40 60 80 100 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 TEMPERATURE (°C) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 38091 G17 38091 G18 38091 G19 TRACK/SS Start-Up Current Sleep Current vs Input Voltage vs TRACK/SS Voltage 130 1.04 A) 120 μ T ( 1.00 A) EN RENT (μ110 P CURR 0.96 P CUR100 TARTU 0.92 E S SLE 90 K/SS C A 0.88 80 R T 70 0.84 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 INPUT VOLTAGE (V) TRACK/SS VOLTAGE (V) 38091 G20 38091 G21 38091fc 6

LTC3809-1 PIN FUNCTIONS MODE (Pin 1): This pin performs two functions: 1) auxiliary IPRG (Pin 6): Three-State Pin to Select Maximum Peak winding feedback input, and 2) Burst Mode operation, Sense Voltage Threshold. This pin selects the maximum pulse skipping or forced continuous mode select. allowed voltage drop between the V and SW pins IN (i.e., the maximum allowed drop across the external To select Burst Mode operation at light loads, tie this P-channel MOSFET). Tie to V , GND or fl oat to select pin to V . Grounding this pin selects forced continuous IN IN 204mV, 85mV or 125mV respectively. operation which allows the inductor current to reverse. Tying this pin to V selects pulse-skipping mode. Do not BG (Pin 7): Bottom (NMOS) Gate Drive Output. This pin FB leave this pin fl oating. drives the gate of the external N-channel MOSFET. This pin has an output swing from PGND to V . TRACK/SS (Pin 2): Tracking Input for the Controller or IN Optional External Soft-Start Input. This pin allows the TG (Pin 8): Top (PMOS) Gate Drive Output. This pin drives start-up of V to “track” the external voltage at this pin the gate of the external P-channel MOSFET. This pin has OUT using an external resistor divider. Tying this pin to V an output swing from PGND to V . IN IN allows V to start up with the internal 0.74ms soft-start. OUT V (Pin 9): Chip Signal Power Supply. This pin powers IN An external soft-start can be programmed by connecting the entire chip, the gate drivers and serves as the positive a capacitor between this pin and ground. Do not leave input to the differential current comparator. this pin fl oating. SW (Pin 10): Switch Node Connection to Inductor. This V (Pin 3): Feedback Pin. This pin receives the remotely FB pin is also the negative input to the differential current sensed feedback voltage for the controller from an external comparator and an input to the reverse current comparator. resistor divider across the output. Normally this pin is connected to the drain of the external I (Pin 4): Current Threshold and Error Amplifi er P-channel MOSFET, the drain of the external N-channel TH Compensation Point. Nominal operating range on this pin MOSFET and the inductor. is from 0.7V to 2V. The voltage on this pin determines the GND (Exposed Pad, Pin 11): Ground connection for threshold of the main current comparator. internal circuits, the gate drivers and the negative input to RUN (Pin 5): Run Control Input. Forcing this pin below the reverse current comparator. The Exposed Pad must 1.1V shuts down the chip. Driving this pin to V or be soldered to the PCB ground. IN releasing this pin enables the chip to start-up with the internal soft-start. 38091fc 7

LTC3809-1 FUNCTIONAL DIAGRAM VIN CIN 9 VIN VOLTAGE VREF SLOPE 6 IPRG REFERENCE 0.6V TG CLK S 8 MP + Q GND ICMP R UNDERVOLTAGE SENSE+ SWITCHING L LOCKOUT – LOGIC AND ANTI-SHOOT- SW BLANKING THROUGH 10 VOUT VIN OSC CIRCUIT COUT PVIN VIN BG UVSD 7 MN 0.7μA RUN 5 + FCB VIN t = 0.74ms INTERNAL 0.15V – SLEEP + SOFT-START OV IREV – 0.68V BURSTDIS GND RB 11 1μA 0.3V + 0.54V TRACK/SS MUX TRK/SS UV 2 – VFB MODE BURSTDIS 1 BURST DEFEAT FCB + 4 ITH RC + VREF – 0.6V CC EAMP+ TRK/SS – 3 VFB RA 38091 FD + SW IREV RICMP – GND 38091fc 8

LTC3809-1 OPERATION (Refer to Functional Diagram) Main Control Loop by releasing the RUN pin, the TRACK/SS pin is charged up by an internal 1μA current source and rises linearly from The LTC3809-1 uses a constant frequency, current mode 0V to above 0.6V. The error amplifi er EAMP compares the architecture. During normal operation, the top external feedback signal V to this ramp instead, and regulates P-channel power MOSFET is turned on when the clock sets FB V linearly from 0V to 0.6V. the RS latch, and is turned off when the current comparator FB (ICMP) resets the latch. The peak inductor current at which When the voltage on the TRACK/SS pin is less than the ICMP resets the RS latch is determined by the voltage on the 0.6V internal reference, the LTC3809-1 regulates the V FB I pin, which is driven by the output of the error amplifi er voltage to the TRACK/SS pin instead of the 0.6V reference. TH (EAMP). The V pin receives the output voltage feedback Therefore V of the LTC3809-1 can track an external FB OUT signal from an external resistor divider. This feedback voltage V during start-up. Typically, a resistor divider on X signal is compared to the internal 0.6V reference voltage V is connected to the TRACK/SS pin to allow the start-up X by the EAMP. When the load current increases, it causes a of V to “track” that of V . For coincident tracking during OUT X slight decrease in V relative to the 0.6V reference, which start-up, the regulated fi nal value of V should be larger FB X in turn causes the I voltage to increase until the average than that of V , and the resistor divider on V has the TH OUT X inductor current matches the new load current. While the top same ratio as the divider on V that is connected to V . OUT FB P-channel MOSFET is off, the bottom N-channel MOSFET is See detailed discussions in the Run and Soft-Start/Tracking turned on until either the inductor current starts to reverse, Functions in the Applications Information Section. as indicated by the current reversal comparator IRCMP, or the beginning of the next cycle. Light Load Operation (Burst Mode Operation, Continuous Conduction or Pulse-Skipping Mode) Shutdown, Soft-Start and Tracking Start-Up (MODE Pin) (RUN and TRACK/SS Pins) The LTC3809-1 can be programmed for either high effi ciency The LTC3809-1 is shut down by pulling the RUN pin low. Burst Mode operation, forced continuous conduction mode In shutdown, all controller functions are disabled and the or pulse-skipping mode at low load currents. To select chip draws only 9μA. The TG output is held high (off) and Burst Mode operation, tie the MODE pin to V . To select IN the BG output low (off) in shutdown. Releasing the RUN forced continuous operation, tie the MODE pin to a DC pin allows an internal 0.7μA current source to pull up the voltage below 0.4V (e.g., GND). Tying the MODE pin to a RUN pin to V . The controller is enabled when the RUN DC voltage above 0.4V and below 1.2V (e.g., V ) enables IN FB pin reaches 1.1V. pulse-skipping mode. The 0.4V threshold between forced continuous operation and pulse-skipping mode can be The start-up of V is based on the three different con- OUT used in secondary winding regulation as described in the nections on the TRACK/SS pin. The start-up of V is OUT Auxiliary Winding Control Using the MODE Pin discussion controlled by the LTC3809-1’s internal soft-start when in the Applications Information section. TRACK/SS is connected to V . During soft-start, the error IN amplifi er EAMP compares the feedback signal V to the When the LTC3809-1 is in Burst Mode operation, the peak FB internal soft-start ramp (instead of the 0.6V reference), current in the inductor is set to approximately one-fourth which rises linearly from 0V to 0.6V in about 1ms. This al- of the maximum sense voltage even though the voltage on lows the output voltage to rise smoothly from 0V to its fi nal the I pin indicates a lower value. If the average induc- TH value while maintaining control of the inductor current. tor current is higher than the load current, the EAMP will decrease the voltage on the I pin. When the I voltage The 1ms soft-start time can be changed by connecting TH TH drops below 0.85V, the internal SLEEP signal goes high the optional external soft-start capacitor C between the SS and the external MOSFET is turned off. TRACK/SS and GND pins. When the controller is enabled 38091fc 9

LTC3809-1 OPERATION (Refer to Functional Diagram) In sleep mode, much of the internal circuitry is turned off, high as Burst Mode operation. During start-up or an reducing the quiescent current that the LTC3809-1 draws. undervoltage condition (V ≤ 0.54V), the LTC3809-1 FB The load current is supplied by the output capacitor. As operates in pulse-skipping mode (no current reversal the output voltage decreases, the EAMP increases the allowed), regardless of the state of the MODE pin. I voltage. When the I voltage reaches 0.925V, the TH TH SLEEP signal goes low and the controller resumes normal Short-Circuit and Current Limit Protection operation by turning on the external P-channel MOSFET The LTC3809-1 monitors the voltage drop ΔV (between SC on the next cycle of the internal oscillator. the GND and SW pins) across the external N-channel When the controller is enabled for Burst Mode or pulse- MOSFET with the short-circuit current limit comparator. skipping operation, the inductor current is not allowed to The allowed voltage is determined by: reverse. Hence, the controller operates discontinuously. ΔV = A • 90mV SC(MAX) The reverse current comparator RICMP senses the where A is a constant determined by the state of the IPRG drain-to-source voltage of the bottom external N-channel pin. Floating the IPRG pin selects A = 1; tying IPRG to V MOSFET. This MOSFET is turned off just before the inductor IN selects A = 5/3; tying IPRG to GND selects A = 2/3. current reaches zero, preventing it from going negative. The inductor current limit for short-circuit protection is In forced continuous operation, the inductor current is determined by ΔV and the on-resistance of the allowed to reverse at light loads or under large transient SC(MAX) external N-channel MOSFET: conditions. The peak inductor current is determined by the voltage on the ITH pin. The P-channel MOSFET is turned ΔV on every cycle (constant frequency) regardless of the I I = SC(MAX) TH SC R pin voltage. In this mode, the effi ciency at light loads is DS(ON) lower than in Burst Mode operation. However, continuous Once the inductor current exceeds I , the short current mode has the advantages of lower output ripple and no SC comparator will shut off the external P-channel MOSFET noise at audio frequencies. until the inductor current drops below I . SC When the MODE pin is set to the V Pin, the LTC3809-1 FB operates in PWM pulse-skipping mode at light loads. In Output Overvoltage Protection this mode, the current comparator ICMP may remain As further protection, the overvoltage comparator (OVP) tripped for several cycles and force the external P-channel guards against transient overshoots, as well as other more MOSFET to stay off for the same number of cycles. The serious conditions that may overvoltage the output. When inductor current is not allowed to reverse (discontinuous the feedback voltage on the V pin has risen 13.33% FB operation). This mode, like forced continuous operation, above the reference voltage of 0.6V, the external P-channel exhibits low output ripple as well as low audible noise MOSFET is turned off and the N-channel MOSFET is turned and reduced RF interference as compared to Burst Mode on until the overvoltage is cleared. operation. However, it provides low current effi ciency higher than forced continuous mode, but not nearly as 38091fc 10

LTC3809-1 OPERATION (Refer to Functional Diagram) Dropout Operation where A is a constant determined by the state of the IPRG pin. Floating the IPRG pin selects A = 1; tying IPRG to When the input supply voltage (V ) approaches the output IN V selects A = 5/3; tying IPRG to GND selects A = 2/3. voltage, the rate of change of the inductor current while the IN The maximum value of V is typically about 1.98V, so external P-channel MOSFET is on (ON cycle) decreases. ITH the maximum sense voltage allowed across the external This reduction means that the P-channel MOSFET will P-channel MOSFET is 125mV, 85mV or 204mV for the remain on for more than one oscillator cycle if the inductor three respective states of the IPRG pin. current has not ramped up to the threshold set by the EAMP on the I pin. Further reduction in the input supply However, once the controller’s duty cycle exceeds 20%, TH voltage will eventually cause the P-channel MOSFET to be slope compensation begins and effectively reduces the turned on 100%; i.e., DC. The output voltage will then be peak sense voltage by a scale factor (SF) given by the determined by the input voltage minus the voltage drop curve in Figure 1. across the P-channel MOSFET and the inductor. The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel Undervoltage Lockout MOSFET: To prevent operation of the P-channel MOSFET below ΔV safe input voltage levels, an undervoltage lockout is I = SENSE(MAX) PK incorporated in the LTC3809-1. When the input supply R DS(ON) voltage (V ) drops below 2.25V, the external P- and IN N-channel MOSFETs and all internal circuits are turned 110 off except for the undervoltage block, which draws only 100 a few microamperes. 90 80 Peak Current Sense Voltage Selection %) 70 and Slope Compensation (IPRG Pin) (MAX 60 = I/I 50 When the LTC3809-1 controller is operating below 20% SF 40 duty cycle, the peak current sense voltage (between the 30 20 V and SW pins) allowed across the external P-channel IN 10 MOSFET is determined by: 0 0 10 20 30 40 50 60 70 80 90 100 V –0.7V ΔV =A• ITH DUTY CYCLE (%) SENSE(MAX) 10 38091 F01 Figure 1. Maximum Peak Current vs Duty Cycle 38091fc 11

LTC3809-1 APPLICATIONS INFORMATION The typical LTC3809-1 application circuit is shown in Figure where I is the inductor peak-to-peak ripple current RIPPLE 8. External component selection for the controller is driven (see Inductor Value Calculation). by the load requirement and begins with the selection of A reasonable starting point is setting ripple current I RIPPLE the inductor and the power MOSFETs. to be 40% of I . Rearranging the above equation OUT(MAX) yields: Power MOSFET Selection 5 ΔV The LTC3809-1’s controller requires two external power R = • SENSE(MAX) forDutyCyycle<20% DS(ON)MAX MOSFETs: a P-channel MOSFET for the topside (main) 6 I OUT(MAX) switch and a N-channel MOSFET for the bottom (synchro- nous) switch. The main selection criteria for the power However, for operation above 20% duty cycle, slope MOSFETs are the breakdown voltage V , threshold compensation has to be taken into consideration to select BR(DSS) voltage V , on-resistance R , reverse transfer the appropriate value of R to provide the required GS(TH) DS(ON) DS(ON) capacitance C , turn-off delay t and the total gate amount of load current: RSS D(OFF) charge QG. 5 ΔV R = •SF• SENSE(MAX) The gate drive voltage is the input supply voltage. Since DS(ON)MAX 6 I OUT(MAX) the LTC3809-1 is designed for operation down to low input voltages, a sublogic level MOSFET (R guaranteed at DS(ON) where SF is a scale factor whose value is obtained from V = 2.5V) is required for applications that work close to GS the curve in Figure 1. this voltage. When these MOSFETs are used, make sure that These must be further derated to take into account the the input supply to the LTC3809-1 is less than the absolute signifi cant variation in on-resistance with temperature. The maximum MOSFET V rating, which is typically 8V. GS following equation is a good guide for determining the re- The P-channel MOSFET’s on-resistance is chosen based quired R at 25°C (manufacturer’s specifi cation), DS(ON)MAX on the required load current. The maximum average load allowing some margin for variations in the LTC3809-1 and current I is equal to the peak inductor current OUT(MAX) external component values: minus half the peak-to-peak ripple current I . The RIPPLE LTC3809-1’s current comparator monitors the drain-to- R = 5•0.9•SF• ΔVSENSE(MAX) source voltage VDS of the top P-channel MOSFET, which DS(ON)MAX 6 IOUT(MAX)•ρρT is sensed between the V and SW pins. The peak inductor IN current is limited by the current threshold, set by the voltage The ρ is a normalizing term accounting for the temperature T on the ITH pin, of the current comparator. The voltage on variation in on-resistance, which is typically about 0.4%/°C, the ITH pin is internally clamped, which limits the maximum as shown in Figure 2. Junction-to-case temperature TJC is current sense threshold ΔVSENSE(MAX) to approximately about 10°C in most applications. For a maximum ambi- 125mV when IPRG is fl oating (85mV when IPRG is tied ent temperature of 70°C, using ρ ~ 1.3 in the above 80°C low; 204mV when IPRG is tied high). equation is a reasonable choice. The output current that the LTC3809-1 can provide is The N-channel MOSFET’s on resistance is chosen based given by: on the short-circuit current limit (I ). The LTC3809- SC ΔV I 1’s short-circuit current limit comparator monitors the I = SENSE(MAX)– RIPPLE drain-to-source voltage V of the bottom N-channel OUT(MAX) DS R 2 DS(ON) MOSFET, which is sensed between the GND and SW pins. 38091fc 12

LTC3809-1 APPLICATIONS INFORMATION 2.0 V TopP-ChannelDutyCycle= OUT V IN 1.5 V −V BottomN-CChannelDutyCycle= IN OUT V IN 1.0 The MOSFET power dissipations at maximum output current are: 0.5 P = VOUT •I 2 •ρ •R +2• V 2 TOP OUT(MAX) T DS(ON) IN V 0 IN –50 0 50 100 150 JUNCTION TEMPERATURE (°C) •IOUT(MAX) •CRSS • f 38091 F02 P = VIN –VOUT •I 2 •ρ •R Figure 2. R vs Temperature BOT OUT(MAX) T DS(ON) DS(ON) V IN The short-circuit current sense threshold ΔV is set Both MOSFETs have I2R losses and the P equation SC TOP approximately 90mV when IPRG is fl oating (60mV when includes an additional term for transition losses, which are IPRG is tied low; 150mV when IPRG is tied high). The largest at high input voltages. The bottom MOSFET losses on-resistance of N-channel MOSFET is determined by: are greatest at high input voltage or during a short-circuit when the bottom duty cycle is 100%. ΔV R = SC DS(ON)MAX I The LTC3809-1 utilizes a non-overlapping, anti-shoot- SC(PEAK) through gate drive control scheme to ensure that the P- and N-channel MOSFETs are not turned on at the same The short-circuit current limit (I ) should be larger SC(PEAK) time. To function properly, the control scheme requires than the I with some margin to avoid interfering OUT(MAX) that the MOSFETs used are intended for DC/DC switching with the peak current sensing loop. On the other hand, applications. Many power MOSFETs, particularly P-channel in order to prevent the MOSFETs from excessive heating MOSFETs, are intended to be used as static switches and and the inductor from saturation, I should be SC(PEAK) therefore are slow to turn on or off. smaller than the minimum value of their current ratings. A reasonable range is: Reasonable starting criteria for selecting the P-channel MOSFET are that it must typically have a gate charge (Q ) I < I < I G OUT(MAX) SC(PEAK) RATING(MIN) less than 25nC to 30nC (at 4.5V ) and a turn-off delay GS Therefore, the on-resistance of N-channel MOSFET should (t ) of less than approximately 140ns. However, due D(OFF) be chosen within the following range: to differences in test and specifi cation methods of various ΔV ΔV MOSFET manufacturers, and in the variations in Q and SC <R < SC G DS(ON) t with gate drive (V ) voltage, the P-channel MOSFET I I D(OFF) IN RATING(MIN) OUT(MAX) ultimately should be evaluated in the actual LTC3809-1 where ΔV is 90mV, 60mV or 150mV with IPRG being application circuit to ensure proper operation. SC fl oated, tied to GND or V respectively. Shoot-through between the P-channel and N-channel IN MOSFETs can most easily be spotted by monitoring the The power dissipated in the MOSFET strongly depends input supply current. As the input supply voltage increases, on its respective duty cycles and load current. When the if the input supply current increases dramatically, then the LTC3809-1 is operating in continuous mode, the duty likely cause is shoot-through. Note that some MOSFETs cycles for the MOSFETs are: 38091fc 13

LTC3809-1 APPLICATIONS INFORMATION that do not work well at high input voltages (e.g., V > The corresponding average current depends on the IN 5V) may work fi ne at lower voltages (e.g., 3.3V). amount of ripple current. Lower inductor values (higher I ) will reduce the load current at which Burst Mode Selecting the N-channel MOSFET is typically easier, since RIPPLE operation begins. for a given R , the gate charge and turn-on and turn-off DS(ON) delays are much smaller than for a P-channel MOSFET. The ripple current is normally set so that the inductor current is continuous during the burst periods. Therefore, Inductor Value Calculation I ≤ I RIPPLE BURST(PEAK) Given the desired input and output voltages, the inductor This implies a minimum inductance of: value and operating frequency, f , directly determine OSC the inductor’s peak-to-peak ripple current: V –V V L ≤ IN OUT • OUT MIN I = VOUT • VIN–VOUT fOSC•IBURST(PEAK) VIN RIPPLE V f •L IN OSC A smaller value than L could be used in the circuit, MIN although the inductor current will not be continuous Lower ripple current reduces core losses in the inductor, during burst periods, which will result in slightly lower ESR losses in the output capacitors and output voltage effi ciency. In general, though, it is a good idea to keep ripple. Thus, highest effi ciency operation is obtained at I comparable to I . low frequency with a small ripple current. Achieving this, RIPPLE BURST(PEAK) however, requires a large inductor. Inductor Core Selection A reasonable starting point is to choose a ripple current Once the value of L is known, the type of inductor must be that is about 40% of I . Note that the largest ripple OUT(MAX) selected. Actual core loss is independent of core size for a current occurs at the highest input voltage. To guarantee fi xed inductor value, but is very dependent on the induc- that ripple current does not exceed a specifi ed maximum, tance selected. As inductance increases, core losses go the inductor should be chosen according to: down. Unfortunately, increased inductance requires more L≥ VIN–VOUT • VOUT turns of wire and therefore copper losses will increase. f •I V OSC RIPPLE IN Ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can Burst Mode Operation Considerations concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that The choice of R and inductor value also determines DS(ON) inductance collapses abruptly when the peak design current the load current at which the LTC3809-1 enters Burst Mode is exceeded. Core saturation results in an abrupt increase operation. When bursting, the controller clamps the peak in inductor ripple current and consequent output voltage inductor current to approximately: ripple. Do not allow the core to saturate! 1 ΔV I = • SENSE(MAX) BURST(PEAK) 4 R DS(ON) 38091fc 14

LTC3809-1 APPLICATIONS INFORMATION Different core materials and shapes will change the size/ This formula has a maximum value at V = 2V , where IN OUT current and price/current relationship of an inductor. Toroid I = I /2. This simple worst-case condition is com- RMS OUT or shielded pot cores in ferrite or permalloy materials are monly used for design because even signifi cant deviations small and don’t radiate much energy, but generally cost do not offer much relief. Note that capacitor manufacturer’s more than powdered iron core inductors with similar ripple current ratings are often based on 2000 hours of life. characteristics. The choice of which style inductor to use This makes it advisable to further derate the capacitor or mainly depends on the price vs size requirements and any to choose a capacitor rated at a higher temperature than radiated fi eld/EMI requirements. New designs for surface required. Several capacitors may be paralleled to meet the mount inductors are available from Coiltronics, Coilcraft, size or height requirements in the design. Due to the high Toko and Sumida. operating frequency of the LTC3809-1, ceramic capacitors can also be used for C . Always consult the manufacturer IN Schottky Diode Selection (Optional) if there is any question. The schottky diode D in Figure 9 conducts current dur- The selection of C is driven by the effective series OUT ing the dead time between the conduction of the power resistance (ESR). Typically, once the ESR requirement MOSFETs. This prevents the body diode of the bottom is satisfi ed, the capacitance is adequate for fi ltering. The N-channel MOSFET from turning on and storing charge output ripple (ΔV ) is approximated by: OUT during the dead time, which could cost as much as 1% ⎛ 1 ⎞ in effi ciency. A 1A Schottky diode is generally a good ΔV ≈I •⎜ESR+ ⎟ size for most LTC3809-1 applications, since it conducts OUT RIPPLE ⎝ 8• f•COUT⎠ a relatively small average current. Larger diode results where f is the operating frequency, C is the output in additional transition losses due to its larger junction OUT capacitance and I is the ripple current in the induc- capacitance. This diode may be omitted if the effi ciency RIPPLE tor. The output ripple is highest at maximum input voltage loss can be tolerated. since I increase with input voltage. RIPPLE C and C Selection IN OUT Setting Output Voltage In continuous mode, the source current of the P-channel The LTC3809-1 output voltage is set by an external MOSFET is a square wave of duty cycle (V /V ). To OUT IN feedback resistor divider carefully placed across the prevent large voltage transients, a low ESR input capacitor output, as shown in Figure 3. The regulated output voltage sized for the maximum RMS current must be used. The is determined by: maximum RMS capacitor current is given by: V •(V –V )1/2 V =0.6V•⎛⎜1+ RB⎞⎟ C RequiredI ≈I • OUT IN OUT OUT ⎝ R ⎠ IN RMS MAX V A IN 38091fc 15

LTC3809-1 APPLICATIONS INFORMATION For most applications, a 59k resistor is suggested for R . Once the controller is enabled, the start-up of V is con- A OUT In applications where minimizing the quiescent current is trolled by the state of the TRACK/SS pin. If the TRACK/SS critical, R should be made bigger to limit the feedback pin is connected to V , the start-up of V is controlled A IN OUT divider current. If R then results in very high impedance, by internal soft-start, which slowly ramps the positive B it may be benefi cial to bypass R with a 50pF to 100pF reference to the error amplifi er from 0V to 0.6V, allowing B capacitor C . V to rise smoothly from 0V to its fi nal value. The default FF OUT internal soft-start time is around 0.74ms. The soft-start VOUT time can be changed by placing a capacitor between the TRACK/SS pin and GND. In this case, the soft-start time LTC3809-1 RB CFF will be approximately: VFB 600mV RA tSS =CSS • 1μA 38091 F03 where 1μA is an internal current source which is always on. Figure 3. Setting Output Voltage When the voltage on the TRACK/SS pin is less than the internal 0.6V reference, the LTC3809-1 regulates the V FB Run and Soft-Start/Tracking Functions voltage to the TRACK/SS pin voltage instead of 0.6V. Therefore the start-up of V can ratiometrically track The LTC3809-1 has a low power shutdown mode which is OUT an external voltage V , according to a ratio set by a resis- controlled by the RUN pin. Pulling the RUN pin below 1.1V X tor divider at TRACK/SS pin (Figure 5a). The ratiometric puts the LTC3809-1 into a low quiescent current shutdown relation between V and V is (Figure 5c): mode (I = 9μA). Releasing the RUN pin, an internal 0.7μA OUT X Q (at VIN = 4.2V) current source will pull the RUN pin up VOUT =RTA • RA+RB to VIN, which enables the controller. The RUN pin can be V R R +R driven directly from logic as showed in Figure 4. X A TA TB VOUT 3.3V OR 5V VX LTC3809-1 RB LTC3809-1 LTC3809-1 RUN RUN RTB VFB TRACK/SS RA 38091 F04 RTA 38091 F5a Figure 4. RUN Pin Interfacing Figure 5a. Using the TRACK/SS Pin to Track V X 38091fc 16

LTC3809-1 APPLICATIONS INFORMATION VX VX E E G G A A LT LT O O V V T T U U TP VOUT TP VOUT U U O O 38091 F05b,c TIME TIME (5b) Coincident Tracking (5c) Ratiometric Tracking Figure 5b and 5c. Two Different Modes of Output Voltage Tracking For coincident tracking (V = V during start-up), Auxiliary Winding Control Using the MODE Pin OUT X R = R , R = R The MODE pin can be used as an auxiliary feedback to TA A TB B provide a means of regulating a fl yback winding output. V should always be greater than V when using the X OUT When this pin drops below its ground-referenced 0.4V tracking function of TRACK/SS pin. threshold, continuous mode operation is forced. The internal current source (1μA), which is for external During continuous mode, current fl ows continuously in soft-start, will cause a tracking error at V . For example, OUT the transformer primary side. The auxiliary winding draws if a 59k resistor is chosen for R , the R current will be TA TA current only when the bottom synchronous N-channel about 10μA (600mV/59k). In this case, the 1μA internal MOSFET is on. When primary load currents are low and/ current source will cause about 10% (1μA/10μA • 100%) or the V /V ratio is close to unity, the synchronous tracking error, which is about 60mV (600mV • 10%) IN OUT MOSFET may not be on for a suffi cient amount of time to referred to V . This is acceptable for most applications. FB transfer power from the output capacitor to the auxiliary If a better tracking accuracy is required, the value of R TA load. Forced continuous operation will support an auxiliary should be reduced. winding as long as there is a suffi cient synchronous Table 1 summarizes the different states in which the MOSFET duty factor. The MODE input pin removes TRACK/SS can be used. the requirement that power must be drawn from the transformer primary side in order to extract power from Table 1. The States of the TRACK/SS Pin the auxiliary winding. With the loop in continuous mode, TRACK/SS Pin FREQUENCY the auxiliary output may nominally be loaded without Capacitor C External Soft-Start SS regard to the primary output load. V Internal Soft-Start IN Resistor Divider V Tracking an External Voltage V OUT X 38091fc 17

LTC3809-1 APPLICATIONS INFORMATION The auxiliary output voltage V is normally set, as shown In a hard short (V = 0V), the top P-channel MOSFET AUX OUT in Figure 6, by the turns ratio N of the transformer: is turned off and kept off until the short-circuit condition is cleared. In this case, there is no current path from V = (N + 1) • V AUX OUT input supply (V ) to either V or GND, which prevents IN OUT excessive MOSFET and inductor heating. VIN + VAUX 105 R6 LTC3809-1TG 1L:1N 1μF VOUT ENT (%)100 VREF R MODE R SW CU 95 R5 + E OR MSEANXSIME UVOMLTAGE BG COUT AG 90 LT O 38091 F06 D V 85 E Z LI Figure 6. Auxiliary Output Loop Connection MA 80 R O N 75 However, if the controller goes into pulse-skipping operation 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 and halts switching due to a light primary load current, then INPUT VOLTAGE (V) 38091 F07 V will droop. An external resistor divider from V to AUX AUX Figure 7. Line Regulation of V and Maximum Sense Voltage the MODE sets a minimum voltage V : REF AUX(MIN) ⎛ R6⎞ Low Supply Voltage V =0.4V•⎜1+ ⎟ AUX(MIN) ⎝ R5⎠ Although the LTC3809-1 can function down to below 2.4V, the maximum allowable output current is reduced as V If V drops below this value, the MODE voltage forces IN AUX decreases below 3V. Figure 7 shows the amount of change temporary continuous switching operation until V is AUX as the supply is reduced down to 2.4V. Also shown is the again above its minimum. effect on V . REF Fault Condition: Short-Circuit and Current Limit Minimum On-Time Considerations If the LTC3809-1’s load current exceeds the short-circuit Minimum on-time, t is the smallest amount of time current limit (I ), which is set by the short-circuit sense ON(MIN) SC that the LTC3809-1 is capable of turning the top P-channel threshold (ΔV ) and the on resistance (R ) of SC DS(ON) MOSFET on. It is determined by internal timing delays and bottom N-channel MOSFET, the top P-channel MOSFET the gate charge required to turn on the top MOSFET. Low is turned off and will not be turned on at the next clock duty cycle and high frequency applications may approach cycle unless the load current decreases below I . In this SC the minimum on-time limit and care should be taken to case, the controller’s switching frequency is decreased ensure that: and the output is regulated by short-circuit (current limit) protection. V t < OUT ON(MIN) f • V OSC IN 38091fc 18

LTC3809-1 APPLICATIONS INFORMATION If the duty cycle falls below what can be accommodated 3) I2R losses are calculated from the DC resistances of the by the minimum on-time, the LTC3809-1 will begin to skip MOSFETs, inductor and/or sense resistor. In continuous cycles (unless forced continuous mode is selected). The mode, the average output current fl ows through L but output voltage will continue to be regulated, but the ripple is “chopped” between the top P-channel MOSFET and current and ripple voltage will increase. The minimum on- the bottom N-channel MOSFET. The MOSFET R DS(ON) time for the LTC3809-1 is typically about 210ns. However, multiplied by duty cycle can be summed with the resistance as the peak sense voltage (I • R ) decreases, of L to obtain I2R losses. L(PEAK) DS(ON) the minimum on-time gradually increases up to about 4) Transition losses apply to the external MOSFET and 260ns. This is of particular concern in forced continuous increase with higher operating frequencies and input applications with low ripple current at light loads. If forced voltages. Transition losses can be estimated from: continuous mode is selected and the duty cycle falls below the minimum on time requirement, the output will be Transition Loss = 2 • VIN2 • IO(MAX) • CRSS • f regulated by overvoltage protection. Other losses, including C and C ESR dissipative losses IN OUT and inductor core losses, generally account for less than Effi ciency Considerations 2% total additional loss. The effi ciency of a switching regulator is equal to the output power divided by the input power times 100%. It is often Checking Transient Response useful to analyze individual losses to determine what is The regulator loop response can be checked by looking limiting effi ciency and which change would produce the at the load transient response. Switching regulators take most improvement. Effi ciency can be expressed as: several cycles to respond to a step in load current. When Effi ciency = 100% – (L1 + L2 + L3 + …) a load step occurs, VOUT immediately shifts by an amount equal to (ΔI ) • (ESR), where ESR is the effective se- LOAD where L1, L2, etc. are the individual losses as a percentage ries resistance of C . ΔI also begins to charge or OUT LOAD of input power. discharge C generating a feedback error signal used OUT Although all dissipative elements in the circuit produce by the regulator to return V to its steady-state value. OUT losses, four main sources usually account for most of During this recovery time, V can be monitored for OUT the losses in LTC3809-1 circuits: 1) LTC3809-1 DC bias overshoot or ringing that would indicate a stability problem. current, 2) MOSFET gate-charge current, 3) I2R losses OPTI-LOOP compensation allows the transient response and 4) transition losses. to be optimized over a wide range of output capacitance and ESR values. 1) The V (pin) current is the DC supply current, given IN in the Electrical Characteristics, which excludes MOSFET The I series R -C fi lter (see Functional Diagram) sets TH C C driver currents. V current results in a small loss that the dominant pole-zero loop compensation. IN increases with V . IN The I external components showed in the fi gure on the TH 2) MOSFET gate-charge current results from switching fi rst page of this data sheet will provide adequate compen- the gate capacitance of the power MOSFET. Each time a sation for most applications. The values can be modifi ed MOSFET gate is switched from low to high to low again, slightly (from 0.2 to 5 times their suggested values) to a packet of charge dQ moves from V to ground. The optimize transient response once the fi nal PC layout is done IN resulting dQ/dt is a current out of V , which is typically and the particular output capacitor type and value have IN much larger than the DC supply current. In continuous been determined. The output capacitor needs to be decided mode, I = f • Q . upon because the various types and values determine the GATECHG P loop feedback factor gain and phase. An output current 38091fc 19

LTC3809-1 APPLICATIONS INFORMATION pulse of 20% to 100% of full load current having a rise A 0.032Ω P-channel MOSFET in Si7540DP is close to time of 1μs to 10μs will produce output voltage and I this value. TH pin waveforms that will give a sense of the overall loop The N-channel MOSFET in Si7540DP has 0.017Ω R . DS(ON) stability. The gain of the loop will be increased by increas- The short-circuit current is: ing R and the bandwidth of the loop will be increased C by decreasing C . The output voltage settling behavior is 90mV C I = =5.3A related to the stability of the closed-loop system and will SC 0.017Ω demonstrate the actual overall supply performance. For So the inductor current rating should be higher than 5.3A. a detailed explanation of optimizing the compensation components, including a review of control loop theory, The LTC3809-1 operates at a frequency of 550kHz. For refer to Application Note 76. continuous Burst Mode operation with 600mA I , RIPPLE the required minimum inductor value is: A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The ⎛ ⎞ 1.8V 1.8V discharged bypass capacitors are effectively put in parallel L = •⎜1− ⎟ =1.88μH MIN 550kHz•600mA ⎝ 2.75V⎠ with C , causing a rapid drop in V . No regulator can OUT OUT deliver enough current to prevent this problem if the load A 6A 2.2μH inductor works well for this application. switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that C will require an RMS current rating of at least 1A IN the load rise time is limited to approximately (25) • (C ). at temperature. A C with 0.1Ω ESR will cause LOAD OUT Thus a 10μF capacitor would be require a 250μs rise time, approximately 60mV output ripple. limiting the charging current to about 200mA. PC Board Layout Checklist Design Example When laying out the printed circuit board, use the following As a design example, assume V will be operating from a checklist to ensure proper operation of the LTC3809-1. IN maximum of 4.2V down to a minimum of 2.75V (powered • The power loop (input capacitor, MOSFET, inductor, by a single lithium-ion battery). Load current requirement output capacitor) should be as small as possible and is a maximum of 2A, but most of the time it will be in a isolated as much as possible from LTC3809-1. standby mode requiring only 2mA. Effi ciency at both low • Put the feedback resistors close to the V pins. The I and high load currents is important. Burst Mode operation FB TH compensation components should also be very close at light loads is desired. Output voltage is 1.8V. The IPRG to the LTC3809-1. pin will be left fl oating, so the maximum current sense threshold ΔVSENSE(MAX) is approximately 125mV. • The current sense traces should be Kelvin connections V right at the P-channel MOSFET source and drain. Maximum Duty Cycle = OUT =65.5% V • Keeping the switch node (SW) and the gate driver nodes IN(MIN) (TG, BG) away from the small-signal components, From Figure 1, SF = 82%. especially the feedback resistors, and I compensation TH components. 5 ΔV R = •0.9•SF• SENSE(MAX) =0.032Ω DS(ON)MAX 6 I •ρρ OUT(MAX) T 38091fc 20

LTC3809-1 TYPICAL APPLICATIONS VIN 2.75V TO 8V 1 10μF MODE 9 VIN 6 8 MP IPRG TG 2C2I0TpHF R1I5TkH 4 ITH LTC3809EDD-1 SW 10 Si7540DP 1.5LμH V2.O5UVT (5A AT 5VIN) 2 7 MN TRACK/SS BG 187k 3 VFB GND RUN 5 Si7540DP 1C5O0UμFT + 11 59k 100pF L: VISHAY IHLP-2525CZ-01 38091 F08 COUT: SANYO 4TPB150MC Figure 8. 550kHz, Synchronous DC/DC Converter with Internal Soft-Start VIN 2.75V TO 8V 10μF 1 MODE 9 VIN 6 8 MP IPRG TG Si3447BDV L 470pF 15k 4 ITH LTC3809EDD-1 SW 10 1.5μH V1.O8UVT 10nF 2A 2 7 MN TRACK/SS BG Si3460DV 118k 3 VFB GND RUN 5 C2O2UμFT D x2 59k 11 (OPT) 100pF L: VISHAY IHLP-2525CZ-01 38091 F09 D: ON SEMI MBRM120LT3 (OPTIONAL) Figure 9. 550kHz, Synchronous DC/DC Converter with External Soft-Start, Ceramic Output Capacitor 38091fc 21

LTC3809-1 TYPICAL APPLICATIONS Synchronous DC/DC Converter with Output Tracking VIN 2.75V TO 8V 1 10μF MODE 9 VIN 6 8 MP IPRG TG Si7540DP L 220pF 15k 4 ITH LTC3809EDD-1 SW 10 1.5μH V1.O8UVT 1.18k 2 7 MN (5A AT 5VIN) Vx TRACK/SS BG Si7540DP + 590Ω COUT 118k 3 5 150μF VFB GND RUN 11 59k 100pF L: VISHAY IHLP-2525CZ-01 38091 TA03 COUT: SANYO 4TPB150MC VOUT < Vx PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 0.38(cid:112) 0.10 TYP 6 10 0.675(cid:112)(cid:0)0.05 3.50(cid:112)(cid:0)0.05 1.65(cid:112)(cid:0)0.05 3.00(cid:112)(cid:0)0.10 1.65(cid:112) 0.10 2.15(cid:112)(cid:0)0.05 (2 SIDES) (4 SIDES) (2 SIDES) PIN 1 PACKAGE TOP MARK OUTLINE (SEE NOTE 6) (DD10) DFN 1103 5 1 0.25(cid:112) 0.05 0.200 REF 0.75(cid:112)(cid:0)0.05 0.25(cid:112) 0.05 0.50 0.50 BSC BSC 2.38(cid:112)(cid:0)0.10 2.38(cid:112)(cid:0)0.05 0.00 – 0.05 (2 SIDES) (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON OF VARIATION ASSIGNMENT ANY SIDE 2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED 3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 38091fc 22

LTC3809-1 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev C) BOTTOM VIEW OF EXPOSED PAD OPTION 2.06(cid:112) 0.102 2(..179104(cid:112)(cid:112) 0.0.10042) 0(..808395(cid:112)(cid:112) 0.0.10257) 1 (.081(cid:112) .004) 0.29 1.83(cid:112) 0.102 REF (.072(cid:112) .004) 5.23 0.05 REF 2.083(cid:112) 0.102 3.20 – 3.45 (.206) (.082(cid:112) .004) (.126 – .136) DETAIL “B” MIN CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 10 NO MEASUREMENT PURPOSE 0.305(cid:112) 0.038 0.50 3.00(cid:112) 0.102 (.0120(cid:112) .0015) (.0197) (.118(cid:112) .004) 0.497(cid:112) 0.076 TYP BSC (NOTE 3) (.0196(cid:112) .003) RECOMMENDED SOLDER PAD LAYOUT 10 9 8 76 REF 4.90(cid:112) 0.152 3.00(cid:112) 0.102 (.193(cid:112) .006) (.118(cid:112) .004) (NOTE 4) DETAIL “A” 0.254 (.010) 0(cid:111) – 6(cid:111) TYP GAUGE PLANE 1 2 3 4 5 0.53(cid:112) 0.152 1.10 0.86 (.021(cid:112) .006) (.043) (.034) MAX REF DETAIL “A” 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016(cid:112) 0.0508 (.007 – .011) (.004(cid:112) .002) 0.50 TYP (.0197) MSOP (MSE) 0908 REV C NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 38091fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 23 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3809-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1628/LTC3728 Dual High Effi ciency, 2-Phase Synchronous Step Down Controllers Constant Frequency, Standby, 5V and 3.3V LDOs, V to 36V, IN LTC1735 High Effi ciency Synchronous Step-Down Controller Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ V ≤ 36V IN LTC1773 Synchronous Step-Down Controller 2.65V ≤ V ≤ 8.5V, I Up to 4A, 10-Lead MSOP IN OUT LTC1778 No R , Synchronous Step-Down Controller Current Mode Operation Without Sense Resistor, SENSE Fast Transient Response, 4V ≤ V ≤ 36V IN LTC1872 Constant Frequency Current Mode Step-Up Controller 2.5V ≤ V ≤ 9.8V, SOT-23 Package, 550kHz IN LTC3411 1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, V : 2.5V to 5.5V, V = 0.8V, I = 60μA, OUT IN OUT Q I = <1μA, MS Package SD LTC3412 2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter 95% Effi ciency, V : 2.5V to 5.5V, V = 0.8V, I = 60μA, OUT IN OUT Q I = <1μA, TSSOP-16E Package SD LTC3416 4A, 4MHz, Monolithic Synchronous Step-Down Regulator Tracking Input to Provide Easy Supply Sequencing, 2.25V ≤ V ≤ 5.5V, 20-Lead TSSOP Package IN LTC3418 8A, 4MHz, Monolithic Synchronous Regulator Tracking Input to Provide Easy Supply Sequencing, 2.25V ≤ V ≤ 5.5V, QFN Package IN LTC3701 2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller 2.5V ≤ V ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP IN LTC3708 2-Phase, No R , Dual Synchronous Controller with Constant On-Time Dual Controller, V Up to 36V, Very Low SENSE IN Output Tracking Duty Cycle Operation, 5mm × 5mm QFN Package LTC3736/LTC3736-2 2-Phase, No RSENSE, Dual Synchronous Controller with 2.75V ≤ VIN ≤ 9.8V, 0.6V ≤ VOUT ≤ VIN, 4mm × 4mm QFN Output Tracking LTC3736-1 Low EMI, 2-Phase, No R , Dual Synchronous Controller with Integrated Spread Spectrum for 20dB Lower “Noise,” SENSE Output Tracking 2.75V ≤ V ≤ 9.8V IN LTC3737 2-Phase, No RSENSE, Dual DC/DC Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 0.6V ≤ VOUT ≤ VIN, 4mm × 4mm QFN LTC3772 Micropower, No R , Constant Frequency Step-Down Controller 40μA No-Load IQ, Non-Synchronous, 2.75V ≤ V ≤ 9.8V, SENSE IN 550kHz, 3mm × 2mm DFN or 8-Lead TSOT-23 Packages. LTC3776 Dual, 2-Phase, No R , Synchronous Controller for DDR/QDR Provides V and V with One IC, 2.75V ≤ V ≤ 9.8V, SENSE DDQ TT IN Memory Termination Adjustable Constant Frequency with PLL Up to 850kHz, Spread Spectrum Operation, 4mm × 4mm QFN and 24-Lead SSOP Packages LTC3808 No RSENSE, Low EMI, Synchronous Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 4mm × 3mm DFN, Spread Spectrum for 20dB Lower Peak Noise LTC3809 No RSENSE, Low EMI, Synchronous DC/DC Controller 2.75V ≤ VIN ≤ 9.8V, 3mm × 3mm DFN and 10-Lead MSOPE Packages, Spread Spectrum for 20dB Lower Peak Noise PolyPhase is a trademark of Linear Technology Corporation. 38091fc 24 Linear Technology Corporation LT 1108 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005