LTC3805-5 Adjustable Frequency Current Mode Flyback/ Boost/SEPIC DC/DC Controller FEATURES DESCRIPTION n V and V Limited Only by External Components The LTC®3805-5 is a current mode DC/DC controller de- IN OUT n 4.5V Undervoltage Lockout Threshold signed to drive an N-channel MOSFET in flyback, boost n Adjustable Slope Compensation and SEPIC converter applications. Operating frequency n Adjustable Overcurrent Protection with Automatic and slope compensation can be programmed by external Restart resistors. Programmable overcurrent sensing protects n Adjustable Operating Frequency (70kHz to 700kHz) the converter from overload and short-circuit conditions. With One External Resistor Soft-start can be programmed using an external capacitor n Synchronizable to an External Clock and the soft-start capacitor also programs an automatic n ±1.5% Reference Accuracy restart feature. n Only 100mV Current Sense Voltage Drop The LTC3805-5 provides ±1.5% output voltage accuracy n RUN Pin with Precision Threshold and Adjustable and consumes only 360µA of quiescent current during Hysteresis normal operation and only 40µA during micropower start- n Programmable Soft-Start with One External Capacitor up. Using a 9.5V internal shunt regulator, the LTC3805-5 n Low Quiescent Current: 360µA can be powered from a high V through a resistor or it IN n Small 10-Lead MSOP and 3mm × 3mm DFN can be powered directly from a low impedance DC voltage from 4.7V to 8.8V. APPLICATIONS The LTC3805-5 is available in the 10-lead MSOP package n Automotive Power Supplies and the 3mm × 3mm DFN package. n Telecom Power Supplies L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered n Isolated Electronic Equipment trademarks, No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Auxiliary/Housekeeping Power Supplies n Power over Ethernet TYPICAL APPLICATION 5V to 12V/1A Boost Converter Efficiency and Power Loss vs Load Current 100 2.5 UPS840 4.3µH VOUT V5IVN 22µF 112AV 95 5V EFFICIENCY 2.0 100µF ×2 VCC 8.5V EFFICIENCY P RUNLTC3805-5GATE 1.33k NCY (%) 90 8.5V LOSS 1.5 OWER L 20k 0.1µF ISTSHFLT ISENOSCE 3k 191k EFFICIE 85 5V LOSS 1 OSS (W) FS FB 80 0.5 SYNC GND 470pF 118k 8mΩ 13.7k 38055 TA01a 75 0 0.01 0.1 1 10 LOAD CURRENT (A) 38055TA01b 38055fe 1

LTC3805-5 ABSOLUTE MAXIMUM RATINGS (Note 1) V to GND OC, I ....................................................–0.3V to 1V CC SENSE Low Impedance Source ........................–0.3V to 8.8V Operating Junction Temperature Range Current Fed ........................................25mA into V * (Notes 2, 3) ...........................................–55°C to 150°C CC SYNC ...........................................................–0.3V to 6V Storage Temperature Range ..................–65°C to 150°C SSFLT...........................................................–0.3V to 5V Lead Temperature (Soldering, 10 sec) FB, I , FS .................................................–0.3V to 3.5V MSE Package ....................................................300°C TH RUN ...........................................................–0.3V to 18V *LTC3805-5 internal clamp circuit regulates V voltage to 9.5V CC PIN CONFIGURATION TOP VIEW TOP VIEW SSFLT 1 10 GATE SSFLT 1 10 GATE ITH 2 9 VCC ITH 2 9 VCC FB 3 11 8 OC FB 3 11 8 OC RUN 4 7 ISENSE RUFNS 45 76 ISSYENNSCE FS 5 6 SYNC MSE PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN EXPOSED PAD (PTINJM 1A1X) =IS 1 G25N°DC,, MθJUAS =T 4B5E° CC/OWN NECTED TO GND TJMAX = 125°C, θJA = 45°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE CONNECTED TO GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3805EMSE-5#PBF LTC3805EMSE-5#TRPBF LTDGX 10-Lead Plastic MSOP –40°C to 85°C LTC3805IMSE-5#PBF LTC3805IMSE-5#TRPBF LTDGX 10-Lead Plastic MSOP –40°C to 125°C LTC3805HMSE-5#PBF LTC3805HMSE-5#TRPBF LTDGX 10-Lead Plastic MSOP –40°C to 150°C LTC3805MPMSE-5#PBF LTC3805MPMSE-5#TRPBF LTDGX 10-Lead Plastic MSOP –55°C to 150°C LTC3805EDD-5#PBF LTC3805EDD-5#TRPBF LDHB 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC3805IDD-5#PBF LTC3805IDD-5#TRPBF LDHB 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 38055fe 2

LTC3805-5 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C, V = 5V, unless otherwise noted (Note 2). A CC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V V Turn-On Voltage V Rising l 4.3 4.5 4.7 V TURNON CC CC V V Turn-Off Voltage V Falling l 3.75 3.95 4.15 V TURNOFF CC CC V V Hysteresis 0.55 V HYST CC V V Shunt Regulator Voltage I = 1mA, V = 0 l 8.8 9.25 9.65 V CLAMP1mA CC CC RUN V V Shunt Regulator Voltage I = 25mA, V = 0 l 8.9 9.5 9.9 V CLAMP25mA CC CC RUN I Input DC Supply Current Normal Operation (f = 200kHz) 360 µA CC OSC (Note 4) V < V or V < V – 100mV l 40 90 µA RUN RUNON CC TURNON (Micropower Start-Up) V RUN Turn-On Voltage V = V + 100mV l 1.122 1.207 1.292 V RUNON CC TURNON V RUN Turn-Off Voltage V = V + 100mV l 1.092 1.170 1.248 V RUNOFF CC TURNON I RUN Hysteresis Current l 4 5 5.8 µA RUN(HYST) V Regulated Feedback Voltage 0°C ≤ T ≤ 85°C (E-Grade) (Note 5) 0.788 0.800 0.812 V FB J –40°C ≤ T ≤ 85°C (E-Grade) (Note 5) l 0.780 0.800 0.812 V J –40°C ≤ T ≤ 125°C (I-Grade) (Note 5) l 0.780 0.800 0.812 V J –40°C ≤ T ≤ 150°C (H-Grade) (Note 5) l 0.770 0.800 0.820 V J –55°C ≤ TJ ≤ 150°C (MP-Grade) l 0.770 0.800 0.820 V I V Input Current V = 1.3V (Note 5) 20 nA FB FB ITH g Error Amplifier Transconductance I Pin Load = ±5µA (Note 5) 333 µA/V m TH DVO(LINE) Output Voltage Line Regulation VTURNOFF < VCC < VCLAMP1mA (Note 5) 0.05 mV/V DVO(LOAD) Output Voltage Load Regulation ITH Sinking 5µA (Note 5) 3 mV/µA I Sourcing 5µA (Note 5) 3 mV/µA TH f Oscillator Frequency R = 350k 70 kHz OSC FS R = 36k 700 kHz FS DC Minimum Switch-On Duty Cycle f = 200kHz 6 9 % ON(MIN) OSC DC Maximum Switch-On Duty Cycle f = 200kHz 70 80 95 % ON(MAX) OSC f As a Function of f 70kHz < f < 700kHz, 67 133 % SYNC OSC OSC 70kHz < f < 700kHz SYNC V Minimum SYNC Amplitude 2.9 V SYNC I Soft-Start Current –6 µA SS I Fault Timeout Current 2 µA FTO t Internal Soft-Start Time No External Capacitor on SSFLT 1.8 ms SS(INT) t Internal Fault Timeout No External Capacitor on SSFLT 4.5 ms FTO(INT) t Gate Drive Rise Time C = 3000pF 30 ns RISE LOAD t Gate Drive Fall Time C = 3000pF 30 ns FALL LOAD V Peak Current Sense Voltage R = 0 (Note 6) l 85 100 115 mV I(MAX) SL I Peak Slope Compensation Output Current (Note 7) 10 µA SL(MAX) V Overcurrent Threshold R = 0 (Note 8) l 85 100 115 mV OCT OC I Overcurrent Threshold Adjust Current 10 µA OC 38055fe 3

LTC3805-5 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: T is calculated from the ambient temperature T and power J A may cause permanent damage to the device. Exposure to any Absolute dissipation P according to the following formula: D Maximum Rating condition for extended periods may affect device T = T + (P • 45°C/W) J A D reliability and lifetime. Note 4: Dynamic supply current is higher due to the gate charge being Note 2: The LTC3805-5 is tested under pulsed conditions such that delivered at the switching frequency. T ≈ T . The LTC3805E-5 is guaranteed to meet specifications from J A Note 5: The LTC3805-5 is tested in a feedback loop that servos V to the FB 0°C to 85°C. Specifications over the –40°C to 85°C operating junction output of the error amplifier while maintaining I at the midpoint of the TH temperature range are assured by design, characterization and correlation current limit range. with statistical process controls. The LTC3805I-5 is guaranteed over the Note 6: Peak current sense voltage is reduced dependent on duty cycle –40°C to 125°C operating junction temperature range, the LTC3805H-5 is and an optional external resistor in series with the SENSE pin. For guaranteed over the full –40°C to 150°C operating junction temperature details, refer to Programmable Slope Compensation in the Applications range and the LTC3805MP-5 is tested and guaranteed over the full –55°C Information section. to 150°C operating temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction Note 7: Guaranteed by design. temperatures greater than 125°C. Note that the maximum ambient Note 8: Overcurrent threshold voltage is reduced dependent on an temperature consistent with these specifications is determined by specific optional external resistor in series with the OC pin. For details, refer to operating conditions in conjunction with board layout, the rated package Programmable Overcurrent in the Applications Information section. thermal resistance and other environmental factors. 38055fe 4

LTC3805-5 TYPICAL PERFORMANCE CHARACTERISTICS Reference Voltage Reference Voltage vs Temperature vs Supply Voltage Oscillator Frequency vs R FS 812 0.800300 800 700 808 0.800200 600 V) 804 0.800100 m 500 V VOLTAGE (FB 789060 V (V)FB00..789090900000 f (kHz)OSC430000 200 792 0.799800 100 788 0.799700 0 –75 –50 –25 0 25 50 75 100 125 150 4 5 6 7 8 9 10 0 100 200 300 400 TEMPERATURE (°C) VCC (V) RFS (kΩ) 38055 G01 38055 G02 38055 G03 Oscillator Frequency Oscillator Frequency RUN Undervoltage Lockout vs Supply Voltage vs Temperature Thresholds vs Temperature 203 202 1.205 202 1.200 VRUN(ON) Hz) k201 201 Y ( 1.195 f (kHz)OSC210909 RFS = 124kΩ OR FREQUENC200 RFS = 124kΩ N VOLTAGE (V)11..119805 T U 198 CILLA199 R1.180 VRUN(OFF) S O 197 1.175 196 198 1.170 4 5 6 7 8 9 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 VCC (V) TEMPERATURE (°C) TEMPERATURE (°C) 38055 G04 38055 G05 38055 G06 RUN Hysteresis Current V Undervoltage Lockout CC vs Temperature Thresholds vs Temperature 5.20 5.0 5.10 T (V) VTURN(ON) U 4.5 O K C O IRUN(HYST) 45..9000 VOLTAGE L 4.0 VTURN(OFF) R E D UN 3.5 4.80 C C V 4.70 3.0 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) 38055 G07 38055 G08 38055fe 5

LTC3805-5 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up I Supply Current I Supply Current V Shunt Regulator Voltage CC CC CC vs Temperature vs Temperature vs Temperature 50 360 9.60 48 9.55 µA) 46 350 VCLAMP25mA UP SUPPLY CURRENT ( 3444382406 UPPLY CURRENT (µA) 333234000 V (V)CLAMP 9999....54430505 ART- 34 S 9.30 VCLAMP1mA ST 310 9.25 32 30 300 9.20 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 38055 G09 38055 G10 38055 G11 Peak Current Sense Voltage Overcurrent Threshold Internal Soft-Start Time vs Temperature vs Temperature vs Temperature 100.8 104 2.20 V)100.6 m V) s) 2.15 PEAK CURRENT SENSE VOLTAGE (11199000999900099.......4224086 OVERCURRENT THRESHOLD (m 1199006802 INTERNAL SOFT-START TIME (m 2122....09100505 99.0 94 1.90 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 38055 G12 38055 G13 38055 G14 External Soft-Start Current External Timeout Current vs Temperature vs Temperature 5.4 2.1 5.3 A) µ ENT (µA) 55..12 URRENT (21..09 R C R 5.0 T U U C O RT 4.9 ME1.8 STA 4.8 L TI OFT- 4.7 RNA1.7 S E I SS 4.6 EXTO1.6 4.5 IFT 4.4 1.5 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) 38055 G15 38055 G16 38055fe 6

LTC3805-5 PIN FUNCTIONS SSFLT (Pin 1): Soft-Start Pin. A capacitor placed from I (Pin 7): Performs two functions: for current mode SENSE this pin to GND (Exposed Pad) controls the rate of rise of control, it monitors the switch current, using the voltage converter output voltage during start-up. This capacitor is across an external current sense resistor. Pin 7 also injects also used for time out after a fault prior to restart. a current ramp that develops slope compensation voltage across an optional external programming resistor. I (Pin 2): Error Amplifier Compensation Point. Normal TH operating voltage range is clamped between 0.7V and OC (Pin 8): Overcurrent Pin. Connect this pin to the ex- 1.9V. ternal switch current sense resistor. An additional resistor programs the overcurrent trip level. FB (Pin 3): Receives the feedback voltage from an external resistor divider across the output. V (Pin 9): Supply Pin. A capacitor must closely decouple CC V to GND (Exposed Pad). RUN (Pin 4): An external resistor divider connects this pin CC to V and sets the thresholds for converter operation. GATE (Pin 10): Gate Drive for the External N-Channel IN MOSFET. This pin swings from GND to V . FS (Pin 5): A resistor connected from this pin to ground CC sets the frequency of operation. GND (Exposed Pad Pin 11): Ground. A capacitor must closely decouple GND to V (Pin 9). The exposed pad SYNC (Pin 6): Input to synchronize the oscillator to an CC must be soldered to electrical ground on PCB for electrical external source. contact and rated thermal performance. BLOCK DIAGRAM 9 4 VCC RUN 800mV SOFT-START RAMP UNDERVOLTAGE REFERENCE LOCKOUT SSFLT 1 SHUTDOWN SOFT-START OVERCURRENT FAULT 10µA COMPARATOR OC 8 + 100mV – CURRENT – COMPARATOR ERROR SWITCHING GATE + AMPLIFIER + R Q LBOLGAINCK AINNGD DRIVER GATE 10 S CIRCUIT FB 3 – SLOPE SHUTDOWN 20mV COMP CURRENT OSCILLATOR RAMP ITH CLAMPS GND 11 ISENSE 1.2V 7 ITH FS SYNC 2 5 6 38055 BD 38055fe 7

LTC3805-5 OPERATION The LTC3805-5 is a programmable-frequency current mode does the voltage on the I pin. The LTC3805-5’s cur- SENSE controller for flyback, boost and SEPIC DC/DC converters. rent comparator trips when the voltage on the I pin SENSE The LTC3805-5 is designed so that none of its pins need exceeds a voltage proportional to the voltage on the I pin. TH to come in contact with the input or output voltages of This resets the SR latch and turns off the external power the power supply circuit of which it is a part, allowing MOSFET. In this way, the peak current levels through the the conversion of voltages well beyond the LTC3805-5’s external MOSFET and the flyback transformer’s primary absolute maximum ratings. and secondary windings are controlled by the voltage on the I pin. If the current comparator does not trip, the TH Main Control Loop LTC3805-5 automatically limits the duty cycle to 80%, resets the SR latch, and turns off the external MOSFET. Please refer to the Block Diagram of this data sheet and the Typical Application shown on the front page. An ex- The path from the FB pin, through the error amplifier, ternal resistive voltage divider presents a fraction of the current comparator and the SR latch implements the output voltage to the FB pin. The divider is designed so closed-loop current mode control required to regulate the that when the output is at the desired voltage, the FB pin output voltage against changes in input voltage or output voltage equals the 800mV internal reference voltage. If current. For example, if the load current increases, the the load current increases, the output voltage decreases output voltage decreases slightly, and sensing this, the slightly, causing the FB pin voltage to fall below the 800mV error amplifier sources current from the I pin, raising TH reference. The error amplifier responds by feeding current the current comparator threshold, thus increasing the peak into the ITH pin causing its voltage to rise. Conversely, if currents through the transformer primary and secondary. the load current decreases, the FB voltage rises above the This delivers more current to the load and restores the 800mV reference and the error amplifier sinks current away output voltage to the desired level. from the I pin causing its voltage to fall. TH The I pin serves as the compensation point for the control TH The voltage at the ITH pin controls the pulse-width modula- loop. Typically, an external series RC network is connected tor formed by the oscillator, current comparator and SR from I to ground and is chosen for optimal response to TH latch. Specifically, the voltage at the ITH pin sets the cur- load and line transients. The impedance of this RC network rent comparator’s trip threshold. The current comparator’s converts the output current of the error amplifier to the ISENSE input monitors the voltage across an external current ITH voltage which sets the current comparator threshold sense resistor in series with the source of the external and commands considerable influence over the dynamics MOSFET. At the start of a cycle, the LTC3805-5’s oscillator of the voltage regulation loop. sets the SR latch and turns on the external power MOSFET. The current through the external power MOSFET rises as 38055fe 8

LTC3805-5 OPERATION Start-Up/Shutdown Setting the Oscillator Frequency The LTC3805-5 has two shutdown mechanisms to disable Connect a frequency set resistor R from the FS pin to FS and enable operation: an undervoltage lockout on the V ground to set the oscillator frequency over a range from CC supply pin voltage, and a precision-threshold RUN pin. The 70kHz to 700kHz. The oscillator frequency is calculated voltage on both pins must exceed the appropriate threshold from: before operation is enabled. The LTC3805-5 transitions 9 24•10 into and out of shutdown according to the state diagram f = OSC shown in Figure 1. Operation in fault timeout is discussed R −1500 FS in a subsequent section. During shutdown the LTC3805-5 The oscillator may be synchronized to an external clock draws only a small 40µA current. using the SYNC input. The rising edge of the external clock The undervoltage lockout (UVLO) mechanism prevents on the SYNC pin triggers the beginning of a switching the LTC3805-5 from trying to drive the external MOSFET period, i.e., the GATE pin going high. The pulse width of gate with insufficient voltage on the V pin. The voltage CC the external clock is quite flexible. at the V pin must initially exceed V = 4.5V to en- CC TURNON able LTC3805-5 operation. After operation is enabled, the Overcurrent Protection voltage on the V pin may fall as low as V = 4V CC TURNOFF With the OC pin connected to the external MOSFET’s current before undervoltage lockout disables the LTC3805-5. See sense resistor, the converter is protected in the event of the Applications Information section for more detail. an overload or short-circuit on the output. During normal The RUN pin is connected to the input voltage using a operation the peak value of current in the external MOSFET, voltage divider. Converter operation is enabled when the as measured by the current sense resistor (plus any adjust- voltage on the RUN pin exceeds V = 1.207V and ment for slope compensation), is set by the voltage on the RUNON disabled when the voltage falls below VRUNOFF = 1.170V. ITH pin operating through the current comparator. As the Additional hysteresis is added by a 5µA current source output current increases, so does the voltage on the ITH pin and so does the peak MOSFET current. acting on the voltage divider’s Thevenin resistance. Setting the input voltage range and hysteresis is further discussed in the Applications Information section. VRUN > VRUNON AND VCC > VTURNON LTC3805-5 VRUN < VRUNOFF LTC3805-5 SHUTDOWN ENABLED VCC < VTURNOFF LTC3805-5 VSSFLT < 0.7V TIFMAEUOLTUT VOC > 100mV 38055 F01 Figure 1. Start-Up/Shutdown State Diagram 38055fe 9

LTC3805-5 OPERATION First, consider operation without overcurrent protection. Add a capacitor C from the SSFLT pin to GND to increase SS For some maximum converter output current, the voltage both the soft-start time and the time for fault timeout. Dur- on the I pin rises to and is clamped at approximately 1.9V. ing soft-start, C is charged with a 6µA current. When the TH SS This corresponds to a 100mV limit on the voltage at the LTC3805-5 comes out of shutdown, the LTC3805-5 quickly I pin. As the output current is further increased, the charges C to about 0.7V at which point GATE begins SENSE SS duty cycle is reduced as the output voltage sags. However, switching. From that point, GATE continues switching with the peak current in the external MOSFET is limited by the increasing duty cycle until the SSFLT pin reaches about 100mV threshold at the I pin. 2.25V at which point soft-start is over and closed-loop SENSE regulation begins. The voltage on the SSFLT pin addition- As the output current is increased further, eventually, ally further charges to about 4.75V. the duty cycle is reduced to the 6% minimum. Since the external MOSFET is always turned on for this minimum C also performs the timeout function in the event of a SS amount of time, the current comparator no longer limits fault. After a fault, C is slowly discharged from about SS the current through the external MOSFET based on the 4.75V to about 0.7V by a 2µA current. When the voltage 100mV threshold. If the output current continues to in- on the SSFLT pin reaches 0.7V the converter attempts to crease, the current through the MOSFET could rise to a restart. More detail on programming the external soft-start level that would damage the converter. fault timeout is described in the Applications Information section. To prevent damage, the overcurrent pin, OC, is also connected to the current sense resistor, and a fault is Powering the LTC3805-5 triggered if the voltage on the OC pin exceeds 100mV. To protect itself, the converter stops operating as described A built-in shunt regulator from the VCC pin to GND limits in the next section. External resistors can be used to ad- the voltage on the VCC pin to approximately 9.5V as long just the overcurrent threshold to voltages higher or lower as the shunt regulator is not forced to sink more than than 100mV as described in the Applications Information 25mA. The shunt regulator is always active, even when section. the LTC3805-5 is in shutdown, since it serves the vital function of protecting the V pin from overvoltage. The CC Soft-Start and Fault Timeout Operation shunt regulator permits the use of a wide variety of pow- ering schemes for the LTC3805-5 even from high voltage The soft-start and fault timeout of the LTC3805-5 uses either sources that exceed the LTC3805-5’s absolute maximum a fixed internal timer or an external timer programmed ratings. Further details on powering schemes are described by a capacitor from the SSFLT pin to GND. The internal in the Applications Information section. soft-start and fault timeout times are minimums and can be increased by placing a capacitor from the SSFLT pin Adjustable Slope Compensation to GND. Operation is shown in Figure 1. The LTC3805-5 injects a 10µA peak current ramp out of Leave the SSFLT pin open to use the internal soft-start and its I pin which can be used, in conjunction with an SENSE fault timeout. The internal soft-start is complete in about external resistor, for slope compensation in designs that 1.8ms. In the event of an overcurrent as detected by the require it. This current ramp is approximately linear and OC pin exceeding 100mV, the LTC3805-5 shuts down and begins at zero current at 6% duty cycle, reaching peak an internal timing circuit waits for a fault timeout of about current at 80% duty cycle. Additional details are provided 4.25ms and then restarts the converter. in the Applications Information section. 38055fe 10

LTC3805-5 APPLICATIONS INFORMATION Many LTC3805-5 application circuits can be derived from The typical application circuit in Figure 9 shows a different the topologies shown on the first page or in the Typical flyback converter bias power strategy for a case in which Applications section of this data sheet. neither the input or output voltage is suitable for providing bias power to the LTC3805-5. A small NPN preregulator The LTC3805-5 itself imposes no limits on allowed input transistor and a Zener diode are used to accelerate the voltage V or output voltage V . These are all determined IN OUT rise of V and reduce the value of the V bias capacitor. by the ratings of the external power components. In Figure 8, CC CC The flyback transformer has an additional bias winding to the factors are: Q1 maximum drain-source voltage (B ), VDSS provide bias power. Note that this topology is very power- on-resistance (R ) and maximum drain current, T1 DS(ON) ful because, by appropriate choice of transformer turns saturation flux level and winding insulation breakdown ratio, the output voltage can be chosen without regard to voltages, C and C maximum working voltage, equiva- IN OUT the value of the input voltage or the V bias power for lent series resistance (ESR), and maximum ripple current CC the LTC3805-5. The number of turns in the bias winding ratings, and D1 and R power ratings. SENSE is chosen according to VCC Bias Power N =N VCC +VD2 BIAS SEC The VCC pin must be bypassed to the GND pin with a VOUT +VD1 minimum 1µF ceramic or tantalum capacitor located im- where N is the number of turns in the bias winding, mediately adjacent to the two pins. Proper supply bypassing BIAS N is the number of turns in the secondary winding, is necessary to supply the high transient currents required SEC V is the desired voltage to power the LTC3805-5, V by the MOSFET gate driver. CC OUT is the converter output voltage, V is the forward voltage D1 For maximum flexibility, the LTC3805-5 is designed so drop of D1 and V is the forward voltage drop of D2. D2 that it can be operated from voltages well beyond the Note that since V is regulated by the converter control OUT LTC3805-5’s absolute maximum ratings. Figure 2 shows loop, V is also regulated although not as precisely. If an CC the simplest case, in which the LTC3805-5 is powered “off-the-shelf” transformer with excessive bias windings with a resistor R connected between the input voltage is used, the resistor, R in Figure 9, can be added to VCC BIAS and V . The built-in shunt regulator limits the voltage on limit the current. CC the V pin to around 9.5V as long as the internal shunt CC regulator is not forced to sink more than 25mA. This pow- Transformer Design Considerations ering scheme has the drawback that the power loss in the Transformer specification and design is perhaps the most resistor reduces converter efficiency and the 25mA shunt critical part of applying the LTC3805-5 successfully. In regulator maximum may limit the maximum-to-minimum addition to the usual list of caveats dealing with high fre- range of input voltage. quency power transformer design, the following should prove useful. VIN LTC3805-5 Turns Ratios RVCC Due to the use of the external feedback resistor divider VCC ratio to set output voltage, the user has relative freedom CVCC GND in selecting transformer turns ratio to suit a given ap- plication. Simple ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in 38055 F02 setting total turns and transformer inductance. Simple Figure 2. Powering the LTC3805-5 via the Internal Shunt Regulator integer turns ratios also facilitate the use of “off-the-shelf” configurable transformers. Turns ratio can be chosen on 38055fe 11

LTC3805-5 APPLICATIONS INFORMATION the basis of desired duty cycle. However, remember that To introduce further user-programmable hysteresis, the the input supply voltage plus the secondary-to-primary LTC3805-5 sources 5µA out of the RUN pin when operation referred version of the flyback pulse (including leakage of LTC3805-5 is enabled. As a result, the falling threshold spike) must not exceed the allowed external MOSFET for the RUN pin also depends on the value of R1 and can breakdown rating. be programmed by the user. The falling threshold for V IN is therefore Leakage Inductance R1+R2 V =V • −R1•5µA Transformer leakage inductance (on either the primary IN(RUN,FALLING) RUNOFF R2 or secondary) causes a voltage spike to occur after the turn off of MOSFET (Q1) in Figure 8. This is increasingly where R1(5µA) is the additional hysteresis introduced prominent at higher load currents, where more stored by the 5µA current sourced by the RUN pin. When in energy must be dissipated. In some cases an RC “snubber” shutdown, the RUN pin does not source the 5µA current circuit will be required to avoid overvoltage breakdown at and the rising threshold for V is simply IN the MOSFET’s drain node. Application Note 19 is a good R1+R2 reference on snubber design. A bifilar or similar winding V =V • IN(RUN,RISING) RUNON technique is a good way to minimize troublesome leak- R2 age inductances. However, remember that this will limit Note that for some applications the RUN pin can be con- the primary-to-secondary breakdown voltage, so bifilar nected to V in which case the V thresholds, V CC CC TURNON winding is not always practical. and V , control operation. TURNOFF Setting Undervoltage and Hysteresis on V IN External Run/Stop Control The RUN pin is connected to a resistive voltage divider To implement external run control, place a small N-channel connected to V as shown in Figure 3. The voltage thresh- IN MOSFET from the RUN pin to GND as shown in Figure 3. old for the RUN pin is V rising and V falling. RUNON RUNOFF Drive the gate of this MOSFET high to pull the RUN pin Note that V – V = 35mV of built-in voltage RUNON RUNOFF to ground and prevent converter operation. hysteresis that helps eliminate false trips. Selecting Feedback Resistor Divider Values The regulated output voltage is determined by the resistor VIN divider across VOUT (R3 and R4 in Figure 8). The ratio of R4 to R3 needed to produce a desired V can be R1 OUT calculated: RUN LTC3805-5 RUN/STOP R3= VOUT−0.8V R4 CONTROL 0.8V (OPTIONAL) R2 Choose resistance values for R3 and R4 to be as large as GND 38055 F03 possible in order to minimize any efficiency loss due to the static current drawn from V , but just small enough so OUT Figure 3. Setting RUN Pin Voltage and Run/Stop Control that when V is in regulation the input current to the V OUT FB pin is less than 1% of the current through R3 and R4. A good rule of thumb is to choose R4 to be less than 80k. 38055fe 12

LTC3805-5 APPLICATIONS INFORMATION Feedback in Isolated Applications For example, with the peak current sense voltage of 100mV on the I pin, a peak switch current of 5A requires Isolated applications do not use the FB pin and error ampli- SENSE a sense resistor of 0.020W. Note that the instantaneous fier but control the I pin directly using an opto-isolator TH peak power in the sense resistor is 0.5W and it must be driven on the other side of the isolation barrier as shown rated accordingly. The LTC3805-5 has only a single sense in Figure 4. For isolated converters, the FB pin is grounded line to this resistor. Therefore, any parasitic resistance which provides pull-up on the I pin. This pull-up is not TH in the ground side connection of the sense resistor will enough to properly bias the opto-isolator which is typically increase its apparent value. In the case of a 0.020W sense biased using a resistor to V . Since the I pin cannot CC TH resistor, one milliohm of parasitic resistance will cause a sink the opto-isolator bias current, a diode is required to 5% reduction in peak switch current. So the resistance of block it from the I pin. A low leakage Schottky diode, TH printed circuit copper traces and vias cannot necessarily or low forward voltage PN junction diode, should be used be ignored. to ensure that the opto-isolator is able to pull I down TH to its lower clamp. Programmable Slope Compensation Oscillator Synchronization The LTC3805-5 injects a ramping current through its I SENSE pin into an external slope compensation resistor R . The oscillator may be synchronized to an external clock SLOPE This current ramp starts at zero right after the GATE pin by connecting the synchronization signal to the SYNC pin. has been high for the LTC3805-5’s minimum duty cycle The LTC3805-5 oscillator and turn-on of the switch are of 6%. The current rises linearly towards a peak of 10µA synchronized to the rising edge of the external clock. The at the maximum duty cycle of 80%, shutting off once the frequency of the external sync signal must be ±33% with GATE pin goes low. A series resistor R connecting the respect to f (as programmed by R ). Additionally, the SLOPE OSC FS I pin to the current sense resistor R develops a value of f must be between 70kHz and 700kHz. SENSE SENSE SYNC ramping voltage drop. From the perspective of the I SENSE pin, this ramping voltage adds to the voltage across the Current Sense Resistor Considerations sense resistor, effectively reducing the current comparator The external current sense resistor (R in Figure 8) SENSE threshold in proportion to duty cycle. This stabilizes the allows the user to optimize the current limit behavior for control loop against subharmonic oscillation. The amount the particular application. As the current sense resistor of reduction in the current comparator threshold (DV ) SENSE is varied from several ohms down to tens of milliohms, can be calculated using the following equation: peak switch current goes from a fraction of an ampere to several amperes. Care must be taken to ensure proper DutyCycle−6% DV = 10µA•R SENSE SLOPE circuit operation, especially with small current sense 80% resistor values. Note: LTC3805-5 enforces 6% < Duty Cycle < 80%. A good ISOLATION starting value for RSLOPE is 3k, which gives a 30mV drop BARRIER in current comparator threshold at 80% duty cycle. VCC Designs that do not operate at greater than 50% duty cycle do not need slope compensation and may replace R LTC3805-5 SLOPE with a direct connection. ITH FB GND 38055 F04 Figure 4. Circuit for Isolated Feedback 38055fe 13

LTC3805-5 APPLICATIONS INFORMATION Overcurrent Threshold Adjustment use Duty Cycle V to calculate DV IN(MIN) SENSE(VIN(MIN)) using the formula in the prior section. For overcurrent Figure 5 shows the connection of the overcurrent pin, OC, protection to trip at exactly the point where current limit- along with the I pin and the current sense resistor SENSE ing would begin set: R located in the source circuit of the power NMOS SENSE which is driven by the GATE pin. The internal overcurrent DV SENSE(VIN(MIN)) threshold on the OC pin is set at V = 100 mV which is the R = OCT OC(CRIT) 10µA same as the peak current sense voltage V = 100 mV on I(MAX) the I pin. The role of the slope compensation adjust- SENSE To find the actual output current that trips overcurrent ment resistor R and the slope compensation current SLOPE protection, calculate the peak switch current I PK(VIN(MIN)) I is discussed in the prior section. In combination with SLOPE from: the overcurrent threshold adjust current I = 10µA, an OC 100mV−DV external resistor ROC can be used to lower the overcurrent I = SENSE(VIN(MIN)) trip threshold from 100mV. This section describes how PK(VIN(MIN)) R SENSE to pick R to achieve the desired performance. In the OC discussion that follows be careful to distinguish between Then calculate the converter output current that corre- “current limit” where the converter continues to run with sponds to I . Again, the calculation depends PK(VIN(MIN)) the I pin limiting current on a cycle-by-cycle basis both on converter type and the details of converter design SENSE while the output voltage falls below the regulation point including inductor current ripple. For minimum input volt- and “overcurrent protection” where the OC pin senses an age, R produces an overcurrent trip at an output OC(CRIT) overcurrent and shuts down the converter for a timeout current just before loss of output voltage regulation and period before attempting an automatic restart. the onset of current limiting. Note that the output current that causes an overcurrent trip is higher for higher input One overcurrent protection strategy is for the converter voltages but that an overcurrent trip will always occur to never enter current limit but to maintain output volt- before loss of output voltage regulation. If desired to age regulation up to the point of tripping the overcurrent meet a specific design target, an increase in R above protection. Operation at minimum input voltage V OC IN(MIN) R can be used to reduce the trip threshold and hits current limiting for the smallest output current and OC(CRIT) make the converter trip for a lower output current. is the design point for this strategy. This calculation is based on steady-state operation. De- First, for operation at V , calculate the duty cycle Duty IN(MIN) pending on design, overcurrent protection can also be Cycle V using the appropriate formula depending on IN(MIN) triggered during a start-up transient, particularly if large whether the converter is a boost, flyback or SEPIC. Then output filter capacitors are being charged as output voltage rises. If that is a problem, output capacitor charging can be slowed by using a larger value of SSFLT capacitor. It is GATE also possible to trip overcurrent protection during a load LTC3805-5 RSLOPE ISLOPE step especially if the trip threshold is lowered by making ISENSE R > R . OC OC(CRIT) ROC IOC = 10µA Another overcurrent protection strategy is keep the con- OC RSENSE verter running as current limiting reduces the duty cycle GND and the output voltage sags. In this case, the goal is often 38055 F05 keep the converter in normal operation over as wide a range Figure 5. Circuit to Decrease Overcurrent Threshold as possible, including current limiting, and to trigger the 38055fe 14

LTC3805-5 APPLICATIONS INFORMATION overcurrent trip only to prevent damage. To implement External Soft-Start Fault Timeout this strategy use a value of R smaller than R . OC OC(CRIT) The external soft-start is programmed by a capacitor C SS This also reduces sensitivity to overcurrent trips caused by from the SSFLT pin to GND. At the initiation of soft-start transient operation. In the limit, set R = 0 and connect OC the voltage on the SSFLT pin is quickly charged to 0.7V the OC pin directly to R . This causes an overcurrent SENSE at which point GATE begins switching. From that point, trip near minimum duty cycle or around 6%. a 6µA current charges the voltage on the SSFLT pin until In some cases it may be desirable to increase the trip the voltage reaches about 2.25V at which point soft-start threshold even further. In this strategy, the converter is is over and the converter enters closed-loop regulation. allowed to operate all the way down to minimum duty The soft-start time t as a function of the soft-start SS(EXT) cycle at which point the cycle-by-cycle current limit of capacitor C is therefore: SS the I pin is lost and switch current goes up propor- SENSE 2.25−0.7V tionally to the output current. Figures 6 and 7 show two t =C SS(EXT) SS 6µA ways to do this. Figure 6 is for relatively low currents with relatively large values of R . Using this circuit the SENSE After soft-start is complete, the voltage on the SSFLT pin overcurrent trip threshold is increased from 100mV to: continues to charge to about a final value of 4.75V. Note R +R that choosing a value of C less than 5.8nF has no effect V = SENSE1 SENSE2100mV SS OC R since it would attempt to program an external soft-start SENSE1 time t less than the mandatory minimum internal SS(EXT) where it is assumed that the values of RSENSE1 and soft-start time tSS(IN) = 1.8ms. R are so small that the I = 10µA threshold adjust- SENSE2 OC If there is an overcurrent fault detected on the OC pin, the ment current produces a negligible change in V . OC LTC3805-5 enters a shutdown mode while a 2µA current For larger currents, values of the current sense resistors discharges the voltage on the SSFLT pin from 4.75V to must be very small and the circuit of Figure 6 becomes about 0.7V. The fault timeout tFTO(EXT) is therefore: impractical. The circuit of Figure 7 can be substituted and the 4.75V−0.7V current sense threshold is increased from 100mV to: tFTO(EXT)=CSS 2µA R1+R2 V = 100mV At this point, the LTC3805-5 attempts a restart. OC R1 In the event of a persistent fault, such as a short-circuit where the values of R1 and R2 should be kept below 10W on the converter output, the converter enters a “hiccup” to prevent the I = 10µA threshold adjustment current mode where it continues to try and restart at repetition OC from producing a shift in VOC. rate determined by CSS. If the fault is eventually removed the converter successfully restarts. GATE GATE LTC3805-5 RSLOPE ISLOPE LTC3805-5 RSLOPE ISLOPE ISENSE ISENSE RSENSE2 R2 IOC = 10µA IOC = 10µA OC OC RSENSE1 R1 RSENSE GND GND 38055 F06 38055 F07 Figure 6. Circuit to Increase the Overcurrent Figure 7. Circuit to Increase the Overcurrent Threshold for Small Switch Currents Threshold for Large Switch Currents 38055fe 15

LTC3805-5 TYPICAL APPLICATIONS 4.56µH VIN BH510-1009 5.5V T0 40V C10INµF 57.6k BAS516 • T1 • 50V MMBT6428LT1 301W 1500µVF PDDS1760 VOUT PDZ6.8B 12V 0.1µF 4.7µF COUT 2A 47µF 16V 1 10 Q1 SSFLT GATE 6.8nF HAT2266 10k 2 LTC3805-5 9 ITH VCC 221k 3 8 FB OC R4 7.15k 45 RUN ISENSE 76 3.01k 0R.S0E0N5SΩE 69.8k FS SYNC 80.6k GND 11 R3 100k 38055 F08 Figure 8. 5.5V to 40V to 12V/2A SEPIC Converter Efficiency and Power Loss vs Load Current 100 3.5 90 EFFICIENCY 3.0 80 70 2.5 P NCY (%) 6500 2.0 OWER L EFFICIE 40 POWER LOSS 1.5 OSS (W 30 5.5V 1.0 ) 10V 20 20V 0.5 10 30V 40V 0 0 0.01 0.1 1 10 LOAD CURRENT (A) 38055 TA04b 38055fe 16

LTC3805-5 TYPICAL APPLICATIONS VIN+ 4PA1277NL5 VOUT+ 18V TO 6 3.3V 72V 2.2µF 2.2µF 3A 100V 100V 221k 221k 7 3 8 100µF 100µF 100µF MMBTA42 D2 2 D1 6.3V 6.3V 6.3V BAS516 150pF RBIAS PDS1040 P6.D8ZV6.8B 200V 68Ω 402Ω 1 VOUT– VIN– BAS516 BA760 FDC2512 10W 0.04Ω VCC BAS516 274Ω 100k BAS516 6.8k 47pF 0.022µF 22.1k VCC PS2801-1-K U2 LT4430 U1 1µF 1µF 1 VIN OPTO 6 2.2nF 56k VIN 1 LTC3805-5 10 2 GND COMP 5 221k 32 ISTSHFLT GAVTCEC 89 0.47µF 3 OC FB 4 38055 F09 FB OC 2200pF 4 7 5 RUN ISENSE 6 250VAC FS GND SYNC 3.01k 15.8k 75k 11 Figure 9. Isolated Telecom Supply: 18V to 72V Input to 3.3V/3A Output Efficiency and Power Loss vs Load Current and V IN 100 4.0 18V 90 36V 3.5 48V 60V 80 3.0 72V NCY (%) 7600 EFFICIENCY 22..50 POWER L E O EFFICI 50 1.5 SS (W ) 40 1.0 30 0.5 POWER LOSS 20 0 0.01 0.1 1 10 LOAD CURRENT (A) 38055 TA03b 38055fe 17

LTC3805-5 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev B) R = 0.125 0.40 ± 0.10 TYP 6 10 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10 2.15 ±0.05 (2 SIDES) (4 SIDES) (2 SIDES) PIN 1 PACKAGE TOP MARK OUTLINE (SEE NOTE 6) (DD) DFN REV B 0309 5 1 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 0.50 BSC BSC 2.38 ±0.10 2.38 ±0.05 0.00 – 0.05 (2 SIDES) (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1664 Rev C) BOTTOM VIEW OF EXPOSED PAD OPTION 2.06 ± 0.102 2(..719140 ±± 0.0.10042) 0(..808395 ±± 0.0.10257) 1 (.081 ± .004) 0.29 1.83 ± 0.102 REF (.072 ± .004) 5.23 2.083 ± 0.102 3.20 – 3.45 0.05 REF (.206) (.082 ± .004) (.126 – .136) DETAIL “B” MIN CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. 10 FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.305 ± 0.038 0.50 3.00 ± 0.102 (.0120T Y±P .0015R)ECOMMENDED SOLDER PAD L(.A0BY1SO9CU7)T (.1(1N8O ±TE . 030)4) 109 8 76 (0..0419976 ± ± 0 ..000736) REF 4.90 ± 0.152 3.00 ± 0.102 (.193 ± .006) (.118 ± .004) (NOTE 4) DETAIL “A” 0.254 (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 1.10 0.86 (.021 ± .006) (.043) (.034) MAX REF DETAIL “A” 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) 0.50 (.004 ± .002) NOTE: TYP (.0197) MSOP (MSE) 0908 REV C 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 38055fe 18

LTC3805-5 REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER D 04/10 Updates to Absolute Maximum Ratings 2 Changes to Electrical Characteristics Table 3 Updates to Note 2 4 Update to Pin 11 in Pin Functions 7 Edits to Start-Up Shutdown in Operation Section 9 Change to Typical Application 17, 20 Updated Related Parts Table 20 E 05/11 Added MP-grade part. Reflected throughout the data sheet 1-20 38055fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3805-5 TYPICAL APPLICATION 5V to 40V to 12V/1A Nonisolated Flyback Converter D1 UPS840 VIN 4T3772 7 V12OVUT 5V TO 40V 8 1A 2.2µF 2.2µF 10k D2 10 100V 100V BAS516 1 9 100µF 100µF MMBTA42 16V 16V 6.8V PDZ6.8B 680Ω 150pF 200V 220Ω CSS 47pF 100pF 0.1µF 51.1k VCC FDC2512 470pF RSENSE 20k U1 4.7µF 0.005Ω 3.65k LTC3805-5 1 10 SSFLT GATE 2 9 3 ITH VCC 8 FB OC VCC 54 RUN ISENSE 67 FS GND SYNC 3.01k 75k 11 38055 TA02 Efficiency and Power Loss vs Load Current 90 8 80 7 70 6 P %) 60 5 OW NCY ( 50 4 ER L E O EFFICI 40 3 SS (W 5.5V ) 30 10V 2 20V 20 30V 1 40V 10 0 0.01 0.1 1 10 LOAD CURRENT (A) 38055 TA02b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3748 100V No Opto Flyback Controller 5V ≤ V ≤ 100V, Boundary Mode Operation, MSOP-16 with Extra High IN Voltage Pin Spacing LT3758 Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency, IN 3mm × 3mm DFN-10 and MSOP-10E LT3575 No Opto-Isolated Flyback with 60V Integrated Switch 3V ≤ V ≤ 40V, Up to 14W, Boundary Mode Operation, TSSOP-16E IN LTC3803/LTC3803-3/ Flyback DC/DC Controller with Fixed 200kHz or V and V Limited Only by External Components, 6-Pin ThinSOT™ IN OUT LTC3803-5 300kHz Operating Frequency Package LTC3873/LTC3873-5 No R ™ Constant Frequency Flyback, Boost, V and V Limited Only by External Components, 8-Pin ThinSOT SENSE IN OUT SEPIC Controller or 2mm × 3mm DFN-8 Packages LT3825 No Opto-Isolated Synchronous Flyback Controller V 16V to 75V Limited by External Components, Up to 60W, TSSOP-16E IN 38055fe 20 Linear Technology Corporation LT 0511 REV E • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2008