LTC2859/LTC2861 20Mbps RS485 Transceivers with Integrated Switchable Termination FeaTures DescripTion n Integrated, Logic-Selectable 120Ω Termination The LTC®2859 and LTC2861 are low power, 20Mbps Resistor RS485/422 transceivers operating on 5V supplies. The n 20Mbps Max Data Rate receiver includes a logic-selectable 120Ω termination, n No Damage or Latchup to ESD: ±15kV HBM one-eighth unit load supporting up to 256 nodes per bus n High Input Impedance Supports 256 Nodes (C-, I-grades), and a failsafe feature that guarantees a high (C-, I-Grades) output state under conditions of floating or shorted inputs. n Operation Up to 105°C (LTC2859H) The driver features a logic-selectable low-EMI 250kbps n 250kbps Low-EMI Mode operating mode, and maintains a high output impedance n Guaranteed Failsafe Receiver Operation Over the over the entire common mode range when disabled or Entire Common Mode Range when the supply is removed. Excessive power dissipation n Current Limited Drivers and Thermal Shutdown caused by bus contention or a fault is prevented by current n Delayed Micropower Shutdown (5µA Max) limiting all outputs and by a thermal shutdown. n Power Up/Down Glitch-Free Driver Outputs n Low Operating Current (900µA Max in Receive Mode) Enhanced ESD protection allows the LTC2859 and LTC2861 n Meets All TIA/EIA-485-A Specifications to withstand ±15kV (human body model) on the transceiver n Available in 10-Pin 3mm × 3mm DFN, 12-Pin interface pins without latchup or damage. 4mm × 3mm DFN and 16-Pin SSOP Packages proDucT selecTion GuiDe applicaTions PART NUMBER DUPLEX PACKAGE n Low Power RS485/RS422 Transceiver LTC2859 Half DFN-10 n Level Translator n Backplane Transceiver LTC2861 Full SSOP-16, DFN-12 L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion LTC2859 LTC2859 LTC2859 at 20Mbps RO R R RO RE RE DI TE TE DE 120Ω 120Ω DE Y DI D D DI Z SLO SLO LTC2859 Y–Z 2859/61 TA01 120Ω 2V/DIV 20ns/DIV 285961 TA02 R D RORETE DE DI SLO 285961fc 1

LTC2859/LTC2861 absoluTe maximum raTinGs (Note 1) Supply Voltage (V ) ...................................–0.3V to 7V Operating Temperature (Note 4) CC Logic Input Voltages (RE, DE, DI, TE, SLO) ....–0.3V to 7V LTC2859C, LTC2861C ..............................0°C to 70°C Interface I/O: LTC2859I, LTC2861I ............................–40°C to 85°C A, B, Y, Z .......................................(V –15V) to +15V LTC2859H ..........................................–40°C to 105°C CC (A-B) or (B-A) with Terminator Enabled ..................6V Storage Temperature Range ..................–65°C to 125°C Receiver Output Voltage (RO) ........–0.3V to (V +0.3V) Lead Temperature (Soldering, 10 sec) CC GN Package ......................................................300°C pin conFiGuraTion TOP VIEW TOP VIEW TOP VIEW RO 1 16 VCC RO 1 12 VCC RE 2 15 A RO 1 10 VCC RE 2 11 A DE 3 14 B RE 2 11 9 B DE 3 13 10 B DE 3 8 A DI 4 13 Z DI 4 9 Z DI 4 7 SLO TE 5 12 Y TE 5 6 GND TE 5 8 Y GND 6 11 SLO GND 6 7 SLO NC 7 10 NC DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN DE PACKAGE NC 8 9 NC EXPOSED PAD (PIN 11) PCB GND CONNECTION 12-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GND CONNECTION GN PACKAGE θJC = 3°C/W TJMAX =θ 1J2C 5=° C4,. 3θ°JCA/ W= 43°C/W 16-LETAJDM A(XN =A R1θ2RJC5O °=WC 4, 0θ0°J.1CA 5/=W0 1) 1P0L°ACS/WTI C SSOP orDer inFormaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2861CDE#PBF LTC2861CDE#TRPBF 2861 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C LTC2861IDE#PBF LTC2861IDE#TRPBF 2861 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C LTC2861CGN#PBF LTC2861CGN#TRPBF 2861 16-Lead Plastic SSOP 0°C to 70°C LTC2861IGN#PBF LTC2861IGN#TRPBF 2861I 16-Lead Plastic SSOP –40°C to 85°C LTC2859CDD#PBF LTC2859CDD#TRPBF LBNX 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2859IDD#PBF LTC2859IDD#TRPBF LBNX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC2859HDD#PBF LTC2859HDD#TRPBF LBNX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 105°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 285961fc 2

LTC2859/LTC2861 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C, V = 5V unless otherwise noted (Note 2). A CC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Driver |V | Differential Driver Output Voltage R = ∞, I = 0mA, V = 4.5V (Figure 1) l V V OD O CC CC R = 27Ω (RS485), V = 4.5V (Figure 1) l 1.5 V V CC CC R = 50Ω (RS422), V = 4.5V (Figure 1) l 2.0 V V CC CC D|VOD| Change in Magnitude of Driver R = 27Ω or R = 50Ω (Figure 1) l 0.2 V Differential Output Voltage for Complementary Output States V Driver Common Mode Output Voltage R = 27Ω or R = 50Ω (Figure 1) l 3.0 V OC D|VOC| Change in Magnitude of Driver R = 27Ω or R = 50Ω (Figure 1) l 0.2 V Common Mode Output Voltage for Complementary Output States I Driver Three-State (High Impedance) DE = OV, V = –7V, +12V l ±10 µA OZD O Output Current on Y and Z (LTC2861 Only) I Maximum Driver Short-Circuit Current –7V ≤ (Y or Z) ≤ 12 (Figure 2) l ±120 ±250 mA OSD Receiver I Receiver Input Current (A, B) DE = TE = 0V, V = 0V or 5V, V or V = 12V, l 125 µA IN2 CC A B Other at 0V (H-Grade) l 250 µA DE = TE = 0V, V = 0V or 5V, V or V = –7V, l –100 µA CC A B Other at 0V (H-Grade) l –145 µA V Receiver Differential Input Threshold –7V ≤ V ≤ 12 l ±0.2 V TH CM Voltage DVTH Receiver Input Hysteresis VCM = 0V 25 mV V Receiver Output HIGH Voltage I = –4mA, V = 200mV, V = 4.5V l 2.4 V OH 0 ID CC V Receiver Output LOW Voltage I = 4mA, V = –200mV, V = 4.5V l 0.4 V OL 0 ID CC I Receiver Three-State (High RE = 5V, 0V ≤ V ≤ V l ±1 µA OZR O CC Impedance) Output Current on RO R Receiver Input Resistance RE = 5V or 0V, DE = TE = 0V l 96 125 kΩ IN –7V ≤ V = V ≤ 12V A B (H-Grade) l 48 125 kΩ R Receiver Input Terminating Resistor TE = 5V, V = 2V, V = –7, 0, 10V l 108 120 156 Ω TERM AB B (Figure 7) Logic V Logic Input High Voltage DE, DI, RE, TE, SLO, V = 4.5V l 2 V IH CC V Logic Input Low Voltage DE, DI, RE, TE, SLO, V = 4.5V l 0.8 V IL CC I Logic Input Current DE, DI, RE, TE, SLO l 0 ±10 µA IN1 Supplies I Supply Current in Shutdown Mode DE = 0V, RE = V , TE = 0V l 0 5 µA SHDN CC I Supply Current in Receive Mode No Load, DE = 0V, RE = 0V, TE = 0V l 540 900 µA CCR I Supply Current in Transmit Mode No Load, DE = V , RE = V , SLO = V , TE = 0V l 630 1000 µA CCT CC CC CC I Supply Current in Transmit SLO Mode No Load, DE = V , RE = V , SLO = 0V, TE = 0V l 670 1100 µA CCTS CC CC I Supply Current in Loopback Mode No Load, DE = V , RE= 0V, SLO = V , TE = 0V l 660 1100 µA CCL CC CC (Both Driver and Receiver Enabled) I Supply Current in Termination Mode DE = 0V, RE = V , TE = V , SLO = V l 640 1180 µA CCRT CC CC CC 285961fc 3

LTC2859/LTC2861 swiTchinG characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C, V = 5V, T = 0 unless otherwise noted (Note 2). A CC E SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Driver in Normal Mode (SLO HIGH) f Maximum Data Rate Note 3 l 20 Mbps MAX t , t Driver Input to Output R = 54Ω, C = 100pF (Figure 3) l 10 50 ns PLHD PHLD DIFF L DtPD Driver Input to Output Difference RDIFF = 54Ω, CL = 100pF (Figure 3) l 1 6 ns |t -t | PLHD PHLD t Driver Output Y to Output Z R = 54Ω, C = 100pF (Figure 3) l 1 ±6 ns SKEWD DIFF L t , t Driver Rise or Fall Time R = 54Ω, C = 100pF (Figure 3) l 4 12.5 ns RD FD DIFF L t , t , t , Driver Enable or Disable Time R = 500Ω, C = 50pF, RE = 0 (Figure 4) l 70 ns ZLD ZHD LZD L L t HZD t , t Driver Enable from Shutdown R = 500Ω, C = 50pF, RE = V (Figure 4) l 8 µs ZHSD ZLSD L L CC tSHDN Time to Shutdown (DE = ↓, RE = VCC) or (DE = 0, RE ↑) l 100 ns (Figure 4) Driver in SLO Mode (SLO LOW) f Maximum Data Rate Note 3 l 250 kbps MAXS t t Driver Input to Output R = 54Ω, C = 100pF (Figure 3) l 0.95 1.5 µs PLHDS, PHLDS DIFF L DtPDS Driver Input to Output Difference RDIFF = 54Ω, CL = 100pF (Figure 3) l 50 500 ns |t -t | PLHR PHLR t Driver Output A to Output B R = 54Ω, C = 100pF (Figure 3) l 200 ±500 ns SKEWDS DIFF L (H-Grade) l 200 ±750 ns t t Driver Rise or Fall Time R = 54Ω, C = 100pF (Figure 3) l 0.9 1.5 µs RDS, FDS DIFF L t t Driver Enable Time R = 500Ω, C = 50pF, RE = 0 (Figure 4) l 300 ns ZHDS, ZLDS L L t t Driver Disable Time R = 500Ω, C = 50pF, RE = 0 (Figure 4) l 70 ns LZDS, HZDS L L t t Driver Enable from Shutdown R = 500Ω, C = 50pF, RE = V (Figure 4) l 8 µs ZHSDS, ZLSDS L L CC tSHDNS Time to Shutdown (DE = 0, RE = ↑) or (DE = ↓, RE = VCC) (Figure 4) l 500 ns Receiver t , t Receiver Input to Output C = 15pF, V = 1.5V, |V | = 1.5V, t and t < l 50 70 ns PLHR PHLR L CM AB R F 4ns (Figure 5) t Differential Receiver Skew C = 15pF (Figure 5) l 1 6 ns SKEWR L |t -t | PLHR PHLR t , t Receiver Output Rise or Fall Time C = 15pF (Figure 5) l 3 12.5 ns RR FR L t , t , t , Receiver Enable/Disable R = 1kΩ, C =15pF, DE = V (Figure 6) l 50 ns ZLR ZHR LZR L L CC t DI = 0 or V HZR CC t , t Receiver Enable from Shutdown R = 1kΩ, C = 15pF, DE = 0V (Figure 6) l 8 µs ZHSR ZLSR L L DI = 0 or V CC t , t Termination Enable or Disable Time V = 0V, V = 2V, RE = V , DE = 0V (Figure 7) l 100 µs RTEN RTZ B AB CC Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Maximum data rate is guaranteed by other measured parameters may cause permanent damage to the device. Exposure to any Absolute and is not tested directly. Maximum Rating condition for extended periods may affect device Note 4: This IC includes overtemperature protection that is intended reliability and lifetime.. to protect the device during momentary overload conditions. Junction Note 2: All currents into device pins are positive; all currents out of device temperature will exceed 125°C when overtemperature protection is active. pins are negative. All voltages are referenced to device ground unless Continuous operation above the specified maximum operating junction otherwise specified. temperature may result in device degradation or failure. 285961fc 4

LTC2859/LTC2861 TesT circuiTs Y Y R GND + GND IOSD OR DI DRIVER VOD OR DI DRIVER VCC Z – R + VCC Z + VOC – –7V to +12V – 2859/61 F01-2 Figure 1. Driver DC Characteristics Figure 2. Driver Output Short-Circuit Current Y DI VCC tPLHD, tPHLD, DI CL OV tPLHDS tSKEWD, tSKEWDStPHLDS DRIVER RDIFF CL Y, Z VO 1/2 VO Z 90% 90% (Y-Z) 0 0 10% 10% tRD, tFD, tRDS tFDS 2859/61 F03 Figure 3. Driver Timing Measurement Y CL RL GOVCNRCD DE OVCVC 1/2 VCC tttZZZLLLDDSD,S,, OVCRC DI DRIVER VCC tZLSDS ttLLZZDD,S GND Z Y or Z VO 1/2 VCC 0.5V RL VCC VOL DE OR VOH 0.5V CL GND Z or Y OV tttZZZHHHDDSD,S,, 1/2 VCC ttttHHSSHHZZDDDD,SNN,,S tZHSDS 2859/61 F04 Figure 4. Driver Enable and Disable Timing Measurement 285961fc 5

LTC2859/LTC2861 TesT circuiTs VAB ±VAB/2 A A-B 0V VCM B RECEIVER RO –VVACBC 90% tPLHR 90%tPHLR ±VAB/2 CL RO 0V VO 10% 1/2 VCC 1/2 VCC 10% tRR tFR tSKEWR = tPLHR – tPHLR 2859/61 F05 Figure 5. Receiver Propagation Delay Measurements 0V OR VCC A RO RL VCC RE V0CVC ttZZLLRSR, 1/2 VCC RECEIVER OR VCC tLZR VCC OR 0V B CL GND RO VOL VO 1/2 VCC 0.5V RE VOH 0.5V RO 1/2 VCC DI = 0V OR VCC 0V tZHR, tHZR tZHSR 2859/61 F06 Figure 6. Receiver Enable/Disable Time Measurements RTERM =VAB IA VCC RO A + TE 1/2 VCC RECEIVER – VAB 0V tRTEN tRTZ 90% B IA 10% + TE – VB 2859/61 F07 Figure 7. Termination Resistance and Timing Measurements 285961fc 6

LTC2859/LTC2861 Typical perFormance characTerisTics T = 25°C, V = 5V, unless otherwise noted. A CC Receiver Skew Driver Propagation Delay vs Temperature Driver Skew vs Temperature vs Temperature 3 18 VAB = 1.5V RDIFF = 54Ω RDIFF = 54Ω CL = 15pF CL = 100pF 16 CL = 100pF 2 SLO = VCC SLO = VCC VER SKEW (ns) 1 ER SKEW (ns) 21 PROP DELAY (ns) 111204 CEI RIV ER RE D 0 DRIV 8 0 6 –1 4 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 285961 G01 285961 G02 285961 G03 Driver Output Low/High Voltage Driver Differential Output Voltage R vs Temperature vs Output Current vs Temperature TERM 135 5 5 130 VOH R = ∞ 4 4 125 V) V) Ω) E ( E ( CE ( 120 TAG 3 TAG 3 R = 100Ω ESISTAN 111150 PUT VOL 2 PUT VOL 2 R = 54Ω R T T U U O O 105 1 VOL 1 100 95 0 0 –40 –20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) OUTPUT CURRENT (mA) TEMPERATURE (°C) 285961 G04 285961 G05 285961 G06 Receiver Output Voltage vs Receiver Propagation Delay Output Current (Source and Sink) vs Temperature Supply Current vs Data Rate 5 70 60 SOURCE VAB = 1.5V 65 CL = 15pF 50 R = 54Ω 4 OLTAGE (V) 3 ELAY (ns) 565005 RRENT (mA) 4300 R = 100Ω V D U PUT 2 ROP 45 LY C UT P PP 20 O U 40 S 1 10 35 SINK R = ∞ 0 30 0 0 1 2 3 4 5 –40 –20 0 20 40 60 80 100 120 0.1 1 10 100 OUTPUT CURRENT (mA) TEMPERATURE (°C) DATA RATE (Mbps) 285961 G07 285961 G08 285961 G09 285961fc 7

LTC2859/LTC2861 pin FuncTions (DD/DE/GN) RO (Pin 1): Receiver Output. If the receiver output is enabled TE (Pin 5): Internal Termination Resistance Enable. A high (RE low) and A > B by 200mV, then RO will be high. If A input will connect a termination resistor (120Ω typical) < B by 200mV, then RO will be low. If the receiver inputs between pins A and B. are open, shorted, or terminated without a valid signal, RO GND (Pins 6,11/6,13/6): Ground. Pins 11 and 13 are will be high. backside thermal pad, connected to Ground. RE (Pin 2): Receiver Enable. A low enables the receiver. SLO (Pins 7/7/11): Driver Slew Rate Control. A low input A high input forces the receiver output into a high imped- will force the driver into a reduced slew rate mode. ance state. Y (Pins -/8/12): Positive Driver Output for LTC2861. DE (Pin 3): Driver Enable. A high on DE enables the driver. A low input will force the driver outputs into a high imped- Z (Pins -/9/13): Negative Driver Output for LTC2861. ance. If RE is high with DE and TE LOW, the part will enter B (Pins 9/10/14): Negative Receiver Input (and Negative a low power shutdown state. Driver Output for LTC2859). DI (Pin 4): Driver Input. If the driver outputs are enabled A (Pins 8/11/15): Positive Receiver Input (and Positive (DE HIGH), then a low on DI forces the driver positive Driver Output for LTC2859). output LOW and negative output HIGH. A high on DI, with the driver outputs enabled, forces the driver positive V (Pins 10/12/16): Positive Supply. 4.5V < V < 5.5V. CC CC output HIGH and negative output LOW. Bypass with 0.1µF ceramic capacitor. 285961fc 8

LTC2859/LTC2861 FuncTion Tables LTC2859 LOGIC INPUTS DE RE TE MODE A, B RO TERMINATOR 0 0 0 Receive R Enabled Off IN 0 0 1 Receive with Term R Enabled On IN 0 1 0 Shutdown R Hi-Z Off IN 0 1 1 Term Only R Hi-Z On IN 1 0 0 Transmit with Receive Driven Enabled Off 1 0 1 Transmit with Receive Driven Enabled On and Term 1 1 0 Transmit Driven Hi-Z Off 1 1 1 Transmit with Term Driven Hi-Z On LTC2861 LOGIC INPUTS DE RE TE MODE A, B Y, Z RO TERMINATOR 0 0 0 Receive R Hi-Z Enabled Off IN 0 0 1 Receive with Term R Hi-Z Enabled On IN 0 1 0 Shutdown R Hi-Z Hi-Z Off IN 0 1 1 Term Only R Hi-Z Hi-Z On IN 1 0 0 Transmit with Receive R Driven Enabled Off IN 1 0 1 Transmit with Receive R Driven Enabled On IN and Term 1 1 0 Transmit R Driven Hi-Z Off IN 1 1 1 Transmit with Term R Driven Hi-Z On IN block DiaGrams LTC2859 LTC2861 A A RE SLEEP/SHUTDOWN (15kV) RE SLEEP/SHUTDOWN (15kV) DE LOGIC AND DELAY 120Ω DE LOGIC AND DELAY 120Ω TE TE RO RECEIVER RO RECEIVER B B (15kV) (15kV) SLO SLO Z (15kV) DI DRIVER DI DRIVER Y (15kV) 2859/61 BD 285961fc 9

LTC2859/LTC2861 applicaTions inFormaTion Driver The LTC2859/LTC2861 also feature thermal shutdown protection that disables the driver, terminator, and receiver The driver provides full RS485 and RS422 compatibility. in case of excessive power dissipation. When enabled, if DI is high, Y-Z is positive for the full duplex device (LTC2861) and A-B is positive for the half- SLO Mode: Slew Limiting for EMI Emissions Control duplex device (LTC2859). The LTC2859/LTC2861 feature a logic-selectable reduced- When the driver is disabled, both outputs are high- slew mode (SLO mode) that softens the driver output impedance. For the full duplex LTC2861, the leakage on edges to control the high frequency EMI emissions from the driver output pins is guaranteed to be less than 10µA equipment and data cables. The reduced slew rate mode over the entire common mode range of –7V to +12V. On is entered by taking the SLO pin low, where the data rate is the half-duplex LTC2859, the impedance is dominated by limited to about 250kbps. Slew limiting also mitigates the the receiver input resistance, R . IN adverse effects of imperfect transmission line termination caused by stubs or mismatched cables. Driver Overvoltage and Overcurrent Protection Figures 8a and 8b show the LTC2861 driver outputs in The driver outputs are protected from short circuits to normal and SLO mode with their corresponding frequency any voltage within the Absolute Maximum range of (V CC spectrums operating at 250kbps. SLO mode significantly –15V) to +15V. The maximum current in this condition reduces the high frequency harmonics. is 250mA. If the pin voltage exceeds about ±10V, current limit folds back to about half of the peak value to reduce overall power dissipation and avoid damaging the part. Y, Z Y–Z Y–Z 1V/DIV 2µs/DIV 10dB/DIV 1.25MHz/DIV 285961 F08a Driver Output at 125kHz into 100Ω Resistor Frequency Spectrum of the Same Signal Figure 8a. Driver Output in Normal Mode Y, Z Y–Z Y–Z 1V/DIV 2µs/DIV 10dB/DIV 1.25MHz/DIV 285961 F08b Driver Output at 125kHz into 100Ω Resistor Frequency Spectrum of the Same Signal Figure 8b. Driver Output in SLO Mode 285961fc 10

LTC2859/LTC2861 applicaTions inFormaTion Receiver and Failsafe ing specification. High temperature H-Grade operation reduces the minimum input resistance to 48k permitting With the receiver enabled, when the absolute value of the 128 receivers on the bus. The input resistance of the differential voltage between the A and B pins is greater than receiver is unaffected by enabling/disabling the receiver 200mV, the state of RO will reflect the polarity of (A-B). or by powering/unpowering the part. The equivalent input The LTC2859/LTC2861 have a failsafe feature that guaran- resistance looking into A and B is shown in Figure 9. tees the receiver output to be in a logic HIGH state when the inputs are either shorted, left open, or terminated Switchable Termination (externally or internally), but not driven for more than Proper cable termination is very important for good signal about 3µs. The delay prevents signal zero crossings from fidelity. If the cable is not terminated with its characteristic being interpreted as shorted inputs and causing RO to go impedance, reflections will result in distorted waveforms. high inadvertently. This failsafe feature is guaranteed to The LTC2859/LTC2861 are the first RS485 transceivers work for inputs spanning the entire common mode range to offer integrated switchable termination resistors on the of –7V to +12V. receiver input pins. This provides the tremendous advan- The receiver output is internally driven high (to VCC) or tage of being able to easily change, through logic control, low (to ground) with no external pull-up needed. When the the proper line termination for optimal performance when receiver is disabled the RO pin becomes Hi-Z with leakage configuring transceiver networks. of less than ±1µA for voltages within the supply range. When the TE pin is high, the termination resistor is en- abled and the differential resistance from A to B is 120Ω. Receiver Input Resistance Figure 10 shows the I/V characteristics between pins A The receiver input resistance from A or B to ground is and B with the termination resistor enabled and disabled. greater than 96k permitting up to a total of 256 receivers The resistance is maintained over the entire RS485 com- per system without exceeding the RS485 receiver load- mon mode range of –7V to +12V as shown in Figure 11. A >96k 60Ω TE 60Ω B 2859/61 F09 >96k Figure 9. Equivalent Input Resistance into A and B Figure 10. Curve Trace Between A and B (on the LTC2859, Valid if Driver is Disabled) with Termination Enabled and Disabled 285961fc 11

LTC2859/LTC2861 applicaTions inFormaTion The integrated termination resistor has a high frequency 150 response which does not limit performance at the maxi- mum specified data rate. Figure 12 shows the magnitude 140 and phase of the termination impedance vs frequency. The Ω) termination resistor cannot be enabled by TE if the device CE ( AN 130 is unpowered or in thermal shutdown mode. ST SI E R Supply Current 120 The unloaded static supply currents in the LTC2859/ LTC2861 are very low —typically under 700µA for all modes 110 –10 –5 0 5 10 15 of operation without the internal terminator enabled. In COMMON MODE VOLTAGE (V) 285961 F11 applications with resistively terminated cables, the supply Figure 11. Termination Resistance current is dominated by the driver load. For example, when vs Common Mode Voltage using two 120Ω terminators with a differential driver output voltage of 2V, the DC current is 33mA, which is sourced by the positive voltage supply. This is true whether the 185 30 terminators are external or internal such as in the LTC2859/ 170 15 LTC2861. Power supply current increases with toggling PHASE Ω) 155 0 dcsuiagtrnare ifdnicut aevn stto ldy ca aatapt arhacigtitehi vf eod ral ottawa doria ndtgeifs fa.en rFdeign tuth crisea pt1ea3rcm ist ihcvoaewn lo sina sdcursep (apfsolyer AGNITUDE ( 112450 MAGNITUDE ––3105 PHASE (°) M 110 –45 the circuit configuration of Figure 3). 95 –60 80 –75 High Speed Considerations 10–1 100 101 A ground plane layout is recommended for the LTC2859/ FREQUENCY (MHz) 285455 F12 LTC2861. A 0.1µF bypass capacitor less than one quarter Figure 12. Termination Magnitude and Phase vs Frequency inch away from the V pin is also recommended. The PC CC board traces connected to signals A/B and Z/Y (LTC2861) should be symmetrical and as short as possible to maintain good differential signal integrity. To minimize capacitive 75 effects, the differential signals should be separated by RDIFF = 54Ω more than the width of a trace and should not be routed 70 on top of each other if they are on different signal planes. A) 65 m Care should be taken to route outputs away from any sen- NT ( 60 CL = 1000pF sitive inputs to reduce feedback effects that might cause RE R U noise, jitter, or even oscillations. For example, in the full C 55 duplex LTC2861, DI and A/B should not be routed near CL = 100pF 50 the driver or receiver outputs. The logic inputs of the LTC2859/LTC2861 have 50mV of 45 102 103 104 105 hysteresis to provide noise immunity. Fast edges on the DATA RATE (kbps) 285961 F13 outputs can cause glitches in the ground and power supplies Figure 13. Supply Current vs Data Rate which are exacerbated by capacitive loading. If a logic input is held near its threshold (typically 1.5V), a noise glitch 285961fc 12

LTC2859/LTC2861 applicaTions inFormaTion from a driver transition may exceed the hysteresis levels represents the specified maximum data rate in the RS485 on the logic and data inputs pins causing an unintended standard. The dashed lines at 250kbps and 20Mbps show state change. This can be avoided by maintaining normal the maximum data rates of the LTC2859/LTC2861 in Low- logic levels on the pins and by slewing inputs through EMI and normal modes, respectively. their thresholds by faster than 1V/µs when transitioning. 10k Good supply decoupling and proper line termination also reduces glitches caused by driver transitions. LOW-EMI MODE Cable Length vs Data Rate FT) 1k MAX DATA RATE H ( T G For a given data rate, the maximum transmission distance N LE NORMAL is bounded by the cable properties. A typical curve of cable LE MODE MAX AB100 DATA RATE length vs data rate compliant with the RS485 standard is C shown in Figure 14. Three regions of this curve reflect RS485 MAX different performance limiting factors in data transmis- DATA RATE 10 sion. In the flat region of the curve, maximum distance is 10k 100k 1M 10M 100M determined by resistive losses in the cable. The downward DATA RATE (bps) 285961 F14 sloping region represents limits in distance and data Figure 14. Cable Length vs Data Rate rate due to AC losses in the cable. The solid vertical line (RS485 Standard Shown in Solid Lines) Typical applicaTions Multi-Node Network with End Termination Using LTC2859 TE = 0V TE = 0V D D R R LTC2859 LTC2859 LTC2859 LTC2859 R R TE = 5V TE = 5V D D 2859/61 TA04 285961fc 13

LTC2859/LTC2861 packaGe DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.125 0.40 ±0.10 TYP 6 10 3.00 ±0.10 1.65 ±0.10 (4 SIDES) (2 SIDES) PIN 1 NOTCH PIN 1 R = 0.20 OR TOP MARK 0.35 × 45° (SEE NOTE 6) CHAMFER (DD) DFN REV C 0310 5 1 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 285961fc 14

LTC2859/LTC2861 packaGe DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695 Rev D) 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 1.70 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 R = 0.115 0.40 ±0.10 (2 SIDES) TYP 7 12 R = 0.05 TYP 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ±0.10 PIN 1 PIN 1 NOTCH TOP MARK R = 0.20 OR (NOTE 6) 0.35 × 45° CHAMFER 6 1 (UE12/DE12) DFN 0806 REV D 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 2.50 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 285961fc 15

LTC2859/LTC2861 packaGe DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* .045 ±.005 (4.801 – 4.978) .009 (0.229) 16 15 14 13 12 11 109 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .015 ±.004 × 45° .0532 – .0688 .004 – .0098 (0.38 ±0.10) (1.35 – 1.75) (0.102 – 0.249) .007 – .0098 0° – 8° TYP (0.178 – 0.249) .016 – .050 .008 – .012 .0250 GN16 (SSOP) 0204 (0.406 – 1.270) (0.203 – 0.305) (0.635) NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 285961fc 16

LTC2859/LTC2861 revision hisTory (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 3/12 Added H-grade Order Information and Electrical Characteristics parameters 2, 3, 4 Revised Receiver Input Resistance section 11 Replaced Figure 12 12 Added Termination Resistor restriction information 12 285961fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 17 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2859/LTC2861 Typical applicaTion Failsafe “0” Application (Idle State = Logic “0”) VCC 100kΩ LTC2859 RO I1 R B "A" 120Ω A "B" DI I2 D 2859/61 TA03 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC2854/LTC2855 3.3V 20Mbps RS485/RS422 Transceivers with Integrated Up to ±25kV HBM ESD, 125°C Operation Switchable Termination LTC2856/LTC2857/ 5V 20Mbps and Slew Rate Limited 15kV RS485/RS422 ±15kV ESD, 125°C Operation LTC2858 Transceivers LTC2850/LTC2851/ 3.3V 20Mbps RS485/RS422 Transceivers ±15kV ESD, 125°C Operation LTC2852 LTC2862/LTC2863/ ±60V Fault Protected 3V to 5.5V RS485/RS422 Transceivers 20Mbps or 250kbps, ±15kV HBM ESD, ±25V Common Mode LTC2864/LTC2865 Range LTM2881 Complete 3.3V Isolated RS485/RS422 µModule® Transceiver 2500V Isolation with Integrated Isolated DC/DC Converter and RMS + Power Switchable Termination LTC485 Low Power RS485 Interface Transceiver I = 300µA (Typ) CC LTC491 Differential Driver and Receiver Pair I = 300µA CC LTC1480 3.3V Ultralow Power RS485 Transceiver 3.3V Operation LTC1483 Ultralow Power RS485 Low EMI Transceiver Controlled Driver Slew Rate LTC1485 Differential Bus Transceiver 10Mbaud Operation LTC1487 Ultralow Power RS485 with Low EMI, Shutdown and High Up to 256 Transceivers on the Bus Input Impedance LTC1520 50Mbps Precision Quad Line Receiver Channel-to-Channel Skew 400ps (Typ) LTC1535 Isolated RS485 Full-Duplex Transceiver 2500V Isolation in Surface Mount Package RMS LTC1685 52Mbps RS485 Transceiver with Precision Delay Propagation Delay Skew 500ps (Typ) LT1785 ±60V Fault Protected RS485 Transceiver 60V Tolerant, 15kV ESD 285961fc 18 Linear Technology Corporation LT 0312 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2006