LTC2400 m 24-Bit Power No Latency DS TM ADC in SO-8 FEATURES DESCRIPTIOU n 24-Bit ADC in SO-8 Package The LTC®2400 is a 2.7V to 5.5V micropower 24-bit n 4ppm INL, No Missing Codes converter with an integrated oscillator, 4ppm INL and n 4ppm Full-Scale Error 0.3ppm RMS noise. It uses delta-sigma technology and n Single Conversion Settling Time provides single cycle settling time for multiplexed appli- for Multiplexed Applications cations. Through a single pin the LTC2400 can be config- n 0.5ppm Offset ured for better than 110dB rejection at 50Hz or 60Hz – 2%, n 0.3ppm Noise or it can be driven by an external oscillator for a user n Internal Oscillator—No External Components defined rejection frequency in the range 1Hz to 120Hz. Required The internal oscillator requires no external frequency n 110dB Min, 50Hz/60Hz Notch Filter setting components. n Reference Input Voltage: 0.1V to V CC The converter accepts any external reference voltage from n Live Zero—Extended Input Range Accommodates 0.1V to V . With its extended input conversion range of CC 12.5% Overrange and Underrange –12.5% V to 112.5% V , the LTC2400 smoothly REF REF n Single Supply 2.7V to 5.5V Operation resolves the offset and overrange problems of preceding n Low Supply Current (200m A) and Auto Shutdown sensors or signal conditioning circuits. APPLICATIOU S The LTC2400 communicates through a flexible 3-wire digital interface which is compatible with SPI and n Weight Scales MICROWIRETM protocols. n Direct Temperature Measurement , LTC and LT are registered trademarks of Linear Technology Corporation. n Gas Analyzers No Latency ∆S is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. n Strain-Gage Transducers n Instrumentation n Data Acquisition n Industrial Process Control n 6-Digit DVMs TYPICAL APPLICATIOU Total Unadjusted Error vs Output Code 10 2.7V TO 5.5V VCC = 5V 1µF VCC= INTERNAL OSC/50Hz REJECTION 86 VTAR E=F 2=5 5°CV VCC FO == EINXTTEERRNNAALL OCSLCO/C6K0 HSzO RUERJCEECTION ppm) 4 FO = LOW LTC2400 OR ( 2 R REFERENCE R 0 E 0.1VVO TLOT AVGCEC VREF SCK RITY –2 3-WIRE EA –4 INPUTA RNAANLOGGE VIN SDO SPI INTERFACE LIN –6 –0.12VREF TO 1.12VREF GND CS –8 2400 TA01 –10 0 8,338,608 16,777,215 OUTPUT CODE (DECIMAL) 2400 TA02 1

LTC2400 ABSOLUTE WMAXIWMUWM RATINUGS PACKAGE/ORDER INUFORWMATIOUN (Notes 1, 2) ORDER PART NUMBER Supply Voltage (VCC) to GND.......................–0.3V to 7V TOP VIEW Analog Input Voltage to GND.......–0.3V to (V + 0.3V) CC VCC 1 8 FO LTC2400CS8 Reference Input Voltage to GND..–0.3V to (V + 0.3V) CC VREF 2 7 SCK LTC2400IS8 Digital Input Voltage to GND........–0.3V to (V + 0.3V) CC VIN 3 6 SDO Digital Output Voltage to GND .....–0.3V to (V + 0.3V) CC GND 4 5 CS S8 PART MARKING Operating Temperature Range S8 PACKAGE LTC2400C ...............................................0(cid:176) C to 70(cid:176) C 8-LEAD PLASTIC SO 2400 LTC2400I............................................ –40(cid:176) C to 85(cid:176) C TJMAX = 125(cid:176)C, q JA = 130(cid:176)C/W 2400I Storage Temperature Range................. –65(cid:176) C to 150(cid:176) C Consult factory for Military grade parts. Lead Temperature (Soldering, 10 sec)..................300(cid:176) C COUNVERTER CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V £ V £ V , (Note 5) l 24 Bits REF CC Integral Nonlinearity V = 2.5V (Note 6) l 2 10 ppm of V REF REF V = 5V (Note 6) l 4 15 ppm of V REF REF Offset Error 2.5V £ V £ V l 0.5 2 ppm of V REF CC REF Offset Error Drift 2.5V £ V £ V 0.01 ppm of V /(cid:176) C REF CC REF Full-Scale Error 2.5V £ V £ V l 4 10 ppm of V REF CC REF Full-Scale Error Drift 2.5V £ V £ V 0.02 ppm of V /(cid:176) C REF CC REF Total Unadjusted Error V = 2.5V 5 ppm of V REF REF V = 5V 10 ppm of V REF REF Output Noise V = 0V (Note 13) 1.5 m V IN RMS Normal Mode Rejection 60Hz – 2% (Note 7) l 110 130 dB Normal Mode Rejection 50Hz – 2% (Note 8) l 110 130 dB Power Supply Rejection, DC V = 2.5V, V = 0V 100 dB REF IN Power Supply Rejection, 60Hz – 2% V = 2.5V, V = 0V, (Notes 7, 15) 110 dB REF IN Power Supply Rejection, 50Hz – 2% V = 2.5V, V = 0V, (Notes 8, 15) 110 dB REF IN AU ALOG IU PUT AU D REFEREU CE The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Voltage Range (Note 14) l –0.125 • V 1.125 • V V IN REF REF V Reference Voltage Range l 0.1 V V REF CC C Input Sampling Capacitance 10 pF S(IN) C Reference Sampling Capacitance 15 pF S(REF) I Input Leakage Current CS = V l –10 1 10 nA IN(LEAK) CC I Reference Leakage Current V = 2.5V, CS = V l –10 1 10 nA REF(LEAK) REF CC 2

LTC2400 DIGITAL I U PUTS AU D DIGITAL OUTPUTS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage 2.7V £ V £ 5.5V l 2.5 V IH CC CS, F 2.7V £ V £ 3.3V 2.0 V O CC V Low Level Input Voltage 4.5V £ V £ 5.5V l 0.8 V IL CC CS, F 2.7V £ V £ 5.5V 0.6 V O CC V High Level Input Voltage 2.7V £ V £ 5.5V (Note 9) l 2.5 V IH CC SCK 2.7V £ V £ 3.3V (Note 9) 2.0 V CC V Low Level Input Voltage 4.5V £ V £ 5.5V (Note 9) l 0.8 V IL CC SCK 2.7V £ V £ 5.5V (Note 9) 0.6 V CC I Digital Input Current 0V £ V £ V l –10 10 m A IN IN CC CS, F O I Digital Input Current 0V £ V £ V (Note 9) l –10 10 m A IN IN CC SCK C Digital Input Capacitance 10 pF IN CS, F O C Digital Input Capacitance (Note 9) 10 pF IN SCK V High Level Output Voltage I = –800m A l V – 0.5V V OH O CC SDO V Low Level Output Voltage I = 1.6mA l 0.4V V OL O SDO V High Level Output Voltage I = –800m A (Note 10) l V – 0.5V V OH O CC SCK V Low Level Output Voltage I = 1.6mA (Note 10) l 0.4V V OL O SCK I High-Z Output Leakage l –10 10 m A OZ SDO POWER REQUIREW E U TS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 2.7 5.5 V CC I Supply Current CC Conversion Mode CS = 0V (Note 12) l 200 300 m A Sleep Mode CS = V (Note 12) l 20 30 m A CC 3

LTC2400 TI W I U G CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f External Oscillator Frequency Range l 2.56 307.2 kHz EOSC t External Oscillator High Period l 0.5 390 m s HEO t External Oscillator Low Period l 0.5 390 m s LEO t Conversion Time F = 0V l 130.66 133.33 136 ms CONV O F = V l 156.80 160 163.20 ms O CC External Oscillator (Note 11) l 20480/f (in kHz) ms EOSC f Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz ISCK External Oscillator (Notes 10, 11) f /8 kHz EOSC D Internal SCK Duty Cycle (Note 10) l 45 55 % ISCK f External SCK Frequency Range (Note 9) l 2000 kHz ESCK t External SCK Low Period (Note 9) l 250 ns LESCK t External SCK High Period (Note 9) l 250 ns HESCK t Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12) l 1.64 1.67 1.70 ms DOUT_ISCK External Oscillator (Notes 10, 11) l 256/f (in kHz) ms EOSC t External SCK 32-Bit Data Output Time (Note 9) l 32/f (in kHz) ms DOUT_ESCK ESCK t CS fl to SDO Low Z l 0 150 ns 1 t2 CS › to SDO High Z l 0 150 ns t3 CS fl to SCK fl (Note 10) l 0 150 ns t4 CS fl to SCK › (Note 9) l 50 ns t SCK fl to SDO Valid l 200 ns KQMAX t SDO Hold After SCK fl (Note 5) l 15 ns KQMIN t SCK Set-Up Before CS fl l 50 ns 5 t SCK Hold After CS fl l 50 ns 6 Note 1: Absolute Maximum Ratings are those values beyond which the Note 10: The converter is in internal SCK mode of operation such that life of the device may be impaired. the SCK pin is used as digital output. In this mode of operation the Note 2: All voltage values are with respect to GND. SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, f , is expressed in kHz. Note 4: Internal Conversion Clock source with the F pin tied EOSC O to GND or to V or to external conversion clock source with Note 12: The converter uses the internal oscillator. CC fEOSC = 153600Hz unless otherwise specified. FO = 0V or FO = VCC. Note 5: Guaranteed by design, not subject to test. Note 13: The output noise includes the contribution of the internal calibration operations. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer Note 14: For reference voltage values VREF > 2.5V the extended input curve. The deviation is measured from the center of the quantization of –0.125 • VREF to 1.125 • VREF is limited by the absolute maximum band. rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF £ Note 7: F = 0V (internal oscillator) or f = 153600Hz – 2% 0.267V + 0.89 • VCC the input voltage range is –0.3V to 1.125 • VREF. O EOSC For 0.267V + 0.89 • V < V £ V the input voltage range is –0.3V (external oscillator). CC REF CC to V + 0.3V. Note 8: F = V (internal oscillator) or f = 128000Hz – 2% CC O CC EOSC Note 15: The DC voltage at V = 4.1V, and the AC voltage applied to (external oscillator). CC V is 2.8V Note 9: The converter is in external SCK mode of operation such that CC P-P the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is f and is expressed in kHz. ESCK 4

LTC2400 TYPICAL PERFORW AU CE CHARACTERISTICS Total Unadjusted Error Negative Input Extended Total (3V Supply) INL (3V Supply) Unadjusted Error (3V Supply) 10 10 10 VCC = 3V VCC = 3V VCC = 3V VREF = 3V VREF = 3V VREF = 3V TA = 90°C 5 5 5 m) m) TA = –55°C, –45°C, 25°C, 90°C m) TA = 25°C p p p p p p R ( 0 R ( 0 R ( 0 O O O ERR TA = –55°C, –45°C, 25°C, 90°C ERR ERR TA = –45°C –5 –5 –5 TA = –55°C –10 –10 –10 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2400 G01 2400 G02 2400 G03 Positive Input Extended Total Total Unadjusted Error Unadjusted Error (3V Supply) (5V Supply) INL (5V Supply) 10 10 10 VCC = 3V VCC = 5V VCC = 5V VREF = 3V 8 VREF = 5V VREF = 5V 6 5 5 TA = –55°C 4 m) m) 2 m) p p p R (p 0 TA = –45°C R (p 0 R (p 0 ERRO TA = 90°C TA = 25°C ERRO –2 TA = –55°C, –45°C, 25°C, 90°C ERRO TA = –55°C, –45°C, 25°C, 90°C –4 –5 –5 –6 –8 –10 –10 –10 3.0 3.1 3.2 3.3 0 1 2 3 4 5 0 1 2 3 4 5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2400 G04 2400 G05 2400 G06 Negative Input Extended Total Positive Input Extended Total Unadjusted Error (5V Supply) Unadjusted Error (5V Supply) Offset Error vs Reference Voltage 10 10 6 VCC = 5V VCC = 5V VCC = 5V VREF = 5V TA = 90°C VREF = 5V 5 TA = 25°C 5 5 TA = –55°C pm) 4 ppm) TA = 25°C ppm) OR (p 3 ERROR ( 0 TA = –45°C ERROR ( 0 TA = 90°C TA = 2T5A° =C –45°C FSET ERR 2 –5 –5 OF 1 TA = –55°C 0 –10 –10 –1 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 5.0 5.1 5.2 5.3 0 1 2 3 4 5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) REFERENCE VOLTAGE 2400 G07 2400 G08 2400 G09 5

LTC2400 TYPICAL PERFORW AU CE CHARACTERISTICS RMS Noise vs Reference Voltage Offset Error vs V RMS Noise vs V CC CC 20 5.0 5.0 VCC = 5V VREF = 2.5V VREF = 2.5V TA = 25°C TA = 25°C TA = 25°C ppm OF V)REF 1105 ROR (ppm) 2.50 SE (ppm) 2.5 MS NOISE ( 5 OFFSET ER–2.5 RMS NOI R 0 –5.0 0 0 1 2 3 4 5 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 REFERENCE VOLTAGE (V) VCC VCC 2400 G10 2400 G11 2400 G12 Noise Histogram RMS Noise vs Code Out Offset Error vs Temperature 1500 1.00 5.0 VCC = 5V VCC = 5V VCC = 5V VREF = 5V VREF = 5V VREF = 5V VIN = 0V VIN = –0.3V TO 5.3V VIN = 0V GS 0.75 TA = 25°C m) 2.5 NUMBER OF READIN1500000 RMS NOISE (ppm)00..2550 OFFSET ERROR (pp–2.50 0 0 –5.0 –1.0 –0.5 0 0.5 1.0 1.5 0 7FFFFF FFFFFF –55 –30 –5 20 45 70 95 120 OUTPUT CODE (ppm) CODE OUT (HEX) TEMPERATURE (°C) 2400 G14 2400 G18 2400 G13 Full-Scale Error Full-Scale Error vs Temperature vs Reference Voltage Full-Scale Error vs V CC 5.0 10.0 6 VCC = 5V VCC = 5V VREF = 5V VIN = VREF VIN = 5V 5 m) 2.5 m) 7.5 m) FULL-SCALE ERROR (pp–2.50 FULL-SCALE ERROR (pp 25..50 FULL-SCALE ERROR (pp 243 1 VREF = 2.5V VIN = 2.5V TA = 25°C –5.0 0 0 –55 –30 –5 20 45 70 95 120 0 1 2 3 4 5 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE (°C) REFERENCE VOLTAGE (V) VCC 2400 G15 2400 G16 2400 G17 6

LTC2400 TYPICAL PERFORW AU CE CHARACTERISTICS Conversion Current vs Temperature Sleep Current vs Temperature PSRR vs Frequency at V CC 230 30 0 VCC = 4.1V 220 VCC = 5.5V 25 –20 VTAIN = = 2 05V°C µURRENT (A) 122910000 VCC = 4.1V µURRENT (A) 1250 VCC = 2.7V, 5.5V TION (dB)––6400 FO = 0 LY C 180 VCC= 2.7V LY C EJEC PP PP 10 R–80 U U 15,360Hz 153,600Hz S 170 S 5 –100 160 150 0 –120 –55 –30 –5 20 45 70 95 120 –55 –30 –5 20 45 70 95 120 1 100 10k 1M TEMPERATURE (°C) TEMPERATURE (°C) FREQUENCY AT VCC (Hz) 2400 G19 2400 G20 2400 G23 PSRR vs Frequency at V PSRR vs Frequency at V Rejection vs Frequency at V CC CC IN –10 0 0 VCC = 4.1V VCC = 4.1V VCC = 5V VIN = 0V VIN = 0V VREF = 5V –30 TA = 25°C –20 TA = 25°C –20 VIN = 2.5V F0 = 0 FO = 0 FO = 0 N (dB)–50 N (dB)–40 N (dB)–40 REJECTIO––9700 REJECTIO––8600 REJECTIO––8600 –110 –100 –100 –130 –120 –120 0 50 100 150 200 250 15200 15250 15300 15350 15400 15450 15500 1 50 100 150 200 250 FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) FREQUENCY AT VIN (Hz) 2400 G21 1635 G22 2400 G24 Rejection vs Frequency at V Rejection vs Frequency at V Rejection vs Frequency at V IN IN IN –60 0 0 VCC = 5V –70 –20 VVRINE F= =2 .55VV –20 –80 FO = 0 –40 N (dB) –90 N (dB)–40 N (dB) –60 REJECTIO ––110100 REJECTIO––8600 REJECTIO –80 –100 –120 –100 –130 –120 SAMPLE RATE = 15.36kHz – 2% –140 –120 –140 –12 –8 –4 0 4 8 12 15100 15200 15300 15400 15500 0 fS/2 fS INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) FREQUENCY AT VIN (Hz) INPUT FREQUENCY 2400 G25 2400 G26 2400 F26 7

LTC2400 TYPICAL PERFORW AU CE CHARACTERISTICS INL vs Output Rate Resolution vs Output Rate 24 24 VCC = 5V VCC = 5V 22 VREF = 5V 22 VREF = 5V TA = 25°C TA = 25°C 20 F0 = EXTERNAL 20 FO = EXTERNAL * S) INL (BITS) 111864 OLUTION (BIT 111864 S E R 12 12 10 10 *RESOLUTION = LOG(VREF/RMS NOISE) LOG (2) 8 8 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 OUTPUT RATE (Hz) OUTPUT RATE (Hz) 2400 G27 2400 G28 PIUN FUUNCTIOUNS V (Pin 1): Positive Supply Voltage. Bypass to GND SDO (Pin 6): Three-State Digital Output. During the data CC (Pin␣4) with a 10m F tantalum capacitor in parallel with output period, this pin is used for serial data output. When 0.1m F ceramic capacitor as close to the part as possible. the chip select CS is HIGH (CS = V ), the SDO pin is in a CC high impedance state. During the Conversion and Sleep V (Pin 2): Reference Input. The reference voltage range REF periods this pin can be used as a conversion status output. is 0.1V to V . CC The conversion status can be observed by pulling CS LOW. V (Pin 3): Analog Input. The input voltage range is IN SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal –0.125 • V to 1.125 • V . For V > 2.5V, the input REF REF REF Serial Clock Operation mode, SCK is used as digital output voltage range may be limited by the pin absolute maxi- for the internal serial interface clock during the data output mum rating of –0.3V to V + 0.3V. CC period. In External Serial Clock Operation mode, SCK is GND (Pin 4): Ground. Shared pin for analog ground, used as digital input for the external serial interface. A digital ground, reference ground and signal ground. Should weak internal pull-up is automatically activated in Internal be connected directly to a ground plane through a mini- Serial Clock Operation mode. The Serial Clock mode is mum length trace or it should be the single-point-ground determined by the level applied to SCK at power up and the in a single point grounding system. falling edge of CS. CS (Pin 5): Active LOW Digital Input. A LOW on this pin F (Pin 8): Frequency Control Pin. Digital input that O enables the SDO digital output and wakes up the ADC. controls the ADC’s notch frequencies and conversion Following each conversion the ADC automatically enters time. When the F pin is connected to V (F = V ), the O CC O CC the Sleep mode and remains in this low power state as converter uses its internal oscillator and the digital filter long as CS is HIGH. A LOW on CS wakes up the ADC. A first null is located at 50Hz. When the F pin is connected O LOW-to-HIGH transition on this pin disables the SDO to GND (F = OV), the converter uses its internal oscillator O digital output. A LOW-to-HIGH transition on CS during the and the digital filter first null is located at 60Hz. When F O Data Output transfer aborts the data transfer and starts a is driven by an external clock signal with a frequency f EOSC, new conversion. the converter uses this signal as its clock and the digital filter first null is located at a frequency f /2560. EOSC 8

LTC2400 FUUCTIOUAL BLOCK DIAGRAW INTERNAL VCC OSCILLATOR GND AUTOCALIBRATION AND CONTROL FO (INT/EXT) VIN ∫ ∫ ∫ SDO ∑ SERIAL ADC SCK INTERFACE CS VREF DECIMATING FIR DAC 2400 FD TEST CIRCUITS VCC SDO 3.4k 3.4k CLOAD = 20pF SDO CLOAD = 20pF HI-Z TO VOH VOL TO VOH VOH TO HI-Z 2400 TA03 HI-Z TO VOL VOH TO VOL VOL TO HI-Z 2400 TA04 APPLICATIOUNS INUFORWMATIOUN Converter Operation Cycle CONVERT The LTC2400 is a low power, delta-sigma analog-to- digital converter with an easy to use 3-wire serial interface. SLEEP Its operation is simple and made up of three states. The converter operating cycle begins with the conversion, followed by a low power sleep state and concluded with 1 CS AND the data output (see Figure 1). The 3-wire interface con- SCK sists of serial data output (SDO), a serial clock (SCK) and 0 a chip select (CS). DATA OUTPUT Initially, the LTC2400 performs a conversion. Once the conversion is complete, the device enters the sleep state. 2400 F01 While in this sleep state, power consumption is reduced by Figure 1. LTC2400 State Transition Diagram 9

LTC2400 APPLICATIOUNS INUFORWMATIOUN an order of magnitude. The part remains in the sleep state conversion and the output data. Therefore, multiplexing as long as CS is logic HIGH. The conversion result is held an analog input voltage is easy. indefinitely in a static shift register while the converter is The LTC2400 performs offset and full-scale calibrations in the sleep state. every conversion cycle. This calibration is transparent to Once CS is pulled low, the device begins outputting the the user and has no effect on the cyclic operation de- conversion result. There is no latency in the conversion scribed above. The advantage of continuous calibration is result. The data output corresponds to the conversion just extreme stability of offset and full-scale readings with re- performed. This result is shifted out on the serial data out spect to time, supply voltage change and temperature drift. pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to Power-Up Sequence reliably latch data on the rising edge of SCK, see Figure 3. The LTC2400 automatically enters an internal reset state The data output state is concluded once 32 bits are read when the power supply voltage V drops below approxi- CC out of the ADC or when CS is brought HIGH. The device mately 2.2V. This feature guarantees the integrity of the automatically initiates a new conversion cycle and the conversion result and of the serial interface mode selec- cycle repeats. tion which is performed at the initial power-up. (See the Through timing control of the CS and SCK pins, the 2-wire I/O sections in the Serial Interface Timing Modes LTC2400 offers several flexible modes of operation section.) (internal or external SCK and free-running conversion When the V voltage rises above this critical threshold, CC modes). These various modes do not require program- the converter creates an internal power-on-reset (POR) ming configuration registers; moreover, they do not dis- signal with duration of approximately 0.5ms. The POR turb the cyclic operation described above. These modes of signal clears all internal registers. Following the POR operation are described in detail in the Serial Interface signal, the LTC2400 starts a normal conversion cycle and Timing Modes section. follows the normal succession of states described above. The first conversion result following POR is accurate Conversion Clock within the specifications of the device. A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter Reference Voltage Range (commonly known as Sinc or Comb filter). For high The LTC2400 can accept a reference voltage from 0V to resolution, low frequency applications, this filter is typi- V . The converter output noise is determined by the CC cally designed to reject line frequencies of 50 or 60Hz plus thermal noise of the front-end circuits, and as such, its their harmonics. In order to reject these frequencies in value in microvolts is nearly constant with reference excess of 110dB, a highly accurate conversion clock is voltage. A decrease in reference voltage will not signifi- required. The LTC2400 incorporates an on-chip highly cantly improve the converter’s effective resolution. On the accurate oscillator. This eliminates the need for external other hand, a reduced reference voltage will improve the frequency setting components such as crystals or oscilla- overall converter INL performance. The recommended tors. Clocked by the on-chip oscillator, the LTC2400 range for the LTC2400 voltage reference is 100mV to V . CC rejects line frequencies (50 or 60Hz – 2%) a minimum of 110dB. Input Voltage Range The converter is able to accommodate system level offset Ease of Use and gain errors as well as system level overrange situa- The LTC2400 data output has no latency, filter settling or tions due to its extended input range, see Figure 2. The redundant data associated with the conversion cycle. LTC2400 converts input signals within the extended input There is a one-to-one correspondence between the range of –0.125 • V to 1.125 • V . REF REF 10

LTC2400 APPLICATIOUNS INUFORWMATIOUN Bit 31 (first output bit) is the end of conversion (EOC) VCC + 0.3V indicator. This bit is available at the SDO pin during the 9/8VREF conversion and sleep states whenever the CS pin is LOW. VREF This bit is HIGH during the conversion and goes LOW ABSOLUTE when the conversion is complete. NORMAL EXTENDED MAXIMUM 1/2VREF INPUT INPUT INPUT RANGE RANGE Bit 30 (second output bit) is a dummy bit (DMY) and is RANGE always LOW. 0 Bit 29 (third output bit) is the conversion result sign indi- –1/8VREF cator (SIG). If V is >0, this bit is HIGH. If V is <0, this IN IN –0.3V bit is LOW. The sign bit changes state during the zero code. 2400 F02 Bit 28 (forth output bit) is the extended input range (EXR) Figure 2. LTC2400 Input Range indicator. If the input is within the normal input range 0␣£ ␣V £ V , this bit is LOW. If the input is outside the IN REF For large values of VREF this range is limited by the normal input range, VIN > VREF or VIN < 0, this bit is HIGH. absolute maximum voltage range of –0.3V to (V + 0.3V). CC The function of these bits is summarized in Table 1. Beyond this range the input ESD protection devices begin to turn on and the errors due to the input leakage current Table 1. LTC2400 Status Bits increase rapidly. Bit 31 Bit 30 Bit 29 Bit 28 Input Range EOC DMY SIG EXR Input signals applied to V may extend below ground by IN V > V 0 0 1 1 IN REF –300mV and above V by 300mV. In order to limit any CC 0 < V £ V 0 0 1 0 IN REF fault current, a resistor of up to 5k may be added in series V = 0+/0– 0 0 1/0 0 IN with the V pin without affecting the performance of the IN V < 0 0 0 0 1 device. In the physical layout, it is important to maintain IN the parasitic capacitance of the connection between this Bit 27 (fifth output bit) is the most significant bit (MSB). series resistance and the V pin as low as possible; IN Bits 27-4 are the 24-bit conversion result MSB first. therefore, the resistor should be located as close as practical to the V pin. The effect of the series resistance Bit 4 is the least significant bit (LSB). IN on the converter accuracy can be evaluated from the Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may curves presented in the Analog Input/Reference Current be included in averaging or discarded without loss of section. In addition a series resistor will introduce a resolution. temperature dependent offset error due to the input leak- age current. A 1nA input leakage current will develop a Data is shifted out of the SDO pin under control of the serial 1ppm offset error on a 5k resistor if V = 5V. This error clock (SCK), see Figure 3. Whenever CS is HIGH, SDO REF has a very strong temperature dependency. remains high impedance and any SCK clock pulses are ignored by the internal data out shift register. Output Data Format In order to shift the conversion result out of the device, CS The LTC2400 serial output data stream is 32 bits long. The must first be driven LOW. EOC is seen at the SDO pin of the first 4 bits represent status information indicating the device once CS is pulled LOW. EOC changes real time from sign, input range and conversion state. The next 24 bits are HIGH to LOW at the completion of a conversion. This the conversion result, MSB first. The remaining 4 bits are signal may be used as an interrupt for an external sub LSBs beyond the 24-bit level that may be included in microcontroller. Bit 31 (EOC) can be captured on the first averaging or discarded without loss of resolution. rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted 11

LTC2400 APPLICATIOUNS INUFORWMATIOUN out on the falling edge of the 31st SCK and may be latched to the value corresponding to 1.125 • V . For input REF on the rising edge of the 32nd SCK pulse. On the falling voltages below –0.125 • V , the conversion result is REF edge of the 32nd SCK pulse, SDO goes HIGH indicating a clamped to the value corresponding to –0.125 • V . REF new conversion cycle has been initiated. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 sum- Frequency Rejection Selection (FO Pin Connection) marizes the output data format. The LTC2400 internal oscillator provides better than 110dB As long as the voltage on the V pin is maintained within normal mode rejection at the line frequency and all its IN the –0.3V to (V + 0.3V) absolute maximum operating harmonics for 50Hz – 2% or 60Hz – 2%. For 60Hz rejec- CC range, a conversion result is generated for any input value tion, FO (Pin 8) should be connected to GND (Pin 4) while from –0.125 • VREF to 1.125 • VREF. For input voltages for 50Hz rejection the FO pin should be connected to VCC greater than 1.125 • V , the conversion result is clamped (Pin␣1). REF CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 4 BIT 0 SDO EOC “0” SIG EXT MSB LSB24 Hi-Z SCK 1 2 3 4 5 27 28 32 SLEEP DATA OUTPUT CONVERSION 2400 F03 Figure 3. Output Data Timing Table 2. LTC2400 Output Data Format Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 … Bit 4 Bit 3-0 Input Voltage EOC DMY SIG EXR MSB LSB SUB LSBs* V > 9/8 • V 0 0 1 1 0 0 0 1 1 ... 1 X IN REF 9/8 • V 0 0 1 1 0 0 0 1 1 ... 1 X REF V + 1LSB 0 0 1 1 0 0 0 0 0 ... 0 X REF V 0 0 1 0 1 1 1 1 1 ... 1 X REF 3/4V + 1LSB 0 0 1 0 1 1 0 0 0 ... 0 X REF 3/4V 0 0 1 0 1 0 1 1 1 ... 1 X REF 1/2V + 1LSB 0 0 1 0 1 0 0 0 0 ... 0 X REF 1/2V 0 0 1 0 0 1 1 1 1 ... 1 X REF 1/4V + 1LSB 0 0 1 0 0 1 0 0 0 ... 0 X REF 1/4V 0 0 1 0 0 0 1 1 1 ... 1 X REF 0+/0– 0 0 1/0** 0 0 0 0 0 0 ... 0 X –1LSB 0 0 0 1 1 1 1 1 1 ... 1 X –1/8 • V 0 0 0 1 1 1 1 0 0 ... 0 X REF V < –1/8 • V 0 0 0 1 1 1 1 0 0 ... 0 X IN REF *The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. **The sign bit changes state during the 0 code. 12

LTC2400 APPLICATIOUNS INUFORWMATIOUN The selection of 50Hz or 60Hz rejection can also be made –60 by driving F to an appropriate logic level. A selection –70 O change during the sleep or data output states will not –80 disturb the converter operation. If the selection is made B) –90 d during the conversion state, the result of the conversion in N ( O –100 progress may be outside specifications but the following CTI E conversions will not be affected. REJ –110 –120 When a fundamental rejection frequency different from –130 50Hz or 60Hz is required or when the converter must be –140 synchronized with an outside source, the LTC2400 can –12 –8 –4 0 4 8 12 operate with an external conversion clock. The converter INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) automatically detects the presence of an external clock 2400 G25 signal at the F pin and turns off the internal oscillator. The O Figure 4. LTC2400 Normal Mode Rejection When frequency f of the external signal must be at least EOSC Using an External Oscillator of Frequency f EOSC 2560Hz (1Hz notch frequency) to be detected. The exter- nal clock signal duty cycle is not significant as long as the operation will not be disturbed if the change of conversion minimum and maximum specifications for the high and clock source occurs during the sleep state or during the low periods t and t are observed. HEO LEO data output state while the converter uses an external While operating with an external conversion clock of a serial clock. If the change occurs during the conversion frequency f , the LTC2400 provides better than 110dB state, the result of the conversion in progress may be EOSC normal mode rejection in a frequency range f /2560 outside specifications but the following conversions will EOSC – 4% and its harmonics. The normal mode rejection as a not be affected. If the change occurs during the data output function of the input frequency deviation from f /2560 state and the converter is in the Internal SCK mode, the EOSC is shown in Figure 4. serial clock duty cycle may be affected but the serial data stream will remain valid. Whenever an external clock is not present at the F pin, the O converter automatically activates its internal oscillator and Table 3 summarizes the duration of each state as a enters the Internal Conversion Clock mode. The LTC2400 function of F . O Table 3. LTC2400 State Duration State Operating Mode Duration CONVERT Internal Oscillator F = LOW 133ms O (60Hz Rejection) F = HIGH 160ms O (50Hz Rejection) External Oscillator F = External Oscillator 20480/f s O EOSC with Frequency f kHz EOSC (f /2560 Rejection) EOSC SLEEP As Long As CS = HIGH Until CS = 0 and SCK DATA OUTPUT Internal Serial Clock F = LOW/HIGH As Long As CS = LOW But Not Longer Than 1.67ms O (Internal Oscillator) (32 SCK cycles) F = External Oscillator with As Long As CS = LOW But Not Longer Than 256/f ms O EOSC Frequency f kHz (32 SCK cycles) EOSC External Serial Clock with As Long As CS = LOW But Not Longer Than 32/f ms SCK Frequency f kHz (32 SCK cycles) SCK 13

LTC2400 APPLICATIOUNS INUFORWMATIOUN SERIAL INTERFACE the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first The LTC2400 transmits the conversion results and re- rising edge of SCK occurs while CS = 0. ceives the start of conversion command through a syn- chronous 3-wire interface. During the conversion and Chip Select Input (CS) sleep states, this interface can be used to assess the converter status and during the data output state it is used The active LOW chip select, CS (Pin 5), is used to test the to read the conversion result. conversion status and to enable the data output transfer as described in the previous sections. Serial Clock Input/Output (SCK) In addition, the CS signal can be used to trigger a new The serial clock signal present on SCK (Pin 7) is used to conversion cycle before the entire serial data transfer has synchronize the data transfer. Each bit of data is shifted out been completed. The LTC2400 will abort any serial data the SDO pin on the falling edge of the serial clock. transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS In the Internal SCK mode of operation, the SCK pin is an pin after the converter has entered the data output state output and the LTC2400 creates its own serial clock by (i.e., after the first rising edge of SCK occurs with CS = 0). dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The Finally, CS can be used to control the free-running modes internal or external SCK mode is selected on power-up and of operation, see Serial Interface Timing Modes section. then reselected every time a HIGH-to-LOW transition is Grounding CS will force the ADC to continuously convert detected at the CS pin. If SCK is HIGH or floating at power- at the maximum output rate selected by F . Tying a O up or during this transition, the converter enters the inter- capacitor to CS will reduce the output rate and power nal SCK mode. If SCK is LOW at power-up or during this dissipation by a factor proportional to the capacitor’s transition, the converter enters the external SCK mode. value, see Figures 12 to 14. Serial Data Output (SDO) SERIAL INTERFACE TIMING MODES The serial data output pin, SDO (Pin 6), drives the serial The LTC2400’s 3-wire interface is SPI and MICROWIRE data during the data output state. In addition, the SDO pin compatible. This interface offers several flexible modes of is used as an end of conversion indicator during the operation. These include internal/external serial clock, conversion and sleep states. 2- or 3-wire I/O, single cycle conversion and autostart. The When CS (Pin 5) is HIGH, the SDO driver is switched to a following sections describe each of these serial interface high impedance state. This allows sharing the serial timing modes in detail. In all these cases, the converter interface with other devices. If CS is LOW during the can use the internal oscillator (F = LOW or F = HIGH) or O O convert or sleep state, SDO will output EOC. If CS is LOW an external oscillator connected to the F pin. Refer to O during the conversion phase, the EOC bit appears HIGH on Table 4 for a summary. Table 4. LTC2400 Interface Timing Modes Conversion Data Connection SCK Cycle Output and Configuration Source Control Control Waveforms External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6 External SCK, 2-Wire I/O External SCK SCK Figure 7 Internal SCK, Single Cycle Conversion Internal CS fl CS fl Figures 8, 9 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10 Internal SCK, Autostart Conversion Internal C Internal Figure 11 EXT 14

LTC2400 APPLICATIOUNS INUFORWMATIOUN External Serial Clock, Single Cycle Operation out the SDO pin on each falling edge of SCK. This enables (SPI/MICROWIRE Compatible) external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK This timing mode uses an external serial clock to shift out and the last bit of the conversion result can be latched on the conversion result and a CS signal to monitor and the 32nd rising edge of SCK. On the 32nd falling edge of control the state of the conversion cycle, see Figure 5. SCK, the device begins a new conversion. SDO goes HIGH The serial clock mode is selected on the falling edge of CS. (EOC = 1) indicating a conversion is in progress. To select the external serial clock mode, the serial clock pin At the conclusion of the data cycle, CS may remain LOW (SCK) must be LOW during each CS falling edge. and EOC monitored as an end-of-conversion interrupt. The serial data output pin (SDO) is HI-Z as long as CS is Alternatively, CS may be driven HIGH setting SDO to HI-Z. HIGH. At any time during the conversion cycle, CS may be As described above, CS may be pulled LOW at any time in pulled LOW in order to monitor the state of the converter. order to monitor the conversion status. While CS is pulled LOW, EOC is output to the SDO pin. EOC Typically, CS remains LOW during the data output state. = 1 while a conversion is in progress and EOC = 0 if the However, the data output state may be aborted by pulling device is in the sleep state. Independent of CS, the device CS HIGH anytime between the first rising edge and the automatically enters the low power sleep state once the 32nd falling edge of SCK, see Figure 6. On the rising edge conversion is complete. of CS, the device aborts the data output state and imme- When the device is in the sleep state (EOC = 0), its diately initiates a new conversion. This is useful for sys- conversion result is held in an internal static shift regis- tems not requiring all 32 bits of output data, aborting an ter. The device remains in the sleep state until the first invalid conversion cycle or synchronizing the start of a rising edge of SCK is seen while CS is LOW. Data is shifted conversion. 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS TEST EOC TEST EOC TEST EOC BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB SUB LSB Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2400 F05 Figure 5. External Serial Clock, Single Cycle Operation 15

LTC2400 APPLICATIOUNS INUFORWMATIOUN 2.7V TO 5.5V 1µF VCC= 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 9 BIT 8 SDO EOC EOC SIG EXR MSB Hi-Z Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2400 F06 Figure 6. External Serial Clock, Reduced Data Output Length External Serial Clock, 2-Wire I/O shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge This timing mode utilizes a 2-wire serial I/O interface. The of SCK. EOC can be latched on the first rising edge of SCK. conversion result is shifted out of the device by an exter- On the 32nd falling edge of SCK, SDO goes HIGH (EOC = nally generated serial clock (SCK) signal, see Figure 7. CS 1) indicating a new conversion has begun. may be permanently tied to ground (Pin 4), simplifying the user interface or isolation barrier. Internal Serial Clock, Single Cycle Operation The external serial clock mode is selected at the end of the This timing mode uses an internal serial clock to shift out power-on reset (POR) cycle. The POR cycle is concluded the conversion result and a CS signal to monitor and approximately 0.5ms after V exceeds 2.2V. The level CC control the state of the conversion cycle, see Figure 8. applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR In order to select the internal serial clock timing mode, the in order to enter the external serial clock timing mode. serial clock pin (SCK) must be floating (HI-Z) or pulled HIGH prior to the falling edge of CS. The device will not Since CS is tied LOW, the end-of-conversion (EOC) can be enter the internal serial clock mode if SCK is driven LOW continuously monitored at the SDO pin during the convert on the falling edge of CS. An internal weak pull-up resistor and sleep states. EOC may be used as an interrupt to an is active on the SCK pin during the falling edge of CS; external controller indicating the conversion result is therefore, the internal serial clock timing mode is auto- ready. EOC = 1 while the conversion is in progress and EOC matically selected if SCK is not externally driven. = 0 once the conversion enters the low power sleep state. On the falling edge of EOC, the conversion result is loaded The serial data output pin (SDO) is HI-Z as long as CS is into an internal static shift register. The device remains in HIGH. At any time during the conversion cycle, CS may be the sleep state until the first rising edge of SCK. Data is pulled LOW in order to monitor the state of the converter. 16

LTC2400 APPLICATIOUNS INUFORWMATIOUN 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB24 SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2400 F07 Figure 7. External Serial Clock, CS = 0 Operation 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION VCC FO == E6X0HTEz RRNEAJELC OTSIOCNILLATOR 10k LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS <tEOCtest CS TEST EOC TEST EOC BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB24 Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2400 F08 Figure 8. Internal Serial Clock, Single Cycle Operation 17

LTC2400 APPLICATIOUNS INUFORWMATIOUN Once CS is pulled LOW, SCK goes LOW and EOC is output shifted out of the SDO pin. The data output cycle begins on to the SDO pin. EOC = 1 while a conversion is in progress this first rising edge of SCK and concludes after the 32nd and EOC = 0 if the device is in the sleep state. rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output When testing EOC, if the conversion is complete (EOC = 0), to the SCK pin. This signal may be used to shift the the device will exit the sleep state and enter the data output conversion result into external circuitry. EOC can be state if CS remains LOW. In order to prevent the device latched on the first rising edge of SCK and the last bit of the from exiting the low power sleep state, CS must be pulled conversion result on the 32nd rising edge of SCK. After the HIGH before the first rising edge of SCK. In the internal 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays SCK timing mode, SCK goes HIGH and the device begins HIGH, and a new conversion starts. outputting data at time t after the falling edge of CS EOCtest (if EOC = 0) or t after EOC goes LOW (if CS is LOW Typically, CS remains LOW during the data output state. EOCtest during the falling edge of EOC). The value of t is 23m s However, the data output state may be aborted by pulling EOCtest if the device is using its internal oscillator (F = logic LOW CS HIGH anytime between the first and 32nd rising edge 0 or HIGH). If F is driven by an external oscillator of of SCK, see Figure 9. On the rising edge of CS, the device O frequency f , then t is 3.6/f . If CS is pulled aborts the data output state and immediately initiates a EOSC EOCtest EOSC HIGH before time t , the device remains in the sleep new conversion. This is useful for systems not requiring EOCtest state. The conversion result is held in the internal static all 32 bits of output data, aborting an invalid conversion shift register. cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the If CS remains LOW longer than t , the first rising EOCtest internal pull-up is not available to restore SCK to a logic edge of SCK will occur and the conversion result is serially 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION VCC FO == E6X0HTEz RRNEAJELC OTSIOCNILLATOR 10k LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS >tEOCtest <tEOCtest CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 8 SDO EOC EOC SIG EXR MSB Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2400 F09 Figure 9. Internal Serial Clock, Reduced Data Output Length 18

LTC2400 APPLICATIOUNS INUFORWMATIOUN HIGH state. This will cause the device to exit the internal pull-up may not be adequate to return SCK to a HIGH level serial clock mode on the next falling edge of CS. This can before CS goes low again. This is not a concern under be avoided by adding an external 10k pull-up resistor to normal conditions where CS remains LOW after detecting the SCK pin or by never pulling CS HIGH when SCK is LOW. EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Whenever SCK is LOW, the LTC2400’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven Internal Serial Clock, 2-Wire I/O, if the device is in the internal SCK timing mode. However, Continuous Conversion certain applications may require an external driver on SCK. If this driver goes HI-Z after outputting a LOW signal, the This timing mode uses a 2-wire, all output (SCK and SDO) LTC2400’s internal pull-up remains disabled. Hence, SCK interface. The conversion result is shifted out of the device remains LOW. On the next falling edge of CS, the device is by an internally generated serial clock (SCK) signal, see switched to the external SCK timing mode. By adding an Figure 10. CS may be permanently tied to ground (Pin 4), external 10k pull-up resistor to SCK, this pin goes HIGH simplifying the user interface or isolation barrier. once the external driver goes HI-Z. On the next CS falling The internal serial clock mode is selected at the end of the edge, the device will remain in the internal SCK timing power-on reset (POR) cycle. The POR cycle is concluded mode. approximately 0.5ms after V exceeds 2.2V. An internal CC A similar situation may occur during the sleep state when weak pull-up is active during the POR cycle; therefore, the CS is pulsed HIGH-LOW-HIGH in order to test the conver- internal serial clock timing mode is automatically selected sion status. If the device is in the sleep state (EOC = 0), SCK if SCK is not externally driven LOW (if SCK is loaded such will go LOW. Once CS goes HIGH (within the time period that the internal pull-up cannot pull the pin HIGH, the defined above as t ), the internal pull-up is activated. external SCK mode will be selected). EOCtest For a heavy capacitive load on the SCK pin, the internal 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB24 SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION SLEEP 2400 F10 Figure 10. Internal Serial Clock, Continuous Operation 19

LTC2400 APPLICATIOUNS INUFORWMATIOUN During the conversion, the SCK and the serial data output Internal Serial Clock, Autostart Conversion pin (SDO) are HIGH (EOC = 1). Once the conversion is This timing mode is identical to the internal serial clock, complete, SCK and SDO go LOW (EOC = 0) indicating the 2-wire I/O described above with one additional feature. conversion has finished and the device has entered the Instead of grounding CS, an external timing capacitor is low power sleep state. The part remains in the sleep state tied to CS. a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output While the conversion is in progress, the CS pin is held cycle begins on the first rising edge of SCK and ends after HIGH by an internal weak pull-up. Once the conversion is the 32nd rising edge. Data is shifted out the SDO pin on complete, the device enters the low power sleep state and each falling edge of SCK. The internally generated serial an internal 25nA current source begins discharging the clock is output to the SCK pin. This signal may be used capacitor tied to CS, see Figure 11. The time the converter to shift the conversion result into external circuitry. EOC spends in the sleep state is determined by the value of the can be latched on the first rising edge of SCK and the last external timing capacitor, see Figures 12 and 13. Once the bit of the conversion result can be latched on the 32nd voltage at CS falls below an internal threshold (» 1.4V), the rising edge of SCK. After the 32nd rising edge, SDO goes device automatically begins outputting data. The data HIGH (EOC = 1) indicating a new conversion is in progress. output cycle begins on the first rising edge of SCK and SCK remains HIGH during the conversion. ends on the 32nd rising edge. Data is shifted out the SDO 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2400 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CEXT VCC CS GND BIT 31 BIT 30 BIT 29 BIT 0 SDO EOC SIG Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2400 F11 Figure 11. Internal Serial Clock, Autostart Operation 20

LTC2400 APPLICATIOUNS INUFORWMATIOUN 7 pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be 6 used to shift the conversion result into external circuitry. 5 After the 32nd rising edge, CS is pulled HIGH and a new C) SE 4 conversion is immediately started. This is useful in appli- (PLE cations requiring periodic monitoring and ultralow power. M 3 A tS Figure 14 shows the average supply current as a function 2 of capacitance on CS. VCC = 5V 1 It should be noticed that the external capacitor discharge VCC = 3V 0 current is kept very small in order to decrease the con- 1 10 100 1000 10000 100000 CAPACITANCE ON CS (pF) verter power dissipation in the sleep state. In the autostart 2400 F12 mode the analog voltage on the CS pin cannot be observed Figure 12. CS Capacitance vs t without disturbing the converter operation using a regular SAMPLE oscilloscope probe. When using this configuration, it is important to minimize the external leakage current at the 8 CS pin by using a low leakage external capacitor and 7 properly cleaning the PCB surface. 6 The internal serial clock mode is selected every time the ATE (Hz) 5 VCC = 5V VCC = 3V voltage on the CS pin crosses an internal threshold volt- R 4 age. An internal weak pull-up at the SCK pin is active while E L MP 3 CS is discharging; therefore, the internal serial clock A S timing mode is automatically selected if SCK is floating. It 2 is important to ensure there are no external drivers pulling 1 SCK LOW while CS is discharging. 0 0 10 100 1000 10000 100000 CAPACITANCE ON CS (pF) DIGITAL SIGNAL LEVELS 2400 F13 The LTC2400’s digital interface is easy to use. Its digital Figure 13. CS Capacitance vs Output Rate inputs (F , CS and SCK in External SCK mode of operation) O accept standard TTL/CMOS logic levels and the internal 300 hysteresis receivers can tolerate edge rates as slow as 100m s. However, some considerations are required to take 250 VCC = 5V )S advantage of exceptional accuracy and low supply current. M R µA200 NT ( VCC = 3V The digital output signals (SDO and SCK in Internal SCK RE150 mode of operation) are less of a concern because they are R U C not generally active during the conversion state. Y L100 P UP In order to preserve the LTC2400’s accuracy, it is very S 50 important to minimize the ground path impedance which may appear in series with the input and/or reference signal 0 1 10 100 1000 10000 100000 and to reduce the current which may flow through this CAPACITANCE ON CS (pF) path. The GND pin should be connected to a low resistance 2400 F14 ground plane through a minimum length trace. The use of Figure 14. CS Capacitance vs Supply Current multiple via holes is recommended to further reduce the 21

LTC2400 APPLICATIOUNS INUFORWMATIOUN connection resistance. The LTC2400’s power supply cur- Parallel termination near the LTC2400 pin will eliminate rent flowing through the 0.01W resistance of the common this problem but will increase the driver power dissipation. ground pin will develop a 2.5m V offset signal. For a A series resistor between 27W and 56W placed near the reference voltage V = 2.5V, this represents a 1ppm driver or near the LTC2400 pin will also eliminate this REF offset error. problem without additional power dissipation. The actual resistor value depends upon the trace impedance and In an alternative configuration, the GND pin of the converter connection topology. can be the single-point-ground in a single point grounding system. The input signal ground, the reference signal Driving the Input and Reference ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) The analog input and reference of the typical delta-sigma should be connected in a star configuration with the com- analog-to-digital converter are applied to a switched ca- mon point located as close to the GND pin as possible. pacitor network. This network consists of capacitors switching between the analog input (V ), ground (Pin 4) IN The power supply current during the conversion state and the reference (V ). The result is small current spikes REF should be kept to a minimum. This is achieved by restrict- seen at both V and V . A simplified input equivalent IN REF ing the number of digital signal transitions occurring circuit is shown in Figure 15. during this period. While a digital input signal is in the range 0.5V to VCC (VCC␣–␣0.5V), the CMOS input receiver draws additional IREF(LEAK) R5SkW current from the power supply. It should be noted that, VREF when any one of the digital input signals (F , CS and SCK IREF(LEAK) O in External SCK mode of operation) is within this range, the IIN VCC AVERAGE INPUT CURRENT: LTC2400 power supply current may increase even if the IIN(LEAK) R5SkW IIN = 0.25(VIN – 0.5 • VREF)fCEQ signal in question is at a valid logic level. For micropower VIN IIN(LEAK) C10EQpF (TYP) operation and in order to minimize the potential errors due RSW 5k to additional ground pin current, it is recommended to GND 2400 F15 drive all digital input signals to full CMOS levels SWITCHING FREQUENCY f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH) [VIL < 0.4V and VOH > (VCC – 0.4V)]. f = fEOSC FOR EXTERNAL OSCILLATORS Severe ground pin current disturbances can also occur Figure 15. LTC2400 Equivalent Analog Input Circuit due to the undershoot of fast digital input signals. Under- shoot and overshoot can occur because of the impedance The key to understanding the effects of this dynamic input mismatch at the converter pin when the transition time of current is based on a simple first order RC time constant an external control signal is less than twice the propaga- model. Using the internal oscillator, the LTC2400’s inter- tion delay from the driver to LTC2400. For reference, on nal switched capacitor network is clocked at 153,600Hz a regular FR-4 board, signal propagation velocity is ap- corresponding to a 6.5m s sampling period. Fourteen time proximately 183ps/inch for internal traces and 170ps/inch constants are required each time a capacitor is switched in for surface traces. Thus, a driver generating a control order to achieve 1ppm settling accuracy. signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter Therefore, the equivalent time constant at V and V IN REF than 2.5 inches. This problem becomes particularly diffi- should be less than 6.5m s/14 = 460ns in order to achieve cult when shared control lines are used and multiple 1ppm accuracy. reflections may occur. The solution is to carefully termi- nate all transmission lines close to their characteristic impedance. 22

LTC2400 APPLICATIOUNS INUFORWMATIOUN Input Current (V ) If the total capacitance at V (see Figure 17) is small IN IN (<0.01m F), relatively large external source resistances (up If complete settling occurs on the input, conversion re- to 20k for 20pF parasitic capacitance) can be tolerated sults will be uneffected by the dynamic input current. If the without any offset/full-scale error. Figures 18 and 19 show settling is incomplete, it does not degrade the linearity a family of offset and full-scale error curves for various performance of the device. It simply results in an offset/ small valued input capacitors (C < 0.01m F) as a function full-scale shift, see Figure 16. To simplify the analysis of IN of input source resistance. input dynamic current, two separate cases are assumed: large capacitance at V (C > 0.01m F) and small capaci- For large input capacitor values (C > 0.01m F), the input IN IN IN tance at V (C < 0.01m F). spikes are averaged by the capacitor into a DC current. The IN IN gain shift becomes a linear function of input source resistance independent of input capacitance, see Figures 20 and 21. The equivalent input impedance is 1.66MW . This results in – 1.5m A of input dynamic current at the extreme values of V (V = 0V and V = V , when IN IN IN REF TUE 0 VCC = 5V VREF = 5V m) –10 TVAIN = = 2 55V°C p p R ( O –20 0 VRVEINF/2 2V40R0 EF1F6 L-SCALE ERR –30 CCICNIN IC=N I= N1= 10 =000 .0000ppp1FFFµF Figure 16. Offset/Full-Scale Shift UL F –40 RSOURCE VIN –50 INTPUT 1 10 100 1k 10k 100k SIGNAL CIN C@ P2A0RpF LTC2400 RSOURCE (Ω) SOURCE 2400 F19 2400 F17 Figure 19. Full-Scale Error vs R (Small C) SOURCE Figure 17. An RC Network at V IN OFFSET ERROR (ppm) 45230000 TVVVACRIN CE= F = = 2 = 055 VC5°VCCCVINIINN C= =I= N1 010 =.000 0001pppµFFFF OFFSET ERROR (ppm)123120005500000 VVVTACRIN CE= F = = 2 = 055 V5°VCV CCIINN C C==I IN 1N1 0 µ==µ F 00F..10µ1FµF 10 50 0 0 1 10 100 1k 10k 100k 0 100200 300400500600700800 9001000 RSOURCE (Ω) RSOURCE (Ω) 2400 F18 2400 F20 Figure 18. Offset vs RSOURCE (Small C) Figure 20. Offset vs RSOURCE (Large C) 23

LTC2400 APPLICATIOUNS INUFORWMATIOUN 0 600 VCC = 5V VCC = 5V FULL-SCALE ERROR (ppm)––––21105050000 CCININ = = 1 10µµCFFINC I=N 0=. 001.1µµFF VTVARIN E= F= 2 =55 V5°VC FULL-SCALE ERROR (ppm)234500000000 VTVARIN E= F= 2 =55 V5°CVCVREF = 10CµVFREF =C 0V.R1EµFF = 1µF –250 100 CVREF = 0.01µF –300 0 0 200 400 600 800 1000 0 200 400 600 800 1000 RSOURCE (Ω) RESISTANCE AT VREF (Ω) 2400 F21 2400 F22 Figure 21. Full-Scale Error vs RSOURCE (Large C) Figure 22. Full-Scale Error vs RVREF (Large C) V = 5V). This corresponds to a 0.3ppm shift in offset REF and full-scale readings for every 1W of input source 50 resistance. VCC = 5V VREF = 5V 40 VIN = 5V In addition to the input current spikes, the input ESD m) TA = 25°C p 30 pcurorrteenctti.o nT hdiiso dleesa khaagvee ac uterrmenpte,r antoumrei ndaelplye n1dneAn t (le– a1k0angAe ROR (p 20 CCVRVREFE F= = 1 100000ppFF R max), results in a fixed offset shift of 10m V for a 10k source E E CVREF = 0.01µF L 10 A resistance. SC LL- 0 FU CVREF = 0pF Reference Current (V ) –10 REF Similar to the analog input, the reference input has a –20 1 10 100 1k 10k 100k dynamic input current. This current has negligible effect RESISTANCE AT VREF(Ω) on the offset. However, the reference current at VIN = VREF 2400 F23 is similar to the input current at full-scale. For large values Figure 23. Full-Scale Error vs R (Small C) of reference capacitance (C > 0.01m F), the full-scale VREF VREF error shift is 0.3ppm/W of external reference resistance independent of the capacitance at V , see Figure 22. If 50 REF VCC = 5V the capacitance tied to V is small (C < 0.01m F), an VREF = 5V REF VREF 40 TA = 25°C input resistance of up to 20k (20pF parasitic capacitance CVREF = 0pF at V ) may be tolerated, see Figure 23. m) 30 CVREF = 100pF REF pp CVREF = 1000pF Unlike the analog input, the integral nonlinearity of the OR ( 20 device can be degraded with excessive external RC time ERR CVREF = 0.01µF L N 10 constants tied to the reference input. If the capacitance at I node V is small (C < 0.01m F), the reference input REF VREF 0 can tolerate large external resistances without reduction –10 in INL, see Figure 24. If the external capacitance is large 1 10 100 1k 10k 100k (CVREF > 0.01m F), the linearity will be degraded by RESISTANCE AT VREF (Ω) 0.15ppm/W independent of capacitance at V , see 2400 F24 REF Figure 25. Figure 24. INL Error vs R (Small C) VREF 24

LTC2400 APPLICATIOUNS INUFORWMATIOUN 160 0 VCC = 5V 140 VTAR E=F 2=5 5°CV –20 120 CVREF = 0.1µF –40 NL ERROR (ppm)168040000 CCVRVREFE F= = 1 10µµFF CVREF = 0.01µF REJECTION (dB) ––6800 I –100 20 –120 0 –20 –140 0 200 400 600 800 1000 0 fS/2 fS RESISTANCE AT VREF (Ω) INPUT FREQUENCY 2400 F25 2400 F26 Figure 25. INL Error vs RVREF (Large C) Figure 26. Sinc4 Filter Rejection In addition to the dynamic reference current, the V ESD digital filter is narrow (» 0.2%) compared to the bandwidth REF protection diodes have a temperature dependent leakage of the frequencies rejected. current. This leakage current, nominally 1nA (– 10nA max), As a result of the oversampling ratio (256) and the digital results in a fixed full-scale shift of 10m V for a 10k source filter, minimal (if any) antialias filtering is required in front resistance. of the LTC2400. If passive RC components are placed in front of the LTC2400 the input dynamic current should be ANTIALIASING considered (see Input Current section). In cases where large effective RC time constants are used, an external One of the advantages delta-sigma ADCs offer over con- buffer amplifier may be required to minimize the effects of ventional ADCs is on-chip digital filtering. Combined with input dynamic current. a large oversampling ratio, the LTC2400 significantly simplifies antialiasing filter requirements. The modulator contained within the LTC2400 can handle large-signal level perturbations without saturating. Signal The digital filter provides very high rejection except at levels up to 40% of V do not saturate the analog modu- integer multiples of the modulator sampling frequency REF lator. These signals are limited by the input ESD protection (f ), see Figure 26. The modulator sampling frequency is S to 300mV below ground and 300mV above V . 256 • F , where F is the notch frequency (typically 50Hz CC O O or 60Hz). The bandwidth of signals not rejected by the 25

LTC2400 TYPICAL APPLICATIONUS SYNCHRONIZATION OF MULTIPLE LTC2400s Increasing the Output Rate Using Multiple LTC2400s Since the LTC2400’s absolute accuracy (total unadjusted A second application uses multiple LTC2400s to increase error) is 10ppm, applications utilizing multiple matched the effective output rate by 4· , see Figure 28. In this case, ADCs are possible. four LTC2400s are interleaved under the control of sepa- rate CS signals. This increases the effective output rate Simultaneous Sampling with Two LTC2400s from 7.5Hz to 30Hz (up to a maximum of 60Hz). Addition- ally, the one-shot output spectrum is unfolded allowing One such application is synchronizing multiple LTC2400s, further digital signal processing of the conversion results. see Figure 27. The start of conversion is synchronized to SCK and SDO may be common to all four LTC2400s. The the rising edge of CS. In order to synchronize multiple four CS rising edges equally divide one LTC2400 conver- LTC2400s, CS is a common input to all the ADCs. sion cycle (7.5Hz for 60Hz notch frequency). In order to To prevent the converters from autostarting a new con- synchronize the start of conversion to CS, 31 or less SCK version at the end of data output read, 31 or fewer SCK clock pulses must be applied to each ADC. clock signals are applied to the LTC2400 instead of 32 (the 32nd falling edge would start a conversion). The exact Both the synchronous and 4· output rate applications use timing and frequency for the SCK signal is not critical the external serial clock and single cycle operation with since it is only shifting out the data. In this case, two reduced data output length (see Serial Interface Timing LTC2400’s simultaneously start and end their conversion Modes section and Figure 6). An external oscillator clock cycles under the external control of CS. is applied commonly to the F pin of each LTC2400 in O order to synchronize the sampling times. Both circuits may be extended to include more LTC2400s. SCK2 SCK1 EXTERNAL OSCILLATOR (153,600HZ) LTC2400 LTC2400 #1 #2 VCC FO VCC FO µCONTROLLER VREF SCK VREF SCK VIN SDO VIN SDO GND CS GND CS CS SDO1 SDO2 VREF (0.1V TO VCC) CS SCK1 31 OR LESS CLOCK CYCLES SCK2 31 OR LESS CLOCK CYCLES SDO1 SDO2 2400 F27 Figure 27. Synchronous Conversion—Extendable 26

LTC2400 TYPICAL APPLICATIONUS VREF (0.1V TO VCC) EXTERNAL OSCILLATOR LTC2400 LTC2400 LTC2400 LTC2400 (153,600HZ) #1 #2 #3 #4 VCC FO VCC FO VCC FO VCC FO VREF SCK VREF SCK VREF SCK VREF SCK VIN SDO VIN SDO VIN SDO VIN SDO µCONTROLLER GND CS GND CS GND CS GND CS SCK SDO CS1 CS2 CS3 CS4 CS1 CS2 CS3 CS4 31 OR LESS SCK CLOCK PULSES SDO 2400 F28 Figure 28. 4· Output Rate LTC2400 System Differential to Single-Ended Simple Differential Front-End Analog Conditioning for the LTC2400 The circuits in Figures 29 and 30 use the LTC1043 dual The circuit in Figure 29 is ideal for wide dynamic range precision, switched capacitor building block. Each circuit differential signals in applications where absolute accu- uses one-half of an LTC1043 to perform a differential to racy is secondary to high resolution, have large signal single-ended conversion over an input common mode swings, source impedances under 500W and use a 5V or range that includes the power supplies. The LTC1043 – 5V supply. samples a differential input voltage, holds it on C and S The circuit achieves a nonlinearity of – 35ppm (a linearity transfers it to a ground-referenced capacitor C . The H accuracy of 14.5 bits), noise of 1.5m V and 21-bit voltage on C is applied to the LTC2400’s input and RMS H resolution. The circuit exhibits a typical 2.75mV zero converted to a digital value. offset. However, this is not an offset that simply shifts the The LTC1043 achieves its best differential to single-ended output code by a constant value. It is a gain error that alters conversion when its internal switching frequency oper- the transfer function’s slope. The gain error revolves ates at a nominal 300Hz, as set by the 0.01m F capacitor C1, around midscale (V /2). This gain error can be corrected REF and when 1m F capacitors are used for C and C . C and in software by measuring the error at 0V input and using S H S C should be a film-type capacitor such as mylar or the result to create a correction factor. H polypropylene. 27

LTC2400 TYPICAL APPLICATIONUS VREFIN 5V 0.1µF 5V 0.1µF 1 2 VCC 5 4 VREF CS CHIP SELECT 3 6 7 8 VIN LTC2400 SDO SERIAL 7 SCK SERIAL LARGE 11 GND FO DIMFFAEGRNEINTTUIDAEL C1µSF C1µHF 4 8 INPUT EXT 12 13 14 16 C1 1/2 0.01µF LTC1043 17 0.1µF –5V 2400 F29 Figure 29. Simple Rail-to-Rail Circuit Converts Differential Signals to Single-Ended Signals LTC2400 High Accuracy Differential to Single-Ended Multiple Inputs Converter for – 5V Supplies The simple circuit shown in Figure 31 takes advantage of The circuit in Figure 30 is ideal for low level differential the LTC2400’s single conversion settling. The LTC1391 signals in applications that have a – 5V supply and need serially programmed multiplexer allows accurate conver- high accuracy without calibration. The circuit combines an sions on each of its eight channels without introducing any LTC1043 and LTC1050 as a differential to single-ended offset, gain or linearity errors with its input signal between amplifier that has an input common mode range that 0V and V , as long as the total capacitance connected to REF includes the power supplies. Resistors R1 and R2 set the the LTC2400’s input is less than 1000pF. A small 2ppm LTC1050’s gain at 101. (typ) error occurs when an active input channel’s signal voltage reaches –300mV (typ). If the excursion below The circuit schematic shows an optional resistor R . This S ground is above –200mV (typ), the error is less than the resistor can be placed in series with the LTC2400’s input LTC2400’s 0.3ppm noise. On the topside, the selected to limit current if the input goes below –300mV. The RMS input signal’s magnitude can go above the 5V supply with resistor does not degrade the converter’s performance as no linearity degradation or increased noise. Figure 31’s long as any capacitance, stray or otherwise, connected circuit can tolerate overdrive on the unselected channel between the LTC2400’s input and ground is less than without conversion degradation as long as the overdrive is 100pF. Higher capacitance will increase offset and full- less than 250mV above the supply voltage or 250mV scale errors (see Input Current section). below ground. The linearity performance is similar to that The circuit achieves a nonlinearity of – 1ppm, input re- shown in the Typical Performance Characteristics section. ferred noise of 0.05m V (averaging 64 samples), 19.6 RMS Errors caused by channel-to-channel crosstalk are less bits resolution for a full-scale input of 40mV, and an overall than the LTC2400’s typical input noise. This remains the accuracy of 20 bits when using an LTC1236-5 precision case for a frequency range of 1Hz to 153.6kHz (the 5V reference. LTC2400’s internal clock frequency or 10f ). When the S frequency reaches 1.536MHz (4V ), the RMS noise typi- P-P cally doubles and the linearity is degraded by 30ppm (typ). 28

LTC2400 TYPICAL APPLICATIONUS 5V 0.1µF VREFIN 5V 0.1µF 5V 0.1µF BRIDGE- 1 TYIPNIPCUATL VFS = 40mV 7 4 8 3 + 7 6 5R.S1*k 3 2 VREFVCC CS 56 CHIP SELECT LTC1050 VIN LTC2400 SDO SERIAL 350Ω 350Ω DIFFIENRPEUNTTIAL 11 1CµSF C1µHF 2 – 40.1µF GND FO SCK 7 SERIAL EXT 12 4 8 350Ω 350Ω R1 9.09k 13 14 –5V 16 R2 90.9k AGND OR C1 1/2 –VEXT 0.01µF LTC1043 *OPTIONAL: LIMITS INPUT CURRENT IF THE 17 INPUT VOLTAGE GOES BELOW –300mV 0.1µF –5V 2400 F30 Figure 30. Differential to Single-Ended Converter for Low Level Inputs, Such as Bridges, Maintains the LTC2400’s High Accuracy 5V VREFIN 5V 0.1µF 0.1µF 1 LTC1391 CH0 1 S0 V+ 16 2 VREFVCC CS 5 CS 2 15 3 6 CH1 S1 D VIN LTC2400 SDO SDO CH2 3 S2 V– 14 SCK 7 SCK CH3 4 S3 DATA 2 13 GND FO 5 12 4 8 CH4 S4 DATA 1 6 11 CH5 S5 CS 7 10 CH6 S6 CLK 8 9 CH7 S7 GND 2400 F31 Figure 31. Multiplex 8-Signal Sources with the LTC1391 and Maintain the LTC2400’s Conversion Accuracy 29

LTC2400 TYPICAL APPLICATIONUS Sample Driver for LTC2400 SPI Interface retrieve the 32-bit result. A fourth port line is used to power the LTC2400, a vivid example of the converter’s The LTC2400 has a very simple serial interface that makes micropower operation. The program’s main sequence interfacing to microprocessors and microcontrollers very activates the LTC2400’s serial interface, uses a loop to easy. Shown in Figures 32 and 34 are listings of sample retrieve the 32 conversion bits, and then places the source codes that can be used to initiate conversions and converter’s interface in a high impedance state and start- retrieve data from the LTC2400. ing the next conversion. All bits are retained in variables The listing in Figure 32 was created by Parallax, Inc. (916- ADlo and ADhi. The code can be found on their web site, 624-8333), for the BASIC Stamp. This code uses indi- www.parallaxinc.com. vidual port lines to control the LTC2400’s conversion and 'LTC2400 Sample Driver '03/17/99 This program is an example showing how to access the ' LTC2400 using the Basic Stamp2 from Parallax. Since ' the BS2 is based on a 16-bit architecture, only the ' upper 16 bits of the 24-bit result are displayed, ' although all 24 bits are retrieved. ADlo var word 'A/D result - lower 16 bits ADhi var word 'A/D result - upper 8 bits Ctr var byte 'loop counter Temp var bit 'temporary bit used for shift SDO con 0 'Serial data connected to P0 SCK con 1 'Serial clock connected to P1 CS con 2 'Chip Select connected to P2 Pwr con 3 'Stamp supplies power connected to P3 '(Uses only 0.3mA!) Init dira = $E 'Set up data direction 'Pwr, CS, and SCK are outputs 'SDO is an input outa = $0 'Initialize outputs 'Pwr, CS, and SCK are low pause 100 'Wait 100mS for I/O to settle high Pwr 'Power up the LTC2400 pause 1 'Wait 1mS for power-on sequence high CS 'Disable the device until we Start 'wish to read it. pause 125 'Eight times second low CS 'Enable the LTC2400 for Ctr = 0 to 31 high SCK 'Cycle clock 32 times gosub ShiftL 30

LTC2400 TYPICAL APPLICATIONUS ADlo.bit0 = in0 'and sample data line low SCK next high CS 'Disable the LTC2400 ADhi = (ADhi<<4)+((ADlo&$F000)>>12) debug ?ADhi 'Discard the lower eight bits goto Start 'and display (debug command). ShiftL Temp = ADlo.bit15 'This routine simply ADlo = ADlo<<1 'performs a 1 bit ADhi = ADhi<<1 'left shift on two ADhi.bit0 = Temp '16 bit variables return Figure 32. This BASIC Stamp Code is an Example of How Easy it is to Retrieve Data from the LTC2400 The listing in Figure 34 is a simple assembler routine for the LTC2400’s serial interface by setting the SS output the 68HC11 microcontroller. It uses PORT D, configuring low, sending a logic low to CS. It next waits in a loop for it for SPI data transfer between the controller and the a logic low on the data line, signifying end-of-conversion. LTC2400. Figure 33 shows the simple 3-wire SPI After the loop is satisfied, four SPI transfers are com- connection. pleted, retrieving the conversion. The main sequence ends by setting SS high. This places the LTC2400’s serial The code begins by declaring variables and allocating four interface in a high impedance state and initiates another memory locations to store the 32-bit conversion result. conversion. This is followed by initializing PORT D’s SPI configuration. The program then enters the main sequence. It activates 68HC11 7 SCK SCK (PD4) 6 LTC2400 SDO MISO (PD2) 5 CS SS (PD5) 2400 F33 Figure 33. Connecting the LTC2400 to a 68HC11 MCU Using the SPI Serial Interface ***************************************************** * This example program transfers the LTC2400's 32-bit output * * conversion result into four consecutive 8-bit memory locations. * ***************************************************** *68HC11 register definition PORTD EQU $1008 Port D data register * " – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD" DDRD EQU $1009 Port D data direction register SPSR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, – ,MODF; – , – , – , – " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC2400's 32 conversion result 31

LTC2400 TYPICAL APPLICATIONUS * DIN1 EQU $00 This memory location holds the LTC2400's bits 31 - 24 DIN2 EQU $01 This memory location holds the LTC2400's bits 23 - 16 DIN3 EQU $02 This memory location holds the LTC2400's bits 15 - 08 DIN4 EQU $03 This memory location holds the LTC2400's bits 07 - 00 * ********************** * Start GETDATA Routine * ********************** * ORG $C000 Program start location INIT1 LDS #$CFFF Top of C page RAM, beginning location of stack LDAA #$2F –,–,1,0;1,1,1,1 * –, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 –,–,1,1;1,0,0,0 STAA DDRD SS*, SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs *DDRD's bit 5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2 * (This assumes an E-Clock frequency of 4MHz. For higher E- * Clock frequencies, change the above value of $50 to a value * that ensures the SCK frequency is 2MHz or less.) GETDATA PSHX PSHY PSHA LDX #$0 The X register is used as a pointer to the memory locations * that hold the conversion data LDY #$1000 BCLR PORTD, Y %00100000 This sets the SS* output bit to a logic * low, selecting the LTC2400 TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer STAA SPDR This writes the byte in the SPI data register and starts * the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR's MSB * and is set to one at the end of an SPI transfer. The branch * will occur while SPIF is a zero. LDAA SPDR Load accumulator A with the current byte of LTC2400 data that was just received STAA 0,X Transfer the LTC2400's data to memory INX Increment the pointer CPX #DIN4+1 Has the last byte been transferred/exchanged? BNE TRFLP1 If the last byte has not been reached, then proceed to the * next byte for transfer/exchange BSET PORTD,Y %00100000 This sets the SS* output bit to a logic high, * de-selecting the LTC2400 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 34. This is an Example of 68HC11 Code That Captures the LTC2400’s Conversion Results Over the SPI Serial Interface Shown in Figure 33 32

LTC2400 TYPICAL APPLICATIONUS Thermocouple Applications This circuit produces a DC offset at the cold junction reference point, of 1mV to 15mV, which must be nulled out Figure 35 shows a thermocouple interface circuit that in software. This DC offset, resulting from the forward demonstrates the practicality of direct connection to the voltage of the diode, is variable from device to device and LTC2400 using even the lowest output thermocouples (in must be calibrated for each unit. this case, a type S thermocouple, with a full-scale output of 18mV). Since the temperature coefficient of the 1N4148 diode is not guaranteed, a trim should be provided to accommo- This topology is the least costly solution for thermocouple date a coefficient from 1.7mV/(cid:176) C to 2.3mV/(cid:176) C. Alterna- sensing. As shown, it is capable of resolving approxi- tively, a transistor can be used as a sensor with Omega mately 0.25(cid:176) C without averaging. Since the LTC2400 does Engineering thermocouple circuit board connectors that not exhibit any easily discernible quantization effects, are available with TO-92 transistor retainer clips, placing averaging can significantly extend the resolution for slow the transistor in physical contact with the cold junction. changing processes. The 1M resistor R shown is intended as an open-circuit In this circuit, a 1N4148 diode provides cold junction TC detection scheme, producing full scale at the input of the compensation by producing, at the positive terminal of the LTC2400. Note that this resistor contributes to the offset thermocouple, an approximation of the average Seebeck and must have low TC, as should the resistors R2 and R3. coefficient for a type S thermocouple over the temperature Since R1 provides forward bias for the diode, its tempera- range expected at the cold junction (0(cid:176) C to 40(cid:176) C). If the ture coefficient is not as critical. operating range is less, the coefficient can be adjusted to produce a better match for the range anticipated. This The circuit in Figure 35 uses only 12% of the LTC2400’s basic circuit can be used with other thermocouples by input range and is able to accommodate the full-scale changing the divide ratio to suit the Seebeck coefficient of output of all thermocouple types. The commonly used the type chosen (see table). 5V 0.1µF 1 COLD JUNCTION RTC R1 ISOTHERMAL 1M 43.2k 2 VCC 5 VREF CS – Cu 3 6 VIN LTC2400 SDO 7 THERMOCOUPLE SCK + Cu GND FO 1N4148 4 8 –2mV/°C 10k R2* 5V 60Hz 50Hz –SB R3* 100Ω *25ppm, 1% TOLERANCE SINGLE POINT GROUND THERMOCOUPLE SEEBECK TYPE COEFFICIENT* R2 J 50.2µV/°C 3.83k K 39.2µV/°C 4.99k S 6.15µV/°C 32.4k 2400 F35 *20°C ≤ TA ≤ 50°C Figure 35. Diode Cold Junction Compensation 33

LTC2400 TYPICAL APPLICATIONUS thermocouple with the highest output is type E, at about Figure 36 shows an inexpensive circuit with removal of the 70mV. This circuit does not provide curvature correction DC offset. The output of the LT®1077 is attenuated in order for the Seebeck effect at the cold junction. If the applica- to produce the required coefficient, as well as reduce the tion requires very high accuracy, the temperature of the noise and offset error contribution. If used with a ther- cold junction should be determined via a separate input mistor, this circuit can be modified to produce curvature to the A/D, using an RTD for example. The cold junction correction. The removal of the offset associated with diode compensation can be performed by implementing the forward voltage, or the 273(cid:176) K overhead on some mono- thermocouple’s NBS polynominal curvature correction lithic temperature sensors, simplifies the use of substan- in software. (The input to the LTC2400 can be multi- tial gain after the thermocouple. Chopper amplifiers such plexed using the LTC1391 with little degradation.) If a as the LTC1050 can extend the noise floor of the LTC2400 separate temperature sensor is used to monitor the cold by as much as a factor of 10 to 20. The use of a gain of 20 junction, the connection from the thermocouple to the in front of the LTC2400 can extend the resolution of a LTC2400 can be direct. The junctions formed at the point thermocouple application to 0.02(cid:176) C or better. where the thermocouple leads meet different metal (e.g., If absolute accuracy is not important, the use of a low copper traces) must be equal in temperature, and the noise bipolar amplifier, such as the LT1028, can extend cold junction sensor must be mounted at that point. Any the resolution an additional order of magnitude. temperature differential between the leads, or any differ- ential between the leads and the temperature sensor will Note that achieving high accuracy in the circuit in Figure 36 introduce an error into the reading. requires a calibration sequence for circuit offset and gain correction. 5V V+ 0.1µF R2 R LM334 174k* SO-8 R1 V– 5V 1 12m26VΩ/°*C 3 + 7 6 R1k5 6.1µV/°C – + 3 2 VREFVCC CS 56 LT1077 VIN LTC2400 SDO 2 7 – SCK 4 GND FO R3 R6 SELECT R3 FOR 4 8 1k* R4 6.19Ω THERMOCOUPLE TYPE 10k* S: 6.19Ω 10k K: 39.2Ω 5V J: 49.9Ω 60Hz 50Hz E: 61.9Ω 2400 F35 *RECOMMENDED 0.1%, – 5ppm IRC AFD SERIES CHIP RESISTORS Figure 36. Inexpensive Amplifier Improves Cold Junction Compensation 34

LTC2400 TYPICAL APPLICATIONUS A simpler, and potentially less expensive solution is the Simple Platinum RTD Interface use of the LT1025 as shown in Figure 37. If high temperature resolution is required over a more The LT1025 incorporates the functions of temperature limited range, Figure 38 can resolve approximately sensor, a precision divider chain required to produce the 0.01(cid:176) C without additional amplification. The resistance of appropriate correction for five different types of thermo- a platinum RTD changes by approximately 0.31W /(cid:176) C at couples, as well as curvature correction. The LT1025 must T = 25(cid:176) C. The 100W to 300W source impedance of this A be located at the cold junction. The use of a thermal mass circuit does not compromise the stability, accuracy or around the cold junction, as well as protection from air noise level of the LTC2400. currents, is advisable. 5V 0.1µF 2 1 VIN 2 VCC 5 LT1025 6 – + 3 VREF CS 6 S VIN LTC2400 SDO GND R– SCK 7 4 5 GND FO TYPE 4 8 S 10k 5V 60Hz 50Hz 2400 F36 Figure 37. The LT1025 Complete Cold Junction Solution 5V 5V 0.1µF 1 R1* 12.1k 2 VCC 5 VREF CS F S 3 6 VIN LTC2400 SDO 7 SCK GND FO Pt RTD 100Ω 4 8 10k 5V 60Hz 50Hz 2400 F37 *VISHAY S102 OR EQUIVALENT Figure 38. Simplest Platinum RTD Interface 35

LTC2400 TYPICAL APPLICATIONUS The 12.1k resistor should be a precision resistor such as or the resistors must exhibit very low temperature coeffi- a Vishay S102 series, or must be temperature stabilized. cients. Precision resistor networks are always a good The excitation current is low enough for most sensors that alternative and are available from Vishay or Caddock. the self-heating effect is near the noise floor of the LTC2400. Half-Bridge Strain Gauge The use of a bipolar amplifier configuration shown in Figure 39 offers a potential resolution of 0.001(cid:176) C The circuit in Figure 40 is a ratiometric half-bridge circuit with direct connection to the LTC2400. The use of two In order to achieve these results, the following effects thin-film strain gauges in a half-bridge configuration can must be considered. Variation in the self-heating of the produce 2mV/V output and approximately 12-bit resolu- RTD element due to air currents is the most difficult tion. The 175W source impedance seen by the LTC2400 challenge. If the RTD is mounted in a sealed glass enclo- does not compromise operation. sure and painted black, the LTC2400 can detect the arrival of a person in the room. This is also true of infrared The optional resistor shown can be up to 5k and will thermocouple sensors (thermopiles) that can also be used provide surge and transient protection for the LTC2400 directly with the LTC2400. A variation of this circuit with if the strain gauges are located some distance from the two RTDs can detect small differential temperatures in LTC2400, or if the strain bearing member is not well order to determine heat inflow or outflow from a process. grounded and may be subject to ESD discharge. Thin- In order for this circuit to be practical, the ambient tem- film strain elements form coupling capacitance to the perature of the amplifier and resistors must be controlled strain bearing member to which they are bonded. If noise VREF R1* 9.09k 5V 0.1µF R2* 5V 9.09k F S 3 + 350Ω 1 2 –LT1028 6 1k TLOTC2400 ELSETMREANINT OPTR5IOk1NAL 3 2 VREFVCC CS 56 VIN LTC2400 SDO 0.1µF 7 Pt RTD 300Ω –5V SCK 100Ω 350Ω GND FO R3* STRAIN 4 8 9.09k ELEMENT 10k R4** 2400 F38 5V 100Ω 60Hz 50Hz *MUST BE 5ppm/°C OR BETTER, AN ARRAY IS RECOMMENDED **MUST BE VERY STABLE <5ppm/°C 2400 F39 Figure 39. Extremely High Resolution RTD Interface Figure 40. Half-Bridge Connection for Strain Gauges 36

LTC2400 TYPICAL APPLICATIONUS pick-up from the strain bearing member is largely 60Hz, dividers, but they are too low to be produced directly by a the LTC2400 will reject it. If serious high frequency noise quartz oscillator. Quartz stability is generally not required, is present on the strain bearing member, it may be as the notches are wide enough that an oscillator with necessary to add buffering in order to allow the use of 0.1% to 1% stability is adequate. noise suppression. In instances where digital generation of these frequencies is not practical due to power, space or cost limitations, and Stable Relaxation Oscillator notches in the range of 4Hz to 120Hz are required, the for External Clock circuit in Figure 41 can be used. Applications that require that the notch produced by the The frequency can be varied over this range by changing LTC2400’s sinc4 filter be placed at some frequency other capacitor C1 over the range of 4000pf to 30pF. For the than 50Hz or 60Hz require an external clock. The fre- resistor values shown, the output frequency in kHz is quency required is 2560· the required notch frequency. approximately 9.5e-6 divided by C1 (C1 in pF). The circuit Simple relaxation oscillators built from logic gates with produces a controlled amount of hysteresis dependent hysteresis such as the 74HC14 are not stable with tem- only on resistor matching and self biases itself around the perature, supply voltage changes, or from device to input threshold. All gates must be in the same package, device. and no loads should be driven from the outputs driving If for example, a remote weigh scale application requires feedback paths. If there are spare gates, they can be used rejection of a resonance at 11Hz, the frequency must be set in parallel with gates B and D for improved drive of to 28.16kHz. In many instances, these frequencies could feedback paths. be produced digitally with a phase lock loop or with digital R1 100k HC04 A B C D fOUT (kHz) = 9.C51 • ( p1F0)–6 C2 C3 15pF C1 15pF R2 R3 47k 47k 2400 F40 C1 MAY VARY FROM 30pF TO 4000pF STABLE OPERATION AT HIGHER FREQUENCIES REQUIRES VALUES OF RESISTOR TO BE REDUCED Figure 41. Stable Relaxation Low Power Oscillator for Notch Tuning 37

LTC2400 TYPICAL APPLICATIONUS The performance of the LTC2400 can be verified using the which graphically captures the conversion results. It can demonstration board DC228, see Figure 42 for the sche- be used to determine noise performance, stability, and matic. This circuit uses the computer’s serial port to with an external source, linearity. As exemplified in the generate power and the SPI digital signals necessary for schematic, the LTC2400 is extremely easy to use. This starting a conversion and reading the result. It includes a demonstration board and associated software is available Labview application software program (see Figure 43) by contacting Linear Technology. D1 BAV74LT1 U2 J6 5V LT1236ACS8-5 R3 EXT V+ J2 6 OUT IN 2 100W 8V TO 15V VREFOUT GND C6 + C5 4 22m F 100m F 16V EXTERNAL JP2 ONBOARD JP1 REF 1 2 3 REF 50Hz 1 2 3 60Hz C4 J1 0.1m F VREFIN C1 U1 10m F LTC2400 U3-2 U3-1 J5 12 VCC FO 87 4 74H3C142 741HC14 5R11k SCLKDTR 1 DB9 C2 VREF SCK 10m F 3 VIN SDO 6 62 4 5 GND CS U3-4 U3-3 7 J3 74HC14 74HC14 3 INPUT C3 9 8 5 6 DOUTCTS 8 10m F 4 J4 9 GROUND U3-6 U3-5 74HC14 74HC14 R2 5 NOTES: UNLESS OTHERWISE SPECIFIED INSTALL SHUNTS ON PIN 2 AND 3 OF JP1 AND JP2 12 1310 11 51k CSRTS 2400 F42 Figure 42. 24-Bit A/D Demo Board Schematic Figure 43. Display Graphic 38

LTC2400 PACKAGE I U FORW ATIOU Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 0.150 – 0.157** (5.791 – 6.197) (3.810 – 3.988) 1 2 3 4 0.010 – 0.020 · 45(cid:176) 0.053 – 0.069 (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) 0.016 – 0.050 0.014 – 0.019 0.050 0.406 – 1.270 (0.355 – 0.483) (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE SO8 0996 PCB LAYOUT AU D FILW Component Side Silkscreen Solder Side Silkscreen Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 39 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2400 PCB LAYOUT AU D FILW Component Side Component Side Solder Mask Component Side Paste Mask Solder Side Solder Side Solder Mask Solder Side Paste Mask RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/(cid:176) C Drift, 0.05% Max LT1025 Micropower Therocouple Cold Junction Compensator LTC1043 Dual Precision Instrumentation Switched Capacito Building Blockr Precise Charge, Balanced Switching, Low Power LTC1050 Precision Chopper Stabilized Op Amp No External Components 5m V Offset, 1.6m V Noise P-P LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/(cid:176) C Drift LT1460 Micropower Series Reference 0.075% Max, 10ppm/(cid:176) C Max Drift, 2.5V, 5V and 10V Versions LTC2401/LTC2402 1-/2-Channel 24-Bits ADCs 3m V Noise, 10-Pin MSOP Package, Ground Sensing LTC2404/LTC2408 4-/8-Channel 24-Bit ADCs Same Performance as LTC2400 LTC2420 20-Bit Micropower ADC 6m V Noise, Pin-Compatible with LTC2400 40 Linear Technology Corporation 2400fa LT/TP 0300 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)4 32-1900 l FAX: (408) 434-0507 l w ww.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 1998

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2400CS8#PBF LTC2400IS8 LTC2400CS8#TR LTC2400IS8#TR LTC2400CS8#TRPBF LTC2400IS8#TRPBF LTC2400CS8 LTC2400IS8#PBF