LT3023 Dual 100mA, Low Dropout, Low Noise, Micropower Regulator FEATURES DESCRIPTION n Low Noise: 20μV (10Hz to 100kHz) The LT®3023 is a dual, micropower, low noise, low drop- RMS n Low Quiescent Current: 20μA/Channel out regulator. With an external 0.01μF bypass capacitor, n Wide Input Voltage Range: 1.8V to 20V output noise drops to 20μV over a 10Hz to 100kHz RMS n Output Current: 100mA/Channel bandwidth. Designed for use in battery-powered systems, n Very Low Shutdown Current: <0.1μA the low 20μA quiescent current per channel makes it an n Low Dropout Voltage: 300mV at 100mA ideal choice. In shutdown, quiescent current drops to less n Adjustable Output from 1.22V to 20V than 0.1μA. Shutdown control is independent for each n Stable with 1μF Output Capacitor channel, allowing for fl exibility in power management. The n Stable with Aluminum, Tantalum or device is capable of operating over an input voltage from Ceramic Capacitors 1.8V to 20V, and can supply 100mA of output current from n Reverse Battery Protected each channel with a dropout voltage of 300mV. Quiescent n No Reverse Current current is well controlled in dropout. n No Protection Diodes Needed The LT3023 regulator is stable with output capacitors as n Overcurrent and Overtemperature Protected low as 1μF. Small ceramic capacitors can be used without n Thermally Enhanced 10-Lead MSOP and DFN the series resistance required by other regulators. Packages Internal protection circuitry includes reverse battery APPLICATIONS protection, current limiting, thermal limiting and reverse current protection. The device is available as an adjust- n Cellular Phones able device with a 1.22V reference voltage. The LT3023 n Pagers regulator is available in the thermally enhanced 10-lead n Battery-Powered Systems MSOP and DFN packages. n Frequency Synthesizers L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other n Wireless Modems trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3V/2.5V Low Noise Regulators 10Hz to 100kHz Output Noise 3.3V AT100mA VIN IN OUT1 20μVRMS NOISE 3.7V TO 1μF SHDN1 0.01μF 10μF 20V 422k SHDN2 BYP1 ADJ1 LT3023 249k 100μVV/ODUIVT 20μVRMS 2.5V AT100mA OUT2 20μVRMS NOISE 0.01μF 261k 10μF BYP2 ADJ2 3023 TA01b GND 249k 3023 TA01 3023fa 1

LT3023 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage .........................................................±20V Output Short-Circut Duration ...........................Indefi nite OUT1, OUT2 Pin Voltage .........................................±20V Operating Junction Temperature Range Input to Output Differential Voltage .........................±20V (Note 2) .............................................–40°C to 125°C ADJ1, ADJ2 Pin Voltage ............................................±7V Storage Temperature Range ...................–65°C to 150°C BYP1, BYP2 Pin Voltage ........................................±0.6V Lead Temperature (Soldering, 10 sec) ..................300°C SHDN1, SHDN2 Pin Voltage ...................................±20V (MSE package only) PIN CONFIGURATION TOP VIEW TOP VIEW BYP2 1 10 OUT2 BYP2 1 10 OUT2 ADJ2 2 9 SHDN2 ADJ2 2 9 SHDN2 GND 3 11 8 IN GND 3 11 8 IN ADJ1 4 7 SHDN1 ADJ1 4 7 SHDN1 BYP1 5 6 OUT1 BYP1 5 6 OUT1 MSE PACKAGE 10-LEAD PLASTIC MSOP 10-LEAD (3mDmD (cid:115)P A3CmKmAG) EPLASTIC DFN EXPOSEDT PJMAADX ( =P I1N5 01°1C) ,I Sθ JGA N=D 4, 0M°CU/SWT, θBJEC S=O 1L0D°ECR/WED TO PCB TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3023EDD#PBF LT3023EDD#TRPBF LAJA 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3023IDD#PBF LT3023IDD#TRPBF LAJA 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3023EMSE#PBF LT3023EMSE#TRPBF LTAHZ 10-Lead Plastic MSOP –40°C to 125°C LT3023IMSE#PBF LT3023IMSE#TRPBF LTAHZ 10-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3023EDD LT3023EDD#TR LAJA 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3023IDD LT3023IDD#TR LAJA 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3023EMSE LT3023EMSE#TR LTAHZ 10-Lead Plastic MSOP –40°C to 125°C LT3023IMSE LT3023IMSE#TR LTAHZ 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 2) A PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage I = 100mA l 1.8 2.3 V LOAD (Notes 3, 11) ADJ1, ADJ2 Pin Voltage V = 2V, I = 1mA 1.205 1.220 1.235 V IN LOAD (Note 3, 4) 2.3V < V < 20V, 1mA < I < 100mA l 1.190 1.220 1.250 V IN LOAD 3023fa 2

LT3023 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 2) A PARAMETER CONDITIONS MIN TYP MAX UNITS Line Regulation (Note 3) ΔV = 2V to 20V, I = 1mA l 1 10 mV IN LOAD Load Regulation (Note 3) V = 2.3V, ΔI = 1mA to 100mA 1 12 mV IN LOAD V = 2.3V, ΔI = 1mA to 100mA l 25 mV IN LOAD Dropout Voltage I = 1mA 0.10 0.15 V LOAD V = V (Notes 5, 6, 11) I = 1mA l 0.19 V IN OUT(NOMINAL) LOAD I = 10mA 0.17 0.22 V LOAD I = 10mA l 0.29 V LOAD I = 50mA 0.24 0.28 V LOAD I = 50mA l 0.38 V LOAD I = 100mA 0.30 0.35 V LOAD I = 100mA l 0.45 V LOAD GND Pin Current (Per Channel) I = 0mA l 20 45 μA LOAD V = V (Notes 5, 7) I = 1mA l 55 100 μA IN OUT(NOMINAL) LOAD I = 10mA l 230 400 μA LOAD I = 50mA l 1 2 mA LOAD I = 100mA l 2.2 4 mA LOAD Output Voltage Noise C = 10μF, C = 0.01μF, I = 100mA, BW = 10Hz to 100kHz 20 μV OUT BYP LOAD RMS ADJ1/ADJ2 Pin Bias Current (Notes 3, 8) 30 100 nA Shutdown Threshold V = Off to On l 0.8 1.4 V OUT V = On to Off l 0.25 0.65 V OUT SHDN1/SHDN2 Pin Current V = 0V l 0 0.5 μA SHDN (Note 9) V = 20V l 1 3 μA SHDN Quiescent Current in Shutdown V = 6V, V = 0V (Both SHDN Pins) 0.01 0.1 μA IN SHDN Ripple Rejection (Note 3) V = 2.72V (Avg), V = 0.5V , f = 120Hz, 55 65 dB IN RIPPLE P-P RIPPLE I = 50mA LOAD Current Limit V = 7V, V = 0V 200 mA IN OUT V = 2.3V, ΔV = –5% l 110 mA IN OUT Input Reverse Leakage Current V = –20V, V = 0V l 1 mA IN OUT Reverse Output Current (Notes 3,10) V = 1.22V, V < 1.22V 5 10 μA OUT IN Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Dropout voltage is the minimum input to output voltage differential may cause permanent damage to the device. Exposure to any Absolute needed to maintain regulation at a specifi ed output current. In dropout, the Maximum Rating condition for extended periods may affect device output voltage will be equal to: V – V . IN DROPOUT reliability and lifetime. Note 7: GND pin current is tested with V = 2.44V and a current source IN Note 2: The LT3023 is tested and specifi ed under pulse load conditions load. This means the device is tested while operating in its dropout region such that T ≅ T . The LT3023E is 100% tested at T = 25°C. Performance or at the minimum input voltage specifi cation. This is the worst-case GND J A A at –40°C and 125°C is assured by design, characterization and correlation pin current. The GND pin current will decrease slightly at higher input with statistical process controls. The LT3023I is guaranteed over the full voltages. –40°C to 125°C operating junction temperature range. Note 8: ADJ1 and ADJ2 pin bias current fl ows into the pin. Note 3: The LT3023 is tested and specifi ed for these conditions with the Note 9: SHDN1 and SHDN2 pin current fl ows into the pin. ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin. Note 10: Reverse output current is tested with the IN pin grounded and the Note 4: Operating conditions are limited by maximum junction OUT pin forced to the rated output voltage. This current fl ows into the OUT temperature. The regulated output voltage specifi cation will not apply pin and out the GND pin. for all possible combinations of input voltage and output current. When Note 11: For the LT3023 dropout voltage will be limited by the minimum operating at maximum input voltage, the output current range must be input voltage specifi cation under some output voltage/load conditions. limited. When operating at maximum output current, the input voltage See the curve of Minimum Input Voltage in the Typical Performance range must be limited. Characteristics. Note 5: To satisfy requirements for minimum input voltage, the LT3023 is tested and specifi ed for these conditions with an external resistor divider (two 250k resistors) for an output voltage of 2.44V. The external resistor divider will add a 5μA DC load on the output. 3023fa 3

LT3023 TYPICAL PERFORMANCE CHARACTERISTICS Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage 500 500 500 = TEST POINTS 450 450 450 400 400 400 V) V) V) AGE (m 335000 TJ = 125°C AGE (m 335000 TJ ≤ 125°C AGE (m335000 IL = 100mA OLT 250 OLT 250 TJ ≤ 25°C OLT250 UT V 200 TJ = 25°C UT V 200 UT V200 IL = 50mA O O O P P P RO 150 RO 150 RO150 IL = 10mA D D D 100 100 100 IL = 1mA 50 50 50 0 0 0 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 –50 –25 0 25 50 75 100 125 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) TEMPERATURE (°C) 3023 G01 3023 G02 3023 G03 Quiescent Current ADJ1 or ADJ2 Pin Voltage Quiescent Current 40 1.240 30 VIN = 6V IL = 1mA TJ = 25°C 35 RL = 250k 1.235 RL = 250k A) 30 IL = 5μA 1.230 A) 25 IL = 5μA ENT (μ 25 GE (V)1.225 ENT (μ 20 VSHDN = VIN UIESCENT CURR 211050 VSHDN = VIN ADJ PIN VOLTA111...222211050 UIESCENT CURR 1150 Q Q 5 5 1.205 VSHDN = 0V VSHDN = 0V 0 1.200 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20 TEMPERATURE (°C) TEMPERATURE (°C) INPUT VOLTAGE (V) 3023 G03 3023 G05 3023 G06 SHDN1 or SHDN2 Pin Threshold GND Pin Current GND Pin Current vs I (On-to-Off) LOAD 2.50 2.50 1.0 2.25 T*FJ O=R 2 V5O°CUT = 1.22V 2.25 VIN = VOUT(NOMINAL) + 1V 0.9 IL = 1mA mA)21..0705 RILL = = 1 1020.m2ΩA* mA)21..0705 D (V) 00..87 T ( T ( OL N1.50 N1.50 H 0.6 E E S R R E CUR1.25 RL = 24.4Ω CUR1.25 THR 0.5 PIN 1.00 IL = 50mA* PIN 1.00 PIN 0.4 ND 0.75 ND 0.75 DN 0.3 G G H 0.50 RL = 1.22k RL = 122Ω 0.50 S 0.2 0.25 IL = 1mA* IL = 10mA* 0.25 0.1 0 0 0 0 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100 –50 –25 0 25 50 75 100 125 INPUT VOLTAGE (V) OUTPUT CURRENT (mA) TEMPERATURE (°C) 3023 G07 3023 G08 3023 G09 3023fa 4

LT3023 TYPICAL PERFORMANCE CHARACTERISTICS SHDN1 or SHDN2 Pin Threshold SHDN1 or SHDN2 Pin Input SHDN1 or SHDN2 Pin Input (Off-to-On) Current Current 1.0 1.0 1.4 0.9 0.9 VSHDN = 20V 1.2 D (V) 00..87 IL = 100mA NT (μA) 00..87 NT (μA) 1.0 OL RE RE ESH 0.6 IL = 1mA CUR 0.6 CUR 0.8 HR 0.5 UT 0.5 UT HDN PIN T 00..43 N PIN INP 00..43 N PIN INP 00..64 S 0.2 HD 0.2 HD S S 0.2 0.1 0.1 0 0 0 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 8 9 10 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) SHDN PIN VOLTAGE (V) TEMPERATURE (°C) 3023 G10 3023 G11 3023 G12 ADJ1 or ADJ2 Pin Bias Current Current Limit Current Limit 100 350 350 90 VOUT = 0V VIN = 7V A) 80 mA)300 TJ = 25°C 300 VOUT = 0V J PIN BIAS CURRENT (n 7654300000 RT-CIRCUIT CURRENT (221150500000 CURRENT LIMIT (mA)221150500000 D O A 20 H S 50 50 10 0 0 0 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C) 3023 G13 3023 G14 3023 G15 Reverse Output Current Reverse Output Current Input Ripple Rejection 100 18 80 TA = 25°C VIN = 0V 90 VIN = 0V VOUT = VADJ = 1.22V 70 μA) 80 VOUT = VADJ μA) 15 PUT CURRENT ( 765000 CINUTROR OEUNTTP FULTO WPISN PUT CURRENT ( 129 EJECTION (dB) 654000 COUT = 10μF T T R SE OU 4300 SE OU 6 PPLE 30 ER ER RI 20 V 20 V RE 10 RE 3 10 IVLI N= =1 020.3mVA + 50mVRMS RIPPLE COUT = 1μF CBYP = 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 –50 –25 0 25 50 75 100 125 0.01 0.1 1 10 100 1000 OUTPUT VOLTAGE (V) TEMPERATURE (°C) FREQUENCY (kHz) 3023 G16 3023 G17 3023 G18 3023fa 5

LT3023 TYPICAL PERFORMANCE CHARACTERISTICS Input Ripple Rejection Input Ripple Rejection Channel-to-Channel Isolation 80 80 70 CBYP = 0.01μF 70 B) 60 B) 60 20m VVO/DUTIV1 CTION (d 50 CBYP = 100pF CBYP = 1000pF CTION (d 50 REJE 40 REJE 40 20m VVO/DUTIV2 PLE 30 PLE 30 P P RI 20 RI 20 VIN = VOUT (NOMINAL) + 100 IVCLIO N=U =T1 0=20 .13m0VAμ +F 50mVRMS RIPPLE 100 1AILVT = +f 5 =00 .1m52VA0PH-Pz RIPPLE CCOBYUPT11,, CCBOYUPT22 == 01.00μ15Fμ0Fμs/DIV 3023 G21a 0.01 0.1 1 10 100 1000 –50 –25 0 25 50 75 100 125 ΔIL1 = 10mA to 100mA FREQUENCY (kHz) TEMPERATURE (°C) ΔIL2 = 10mA to 100mA VIN = 6V, VOUT1 = VOUT2 = 5V 3023 G19 3023 G20 Channel-to-Channel Isolation Minimum Input Voltage Load Regulation 100 2.5 0 ILOAD = 100mA PER CHANNEL B) 90 –1 d TION ( 80 E (V) 2.0 IL = 100mA V) –2 A 70 G m –3 EL-TO-CHANNEL ISOL 65430000 NIMUM INPUT VOLTA 11..50 IL = 50mA LOAD REGULATION ( ––––4567 NN 20 MI 0.5 –8 A H 10 –9 C ΔIL = 1mA TO 100mA 0 0 –10 0.01 0.1 1 10 100 1000 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C) 3023 G21b 3023 G22 3023 G23 RMS Output Noise vs Output Noise Spectral Density Output Noise Spectral Density Bypass Capacitor 10 10 160 Hz) COUT = 10μF Hz) COUT = 10μF COUT = 10μF OUTPUT NOISE SPECTRAL DENSITY (μV/√00.0.111 CILB =Y P1 0=V0 O0mUVTAO SUET T= VFOADRJ 5V OUTPUT NOISE SPECTRAL DENSITY (μV/√ 00.0.111 IVVLO O=UUC T1TB 0=YS0VPEm AT=DA F0JO.0R1 μ5FV CCBYBPY P= = 1 100000ppFF OUTPUT NOISE (μV)RMS111420864200000000 VOUT =VVOAUDTJ SET FORIfL =5 = V1 100H0zm TAO 100kHz 0.01 0.1 1 10 100 0.01 0.1 1 10 100 10 100 1k 10k FREQUENCY (kHz) FREQUENCY (kHz) CBYP (pF) 3023 G24 3023 G25 3023 G26 3023fa 6

LT3023 TYPICAL PERFORMANCE CHARACTERISTICS RMS Output Noise vs 10Hz to 100kHz Output Noise 10Hz to 100kHz Output Noise Load Current (10Hz to 100kHz) C = 0 C = 100pF BYP BYP 160 COUT = 10μF 140 CBYP = 0μF CBYP = 0.01μF )MS120 VOUT SET FOR 5V E (μVR100 100μ VV/ODUIVT 100μ VV/ODUIVT OIS 80 N UT 60 VOUT =VADJ P T U O 40 VOUT SET FOR 5V 1ms/DIV 3023 G28 1ms/DIV 3023 G29 20 0 VOUT =VADJ CILO =U T1 0=0 1m0AμF CILO =U T1 0=0 1m0AμF 0.01 0.1 1 10 100 VOUT SET FOR 5V OUT VOUT SET FOR 5V OUT LOAD CURRENT (mA) 3023 G27 10Hz to 100kHz Output Noise 10Hz to 100kHz Output Noise C = 1000pF C = 0.01μF BYP BYP VOUT VOUT 100μV/DIV 100μV/DIV 1ms/DIV 3023 G30 1ms/DIV 3023 G31 COUT = 10μF COUT = 10μF IL = 100mA IL = 100mA VOUT SET FOR 5V OUT VOUT SET FOR 5V OUT Transient Response Transient Response C = 0 C = 0.01μF BYP BYP 0.2 0.04 E E LTAGN (V) 0.1 LTAGN (V) 0.02 OUTPUT VODEVIATIO––00..012 VCIINN == 61V0μF OUTPUT VODEVIATIO––00..00024 VCIINN == 61V0μF COUT = 10μF COUT = 10μF T VOUTSET FOR 5V OUT T VOUTSET FOR 5V OUT EN 100 EN 100 R R CURmA) 50 CURmA) 50 AD ( 0 AD ( 0 O O L L 0 400 800 1200 1600 2000 0 20 40 60 80 100120140160180 200 TIME (μs) TIME (μs) 3023 G32 3023 G33 3023fa 7

LT3023 PIN FUNCTIONS GND (Pin 3): Ground. SHDN1/SHDN2 (Pins 7/9): Shutdown. The SHDN1/SHDN2 pins are used to put the corresponding channel of the ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to LT3023 regulator into a low power shutdown state. The the error amplifi ers. These pins are internally clamped to output will be off when the pin is pulled low. The SHDN1/ ±7V. They have a bias current of 30nA which fl ows into the SHDN2 pins can be driven either by 5V logic or open-col- pin (see curve of ADJ1/ADJ2 Pin Bias Current vs Tempera- lector logic with pull-up resistors. The pull-up resistors ture in the Typical Performance Characteristics section). are required to supply the pull-up current of the open- The ADJ1 and ADJ2 pin voltage is 1.22V referenced to collector gates, normally several microamperes, and the ground and the output voltage range is 1.22V to 20V. SHDN1/SHDN2 pin current, typically 1μA. If unused, the BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are pin must be connected to V . The device will not function IN used to bypass the reference of the LT3023 regulator to if the SHDN1/SHDN2 pins are not connected. achieve low noise performance from the regulator. The IN (Pin 8): Input. Power is supplied to the device through BYP1/BYP2 pins are clamped internally to ±0.6V (one V ) BE the IN pin. A bypass capacitor is required on this pin if from ground. A small capacitor from the corresponding the device is more than six inches away from the main output to this pin will bypass the reference to lower the input fi lter capacitor. In general, the output impedance of output voltage noise. A maximum value of 0.01μF can a battery rises with frequency, so it is advisable to include be used for reducing output voltage noise to a typical a bypass capacitor in battery-powered circuits. A bypass 20μV over a 10Hz to 100kHz bandwidth. If not used, RMS capacitor in the range of 1μF to 10μF is suffi cient. The this pin must be left unconnected. LT3023 regulator is designed to withstand reverse volt- OUT1/OUT2 (Pins 6/10): Output. The outputs supply power ages on the IN pin with respect to ground and the OUT to the loads. A minimum output capacitor of 1μF is required pin. In the case of a reverse input, which can happen if to prevent oscillations. Larger output capacitors will be a battery is plugged in backwards, the device will act as required for applications with large transient loads to limit if there is a diode in series with its input. There will be peak voltage transients. See the Applications Information no reverse current fl ow into the regulator and no reverse section for more information on output capacitance and voltage will appear at the load. The device will protect both reverse output characteristics. itself and the load. Exposed Pad (Pin 11): Ground. This pin must be soldered to the PCB and electrically connected to ground. 3023fa 8

LT3023 APPLICATIONS INFORMATION The LT3023 is a dual 100mA low dropout regulator with mis iccaroppabolwe eorf q suuiepspclyeinntg c 1u0rr0emntA a npder s chhuatdnonweln a.t T ah ed rdoepvoicuet VIN IN OLTU3T012/O3UT2 R2+ VOUT VOUT=1.22V⎛⎝⎜1+RR21⎞⎠⎟+(IADJ)(R2) voltage of 300mV. Output voltage noise can be lowered VADJ=1.22V ADJ1/ADJ2 to 20μV over a 10Hz to 100kHz bandwidth with the GND IADJ=30nA AT 25°C RMS R1 OUTPUT RANGE = 1.22V TO 20V addition of a 0.01μF reference bypass capacitor. Addition- 3023 F01 ally, the reference bypass capacitor will improve transient Figure 1. Adjustable Operation response of the regulator, lowering the settling time for transient load conditions. The low operating quiescent The device is tested and specifi ed with the ADJ1/ADJ2 current (20μA per channel) drops to less than 1μA in pin tied to the corresponding OUT1/OUT2 pin for an out- shutdown. In addition to the low quiescent current, the put voltage of 1.22V. Specifi cations for output voltages LT3023 regulator incorporates several protection features greater than 1.22V will be proportional to the ratio of the which make it ideal for use in battery-powered systems. desired output voltage to 1.22V: V /1.22V. For example, OUT The device is protected against both reverse input and load regulation for an output current change of 1mA to reverse output voltages. In battery backup applications 100mA is –1mV typical at V = 1.22V. At V = 12V, OUT OUT where the output can be held up by a backup battery when load regulation is: the input is pulled to ground, the LT3023 acts like it has a (12V/1.22V)(–1mV) = –9.8mV diode in series with its output and prevents reverse current fl ow. Additionally, in dual supply applications where the Bypass Capacitance and Low Noise Performance regulator load isreturned to a negative supply, the output can be pulled below ground by as much as 20V and still The LT3023 regulator may be used with the addition of a allow the device to start and operate. bypass capacitor from V to the corresponding BYP1/ OUT BYP2 pin to lower output voltage noise. A good quality Adjustable Operation low leakage capacitor is recommended. This capacitor will bypass the reference of the regulator, providing a The LT3023 has an output voltage range of 1.22V to 20V. low frequency noise pole. The noise pole provided by this The output voltage is set by the ratio of two external resis- bypass capacitor will lower the output voltage noise to tors as shown in Figure 1. The device servos the output as low as 20μV with the addition of a 0.01μF bypass to maintain the corresponding ADJ1/ADJ2 pin voltage RMS capacitor. Using a bypass capacitor has the added benefi t at 1.22V referenced to ground. The current in R1 is then of improving transient response. With no bypass capacitor equal to 1.22V/R1 and the current in R2 is the current in and a 10μF output capacitor, a 10mA to 100mA load step R1 plus the ADJ1/ADJ2 pin bias current. The ADJ1/ADJ2 will settle to within 1% of its fi nal value in less than 100μs. pin bias current, 30nA at 25°C, fl ows through R2 into the With the addition of a 0.01μF bypass capacitor, the output ADJ1/ADJ2 pin. The output voltage can be calculated us- will stay within 1% for a 10mA to 100mA load step (see ing the formula in Figure 1. The value of R1 should be no Transient Reponse in Typical Performance Characteristics greater than 250k to minimize errors in the output voltage section). However, regulator start-up time is proportional caused by the ADJ1/ADJ2 pin bias current. Note that in to the size of the bypass capacitor, slowing to 15ms with shutdown the output is turned off and the divider current will a 0.01μF bypass capacitor and 10μF output capacitor. be zero. Curves of ADJ1/ADJ2 Pin Voltage vs Temperature and ADJ1/ADJ2 Pin Bias Current vs Temperature appear in the Typical Performance Characteristics. 3023fa 9

LT3023 APPLICATIONS INFORMATION Output Capacitance and Transient Response and temperature coeffi cients as shown in Figures 3 and 4. When used with a 5V regulator, a 16V 10μF Y5V capacitor The LT3023 regulator is designed to be stable with a can exhibit an effective value as low as 1μF to 2μF for the wide range of output capacitors. The ESR of the out- DC bias voltage applied and over the operating tempera- put capacitor affects stability, most notably with small ture range. The X5R and X7R dielectrics result in more capacitors. A minimum output capacitor of 1μF with an stable characteristics and are more suitable for use as the ESR of 3Ω or less is recommended to prevent oscilla- output capacitor. The X7R type has better stability across tions. The LT3023 is a micropower device and output temperature, while the X5R is less expensive and is avail- transient response will be a function of output capacitance. able in higher values. Care still must be exercised when Larger values of output capacitance decrease the peak using X5R and X7R capacitors; the X5R and X7R codes deviations and provide improved transient response for only specify operating temperature range and maximum larger load current changes. Bypass capacitors, used to capacitance change over temperature. Capacitance change decouple individual components powered by the LT3023, due to DC bias with X5R and X7R capacitors is better than will increase the effective output capacitor value. With Y5V and Z5U capacitors, but can still be signifi cant enough larger capacitors used to bypass the reference (for low to drop capacitor values below appropriate levels. Capaci- noise operation), larger values of output capacitors are tor DC bias characteristics tend to improve as component needed. For 100pF of bypass capacitance, 2.2μF of output capacitor is recommended. With a 330pF bypass capacitor 20 or larger, a 3.3μF output capacitor is recommended. The BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF shaded region of Figure 2 defi nes the region over which 0 the LT3023 regulator is stable. The minimum ESR needed %) X5R is defi ned by the amount of bypass capacitance used, while UE (–20 L A the maximum ESR is 3Ω. V N –40 E I G Extra consideration must be given to the use of ceramic N A–60 H capacitors. Ceramic capacitors are manufactured with a C Y5V variety of dielectrics, each with different behavior across –80 temperature and applied voltage. The most common –100 dielectrics used are specifi ed with EIA temperature char- 0 2 4 6 8 10 12 14 16 DC BIAS VOLTAGE (V) acteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and 3023 F03 Y5V dielectrics are good for providing high capacitances Figure 3. Ceramic Capacitor DC Bias Characteristics in a small package, but they tend to have strong voltage 4.0 40 3.5 20 3.0 %) 0 X5R 2.5 STABLE REGION UE ( Ω) AL –20 R ( 2.0 N V ES E I –40 1.5 CBYP = 0 NG Y5V CBYP = 100pF HA –60 1.0 CBYP = 330pF C 0.5 CBYP > 3300pF –80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF 0 –100 1 2 3 4 5 6 7 8 910 –50 –25 0 25 50 75 100 125 OUTPUT CAPACITANCE (μF) TEMPERATURE (°C) 3023 F02 3023 F04 Figure 2. Stability Figure 4. Ceramic Capacitor Temperature Characteristics 3023fa 10

LT3023 APPLICATIONS INFORMATION case size increases, but expected capacitance at operating Characteristics section. Power dissipation will be equal voltage should be verifi ed. to the sum of the two components listed above. Power dissipation from both channels must be considered during Voltage and temperature coeffi cients are not the only thermal analysis. sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates The LT3023 regulator has internal thermal limiting de- voltage across its terminals due to mechanical stress, signed to protect the device during overload conditions. similar to the way a piezoelectric accelerometer or micro- For continuous normal conditions, the maximum junction phone works. For a ceramic capacitor the stress can be temperature rating of 125°C must not be exceeded. It is induced by vibrations in the system or thermal transients. important to give careful consideration to all sources of The resulting voltages produced can cause appreciable thermal resistance from junction to ambient. Additional amounts of noise, especially when a ceramic capacitor is heat sources mounted nearby must also be considered. used for noise bypassing. A ceramic capacitor produced For surface mount devices, heat sinking is accomplished Figure 5’s trace in response to light tapping from a pencil. by using the heat spreading capabilities of the PC board Similar vibration induced behavior can masquerade as and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat gener- COUT = 10μF ated by power devices. CBYP = 0.01μF ILOAD = 100mA The following tables list thermal resistance for several different board sizes and copper areas. All measurements VOUT were taken in still air on 3/32" FR-4 board with one ounce 500μV/DIV copper. Table 1. MSE Package, 10-Lead MSOP COPPER AREA THERMAL RESISTANCE 100ms/DIV 3023 F05 TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 40°C/W Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor 1000mm2 2500mm2 2500mm2 45°C/W increased output voltage noise. 225mm2 2500mm2 2500mm2 50°C/W 100mm2 2500mm2 2500mm2 62°C/W Thermal Considerations *Device is mounted on topside. The power handling capability of the device will be limited Table 2. DD Package, 10-Lead DFN by the maximum rated junction temperature (125°C). The COPPER AREA power dissipated by the device will be made up of two THERMAL RESISTANCE TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) components (for each channel): 2500mm2 2500mm2 2500mm2 40°C/W 1. Output current multiplied by the input/output voltage 1000mm2 2500mm2 2500mm2 45°C/W differential: (I )(V – V ), and OUT IN OUT 225mm2 2500mm2 2500mm2 50°C/W 2. GND pin current multiplied by the input voltage: 100mm2 2500mm2 2500mm2 62°C/W (I )(V ). *Device is mounted on topside. GND IN The thermal resistance juncton-to-case (θ ), measured The ground pin current can be found by examining the JC at the Exposed Pad on the back of the die is 10°C/W. GND Pin Current curves in the Typical Performance 3023fa 11

LT3023 APPLICATIONS INFORMATION Calculating Junction Temperature limiting and thermal limiting, the devices are protected against reverse input voltages, reverse output voltages Example: Given an output voltage on the fi rst channel of and reverse voltages from output to input. 3.3V, an output voltage of 2.5V on the second channel, an input voltage range of 4V to 6V, output current ranges of Current limit protection and thermal overload protection 0mA to 100mA for the fi rst channel and 0mA to 50mA for the are intended to protect the device against current overload second channel, with a maximum ambient temperature of conditions at the output of the device. For normal operation, 50°C, what will the maximum junction temperature be? the junction temperature should not exceed 125°C. The power dissipated by each channel of the device will The input of the device will withstand reverse voltages be equal to: of 20V. Current fl ow into the device will be limited to less than 1mA (typically less than 100μA) and no negative I (V – V ) + I (V ) OUT(MAX) IN(MAX) OUT GND IN(MAX) voltage will appear at the output. The device will protect where (for the fi rst channel): both itself and the load. This provides protection against batteries which can be plugged in backward. I = 100mA OUT(MAX) VIN(MAX) = 6V The output of the LT3023 can be pulled below ground IGND at (IOUT = 100mA, VIN = 6V) = 2mA without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by so: 20V. The output will act like an open circuit; no current will P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W fl ow out of the pin. If the input is powered by a voltage and (for the second channel): source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. In I = 50mA OUT(MAX) this case, grounding the SHDN1/SHDN2 pins will turn off V = 6V IN(MAX) the device and stop the output from sourcing the short- I at (I = 50mA, V = 6V) = 1mA GND OUT IN circuit current. so: The ADJ1 and ADJ2 pins can be pulled above or below P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ1 and The thermal resistance will be in the range of 40°C/W to ADJ2 pins will act like an open circuit when pulled below 60°C/W depending on the copper area. So the junction ground and like a large resistor (typically 100k) in series temperature rise above ambient will be approximately with a diode when pulled above ground. equal to: In situations where the ADJ1 and ADJ2 pins are connected (0.28W + 018W)(60°C/W) = 27.8°C to a resistor divider that would pull the pins above their 7V The maximum junction temperature will then be equal to clamp voltage if the output is pulled high, the ADJ1/ADJ2 the maximum junction temperature rise above ambient pin input current must be limited to less than 5mA. For plus the maximum ambient temperature or: example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output T = 50°C + 27.8°C = 77.8°C JMAX is forced to 20V. The top resistor of the resistor divider Protection Features must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ1/ADJ2 pin is at 7V. The 13V The LT3023 regulator incorporates several protection difference between output and ADJ1/ADJ2 pin divided by features which makes it ideal for use in battery-powered the 5mA maximum current into the ADJ1/ADJ2 pin yields circuits. In addition to the normal protection features a minimum top resistor value of 2.6k. associated with monolithic regulators, such as current 3023fa 12

LT3023 APPLICATIONS INFORMATION In circuits where a backup battery is required, several 100 TA = 25°C different input/output conditions can occur. The output 90 VIN = 0V voltage may be held up while the input is either pulled μA) 80 VOUT = VADJ T ( CURRENT FLOWS to ground, pulled to some intermediate voltage or is left EN 760 INTO OUTPUT PIN R R open circuit. Current fl ow back into the output will follow U 60 C the curve shown in Figure 6. UT 50 P T U 40 O When the IN pin of the LT3023 is forced below the OUT1 SE 30 R or OUT2 pins or the OUT1/OUT2 pins are pulled above the VE 20 E R IN pin, input current will typically drop to less than 2μA. 10 This can happen if the input of the device is connected 0 0 1 2 3 4 5 6 7 8 9 10 to a discharged (low voltage) battery and the output is OUTPUT VOLTAGE (V) held up by either a backup battery or a second regulator 3023 F06 circuit. The state of the SHDN1/SHDN2 pins will have no Figure 6. Reverse Output Current effect on the reverse output current when the output is pulled above the input. TYPICAL APPLICATIONS Noise Bypassing Slows Startup, Allows Outputs to Track VSHDN1/SHDN2 1V/DIV VOUT1 1V/DIV VOUT2 1V/DIV VIN 3.7V TO 20V IN OUT1 3.3V AT 100mA 0.01μF 10μF 1μF BYP1 422k 2ms/DIV 3023 TA02b ADJ1 249k LT3023 Startup Time OFF ON SHDN1 OUT2 2.5V 100 0.01μF 10μF AT 100mA SHDN2 BYP2 261k ADJ2 GND 249k ms) 10 E ( M 3023 TA02a TI P U T R TA 1 S 0.1 10 100 1000 10000 CBYP (pF) 3023 TA02c 3023fa 13

LT3023 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 0.38 ± 0.10 TYP 6 10 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10 2.15 ±0.05 (2 SIDES) (4 SIDES) (2 SIDES) PIN 1 PACKAGE TOP MARK OUTLINE (SEE NOTE 6) (DD) DFN 1103 5 1 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 0.50 BSC BSC 2.38 ±0.10 2.38 ±0.05 (2 SIDES) 0.00 – 0.05 (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2.DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3023fa 14

LT3023 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev B) BOTTOM VIEW OF EXPOSED PAD OPTION 2(..719140 ±± 0.0.10042) 0(..808395 ±± 0.0.10257) 1 (2..00861 ± ± 0 ..010042) 1.83 ± 0.102 (.072 ± .004) 5.23 2.083 ± 0.102 3.20 – 3.45 (.206) (.082 ± .004) (.126 – .136) MIN 10 0.305 ± 0.038 0.50 3.00 ± 0.102 (.0120 ± .0015) (.0197) (.118 ± .004) 0.497 ± 0.076 TYP BSC (NOTE 3) (.0196 ± .003) RECOMMENDED SOLDER PAD LAYOUT 10 9 8 76 REF 4.90 ± 0.152 3.00 ± 0.102 (.193 ± .006) (.118 ± .004) (NOTE 4) DETAIL “A” 0.254 (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 1.10 0.86 (.021 ± .006) (.043) (.034) MAX REF DETAIL “A” 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) (.004 ± .002) 0.50 TYP (.0197) MSOP (MSE) 0307 REV B NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3023fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 15 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT3023 TYPICAL APPLICATION Startup Sequencing Turn-On Waveforms VSHDN1 1V/DIV VIN 3.3V 3.7V TO 20V IN OUT1 AT VOUT1 100mA 1V/DIV 1μF LT3023 0.01μF 10μF VOUT2 BYP1 422k 35.7k 1V/DIV ADJ1 249k 28k 2.5V 2ms/DIV 3023 TA03b OFF ON SHDN1 OUT2 AT 0.01μF 10μF 100mA Turn-Off Waveforms SHDN2 BYP2 261k ADJ2 GND 0.47μF 249k VSHDN1 1V/DIV 3023 TA03a VOUT1 1V/DIV VOUT2 1V/DIV 2ms/DIV 3023 TA03c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1129 700mA, Micropower, LDO V : 4.2V to 30V, V = 3.75V, I = 50μA, I = 16μA, DD, SOT-223, S8,TO220, IN OUT(MIN) Q SD TSSOP20 Packages LT1175 500mA, Micropower Negative LDO Guaranteed Voltage Tolerance and Line/Load Regulation, V : –20V to –4.3V, IN V = –3.8V, I = 45μA, I = 10μA, DD,SOT-223, S8 Packages OUT(MIN) Q SD LT1185 3A, Negative LDO Accurate Programmable Current Limit, Remote Sense, V : –35V to –4.2V, V IN OUT(MIN) = –2.40V, I = 2.5mA, I <1μA, TO220-5 Package Q SD LT1761 100mA, Low Noise Micropower, LDO Low Noise < 20μV Stable with 1μF Ceramic Capacitors, V : 1.8V to 20V, RMS, IN V 1.22V, I = 20μA, I <1μA, ThinSOT Package OUT(MIN) = Q SD LT1762 150mA, Low Noise Micropower, LDO Low Noise < 20μV V : 1.8V to 20V, V = 1.22V, I = 25μA, I <1μA, RMS, IN OUT(MIN) Q SD MS8 Package LT1763 500mA, Low Noise Micropower, LDO Low Noise < 20μV V : 1.8V to 20V, V = 1.22V, I = 30μA, I <1μA, RMS, IN OUT(MIN) Q SD S8 Package LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO Low Noise < 40μV "A" Version Stable with Ceramic Capacitors, V : 2.7V to 20V, RMS, IN V = 1.21V, I = 1mA, I <1μA, DD, TO220 Packages OUT(MIN) Q SD LTC1844 150mA, Very Low Drop-Out LDO Low Noise < 30μV , Stable with 1μF Ceramic Capacitors, V : 1.6V to 6.5V, RMS IN V = 1.25V, I = 40μA, I <1μA, ThinSOT Package OUT(MIN) Q SD LT1962 300mA, Low Noise Micropower, LDO Low Noise < 20μV V : 1.8V to 20V, V = 1.22V, I = 30μA, I <1μA, RMS, IN OUT(MIN) Q SD MS8 Package LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO Low Noise < 40μV "A" Version Stable with Ceramic Capacitors, V : 2.1V to 20V, RMS, IN V = 1.21V, I = 1mA, I <1μA, DD, TO220, SOT-223, S8 Packages OUT(MIN) Q SD LT1964 200mA, Low Noise Micropower, Negative LDO Low Noise < 30μV Stable with Ceramic Capacitors, V : –0.9V to –20V, RMS, IN V = –1.21V, I = 30μA, I = 3μA, ThinSOT Package OUT(MIN) Q SD LTC3407 Dual 600mA. 1.5MHz Synchronous Step Down V : 2.5V to 5.5V, V = 0.6 V, I = 40μA, I <1μA, MSE Package IN OUT(MIN) Q SD DC/DC Converter 3023fa 16 Linear Technology Corporation LT 0208 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003