LT1999-10/LT1999-20/ LT1999-50 High Voltage, Bidirectional Current Sense Amplifier FeaTures DescripTion n Buffered Output with 3 Gain Options: The LT®1999 is a high speed precision current sense am- 10V/V, 20V/V, 50V/V plifier, designed to monitor bidirectional currents over a n Gain Accuracy: 0.5% Max wide common mode range. The LT1999 is offered in three n Input Common Mode Voltage Range: –5V to 80V gain options: 10V/V, 20V/V, and 50V/V. n AC CMRR > 80dB at 100kHz The LT1999 senses current via an external resistive shunt n Input Offset Voltage: 1.5mV Max and generates an output voltage, indicating both magnitude n –3dB Bandwidth: 2MHz and direction of the sensed current. The output voltage is n Smooth, Continuous Operation Over Entire Common referenced halfway between the supply voltage and ground, Mode Range or an external voltage can be used to set the reference n 4kV HBM Tolerant and 1kV CDM Tolerant level. With a 2MHz bandwidth and a common mode input n Low Power Shutdown <10µA range of –5V to 80V, the LT1999 is suitable for monitor- n –55°C to 150°C Operating Temperature Range ing currents in H-Bridge motor controls, switching power n 8-Lead MSOP and 8-Lead SO (Narrow) Packages supplies, solenoid currents, and battery charge currents n 8-Lead MSOP Pinout Option Engineered for FMEA from full charge to depletion. The LT1999 operates from an independent 5V supply applicaTions and draws 1.55mA. A shutdown mode is provided for n High Side or Low Side Current Sensing minimizing power consumption. n H-Bridge Motor Control The LT1999 is available in an 8-lead SOP, an 8-lead MSOP n Solenoid Current Sense (original pinout), or an 8-lead pinout option engineered n High Voltage Data Acquisition for FMEA. n PWM Control Loops L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Fuse/MOSFET Monitoring Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion Full Bridge Armature Current Monitor VS LT1999 V+ 5V V+ 2µA 1 SHDN 8 VSHDN 2.5V VOUT + RG RS V+IN 2 V+4k 0.8k – +– 7 VOUT (2V/DIV)UT +INV (20V/D V–IN V+ VO V+IN IV) 3 4k 0.8k 160k 6 VREF 5V V+ 160k 0.1µF 4 TIME (10µs/DIV) 1999 TA01b 5 0.1µF 1999 TA01a 1999fd 1 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 absoluTe MaxiMuM raTings (Note 1) Differential Input Voltage Specified Temperature Range (Note 6) +IN to –IN (Notes 1, 3) .................................±60V, 10ms LT1999C ..................................................0°C to 70°C +IN to GND, –IN to GND (Note 2) .............–5.25V to 88V LT1999I ................................................–40°C to 85°C Total Supply Voltage (V+ to GND) ................................6V LT1999H ............................................–40°C to 125°C Input Voltage Pins 6 and 8 ...................V+ + 0.3V, –0.3V LT1999MP .........................................–55°C to 150°C Output Short-Circuit Duration (Note 4) ............Indefinite Junction Temperature ...........................................150°C Operating Ambient Temperature (Note 5) Storage Temperature Range ..................–65°C to 150°C LT1999C ..............................................–40°C to 85°C LT1999I ................................................–40°C to 85°C LT1999H ............................................–40°C to 125°C LT1999MP .........................................–55°C to 150°C pin conFiguraTion TOP VIEW ORIGINAL MSOP PINOUT MSOP PINOUT ENGINEERED FOR FMEA TOP VIEW TOP VIEW V+ 1 8 SHDN V+ 1 8 SHDN +IN 1 8 SHDN +IN 2 7 OUT +IN 2 7 OUT –IN 2 7 OUT –IN 3 6 REF –IN 3 6 REF NC 3 6 REF V+ 4 5 GND V+ 4 5 GND V+ 4 5 GND MS8 PACKAGE MS8 PACKAGE 8-LEAD PLASTIC MSOP 8-LEAD PLASTIC MSOP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, ΘJA = 300°C/W TJMAX = 150°C, ΘJA = 300°C/W TJMAX = 150°C, ΘJA = 190°C/W orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1999CMS8-10#PBF LT1999CMS8-10#TRPBF LTFPB 8-Lead Plastic MSOP 0°C to 70°C LT1999IMS8-10#PBF LT1999IMS8-10#TRPBF LTFPB 8-Lead Plastic MSOP –40°C to 85°C LT1999HMS8-10#PBF LT1999HMS8-10#TRPBF LTFPB 8-Lead Plastic MSOP –40°C to 125°C LT1999MPMS8-10#PBF LT1999MPMS8-10#TRPBF LTFQP 8-Lead Plastic MSOP –55°C to 150°C LT1999CMS8-10F#PBF LT1999CMS8-10F#TRPBF LTGVB 8-Lead MSOP FMEA Pinout 0°C to 70°C LT1999IMS8-10F#PBF LT1999IMS8-10F#TRPBF LTGVB 8-Lead MSOP FMEA Pinout –40°C to 85°C LT1999HMS8-10F#PBF LT1999HMS8-10F#TRPBF LTGVB 8-Lead MSOP FMEA Pinout –40°C to 125°C LT1999MPMS8-10F#PBF LT1999MPMS8-10F#TRPBF LTGVB 8-Lead MSOP FMEA Pinout –55°C to 150°C LT1999CS8-10#PBF LT1999CS8-10#TRPBF 199910 8-Lead Plastic SO 0°C to 70°C LT1999IS8-10#PBF LT1999IS8-10#TRPBF 199910 8-Lead Plastic SO –40°C to 85°C LT1999HS8-10#PBF LT1999HS8-10#TRPBF 199910 8-Lead Plastic SO –40°C to 125°C LT1999MPS8-10#PBF LT1999MPS8-10#TRPBF 99MP10 8-Lead Plastic SO –55°C to 150°C LT1999CMS8-20#PBF LT1999CMS8-20#TRPBF LTFNZ 8-Lead Plastic MSOP 0°C to 70°C LT1999IMS8-20#PBF LT1999IMS8-20#TRPBF LTFNZ 8-Lead Plastic MSOP –40°C to 85°C LT1999HMS8-20#PBF LT1999HMS8-20#TRPBF LTFNZ 8-Lead Plastic MSOP –40°C to 125°C LT1999MPMS8-20#PBF LT1999MPMS8-20#TRPBF LTFQQ 8-Lead Plastic MSOP –55°C to 150°C 1999fd 2 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1999CMS8-20F#PBF LT1999CMS8-20F#TRPBF LTGVC 8-Lead MSOP FMEA Pinout 0°C to 70°C LT1999IMS8-20F#PBF LT1999IMS8-20F#TRPBF LTGVC 8-Lead MSOP FMEA Pinout –40°C to 85°C LT1999HMS8-20F#PBF LT1999HMS8-20F#TRPBF LTGVC 8-Lead MSOP FMEA Pinout –40°C to 125°C LT1999MPMS8-20F#PBF LT1999MPMS8-20F#TRPBF LTGVC 8-Lead MSOP FMEA Pinout –55°C to 150°C LT1999CS8-20#PBF LT1999CS8-20#TRPBF 199920 8-Lead Plastic SO 0°C to 70°C LT1999IS8-20#PBF LT1999IS8-20#TRPBF 199920 8-Lead Plastic SO –40°C to 85°C LT1999HS8-20#PBF LT1999HS8-20#TRPBF 199920 8-Lead Plastic SO –40°C to 125°C LT1999MPS8-20#PBF LT1999MPS8-20#TRPBF 99MP20 8-Lead Plastic SO –55°C to 150°C LT1999CMS8-50#PBF LT1999CMS8-50#TRPBF LTFPC 8-Lead Plastic MSOP 0°C to 70°C LT1999IMS8-50#PBF LT1999IMS8-50#TRPBF LTFPC 8-Lead Plastic MSOP –40°C to 85°C LT1999HMS8-50#PBF LT1999HMS8-50#TRPBF LTFPC 8-Lead Plastic MSOP –40°C to 125°C LT1999MPMS8-50#PBF LT1999MPMS8-50#TRPBF LTFQR 8-Lead Plastic MSOP –55°C to 150°C LT1999CMS8-50F#PBF LT1999CMS8-50F#TRPBF LTGVD 8-Lead MSOP FMEA Pinout 0°C to 70°C LT1999IMS8-50F#PBF LT1999IMS8-50F#TRPBF LTGVD 8-Lead MSOP FMEA Pinout –40°C to 85°C LT1999HMS8-50F#PBF LT1999HMS8-50F#TRPBF LTGVD 8-Lead MSOP FMEA Pinout –40°C to 125°C LT1999MPMS8-50F#PBF LT1999MPMS8-50F#TRPBF LTGVD 8-Lead MSOP FMEA Pinout –55°C to 150°C LT1999CS8-50#PBF LT1999CS8-50#TRPBF 199950 8-Lead Plastic SO 0°C to 70°C LT1999IS8-50#PBF LT1999IS8-50#TRPBF 199950 8-Lead Plastic SO –40°C to 85°C LT1999HS8-50#PBF LT1999HS8-50#TRPBF 199950 8-Lead Plastic SO –40°C to 125°C LT1999MPS8-50#PBF LT1999MPS8-50#TRPBF 99MP50 8-Lead Plastic SO –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, 0°C < T < 70°C for C-grade parts, –40°C < T < 85°C for I-grade parts, and –40°C < T < 125°C for H-grade parts, otherwise A A A specifications are at T = 25°C. V+ = 5V, GND = 0V, V = 12V, V = floating, V = floating, unless otherwise specified. See Figure 2. A CM REF SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Full-Scale Input Sense Voltage (Note 7) LT1999-10 l –0.35 0.35 V SENSE V = V – V LT1999-20 l –0.2 0.2 V SENSE +IN –IN LT1999-50 l –0.08 0.08 V V CM Input Voltage Range l –5 80 V CM R Differential Input Impedance ΔV = ±2V/Gain l 6.4 8 9.6 kΩ IN(DIFF) INDIFF R CM Input Impedance ΔV = 5.5V to 80V l 5 20 MΩ INCM CM ΔV = –5V to 4.5V l 3.6 4.8 6 kΩ CM V Input Referred Voltage Offset –750 ±500 750 μV OSI l –1500 1500 μV ΔV /ΔT Input Referred Voltage Offset Drift 5 μV/°C OSI A Gain LT1999-10 l 9.95 10 10.05 V/V V LT1999-20 l 19.9 20 20.1 V/V LT1999-50 l 49.75 50 50.25 V/V A Error Gain Error ΔV = ±2V l –0.5 ±0.2 0.5 % V OUT 1999fd 3 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, 0°C < T < 70°C for C-grade parts, –40°C < T < 85°C for I-grade parts, and –40°C < T < 125°C for H-grade parts, otherwise A A A specifications are at T = 25°C. V+ = 5V, GND = 0V, V = 12V, V = floating, V = floating, unless otherwise specified. See Figure 2. A CM REF SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Input Bias Current V > 5.5V l 100 137.5 175 μA B CM I(+IN) = I(–IN) V = –5V l –2.35 –1.95 –1.5 mA CM (Note 8) V = 0.5V, 0V < V < 80V l 0.001 2.5 μA SHDN CM I Input Offset Current V > 5.5V l –1 1 μA OS CM I = I(+IN) – I(–IN) V = –5V l –10 10 μA OS CM (Note 8) V = 0.5V, 0V < V < 80V l –2.5 2.5 μA SHDN CM PSRR Supply Rejection Ratio V+ = 4.5V to 5.5V l 68 77 dB CMRR Sense Input Common Mode Rejection V = –5V to 80V l 96 105 dB CM V = –5V to 5.5V l 96 120 dB CM V = 12V, 7V , f = 100kHz, l 75 90 dB CM P-P V = 0V, 7V , f = 100kHz l 80 100 dB CM P-P e Differential Input Referred Noise Voltage Density f = 10kHz 97 nV/√Hz n f = 0.1Hz to 10Hz 8 μV P-P REF REF Pin Rejection, V+ = 5.5V RR ΔV = 3.0V LT1999-10 l 62 70 dB REF ΔV = 3.25V LT1999-20 l 62 70 dB REF ΔV = 3.25V LT1999-50 l 62 70 dB REF R REF Pin Input Impedance l 60 80 100 kΩ REF V = 0.5V l 0.15 0.4 0.65 MΩ SHDN V Open Circuit Voltage l 2.45 2.5 2.55 V REF V = 0.5V l 1 2.5 2.75 V SHDN V REF Pin Input Range (Note 9) LT1999-10 l 1.25 V+ – 1.25 V REFR LT1999-20 l 1.125 V+ – 1.125 V LT1999-50 l 1.125 V+ – 1.125 V I Pin Pull-Up Current V+ = 5.5V, V = 0V l –6 –2 μA SHDN SHDN V SHDN Pin Input High l V+ – 0.5 V IH V SHDN Pin Input Low l 0.5 V IL f Small Signal Bandwidth LT1999-10 2 MHz 3dB LT1999-20 2 MHz LT1999-50 1.2 MHz SR Slew Rate 3 V/μs t Settling Time due to Input Step, ΔV = ±2V 0.5% Settling 2.5 μs s OUT t Common Mode Step Recovery Time LT1999-10 0.8 μs r ΔV = ±50V, 20ns LT1999-20 1 μs CM (Note 10) LT1999-50 1.3 μs V Supply Voltage (Note 11) l 4.5 5 5.5 V S I Supply Current V > 5.5V l 1.55 1.9 mA S CM V = –5V l 5.8 7.1 mA CM V+ = 5.5V, V = 0.5V, V > 0V l 3 10 μA SHDN CM R Output Impedance ΔI = ±2mA 0.15 Ω O O I Sourcing Output Current R = 50Ω to GND l 6 31 40 mA SRC LOAD I Sinking Output Current R = 50Ω to V+ l 15 26 40 mA SNK LOAD V Swing Output High (with Respect to V+) R = 1kΩ to Mid-Supply l 125 250 mV OUT LOAD R = Open l 5 125 mV LOAD Swing Output Low (with Respect to V–) R = 1kΩ to Mid-Supply l 250 400 mV LOAD R = Open l 150 225 mV LOAD t Turn-On Time V = 0V to 5V 1 μs ON SHDN t Turn-Off Time V = 5V to 0V 1 μs OFF SHDN 1999fd 4 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, –55°C < T < 150°C for MP-grade parts, otherwise specifications are at T = 25°C. V+ = 5V, GND = 0V, V = 12V, A A CM V = floating, V = floating, unless otherwise specified. See Figure 2. REF SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Full-Scale Input Sense Voltage (Note 7) LT1999-10 l –0.35 0.35 V SENSE V = V – V LT1999-20 l –0.2 0.2 V SENSE +IN –IN LT1999-50 l –0.08 0.08 V V CM Input Voltage Range l –5 80 V CM R Differential Input Impedance ΔV = ±2V/GAIN l 6.4 8 9.6 kΩ IN(DIFF) INDIFF R CM Input Impedance ΔV = 5.5V to 80V l 5 20 MΩ INCM CM ΔV = –5V to 4.5V l 3.6 4.8 6 kΩ CM V Input Referred Voltage Offset –750 ±500 750 μV OSI l –2000 2000 μV ΔV /ΔT Input Referred Voltage Offset Drift 8 μV/°C OSI A Gain LT1999-10 l 9.95 10 10.05 V/V V LT1999-20 l 19.9 20 20.1 V/V LT1999-50 l 49.75 50 50.25 V/V A Error Gain Error ΔV = ±2V l –0.5 ±0.2 0.5 % V OUT I Input Bias Current V > 5.5V l 100 137.5 180 μA B CM I(+IN) = I(–IN) V = –5V l –2.35 –1.95 –1.5 mA CM (Note 8) V = 0.5V, 0V < V < 80V l 0.001 10 μA SHDN CM I Input Offset Current V > 5.5V l –1 1 μA OS CM I = I(+IN) – I(–IN) V = –5V l –10 10 μA OS CM (Note 8) V = 0.5V, 0V < V < 80V l –10 10 μA SHDN CM PSRR Supply Rejection Ratio V+ = 4.5V to 5.5V l 68 77 dB CMRR Sense Input Common Mode Rejection V = –5V to 80V l 96 105 dB CM V = –5V to 5.5V l 96 120 dB CM V = 12V, 7V , f = 100kHz, l 75 90 dB CM P-P V = 0V, 7V , f = 100kHz l 80 100 dB CM P-P e Differential Input Referred Noise Voltage Density f= 10kHz 97 nV/√Hz n f = 0.1Hz to 10Hz 8 μV P-P REF REF Pin Rejection, V+ = 5.5V RR ΔV = 2.75V LT1999-10 l 62 70 dB REF ΔV = 3.25V LT1999-20 l 62 70 dB REF ΔV = 3.25V LT1999-50 l 62 70 dB REF R REF Pin Input Impedance l 60 80 100 kΩ REF V = 0.5V l 0.15 0.4 0.65 MΩ SHDN V Open Circuit Voltage l 2.45 2.5 2.55 V REF V = 0.5V l 0.25 2.5 2.75 V SHDN V REF Pin Input Range (Note 9) LT1999-10 l 1.5 V+ – 1.25 V REFR LT1999-20 l 1.125 V+ – 1.125 V LT1999-50 l 1.125 V+ – 1.125 V I Pin Pull-Up Current V+ = 5.5V, V = 0V l –6 –2 μA SHDN SHDN V SHDN Pin Input High l V+ – 0.5 V IH V SHDN Pin Input Low l 0.5 V IL f Small Signal Bandwidth LT1999-10 2 MHz 3dB LT1999-20 2 MHz LT1999-50 1.2 MHz SR Slew Rate 3 V/μs t Settling Time Due to Input Step, ΔV = ±2V 0.5% Settling 2.5 μs S OUT 1999fd 5 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, –55°C < T < 150°C for MP-grade parts, otherwise specifications are at T = 25°C. V+ = 5V, GND = 0V, V = 12V, A A CM V = floating, V = floating, unless otherwise specified. See Figure 2. REF SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Common Mode Step Recovery Time LT1999-10 0.8 μs r ΔV = ±50V, 20ns LT1999-20 1 μs CM (Note 10) LT1999-50 1.3 μs V Supply Voltage (Note 11) l 4.5 5 5.5 V S I Supply Current V > 5.5V l 1.55 1.9 mA S CM V = –5V l 5.8 7.1 mA CM V+ = 5.5V, V = 0.5V, V > 0V l 3 25 μA SHDN CM R Output Impedance ΔI = ±2mA 0.15 Ω O O I Sourcing Output Current R = 50Ω to GND l 3 31 40 mA SRC LOAD I Sinking Output Current R = 50Ω to V+ l 10 26 40 mA SNK LOAD V Swing Output High (with Respect to V+) R = 1kΩ to Mid-Supply l 125 250 mV OUT LOAD R = Open l 5 125 mV LOAD Swing Output Low (with Respect to V–) R = 1kΩ to Mid-Supply l 250 400 mV LOAD R = Open l 150 225 mV LOAD t Turn-On Time V = 0V to 5V 1 μs ON SHDN t Turn-Off Time V = 5V to 0V 1 μs OFF SHDN Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Full-scale sense (V ) gives indication of the maximum SENSE may cause permanent damage to the device. Exposure to any Absolute differential input that can be applied with better than 0.5% gain accuracy. Maximum Rating condition for extended periods may affect device Gain accuracy is degraded when the output saturates against either power reliability and lifetime. supply rail. V is verified with V+ = 5.5V, V = 12V, with the REF pin SENSE CM Note 2: Pin 2 (+IN) and Pin 3 (–IN) are protected by ESD voltage clamps set to it’s voltage range limits. The maximum VSENSE is verified with the which have asymmetric bidirectional breakdown characteristics with respect REF pin set to it’s minimum specified limit, verifying the gain error is less to the GND pin (Pin 5). These pins can safely support common mode than 0.5% at the output. The minimum VSENSE is verified with the REF pin voltages which vary from –5.25V to 88V without triggering an ESD clamp. set to its maximum specified limit, verifying the gain error at the output is less than 0.5%. See Note 9 for more information. Note 3: Exposure to differential sense voltages exceeding the normal operating range for extended periods of time may degrade part Note 8: IB is defined as the average of the input bias currents to the +IN performance. A heat sink may be required to keep the junction temperature and –IN pins (Pins 2 and 3). A positive current indicates current flowing below the Absolute Maximum Rating when the inputs are stressed into the pin. IOS is defined as the difference of the input bias currents. differentially. The amount of power dissipated in the LT1999 due to input IOS = I(+IN) – I(–IN) overdrive can be approximated by: Note 9: The REF pin voltage range is the minimum and maximum limits (V −V )2 that ensures the input referred voltage offset does not exceed ±3mV over P = +IN −IN the I, C, and H temperature ranges, and ±3.5mV over the MP temperature DISS 8kΩ range. Note 4: A heat sink may be required to keep the junction temperature Note 10: Common mode recovery time is defined as the time it takes the below the absolute maximum rating. output of the LT1999 to recover from a 50V, 20ns input common mode Note 5: The LT1999C/LT1999I are guaranteed functional over the operating voltage transition, and settle to within the DC amplifier specifications. temperature range –40°C to 85°C. The LT1999H is guaranteed functional Note 11: Operating the LT1999 with V+ < 4.5V is possible, although the over the operating temperature range –40°C to 125°C. The LT1999MP is LT1999 is not tested or specified in this condition. See the Applications guaranteed functional over the operating temperature range –55°C to 150°C. Information section. Junction temperatures greater than 125°C will promote accelerated aging. The LT1999 has a demonstrated typical life beyond 1000 hours at 150°C. Note 6: The LT1999C is guaranteed to meet specified performance from 0°C to 70°C. The LT1999C is designed, characterized, and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1999I is guaranteed to meet specified performance from –40°C to 85°C. The LT1999H is guaranteed to meet specified performance from –40°C to 125°C. The LT1999MP is guaranteed to meet specified performance from –55°C to 150°C. 1999fd 6 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical perForMance characTerisTics Supply Current vs Input Common Mode Supply Current vs Temperature Supply Current vs Supply Voltage 7 1.8 4.0 V+ = 5V VSHDN = OPEN 150°C VCM = 12V VINDIFF = 0V 3.5 130°C 6 VCM = 12V 90°C 25°C 1.7 3.0 5 –45°C –55°C 2.5 mA) 4 mA) 1.6 mA) 2.0 I (S3 I (S V+ = 5.5V I (S 1.5 2 1.5 V+ = 4.5V 1.0 1 0.5 0 1.4 0 –5 5 15 25 35 45 55 65 7580 –55 –30 –5 20 45 70 95 120 145 0 1 2 3 4 5 VCM (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) 1999 G01 1999 G02 1999 G03 Supply Current Shutdown Supply Current Shutdown Input Bias Current vs SHDN Pin Voltage vs Temperature vs Input Common Mode 10 10 1000 VV+C M= =5 V12V VVSINHDDINFF == 00VV VV+S H=D 5NV = 0V TA = 150°C 8 VCM = 12V VSENSE = 0V 1 TA =130°C 100 6 I (mA)S 0.1 TA = 150°C I (µA)S 4 V+ = 5.5V I (nA)B TA =110°C 10 TA = 90°C 0.01 V+ = 4.5V 2 TA = –55°C TA = 70°C TA = 25°C 0.001 0 1 0 1 2 3 4 5 –55 –30 –5 20 45 70 95 120 145 0 20 40 60 80 100 VSHDN (V) TEMPERATURE (°C) VCM (V) 1999 G04 1999 G05 1999 G06 Input Bias Current Input Impedance vs Input Common Mode Input Bias Current vs Temperature vs Input Common Mode Voltage 0.5 146 100000 V+ = 5V VSHDN = OPEN 144 VVI+N =D I5FFV = 0V COMMON MODE INPUT 0 10000 IMPEDANCE 142 Ω) I (mA)B––10..05 I (µA)B114308 VVCCMM == 850.5VV MPEDANCE (k 1100000 136 I DIFFERENTIAL INPUT IMPEDANCE –1.5 10 134 –2.0 132 1 –5 5 15 25 35 45 55 65 7580 –55 –30 –5 20 45 70 95 120 145 –5 5 15 25 35 45 55 65 75 VCM (V) TEMPERATURE (°C) VCM (V) 1999 G07 1999 G08 1999 G09 1999fd 7 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical perForMance characTerisTics Input Referred Voltage Offset Input Referred Voltage Offset vs Temperature and Gain Option vs Input Common Mode Voltage 1500 1500 VCM = 12V V+ = 5V 12 UNITS PLOTTED TA = 25°C 1000 1000 12 UNITS PLOTTED 500 500 V) V) µ µ (OSI 0 (OSI 0 V V –500 –500 –1000 LT1999-10 –1000 LT1999-10 LT1999-20 LT1999-20 LT1999-50 LT1999-50 –1500 –1500 –55 –30 –5 20 45 70 95 120 145 –5 5 15 25 35 45 55 65 75 TEMPERATURE (°C) VCM (V) 1999 G10 1999 G11 LT1999-10 Small Signal LT1999-20 Small Signal Frequency Response Frequency Response 30 180 35 180 25 135 30 135 GAIN GAIN 20 90 25 90 15 45 P 20 45 P GAIN (dB)105 PHASE 0–45 HASE (DEG) GAIN (dB)1150 PHASE 0–45 HASE (DEG) 0 –90 5 –90 –5 –135 0 –135 VOUT = 0.5VP-P AT 1kHz VOUT = 0.5VP-P AT 1kHz –10 –180 –5 –180 1 10 100 1000 10000 1 10 100 1000 10000 FREQUENCY (kHz) FREQUENCY (kHz) 1999 G12 1999 G13 LT1999-50 Small Signal Gain Error Frequency Response Gain Error vs Temperature vs Input Common Mode Voltage 40 180 0.50 0.50 VCM = 12V V+ = 5V 35 GAIN 135 12 UNITS PLOTTED TA = 25°C 12 UNITS PLOTTED 30 90 0.25 0.25 GAIN (dB)221505 PHASE 40–545 PHASE (DEG) AIN ERROR (%) 0 AIN ERROR (%) 0 G G 10 –90 –0.25 –0.25 LT1999-10 LT1999-10 5 –135 LT1999-20 LT1999-20 VOUT = 0.5VP-P AT 1kHz LT1999-50 LT1999-50 0 –180 –0.50 –0.50 1 10 100 1000 10000 –55 –30 –5 20 45 70 95 120 145 –5 5 15 25 35 45 55 65 75 FREQUENCY (kHz) TEMPERATURE (°C) VCM (V) 1999 G14 1999 G15 1999 G16 1999fd 8 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical perForMance characTerisTics LT1999-10 Pulse Response LT1999-20 Pulse Response LT1999-50 Pulse Response VSENSE VSENSE VSENSE V (0.5V/DIV)SENSE VOUT OUTV (1V/DIV) V (0.2V/DIV)SENSE VOUT OUTV (1V/DIV) V (0.1V/DIV)SENSE VOUT OUTV (1V/DIV) TIME (2µs/DIV) 1999 G17 TIME (2µs/DIV) 1999 G18 TIME (2µs/DIV) 1999 G19 LT1999-10 2V Step Response LT1999-20 2V Step Response Settling Time Settling Time 4.5 0.100 4.5 0.20 4.0 0.075 4.0 0.15 VOUT VOUT 3.5 0.050 3.5 0.10 O O U U 3.0 0.025 TP 3.0 0.05 TP (V)UT 2.5 0 UT ER (V)UT 2.5 0 UT ER O R O R V O V O 2.0 –0.025 R 2.0 –0.05 R OUTPUT ERROR (V) OUTPUT ERROR (V) 1.5 –0.050 1.5 –0.01 1.0 –0.075 1.0 –0.15 0.5 –0.100 0.5 –0.20 TIME (1µs/DIV) 1999 G20 –1 0 1 2 3 4 5 6 7 8 9 10 TIME (1µs/DIV) 1999 G21 LT1999-50 2V Step Response Settling Time CMRR vs Frequency CMRR vs Frequency 4.5 0.500 120 120 LT1999-10 LT1999-10 4.0 0.375 LT1999-20 LT1999-20 100 LT1999-50 100 LT1999-50 VOUT 3.5 0.250 O U 80 80 3.0 0.125 T V (V)OUT22..50 0–0.125PUT ERROR CMRR (dB) 60 CMRR (dB) 60 (V 40 40 ) 1.5 OUTPUT ERROR –0.250 20 VVC+ M= =5 V12V 20 VVC+ M= =5 V0V 1.0 –0.375 TA = 25°C TA = 25°C 6 UNITS PLOTTED 6 UNITS PLOTTED 0.5 –0.500 0 0 TIME (1µs/DIV) 1999 G22 1 10 100 1000 10000 1 10 100 1000 10000 FREQUENCY (kHz) FREQUENCY (kHz) 1999 G23 1999 G24 1999fd 9 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical perForMance characTerisTics LT1999-10 Common Mode Rising LT1999-10 Common Mode Falling Edge Step Response Edge Step Response VCM, tRISE ≈ 20ns VCM, tFALL ≈ 20ns V (0.5V/DIV)OUT CMV (25V/DIV) V (0.5V/DIV)OUT CMV (25V/DIV) VOUT VOUT TIME (0.5µs/DIV) 1999 G25 TIME (0.5µs/DIV) 1999 G26 LT1999-20 Common Mode Rising LT1999-20 Common Mode Falling Edge Step Response Edge Step Response VCM, tRISE ≈ 20ns V) V V) VCM, tFALL ≈ 20ns V DI CM DI CM 5V/ (2 5V/ (2 (0.OUT 5V/DIV (0.OUT 5V/DIV V ) V ) VOUT VOUT TIME (0.5µs/DIV) 1999 G27 TIME (0.5µs/DIV) 1999 G28 LT1999-50 Common Mode Rising Edge Step Response LT1999-50 Common Mode Rising LT1999-50 Common Mode Falling V CM Edge Step Response Edge Step Response tRISE(cid:1)20ns VCM, tRISE ≈ 20ns 0.5 V / div) 25V / div) DIV) CMV DIV) VCM, tFALL ≈ 20ns CMV V (OUT V (CM 5V/ (2 5V/ (2 (0.OUT 5V/DIV (0.OUT 5V/DIV V ) V VOUT ) VOUT TIME (0.5 (cid:1)s / div) TIME (0.5µs/DIV) 1999 G29 TIME (0.5µs/DIV) 1999 G30 1999fd 10 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical perForMance characTerisTics LT1999 Input Referred Noise Short-Circuit Current REF Open Circuit Voltage Density vs Frequency vs Temperature vs Temperature 1000 40 3.0 30 SINKING 2.5 ACTIVE MODE nV/√Hz) 2100 GE (V) 2.0 SHDN MODE OISE DENSITY ( 100 I (mA)SC –100 REF PIN VOLTA 11..05 N –20 SOURCING 0.5 –30 V+ = 5V 10 –40 0 0.001 0.01 0.1 1 10 1000 10000 –55 –30 –5 20 45 70 95 120 145 –55 –30 –5 20 45 70 95 120 145 FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C) 1999 G31 1999 G32 1999 G33 SHDN Pin Current vs SHDN Pin Turn-On/Turn-Off Time Voltage and Temperature vs SHDN Voltage 0 V+ = 5V VCM = 12V VCM = 12V IS S –1 HD N I (µA)SHDN –2 TTTAAA === 12–5550°5C°°CC I (1mA/DIV)S SHUTDOWN PIN VOLTAGE (5 V –3 /DIV VSHDN ) –4 0 1 2 3 4 5 TIME (1µs/DIV) 1999 G35 VSHDN (V) 1999 G34 V vs V Over the Sense OUT SENSE V vs V ABSMAX Range OUT SENSE 6 6 VREF = 2.5V VOUT PHASE REVERSAL FOR VSENSE < –25V 5 5 4 4 V) 3 V) 3 (UT (UT VO 2 VO 2 1 1 LT1999-10 LT1999-10 0 0 LT1999-20 LT1999-20 LT1999-50 VREF = 2.5V LT1999-50 –1 –1 –0.25 –0.15 –0.05 0.05 0.15 0.25 –60 –30 0 30 60 VSENSE (V) VSENSE (V) 1999 G36 1999 G37 1999fd 11 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 pin FuncTions (LT1999-XX/LT1999-XXF) V+ (Pins 1, 4/Pin 4): Power Supply Voltage. Pins 1 and 4 OUT (Pin 7/Pin 7): Voltage Output. V = A •(V ± OUT V SENSE are tied internally together. The specified range of opera- V ), where A is the gain, and V is the input referred OSI V OSI tion is 4.5V to 5.5V, but lower supply voltages (down to offset voltage. The output amplifier has a low impedance approximately 4V) is possible although the LT1999 is not output and is designed to drive up to 200pF capacitive tested or characterized below 4.5V. See the Applications loads directly. Capacitive loads exceeding 200pF should Information section. be decoupled with an external resistor of at least 100Ω. +IN (Pin 2/Pin 1): Positive Sense Input Pin. SHDN (Pin 8/Pin 8): Shutdown Pin. When pulled to within 0.5V of GND (Pin 5), will place the LT1999 into low power –IN (Pin 3/Pin 2): Negative Sense Input Pin. shutdown. If the pin is left floating, an internal 2µA pull- NC (NA/Pin 3) up current source will place the LT1999 into the active (amplifying) state. GND (Pin 5/Pin 5): Ground Pin. REF (Pin 6/Pin 6): Reference Pin Input. The REF pin sets the output common mode level and is set halfway between V+ and GND using a divider made of two 160k resistors. The default open circuit potential of the REF pin is mid-supply. It can be overdriven by an external voltage source cable of driving 80k to a mid-supply potential (see the Electrical Characteristics table for its specified input voltage range). 1999fd 12 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 block DiagraM LT1999 V+ LT1999-XXF V+ V+ 2µA 4k 2µA 1 1 SHDN 8 V+ 0.8k SHDN 8 + RG 0.8k + RG 4k 4k – 2 – 2 – – V+ 0.8k + 7 + 7 V+ V+ 0.8k 160k 160k 4k 3 6 3 NC 6 160k 160k V+ V+ 4 5 4 5 1999 BD 1999 BD Figure 1. Simplified Block Diagram TesT circuiT LT1999 V+ 1 4k LT1999F V+ 5V 1 V+ 2µA +– + V+ 0.8k 2µA SHDN 8 VSHDN VIN(DIFF) SHDN 8 VSHDN + RG VCM +– +– – 0.8k + RG 4k 2 – – 2 4k – – 7 7 +– + V+ 0.8k + VOUT + VOUT VIN(DIFF) V+ 3 V+ VCM +– +– – 4k 0.8k 160k VREF NC 160k VREF 3 6 6 5V V+ 160k 0.1µF 5V V+ 160k 0.1µF 4 5 4 5 0.1µF 0.1µF 1999 F02 1999 F02 Figure 2. Test Circuit 1999fd 13 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion The LT1999 current sense amplifier provides accurate The voltage difference between the OUT pin and the REF bidirectional monitoring of current through a user-selected pin represent both polarity and magnitude of the sensed sense resistor. The voltage generated by the current flowing voltage. The noninverting input of amplifier A is biased O in the sense resistor is amplified by a fixed gain of 10V/V, by a resistive 160k to 160k divider tied between V+ and 20V/V or 50V/V (LT1999-10, LT1999-20, or LT1999-50 GND to set the default REF pin bias to mid-supply. respectively) and is level shifted to the OUT pin. The volt- age difference and polarity of the OUT pin with respect Case 2: –5V < VCM < V+ to REF (Pin 6) indicates magnitude and direction of the For common mode inputs which transition or are set below current in the sense resistor. the supply voltage, diode D1 will turn on and will provide a source of current through R and R to bias the inputs +S –S THEORY OF OPERATION of transconductance amplifier G at least 2.25V above IN GND. The transition is smooth and continuous; there are Refer to the Block Diagram (Figure 1). negligible changes to either gain or amplifier voltage off- Case 1: V+ < V < 80V set. The only difference in amplifier operation is the bias CM currents provided by D1 through R and R are steered +S –S For input common mode voltages exceeding the power through the input pins, otherwise amplifier operation is supply, one can assume D1 of Figure 1 is completely off. identical. The inputs to transconductance amplifier G are IN The sensed voltage (V ) is applied across Pin 2 (+IN) SENSE still forced to equal potentials forcing any differential volt- and Pin 3 (–IN) to matched resistors R and R (nomi- +IN –IN ages appearing at the +IN and –IN pins into a differential nally 4k each). The opposite ends of R and R are +IN –IN current. This differential current is combined, level-shifted, forced to equal potentials by transconductor G , which IN and converted back into a voltage by trans-resistance convert the differentially sensed voltage into a sensed amplifier A and Resistor R . Resistors R and R are O G +S –S current. The sensed current in R and R is combined, +IN –IN trimmed to match R and R respectively, to prevent +IN –IN level-shifted, and converted back into a voltage by trans- common mode to differential conversion from occurring resistance amplifier A and resistor R . Amplifier A pro- O G O (to the extent of the matched trim) when the input com- vides high open loop gain to accurately convert the sensed mon mode transitions below V+. current back into a voltage and to drive external loads. The As described in case 1, the output is determined by the theoretical output voltage is determined by the sensed sense voltage and the ratio of two on-chip resistors: voltage (V ), and the ratio of two on-chip resistors: SENSE R V −V =V •RG VOUT−VREF =VSENSE• G OUT REF SENSE R R IN IN where where R +R R =R+IN +R−IN nominally 4k RIN= +IN −IN IN 2 2 For the LT1999-10, R is nominally 40k. For the LT1999-20, G R is nominally 80k, and for the LT1999-50, R is nomi- G G nally 200k. 1999fd 14 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion Input Common Mode Range –2.0 The LT1999 was optimized for high common mode re- –2.5 jection. Its input stage is balanced and fully differential, –3.0 BELOW GROUND INPUT V) COMMON MODE RANGE dmeosdigen seigdn toa lasm. Tphliefrye d iisff neeregnlitgiaibl sleig cnroaslss aonvde rr edjiesctot crtoiomnm doune (R LIMIT)––43..05 SLIUMPIPTLEYD V BOYL TVA+G E to sense voltage reversals. The amplifier is most linear in WE O BELOW GROUND INPUT the zero-sense region. M(L–4.5 COMMON MODE RANGE VC LIMITED BY ESD CLAMPS –5.0 With the V+ supply configured within the specified and tested range (4.5V < V+ < 5.5V), the LT1999’s common –5.5 TYPICAL ESD CLAMP VOLTAGE mode range extends from –5V to 80V. Pushing +IN and –6.0 4 4.25 4.5 4.75 5 5.25 5.5 –IN beyond the limits specified in the Absolute Maximum SUPPLY VOLTAGE (V) 1999 F03 table can turn on the voltage clamps designed to protect Figure 3. Lower Input Common Mode vs Supply Voltage the +IN and –IN pins during ESD events. It is possible to operate the LT1999 on power supplies Output Common Mode Range as low as 4V (although it is not tested or specified below The LT1999’s output common mode level is set by the 4.5V). Operating the LT1999 on supplies below 4V will voltage on the REF pin. The REF pin sits in the middle of produce erratic behavior. When operating the LT1999 a 160k to 160k voltage divider connected between V+ and with supplies as low as 4V, the common mode range for GND which sets the default open circuit potential of the inputs which extend below GND is reduced. Refer to the Block Diagram (Figure 1). For inputs driven below V+, REF pin to mid-supply. It can be overdriven by an external voltage source capable of driving 80k tied to a mid-supply diode D1 conducts. For proper operation, the input to the potential. See the Electrical Characteristics table for the transconductor V(G ) must be biased at approximately +IN REF pin’s specified input voltage range. 2.25V above the GND pin. V(G ) sits on the centertap +IN of a voltage divider comprised of R+S and R+IN V(G–IN) Differential sampling of the OUT pin with respect the REF likewise sits in the middle of the voltage divider comprised pin provides the best noise immunity. Measurements of of R–S , and R–IN). The voltage on V(G+IN) input is given the output voltage made differentially with respect to the by the following equation: REF pin will provide the highest power supply and com- mon mode rejection. Otherwise, power supply or GND pin V(G+IN)=V+IN• R+S +(V+−VD1)• R+IN disturbances are divided by the REF pin’s voltage divider R +R R +R +S +IN +S +IN and appear directly at the noninverting input of the trans- Setting V(G+IN) = 2.25V, the ratio (R+IN/R+S) to 5, and VD1 resistance amplifier AO and are not rejected. equal to 0.8V (cold temperatures), a plot of the lower input If not driven by a low impedance (<100Ω), the REF pin common mode range plotted against supply is shown in should be filtered with at least 1nF of capacitance to a Figure 3. low impedance, low noise ground plane. This external capacitance will also provide a charge reservoir during high frequency sampling of the REF pin by ADC inputs attached to this pin. 1999fd 15 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion Shutdown Capability the bandwidth of the LT1999 that may introduce errors. The pole is set by the following equation: If SHDN (Pin 8) is driven to within 0.5V of GND, the LT1999 is placed into a low power shutdown state in which the f = 1/(π•(R + R )•C ) ≈ 10MHz filt +IN –IN F part will draw about 3μA from the V+ supply. The input Both the resistors and capacitors have a ±15% variation pins (+IN and –IN) will draw approximately 1nA if biased so the pole can vary by approximately ±30% over manu- within the range of 0V to 80V (with no differential voltage facturing process and temperature variations. applied). If the input pins are pulled below the GND pin, each input appears as a diode tied to GND in series with The layout for lowest EMI/noise susceptibility is achieved approximately 4k of resistance. The REF pin appears as by keeping short direct connections and minimizing loop approximately 0.4MΩ tied to a mid-supply potential. The areas (see Figure 4). If the user-supplied sense resistor output appears as reverse biased diodes tied between the cannot be placed in close proximity to the LT1999, the output to either V+ or GND pins. surface area of the loop comprising connections of +IN to R and back to –IN should be minimized. This SENSE EMI Filtering and Layout Practices requires routing PCB traces connecting +IN to R SENSE and –IN to R adjacent with one another with minimal An internal 1st order differential lowpass noise/EMI SENSE separation. The metal traces connecting +IN to the sense suppression filter with a –3dB bandwidth of 10MHz (ap- resistor and –IN to the sense resistor should match and proximately 5× the LT1999’s –3dB bandwidth) is included use the same trace width. to help improve the LT1999’s EMI susceptibility and to assist with the rejection of high frequency signals beyond Bypassing the V+ pin to the GND pin with a 0.1µF capacitor with short wiring connection is recommended. † 1 V+ SHDN 8 FROM DC SOURCE 2 +IN OUT 7 DIFFERENTIAL RSENSE * ANALOG OUT 3 –IN REF 6 TO LOAD 4 V+ GND 5 ** SUPPLY BYPASS CAPACITOR 1999 F03 * KEEP LOOP AREA COMPRISING RSENSE, +IN AND –IN PINS AS SMALL AS POSSIBLE. ** REF BYPASS TIED TO A LOW NOISE, LOW IMPEDANCE SIGNAL GROUND PLANE. † OPTIONAL 10pF CAPACITOR TO PREVENT dV/dt EDGES ON INPUT COUPLING TO FLOATING SHDN PIN. Figure 4. Recommended Layout 1999fd 16 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion The REF pin should be either driven by a low source im- Selection of the Current Sense Resistor pedance (<100Ω) or should be bypassed with at least 1nF The external sense resistor selection presents a delicate to a low impedance, low noise, signal ground plane (see trade-off between power dissipation in the resistor and Figure 4). Larger bypass capacitors on both V+ pins, and current measurement accuracy. the REF pin, will extend enhanced AC CMRR, and PSRR performance to lower frequencies. Bypassing the REF pin In high current applications, the user may want to minimize to a quiet ground plane filters the V+ pin or GND pin noise the power dissipated in the sense resistor. The sense re- that is sensed by the REF pin voltage divider and applied sistor current will create heat and voltage loss, degrading to the noninverting input of output amplifier A . Any com- efficiency. As a result, the sense resistor should be as O mon I•R drops generated by pulsating ground currents in small as possible while still providing adequate dynamic common with the REF pin filter capacitor can compromise range required by the measurement. The dynamic range is the filtering performance and should be avoided. the ratio between the maximum accurately produced signal generated by the voltage across the sense resistor, and If the SHDN pin is not driven and is left floating, routing the minimum accurately reproduced signal. The minimum a PCB trace connecting Pins 1 and 8 under the part will accurately reproduced signal is primarily dictated by the act as a shield, and will help limit edge coupling from the voltage offset of the LT1999. The maximum accurately inputs (Pins 2 and 3) to the SHDN pin. Periodic pulses on reproduced signal is dictated by the output swing of the the inputs with fast edges may glitch the high impedance LT1999. SHDN pin, periodically putting the part into low power shutdown. Additional precaution against this may be taken Thus the dynamic range for the LT1999 can be thought of by adding an optional small (~10pF) capacitor may be tied the maximum sense voltage divided by the input referred between V+ (Pin 1) and Pin 8. voltage offset or: ΔV Finally, when connecting the LT1999 inputs to the sense OUT(MAX) Dynamic Range= resistor, it is important to use good Kelvin sensing prac- GAIN•VOSI tices (sensing the resistor in a way that excludes PCB trace The above equation tells us that the dynamic range is I•R voltage drops). For sense resistors less than 1Ω, one inversely proportional to the gain of the LT1999. Thus, might consider using a 4-wire sense resistor to sense the if accuracy is of greater importance than efficiency or resistive element accurately. power loss, the LT1999-10 used with the highest valued sense resistor possible is recommended. If efficiency, heat generated, and power loss in the resistive shunt is the primary concern, the LT1999-50 and the lowest value sense resistor possible is recommended. The LT1999-20 is available for applications somewhere in between these two extremes. 1999fd 17 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion Pinout Option Engineered for FMEA (Failure Mode and The purpose of the FMEA is to emulate single faults and Effects Analysis) determine whether or not they are destructive and/or lead to conditions which could damage surrounding The LT1999 family of ICs is available with an 8-lead components. The LT1999-XXF is configured as shown MSOP pinout option engineered for FMEA (Failure Mode in Figure 2, with an input common mode of either 12V and Effects Analysis): (LT1999-10F, LT1999-20F and the or 0V. Each pin is systematically shorted to its adjacent LT1999-50F). See Figure 5 below. pin (emulating solder bridging) and the resulting effects The LT1999-XXF is designed to meet the most stringent recorded. Each pin is then opened (emulating a cold solder automotive requirements and to satisfactorily survive single joint) with the resulting effects recorded. faults due to the most common PCB defects: 1) open pins In all instances, the LT1999-XXF recovers when these due to cold solder joints and 2) adjacent pin short circuits fault conditions are removed. Furthermore, the output pin due to adjacent pin solder bridging. The No-Connect Pin (OUT) has been verified to never exceed the pin’s nominal (Pin 3) has been inserted between the input pin (–IN) output range of 0V to 5V during fault testing. and the V+ supply pin to isolate the input voltages which may range from –5V to 80V from solder bridging to the Table 1 lists the behavior which results from shorting V+ supply (typically 5V). Pin 3 is not connected internally adjacent pins and Table 2 details the behavior from open- to the die and should be left unconnected. ing any pin. V+ R+IN 2µA +IN 2k 2k 4.5k 1 SHDN 8 0.8k CF V+ +G RG 4pF – –IN 2k 2k 0.8k – OUT 2 7 + V+ R–IN 300Ω 160k REF 3 NC 6 160k V+ GND 4 5 1999 F05a Figure 5. Simplified Block Diagram of the LT1999-XXF 1999fd 18 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion Table 1: Behavior due to Adjacent Pin-to-Pin Shorts for the LT1999-10F, LT1999-20F, or the LT1999-50F Adjacent Pin Short Test: (V+ = 5V, Tested at V = 0V, V = 12V, V = 80V) CM CM CM Adjacent Pins Recovery when PIN # Shorted Fault is removed BEHAVIOR 1 – 2 +IN – –IN YES V approaches the voltage on pin V . OUT REF 2 – 3 –IN – NC YES The circuit behaves normally. 3 – 4 NC – V+ YES The circuit behaves normally. 5 – 6 GND – REF YES V follows the voltage on Pin 6 or 0V. OUT 6 – 7 REF – OUT YES V approaches 5.0V OUT 7 – 8 OUT – SHDN YES Supply Current drops by 5%. Table 2: Behavior due to open pins for the LT1999-10F, LT1999-20F, or the LT1999-50F Open Pin Test (V+ = 5V, Tested at V = 0V, V = 12V, V = 80V) CM CM CM Recovery when PIN # Pin Opened Fault is removed BEHAVIOR 1 +IN YES V may go to either V+ or GND, depending on the voltage applied to –IN. Generally, for –5V< –IN< 4V, OUT OUT will be near 5V. For –IN > 5V, OUT will be near 0V. In the range of 4V < –IN < 5V, OUT may go to either V+ or GND, depending on the voltage applied to –IN. The open input (+IN) is biased internal to the IC to one diode below V+. 2 –IN YES V may go to either V+ or GND, depending on the voltage applied to +IN. Generally, for –5V < +IN < 4V, OUT OUT will be near 0V. For +IN > 5V, OUT will be at 5V. In the range of 4V < –IN < 5V, OUT may go to either V+ or GND, depending on the voltage applied to +IN. The open input (–IN) is biased internal to the IC to one diode below V+. 3 NC YES The circuit behaves normally. 4 V+ YES The circuit will behave as if powered off. 5 GND YES OUT, REF will float up towards 3.9V. 6 REF YES The circuit behaves normally with more broadband noise on OUT. 7 OUT YES No V signal. OUT 8 SHDN YES The low power shutdown feature will not function, otherwise the circuit behaves normally in the active state. FMEA information in this document (not limited to, but including the description of behavior under specific pin-connection conditions) is provided for convenience only. Ultimately, the end-user is responsible for verifying proper and reliable operation in each actual application. Linear Technology assumes no liability whatsoever with providing this information. 1999fd 19 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 applicaTions inForMaTion Fuse Monitor power in the precision on-chip input resistors. Precaution should be taken to prevent junction temperatures from The inputs can be overdriven without fear of damaging exceeding the Absolute Maximum ratings (see Note 3 in the the LT1999. This makes the LT1999 ideal for monitoring Electrical Characteristics section). Secondly, if the load is fuses if either +IN or –IN are shorted to ground while the inductive, and the fuse blows open without a clamp diode, other is at the full common mode supply voltage (see energy stored in the inductive load will be dissipated in Figure 6). If the fuse in Figure 6 opens with the +IN tied the LT1999, which could cause damage. A simple steering to the positive supply, the load will pull –IN to GND. The diode as shown in Figure 6 will prevent this from happen- output will be forced to the positive V+ supply rail. If it is ing, and will protect the LT1999 from damage. desired that the output be near ground if the fuse opens, it is a simple matter of swapping the inputs. Precautions Finally, the user should be aware that in fuse monitoring should be followed: First, when the inputs are stressed applications with the sense voltage (V = V – V ) SENSE +IN –IN differentially due to the fuse blowing open, a large voltage being driven in excess of –25V, the output of the LT1999 drop will be placed across the +IN to –IN pins, dissipating will undergo phase reversal (see Figure 7). VS LT1999 V+ 5V V+ 2µA ON OFF VSHDN 1 SHDN 8 VSHDN ILOAD + RG – V+IN 2 4k – 7 VOUT V+ VOUT FUSE 0.8k + V+ VREF RSVE–NISNE 3 4k 0.8k 160k 6 VREF 5V V+ 160k 0.1µF STEERING LOAD DIODE 4 5 0.1µF 1999 F05 Figure 6. Using the LT1999 to Monitor a Fuse VOUT PHASE REVERSAL FOR VSENSE < –25V V) DI V/ 1 (UT O V VREF = 2.5V –60 –45 –30 –15 0 15 30 45 60 VSENSE (V) 1999 F06 Figure 7. A Plot of the LT1999’s Output Voltage vs VSENSE (VSENSE = V+IN – V–IN). In Applications Where the Sense Voltage Is Driven in Excess of –25V, the Output of the LT1999 Will Undergo Phase Reversal 1999fd 20 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical applicaTions Solenoid Current Monitor Bidirectional PWM Motor Monitor The solenoid of Figure 8 consists of a coil of wire in an Pulse width modulation is commonly used to efficiently iron case with permeable plunger that acts as a movable vary the average voltage applied across a DC motor. The element. When the MOSFET turns on, the diode is reversed H-bridge topology of Figure 10 allows full 4-quadrant biased off, and current flows through R to actuate control: clockwise control, counter-clockwise control, SENSE the solenoid. If the MOSFET is turned off, the current clockwise regeneration, and counter-clockwise regen- in the MOSFET is interrupted, but the energy stored in eration. The LT1999 in conjunction with a non-inductive the solenoid causes the diode to turn on and current to current shunt is used to monitor currents in the rotor. freewheel in the loop consisting of the diode, R and The LT1999 can be used to detect stuck rotors, provide SENSE the solenoid. detection of overcurrent conditions in general, or provide current mode feedback control. Figure 8 shows the LT1999 monitoring currents in a ground referenced solenoid used when the coil is hard Figure 11 shows a plot of the output voltage of the LT1999. tied to the case, and is tied to ground. Figure 9 shows a supply referenced solenoid whose coil is insulated from the case. The LT1999 will interface equally well to either of these two configurations. VS LT1999 V+ OFF 5V V+ 2µA ON 1 SHDN 8 VSHDN + RG – V+IN 2 4k – 7 V+ 0.8k + VOUT VOUT 2.5V RSENSEV–IN5V 3 V+4k 0.8k V+116600kk 6 VREF 0.1µF V (0.5V/DIV)OUT SOLENOID PLUNSGOELRE NPOUILDL SR EINLEASES +INV (10V/DIV) V+IN SOLENOID 4 5 0.1µF 1999 F07a TIME (50ms/DIV) 1999 F07b Figure 8. Solenoid Current Monitor for Ground Tied Solenoid. The Common Mode Inputs to the LT1999 Switch Between V and One Diode Drop Below Ground S 1999fd 21 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical applicaTions VS LT1999 V+ 5V V+ 2µA 1 SHDN 8 VSHDN SOLENOID + RG – V+IN 2 4k – 7 V+ 0.8k + VOUT ON RSENSEV–IN5V 3 V+4k 0.8k V+116600kk 6 VREF 0.1µF V (0.5V/DIV)OUT SOLENOID PLUNSGVOEOLRUET NPOUILDL SR EINLVE+AINSES 2.5V+INV (10V/DIV) OFF 4 5 0.1µF 1999 F08a TIME (50ms/DIV) 1999 F08b Figure 9. Solenoid Current Monitor for Non-Grounded Solenoids. This Circuit Performs the Same Function as Figure 7 Except One End of the Solenoid Is Tied to V . The Common Mode S Voltage of Inputs of the LT1999 Switch Between Ground and One Diode Drop Above V S 1999fd 22 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 Typical applicaTions 5V V+ LT1999-20 V+ 10µF 1 2µA SHDN 8 VSHDN + 80k 0.1µF 24V – 2 4k – C4 V+IN V+ 0.8k + 7 VOUT 1000µF V–IN V+ 3 4k 0.8k 160k H-BRIDGE VBRIDGE 6 VREF 160k 5V 0.1µF 5V V+ 5 4 PWM INPUT RSENSE 1999 F09 0.025Ω OUTA PWM IN DIRECTION 24V MOTOR OUTB BRAKE INPUT GND Figure 10. Armature Current Monitor for DC Motor Applications VOUT 2.5V DIV) +INV (2V/UT (20V/D VO V+IN IV) TIME (20µs/DIV) 1999 F10 Figure 11. LT1999 Output Waveforms for the Circuit of Figure 10 1999fd 23 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev G) 3.00 ±0.102 (.118 ±.004) 0.52 (NOTE 3) 8 7 6 5 (.0205) REF 3.00 ±0.102 4.90 ±0.152 0.889 ±0.127 DETAIL “A” (.118 ±.004) (.035 ±.005) 0.254 (.193 ±.006) (NOTE 4) (.010) 0° – 6° TYP GAUGE PLANE 5.10 1 2 3 4 (.M20IN1) (3.1.2206 –– 3.1.4356) (0..05231 ± ±0..010562) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 0.42 ± 0.038 0.65 (.007) (.0165 ±.0015) (.0256) SEATING TYP BSC PLANE 0.22 – 0.38 0.1016 ±0.0508 RECOMMENDED SOLDER PAD LAYOUT (.009 – .015) (.004 ±.002) TYP 0.65 MSOP (MS8) 0213 REV G (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .189 – .197 .045 ±.005 (4.801 – 5.004) .050 BSC NOTE 3 8 7 6 5 .245 MIN .160 ±.005 .150 – .157 .228 – .244 (3.810 – 3.988) (5.791 – 6.197) NOTE 3 .030 ±.005 TYP 1 2 3 4 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° .053 – .069 (0.254 – 0.508) (1.346 – 1.752) .004 – .010 .008 – .010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) .016 – .050 .014 – .019 .050 (0.406 – 1.270) (0.355 – 0.483) (1.270) NOTE: INCHES TYP BSC 1. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 REV G 0212 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 1999fd 24 For more information www.linear.com/LT1999

LT1999-10/LT1999-20/ LT1999-50 revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 5/11 Revised +IN and –IN pin descriptions in Pin Functions section 12 B 3/12 Revised Voltage Output Swing Low specification (V ) under a loaded condition of 1kΩ to mid-supply. 4, 6 OUT Updated Figure 4 to multicolor. 16 C 2/15 Addition of MSOP Pinout Option Engineered for FMEA All Correction to AV Specification for LT1999-50 from 48.75 to 49.75 5 Update to Pin Functions to include Pinout Option Engineered for FMEA 12 Addition of New Application Information "Pinout Option Engineered for FMEA" 18, 19 Addition of Figure 5 and Renumbering of Figures 6 to 11 18 to 23 Addition of Table 1 and Table 2 19 D 6/15 LT1999F added to Figure 1 (Simplified Block Diagram) 13 LT1999F added to Figure 2 (Test Circuit) 14 Additional test condition (V = 80) added to table 1 and table 2 19 CM Note added regarding the use of FMEA information 19 1999fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 25 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnecFtioorn mof oitrse c iirncfuoitrsm asa dtieosncr wibewdw h.elrineiena wr.icll onmot /inLTfr1in9g9e 9on existing patent rights.

LT1999-10/LT1999-20/ LT1999-50 Typical applicaTion Battery Charge Current and Load Current Monitor V = 0.25V/A, Maximum Measured Current ±9.5A OUT 0.025Ω CHARGER BAT 42V LOAD LT1999-10 V+ 5V 5V V+ 2µA 0.1µF 1 SHDN 8 VSHDN 0.1µF 10µF + 40k – V+IN 2 4k – 7 VOUT V+ 0.8k + + +IN VCC VREF CS V+ VOUT LTC2433-1 SCK V–IN 3 4k 0.8k 160k 6 VREF – –IN SDO 5V V+ 160k 0.1µF 4 5 0.1µF 1999 TA02 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LT1787/ Precision, Bidirectional High Side Current Sense Amplifier 2.7V to 60V Operation, 75μV Offset, 60μA Current Draw LT1787HV LT6100 Gain-Selectable High Side Current Sense Amplifier 4.1V to 48V Operation, Pin-Selectable Gain: 10V/V, 12.5V/V, 20V/V, 25V/V, 40V/V, 50V/V LTC6101/ High Voltage High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, External Resistor Set Gain, SOT23 LTC6101HV LTC6102/ Zero Drift High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, ±10μV Offset, 1μs Step Response, LTC6102HV MSOP8/DFN Packages LTC6103 Dual High Side Precision Current Sense Amplifier 4V to 60V, Gain Configurable, 8-Pin MSOP Package LTC6104 Bidirectional, High Side Current Sense 4V to 60V, Gain Configurable, 8-Pin MSOP Package LT6106 Low Cost, High Side Precision Current Sense Amplifier 2.7V to 36V, Gain Configurable, SOT23 Package LT6105 Precision, Extended Input Range Current Sense Amplifier –0.3 to 44V, Gain Configurable, 8-Pin MSOP Package LTC4150 Coulomb Counter/Battery Gas Gauge Indicates Charge Quantity and Polarity LT1990 Precision, 100μA Gain Selectable Amplifier 2.7V to 36V Operation, CMRR > 70dB, Input Voltage = ±250V LT1991 ±250V Input Range Difference Amplifier 2.7V to 36V Operation, 50μV Offset, CMRR > 75B, Input Voltage = ±60V LT1637/LT1638 1.1/1.2MHz, 0.4V/μs Over-The-Top, Rail-to-Rail Input and 0.4V/μs Slew Rate, 230μA per Amplifier Output Amplifier 1999fd 26 Linear Technology Corporation LT 0615 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT1999 ((440088)) 443322--11990000 ll FFAAXX:: ((440088)) 443344--00550077 l l w wwwww.l.ilnineeaar.cr.coomm/LT1999  LINEAR TECHNOLOGY CORPORATION 2010