Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 LP2998/LP2998-Q1 DDR Termination Regulator 1 Features 3 Description • AEC-Q100TestGuidancewiththefollowing The LP2998 linear regulator is designed to meet 1 JEDEC SSTL-2 and JEDEC SSTL-18 specifications results(SOPowerPAD-8): for termination of DDR-SDRAM and DDR2 memory. – DeviceHBMESDClassificationLevelH1C The device also supports DDR3 and DDR3L VTT bus – JunctionTemperatureRange –40°Cto125°C termination with V min of 1.35 V. The device DDQ • 1.35VMinimumV contains a high-speed operational amplifier to provide DDQ excellent response to load transients. The output • SourceandSinkCurrent stage prevents shoot through while delivering 1.5 A • LowOutputVoltageOffset continuous current and transient peaks up to 3 A in • NoExternalResistorsRequired the application as required for DDR-SDRAM termination. The LP2998 also incorporates a • LinearTopology VSENSE pin to provide superior load regulation and • SuspendtoRam(STR)Functionality a V output as a reference for the chipset and REF • LowExternalComponentCount DIMMs. • ThermalShutdown An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend 2 Applications To RAM (STR) functionality. When SD is pulled low the V output will tri-state providing a high • DDR1,DDR2,DDR3,andDDR3LTermination TT impedance output, but, V will remain active. A Voltage REF power savings advantage can be obtained in this • AutomotiveInfotainment modethroughlowerquiescentcurrent. • FPGA DeviceInformation(1) • Industrial/MedicalPC PARTNUMBER PACKAGE BODYSIZE(NOM) • SSTL-18,SSTL-2,andSSTL-3Termination LP2998 SOPowerPAD™(8) 4.89mmx3.90mm • HSTLTermination LP2998 SOIC(8) 4.90mmx3.91mm LP2998-Q1 SOPowerPAD™(8) 4.89mmx3.90mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic LP2998 SD SD VREF VREF = 0.75V + VDDQ = 1.5V VDDQ CREF VDD = 2.5V AVIN VSENSE PVIN VTT VTT = 0.75V + + CIN GND COUT 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram ......................................11 2 Applications........................................................... 1 8.3 FeatureDescription.................................................11 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................11 4 SimplifiedSchematic............................................. 1 9 ApplicationandImplementation........................ 13 9.1 ApplicationInformation ..........................................13 5 RevisionHistory..................................................... 2 9.2 TypicalApplication..................................................15 6 PinConfigurationandFunctions......................... 3 10 PowerSupplyRecommendations..................... 20 6.1 PinDescriptions........................................................3 11 Layout................................................................... 20 7 Specifications......................................................... 5 11.1 LayoutGuidelines.................................................20 7.1 AbsoluteMaximumRatings .....................................5 11.2 LayoutExamples...................................................21 7.2 HandlingRatings:LP2998........................................5 12 DeviceandDocumentationSupport................. 22 7.3 HandlingRatings:LP2998-Q1..................................5 7.4 RecommendedOperatingConditions.......................5 12.1 RelatedLinks........................................................22 7.5 ThermalInformation..................................................5 12.2 Trademarks...........................................................22 7.6 ElectricalCharacteristics...........................................6 12.3 ElectrostaticDischargeCaution............................22 7.7 TypicalCharacteristics..............................................8 12.4 Glossary................................................................22 8 DetailedDescription............................................ 11 13 Mechanical,Packaging,andOrderable Information........................................................... 22 8.1 Overview.................................................................11 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionJ(December2013)toRevisionK Page • AddedDDR3supportthroughoutdatasheet.......................................................................................................................... 1 • ChangedformattingtomatchnewTIdatasheetguidelines;addedDeviceInformationandHandlingRatingstables, PowerSupply,LayoutExamples,andDeviceandDocumentationSupportsections;reformattedDetailed DescriptionandApplicationandImplementationsections. ................................................................................................... 1 • ChangedElectricalChartableconditionstatement .............................................................................................................. 6 • ChangedElectricalChartableconditionstatement .............................................................................................................. 7 ChangesfromRevisionI(April2013)toRevisionJ Page • AddedAEC-Q100TestGuidance.......................................................................................................................................... 1 • ChangedlayoutofNationalDataSheettoTIformat........................................................................................................... 20 2 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 6 Pin Configuration and Functions SOPowerPAD 8-LEADDDA TOPVIEW GND 1 8 VTT SD 2 7 PVIN GND VSENSE 3 6 AVIN VREF 4 5 VDDQ SOIC 8-LEADD TOPVIEW GND 1 8 VTT SD 2 7 PVIN VSENSE 3 6 AVIN VREF 4 5 VDDQ PinFunctions PIN NUMBER TYPE DESCRIPTION 1 GND Ground 2 SD Shutdown 3 VSENSE FeedbackpinforregulatingV . TT 4 VREF BufferedinternalreferencevoltageofV /2 DDQ 5 VDDQ InputforinternalreferenceequaltoV /2 DDQ 6 AVIN Analoginputpin 7 PVIN Powerinputpin 8 VTT Outputvoltageforconnectiontoterminationresistors EP Exposedpadthermalconnection.ConnecttoGround. 6.1 Pin Descriptions AVINANDPVIN AVINandPVINaretheinputsupplypinsfortheLP2998.AVINisusedtosupplyalltheinternalcontrolcircuitry.PVIN, however,isusedexclusivelytoprovidetherailvoltagefortheoutputstageusedtocreateVTT.Thesepinshavethe capabilitytoworkoffseparatesuppliesdependingontheapplication.HighervoltagesonPVINwillincreasethe maximumcontinuousoutputcurrentbecauseofoutputRDSONlimitationsatvoltagesclosetoVTT.Thedisadvantage ofhighvaluesofPVINisthattheinternalpowerlosswillalsoincrease,thermallylimitingthedesign.ForSSTL-2 applications,agoodcompromisewouldbetoconnecttheAVINandPVINdirectlytogetherat2.5V.Thiseliminatesthe needforbypassingthetwosupplypinsseparately.TheonlylimitationoninputvoltageselectionisthatPVINmustbe equaltoorlowerthanAVIN.ItisrecommendedtoconnectPVINtovoltagerailsequaltoorlessthan3.3Vtoprevent thethermallimitfromtrippingbecauseofexcessiveinternalpowerdissipation.Ifthejunctiontemperatureexceedsthe thermalshutdownthanthepartwillenterashutdownstateidenticaltothemanualshutdownwhereV istri-statedand TT V remainsactive. REF VDDQ VDDQistheinputusedtocreatetheinternalreferencevoltageforregulatingV .Thereferencevoltageisgenerated TT fromaresistordivideroftwointernal50kΩresistors.ThisensuresthatV willtrackVDDQ/2precisely.Theoptimal TT implementationofVDDQisasaremotesense.ThiscanbeachievedbyconnectingVDDQdirectlytothe2.5Vrailat theDIMMinsteadofAVINandPVIN.ThisensuresthatthereferencevoltagetrackstheDDRmemoryrailsprecisely withoutalargevoltagedropfromthepowerlines.ForSSTL-2applicationsVDDQwillbea2.5Vsignal,whichwill createa1.25VterminationvoltageatV (SeeElectricalCharacteristicsTableforexactvaluesofV over TT TT temperature). Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Pin Descriptions (continued) Thepurposeofthesensepinistoprovideimprovedremoteloadregulation.Inmostmotherboardapplicationsthe V SENSE terminationresistorswillconnecttoV inalongplane.Iftheoutputvoltagewasregulatedonlyattheoutputofthe TT LP2998thenthelongtracewillcauseasignificantIRdropresultinginaterminationvoltageloweratoneendofthebus thantheother.TheV pincanbeusedtoimprovethisperformance,byconnectingittothemiddleofthebus.This SENSE willprovideabetterdistributionacrosstheentireterminationbus.IfremoteloadregulationisnotusedthentheV SENSE pinmuststillbeconnectedtoV .CareshouldbetakenwhenalongV traceisimplementedincloseproximityto TT SENSE thememory.NoisepickupintheV tracecancauseproblemswithpreciseregulationofV .Asmall0.1uF SENSE TT ceramiccapacitorplacednexttotheV pincanhelpfilteranyhighfrequencysignalsandpreventingerrors. SENSE SHUTDOWN TheLP2998containsanactivelowshutdownpinthatcanbeusedtotri-stateVTT.DuringshutdownV shouldnotbe TT exposedtovoltagesthatexceedAVIN.WiththeshutdownpinassertedlowthequiescentcurrentoftheLP2998will drop,however,V willalwaysmaintainitsconstantimpedanceof100kΩforgeneratingtheinternalreference. DDQ Therefore,tocalculatethetotalpowerlossinshutdownbothcurrentsneedtobeconsidered.Formoreinformationrefer totheThermalDissipationsection.Theshutdownpinalsohasaninternalpull-upcurrent,thereforetoturntheparton theshutdownpincaneitherbeconnectedtoAVINorleftopen. V V providesthebufferedoutputoftheinternalreferencevoltageVDDQ/2.Thisoutputshouldbeusedtoprovidethe REF REF referencevoltagefortheNorthbridgechipsetandmemory.Sincetheseinputsaretypicallyanextremelyhigh impedance,thereshouldbelittlecurrentdrawnfromV .Forimprovedperformance,anoutputbypasscapacitorcan REF beused,locatedclosetothepin,tohelpwithnoise.Aceramiccapacitorintherangeof0.1µFto0.01µFis recommended.Thisoutputremainsactiveduringtheshutdownstateandthermalshutdowneventsforthesuspendto RAMfunctionality. V V istheregulatedoutputthatisusedtoterminatethebusresistors.Itiscapableofsinkingandsourcingcurrentwhile TT TT regulatingtheoutputpreciselytoVDDQ/2.TheLP2998isdesignedtohandlepeaktransientcurrentsofupto±3A withafasttransientresponse.ThemaximumcontinuouscurrentisafunctionofV andcanbeviewedintheTypical IN Characteristicssection.Ifatransientisexpectedtolastabovethemaximumcontinuouscurrentratingforasignificant amountoftimethentheoutputcapacitorshouldbesizedlargeenoughtopreventanexcessivevoltagedrop.Despite thefactthattheLP2998isdesignedtohandlelargetransientoutputcurrentsitisnotcapableofhandlingtheseforlong durations,underallconditions.Thereasonforthisisthestandardpackagesarenotabletothermallydissipatetheheat asaresultoftheinternalpowerloss.Iflargecurrentsarerequiredforlongerdurations,thencareshouldbetakento ensurethatthemaximumjunctiontemperatureisnotexceeded.Properthermalderatingshouldalwaysbeused(please refertotheThermalDissipationsection).IfthejunctiontemperatureexceedsthethermalshutdownpointthanV will TT tri-stateuntilthepartreturnsbelowthehysteretictrip-point. 4 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 7 Specifications 7.1 Absolute Maximum Ratings (1)(2) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT AVINtoGND −0.3 6 V PVINtoGND –0.3 AVIN V VDDQ(3) −0.3 6 V Junctiontemperature 150 °C Leadtemperature(soldering,10sec) 260 °C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute–maximum–ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) VDDQvoltagemustbelessthan2x(AVIN-1)or6V,whicheverissmaller. 7.2 Handling Ratings: LP2998 MIN MAX UNIT T Storagetemperaturerange −65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all V(ESD) Electrostaticdischarge pins(1) −1000 1000 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Handling Ratings: LP2998-Q1 MIN MAX UNIT T Storagetemperaturerange −65 150 °C stg V Electrostaticdischarge Humanbodymodel(HBM),perAECQ100-002(1) −1000 1000 V (ESD) (1) AECQ100-002indicatesHBMstressingisdoneinaccordancewiththeANSI/ESDA/JEDECJS-001specification.TheLP2998-Q1is ratedatAEC-Q100ESDHBMClassificationLevelH1C. 7.4 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Junctiontemperature(1) –40 125 °C AVINtoGND 2.2 5.5 V PVINsupplyvoltage 0 AVIN V SDinputvoltage 0 AVIN V (1) Atelevatedtemperatures,devicesmustbederatedbasedonthermalresistance. 7.5 Thermal Information LP2998/LP2998-Q1 LP2998 THERMALMETRIC(1) SOPowerPAD SOIC UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 43 151 °C/W θJA (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com 7.6 Electrical Characteristics TypicallimitstestedatT =25°C.Minimumandmaximumlimitsapplyoverthefulloperatingjunctiontemperaturerange(T = J J –40°Cto125°C).(1)Unlessotherwisespecified,AVIN=PVIN=2.5V,VDDQ=2.5V.(2) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VIN=VDDQ=2.3V 1.135 1.158 1.185 V voltage(DDRI) VIN=VDDQ=2.5V 1.235 1.258 1.285 REF VIN=VDDQ=2.7V 1.335 1.358 1.385 PVIN=VDDQ=1.7V 0.837 0.860 0.887 V V voltage(DDRII) PVIN=VDDQ=1.8V 0.887 0.910 0.937 V REF REF PVIN=VDDQ=1.9V 0.936 0.959 0.986 PVIN=VDDQ=1.35V 0.669 0.684 0.699 V Voltage(DDRIII) PVIN=VDDQ=1.5V 0.743 0.758 0.773 REF PVIN=VDDQ=1.6V 0.793 0.808 0.823 Z V OutputImpedance I =–30to30µA 2.5 kΩ VREF REF REF I =0A OUT VIN=VDDQ=2.3V 1.120 1.159 1.190 VIN=VDDQ=2.5V 1.210 1.259 1.290 VIN=VDDQ=2.7V 1.320 1.359 1.390 V V OutputVoltage(DDRI) (3) V TT TT I =±1.5A OUT VIN=VDDQ=2.3V 1.125 1.159 1.190 VIN=VDDQ=2.5V 1.225 1.259 1.290 VIN=VDDQ=2.7V 1.325 1.359 1.390 I =0A,AVIN=2.5V OUT PVIN=VDDQ=1.7V 0.822 0.856 0.887 PVIN=VDDQ=1.8V 0.874 0.908 0.939 PVIN=VDDQ=1.9V 0.923 0.957 0.988 V OutputVoltage(DDRII) (3) V TT I =±0.5A,AVIN=2.5V OUT PVIN=VDDQ=1.7V 0.820 0.856 0.890 PVIN=VDDQ=1.8V 0.870 0.908 0.940 PVIN=VDDQ=1.9V 0.920 0.957 0.990 I =0A,AVIN=2.5V OUT PVIN=VDDQ=1.35V 0.656 0.677 0.698 PVIN=VDDQ=1.5V 0.731 0.752 0.773 PVIN=VDDQ=1.6V 0.781 0.802 0.823 I =0.2A,AVIN=2.5V OUT 0.667 0.688 0.710 PVIN=VDDQ=1.35V I =-0.2A,AVIN=2.5V OUT 0.641 0.673 0.694 V OutputVoltage(DDRIII) (3) PVIN=VDDQ=1.35V V TT I =0.4A,AVIN=2.5V OUT 0.740 0.763 0.786 PVIN=VDDQ=1.5V I =–0.4A,AVIN=2.5V OUT 0.731 0.752 0.773 PVIN=VDDQ=1.5V I =0.5A,AVIN=2.5V OUT 0.790 0.813 0.836 PVIN=VDDQ=1.6V I =–0.5A,AVIN=2.5V OUT 0.781 0.802 0.823 PVIN=VDDQ=1.6V (1) Limitsare100%productiontestedat25°C.Limitsovertheoperatingtemperaturerangearespecifiedthroughcorrelationusing StatisticalQualityControl(SQC)methods.ThelimitsareusedtocalculateTexasInstruments'AverageOutgoingQualityLevel(AOQL). (2) VINisdefinedasVIN=AVIN=PVIN. (3) V loadregulationistestedbyusinga10mscurrentpulseandmeasuringV . TT TT 6 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 Electrical Characteristics (continued) TypicallimitstestedatT =25°C.Minimumandmaximumlimitsapplyoverthefulloperatingjunctiontemperaturerange(T = J J –40°Cto125°C).(1)Unlessotherwisespecified,AVIN=PVIN=2.5V,VDDQ=2.5V.(2) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I =0A –30 0 30 OUT V OutputVoltageOffset(V – VTT)forDDRI (3) REF IOUT=–1.5A –30 0 30 TT I =1.5A –30 0 30 OUT I =0A –30 0 30 OUT V OutputVoltageOffset(V – VOSVtt VTTTT)forDDRII (3) REF IOUT=–0.5A –30 0 30 mV I =0.5A –30 0 30 OUT I =0A –30 0 30 OUT VTTOutputVoltageOffset(VREF– IOUT=±0.2A –30 0 30 VTT)forDDRIII (3) IOUT=±0.4A –30 0 30 I =±0.5A –30 0 30 OUT I QuiescentCurrent (4) I =0A 320 500 µA Q OUT Z VDDQInputImpedance 100 kΩ VDDQ I Quiescentcurrentinshutdown (4) SD=0V 115 150 SD µA I Shutdownleakagecurrent SD=0V 2 5 Q_SD V MinimumShutdownHighLevel 1.9 IH V V MaximumShutdownLowLevel 0.8 IL SD=0V Iv V leakagecurrentinshutdown 1 10 µA TT V =1.25V TT I V Inputcurrent 13 nA SENSE SENSE T ThermalShutdown (5) 165 SD °C T ThermalShutdownHysteresis 10 SD_HYS (4) QuiescentcurrentdefinedasthecurrentflowintoAVIN. (5) Themaximumallowablepowerdissipationisafunctionofthemaximumjunctiontemperature,T ,thejunctiontoambientthermal J(MAX) resistance,R ,andtheambienttemperature,T .Exceedingthemaximumallowablepowerdissipationwillcauseexcessivedie θJA A temperatureandtheregulatorwillgointothermalshutdown. Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com 7.7 Typical Characteristics UnlessotherwisespecifiedAVIN=PVIN=2.5V. 400 1050 350 900 300 750 250 600 A) A) u u I (Q 200 I (Q 450 150 300 100 150 50 0 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) AVIN (V) Figure1.I vsAV InSD Figure2.I vsAv Q IN Q IN 4 1.40 3.5 1.35 3 1.30 V (V)SD 2.52 V (V)REF 1.25 1.20 1.5 1 1.15 0.5 1.10 2 2.5 3 3.5 4 4.5 5 5.5 -30 -20 -10 0 10 20 30 AVIN (V) IREF (uA) Figure3.V andV Figure4.V vsI IH IL REF REF 3 3 2.5 2.5 2 2 V (V)REF 1.5 V (V)TT 1.5 1 1 0.5 0.5 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 VDDQ (V) VDDQ (V) Figure5.V vsV Figure6.V vsV REF DDQ TT DDQ 8 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 Typical Characteristics (continued) UnlessotherwisespecifiedAVIN=PVIN=2.5V. 400 1050 350 900 25oC 300 -40°C 750 -40oC A) 250 25°C A) 600 85oC (PSD 200 85°C I (PQ 450 125oC I 125°C 300 150 150 100 0 50 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) AVIN (V) Figure7.ISDvsAVINOverTemperature Figure8.IQvsAVINOverTemperature 1.4 1.8 1.2 1.7 A) 1 A) 1.6 NT ( NT ( URRE 0.8 URRE 1.5 UT C 0.6 UT C 1.4 OUTP 0.4 OUTP 1.3 0.2 1.2 0 1.1 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) AVIN (V) V =2.5V PV =1.8V V =2.5V PV =2.5V DDQ IN DDQ IN Figure9.MaximumSourcingCurrentvsAV Figure10.MaximumSourcingCurrentvsAV IN IN 3 3.0 2.8 2.8 A) A) 2.6 URRENT ( 2.6 URRENT ( 2.4 UT C 2.4 UT C 2.2 OUTP OUTP 2.0 2.2 1.8 2 1.6 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) AVIN (V) V =2.5V PV =3.3V V =2.5V DDQ IN DDQ Figure11.MaximumSourcingCurrentvsAV Figure12.MaximumSinkingCurrentvsAV IN IN Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Typical Characteristics (continued) UnlessotherwisespecifiedAVIN=PVIN=2.5V. 1.4 2.4 1.2 2.2 A) 1 A) 2 NT ( NT ( URRE 0.8 URRE 1.8 UT C 0.6 UT C 1.6 OUTP 0.4 OUTP 1.4 0.2 1.2 0 1 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 AVIN (V) AVIN (V) V =1.8V PV =1.8V V =1.8V DDQ IN DDQ Figure13.MaximumSourcingCurrentvsAV Figure14.MaximumSinkingCurrentvsAV IN IN 3 2.8 A) URRENT ( 2.6 UT C 2.4 UTP O 2.2 2 3 3.5 4 4.5 5 5.5 AVIN (V) V =1.8V PV =3.3V DDQ IN Figure15.MaximumSourcingCurrentvsAV IN 10 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 8 Detailed Description 8.1 Overview The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with V min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent DDQ response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current andtransientpeaksupto3AintheapplicationasrequiredforDDR-SDRAMtermination. 8.2 Functional Block Diagram SD VDDQ AVIN PVIN 50k + - VREF - + VTT 50k V SENSE GND 8.3 Feature Description The LP2998 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-18. The output, V is capable of sinking and sourcing current while regulating the output voltage equal to TT VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2998 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits theLP2998toprovideaterminationsolutionforDDR3-SDRAMandDDR3L-SDRAMmemory. 8.4 Device Functional Modes TheLP2998canalsobeusedtoprovideaterminationvoltageforotherlogicschemessuchasSSTL-3orHSTL. SeriesStubTerminationLogic(SSTL)wascreatedtoimprovesignalintegrityofthedatatransmissionacrossthe memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one R series resistor from the chipset to the memory and one R termination S T resistor. Typical values for R and R are 25 Ω, although these can be changed to scale the current S T requirementsfromtheLP2998.ThisimplementationcanbeseenbelowinFigure16. Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Device Functional Modes (continued) VDD VTT RT MEMORY RS CHIPSET VREF Figure16. SSTL-TerminationScheme 12 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 9 Application and Implementation 9.1 Application Information 9.1.1 InputCapacitor The LP2998 does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2998 is placed close to the bulk capacitance from the output of the 2.5 V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47 uF capacitor should be placed as close to possible to the PVIN rail. An additional 0.1 uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from couplingintothedevice. 9.1.2 OutputCapacitor TheLP2998hasbeendesignedtobeinsensitiveofoutputcapacitorsizeorESR(EquivalentSeriesResistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of V . As a general recommendation the TT output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are highlightedbelow: AL-Itshouldbenotedthatmanyaluminumelectrolyticsonlyspecifyimpedanceatafrequencyof120Hz,which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2998. To improve the ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESRrapidlyincreaseatcoldtemperatures. Ceramic-Ceramiccapacitorstypicallyhavealowcapacitance,intherangeof10to100 µFrange,buttheyhave excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic capacitors. Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance arecritical,althoughtheircostistypicallyhigherthananyothercapacitor. 9.1.3 ThermalDissipation Since the LP2998 is a linear regulator any current flow from V will result in internal power dissipation TT generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (T ) can be calculated given the maximum Rmax ambienttemperature(T )oftheapplicationandthemaximumallowablejunctiontemperature(T ). Amax Jmax T =T −T (1) Rmax Jmax Amax Fromthisequation,themaximumpowerdissipation(P )ofthepartcanbecalculated: Dmax P =T /R (2) Dmax Rmax θJA The R of the LP2998 will be dependent on several variables: the package used; the thickness of copper; the θJA numberofviasandtheairflow. Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Application Information (continued) 180 170 160 150 SOP Board 140 TJA 130 120 110 JEDEC Board 100 90 80 0 200 400 600 800 1000 AIRFLOW (Linear Feet per Minute) Figure17. R vsAirflow(SOIC-8) θJA Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With carefullayoutitispossibletoreducetheR furtherthanthenominalvaluesshowninFigure17. θJA Layout is also extremely critical to maximize the output current with the SO PowerPAD package. By simply placingviasundertheDAPtheθ canbeloweredsignificantly. JA Additional improvements in lowering the R can also be achieved with a constant airflow across the package. θJA Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 18 shows how the R varies θJA withairflow. 51 50 49 W) oC/( 48 qJA 47 46 45 0 100 200 300 400 500 600 AIRFLOW (Linear Feet Per Minute) Figure18. R vsAirflowSpeed(JedecBoardwith4Vias) ΘJA Optimizing the R and placing the LP2998 in a section of a board exposed to lower ambient temperature θJA allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at V , either sinking or sourcing, and quiescent current TT at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation canbecalculatedfromthefollowingequations: P =P +P +P (3) D AVIN VDDQ VTT P =I *V (4) AVIN AVIN AVIN P =V *I =V xR (5) VDDQ VDDQ VDDQ VDDQ2 VDDQ To calculate the maximum power dissipation at V both conditions at V need to be examined, sinking, and TT TT sourcing current. Although only one equation will add into the total, V cannot source and sink current TT simultaneously. 14 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 Application Information (continued) P =V xI (Sinking)or (6) VTT VTT LOAD P =(V -V )xI (Sourcing) (7) VTT PVIN VTT LOAD The power dissipation of the LP2998 can also be calculated during the shutdown state. During this condition the output V will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any TT current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN andtheconstantimpedancethatisseenattheVDDQpin. P =P +P (8) D AVIN VDDQ P =I xV (9) AVIN AVIN AVIN P =V *I =V xR (10) VDDQ VDDQ VDDQ VDDQ2 VDDQ 9.2 Typical Application Several different application circuits are shown below to illustrate some of the options that are possible in configuring the LP2998. Graphs of the individual circuit performance can be found in the Typical Characteristics section.ThesecurvesillustratehowthemaximumoutputcurrentisaffectedbychangesinAVINandPVIN. LP2998 SD SD VREF VREF = 0.75V + 0.01PF VDDQ = 1.5V VDDQ VDD = 2.5V AVIN VSENSE PVIN VTT VTT = 0.75V + + 47PF GND 220PF Figure19. TypicalApplicationCircuit 9.2.1 DDR-IIIApplications With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2998 in applications utilizingDDR-IIImemory.Theoutputstageisconnectedtothe1.5VrailandtheAVINpincanbeconnectedtoa 2.2Vto5.5Vrail. LP2998 SD SD VREF VREF = 0.75V + VDDQ = 1.5V VDDQ CREF AVIN = 2.2V to 5.5V AVIN VSENSE PVIN = 1.5V PVIN VTT VTT = 0.75V + + CIN GND COUT Figure20. RecommendedDDR-IIITermination If it is not desirable to use the 1.5 V - 2.5 V rail it is possible to connect the output stage to a 3.3 V rail. Care shouldbetakentonotexceedthemaximumjunctiontemperatureasthethermaldissipationincreaseswithlower V output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3 TT V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current. Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Typical Application (continued) 9.2.2 DDR-IIApplications With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2998 in applications utilizing DDR-II memory. Figure 21 and Figure 22 show several implementations of recommended circuits with output curves displayed in the Typical Characteristics. Figure 21 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8 V rail and the AVIN pin can be connected to eithera3.3Vor5Vrail. LP2998 SD SD VREF VREF = 0.9V + 0.01 PF AVIN = 2.5V AVIN VDDQ = 1.8V VDDQ VSENSE PVIN VTT VTT = 0.9V + + 47 PF GND 220 PF Figure21. RecommendedDDR-IITermination If it is not desirable to use the 1.8 V rail it is possible to connect the output stage to a 3.3 V rail. Care should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower V TT output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3 V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current. LP2998 SD SD VREF VREF = 0.9V + VDDQ = 1.8V VDDQ CREF AVIN = 3.3V or 5.5V AVIN VSENSE PVIN = 3.3V PVIN VTT VTT = 0.9V + + CIN GND COUT Figure22. DDR-IITerminationwithHigherVoltageRails 9.2.3 SSTL-2Applications For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all the input rails to the 2.5 V rail. This provides an optimal trade-off between power dissipation and component countandselection.AnexampleofthiscircuitcanbeseeninFigure23. 16 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 Typical Application (continued) LP2998 SD SD VREF VREF = 1.25V + VDDQ = 2.5V VDDQ CREF VDD = 2.5V AVIN VSENSE PVIN VTT VTT = 1.25V + + CIN GND COUT Figure23. RecommendedSSTL-2Implementation If power dissipation or efficiency is a major concern then the LP2998 has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8 V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5 V, 3.3 V, or 5 V. This allows the internal power dissipation to be lowered when sourcing current from V . The disadvantage of this circuit is that the maximum continuous current TT is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasingtheoutputcapacitancecanalsohelpifperiodsoflargeloadtransientswillbeencountered. LP2998 SD SD VREF VREF = 1.25V + VDDQ = 2.5V VDDQ CREF AVIN = 2.2V to 5.5V AVIN VSENSE PVIN = 1.8V PVIN VTT VTT = 1.25V + + CIN GND COUT Figure24. LowerPowerDissipationSSTL-2Implementation The third option for SSTL-2 applications in the situation that a 1.8 V rail is not available and it is not desirable to use 2.5 V, is to connect the LP2998 power rail to 3.3 V. In this situation AVIN will be limited to operation on the 3.3 V or 5 V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the LP2998 from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3 V rail. LP2998 SD SD VREF VREF = 1.25V + VDDQ = 2.5V VDDQ CREF AVIN = 3.3V or 5V AVIN VSENSE PVIN = 3.3V PVIN VTT VTT = 1.25V + + CIN GND COUT Figure25. SSTL-2ImplementationwithHigherVoltageRails Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com Typical Application (continued) 9.2.4 LevelShifting If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times V for regulating the output voltage. Several options are available to scale the output to DDQ any voltage required. One method is to level shift the output by using feedback resistors from V to the V TT SENSE pin. This has been illustrated in Figure 26 and Figure 27. Figure 26 shows how to use two resistors to level shift V above the internal reference voltage of VDDQ/2. To calculate the exact voltage at V the following equation TT TT canbeused. V =VDDQ/2(1+R1/R2) (11) TT LP2998 VDDQ VDDQ VDD AVIN VTT VTT R1 + PVIN VSENSE +COUT CIN GND R2 Figure26. IncreasingVTTbyLevelShifting Conversely, the R2 resistor can be placed between V and V to shift the V output lower than the SENSE DDQ TT internalreferencevoltageofVDDQ/2.TheequationsrelatingVTTandtheresistorscanbeseenbelow: V =VDDQ/2(1-R1/R2) (12) TT LP2998 R2 VDDQ VDDQ VSENSE VDD AVIN R1 PVIN VTT VTT + CIN + GND COUT Figure27. DecreasingVTTbyLevelShifting 9.2.4.1 OutputCapacitorSelection For applications utilizing the LP2998 to terminate SSTL-2 I/O signals the typical application circuit shown in Figure28canbeimplemented. LP2998 SD SD VREF VREF = 0.9V + AVIN = 2.5V AVIN CREF VDDQ = 1.8V VDDQ VSENSE PVIN VTT VTT = 0.9V + + CIN GND COUT Figure28. TypicalSSTL-2ApplicationCircuit 18 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 Typical Application (continued) This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where V is distributed across a long plane it is advisable to use multiple TT bulk capacitors and addition to high frequency decoupling. Figure 29 shown below depicts an example circuit where 2 bulk output capacitors could be situated at both ends of the V plane for optimal placement. Large TT aluminumelectrolyticcapacitorsareusedfortheirlowESRandlowcost. LP2998 SD SD VREF VREF = 1.25V + VDDQ = 2.5V VDDQ 0.01 PF VDD = 2.5V AVIN VSENSE PVIN VTT VTT = 1.25V 47 PF + GND +330 PF +330 PF Figure29. TypicalSSTL-2ApplicationCircuitforMotherboards In most PC applications an extensive amount of decoupling is required because of the long interconnects encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic capacitorsintherangeof1000 µFaretypicallyused. 9.2.5 HSTLApplications The LP2998 can be easily adapted for HSTL applications by connecting V to the 1.5 V rail. This will produce DDQ a V and V voltage of approximately 0.75 V for the termination resistors. AVIN and PVIN should be TT REF connectedtoa2.5Vrailforoptimalperformance. LP2998 SD SD VREF VREF = 0.75V + VDDQ = 1.5V VDDQ CREF VDD = 2.5V AVIN VSENSE PVIN VTT VTT = 0.75V + + CIN GND COUT Figure30. HSTLApplication 9.2.6 QDRApplications Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this increase in bus lines has the effect of increasing the current levels required for termination. The recommended approach in terminating multiple channels is to use a dedicated LP2998 for each channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate V signals can be used for each DIMM REF bankfromthecorrespondingregulatorwiththechipsetreferenceprovidedbyalocalresistordivideroroneofthe LP2998 signals. Because V and V are expected to track and the part to part variations are minor, there REF TT shouldbelittledifferencebetweenthereferencesignalsofeachLP2998. Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com 10 Power Supply Recommendations There are several recommendations for the LP2998 input power supply. An input capacitor is not required but is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2998 is placed close to the bulk capacitance from the output of the 2.5 V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47 uF capacitor should be placed as close to possible to the PVIN rail. An additional 0.1 uF ceramic capacitor can be placed on theAVINrailtopreventexcessivenoisefromcouplingintothedevice. 11 Layout 11.1 Layout Guidelines 1. TheinputcapacitorforthepowerrailshouldbeplacedascloseaspossibletothePVINpin. 2. V should be connected to the V termination bus at the point where regulation is required. For SENSE TT motherboardapplicationsanideallocationwouldbeatthecenteroftheterminationbus. 3. V can be connected remotely to the V rail input at either the DIMM or the Chipset. This provides the DDQ DDQ mostaccuratepointforcreatingthereferencevoltage. 4. For improved thermal performance excessive top side copper should be used to dissipate heat from the package.Numerousviasfromthegroundconnectiontotheinternalgroundplanewillhelp.Additionallythese canbelocatedunderneaththepackageifmanufacturingstandardspermit. 5. Care should be taken when routing the V trace to avoid noise pickup from switching I/O signals. A 0.1 SENSE µF ceramic capacitor located close to the can also be used to filter any unwanted high frequency SENSE signal.Thiscanbeanissueespeciallyiflong tracesareused. SENSE 6. V should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This REF capacitorshouldbelocatedascloseaspossibletotheV pin. REF 20 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 www.ti.com SNVS521K–DECEMBER2007–REVISEDAUGUST2014 11.2 Layout Examples Figure 31 and Figure 32 are layout examples for the LP2998/Q1. These examples are taken from the LP2998EVM. Figure31. LP2998EVMSOPowerPADLayoutExample(Front) Figure32. LP2998EVMSOPowerPADLayoutExample(Back) Copyright©2007–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LP2998 LP2998-Q1

LP2998,LP2998-Q1 SNVS521K–DECEMBER2007–REVISEDAUGUST2014 www.ti.com 12 Device and Documentation Support 12.1 Related Links Table 1 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY LP2998 Clickhere Clickhere Clickhere Clickhere Clickhere LP2998-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere 12.2 Trademarks PowerPADisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 22 SubmitDocumentationFeedback Copyright©2007–2014,TexasInstrumentsIncorporated ProductFolderLinks:LP2998 LP2998-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP2998MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP2998 & no Sb/Br) MA LP2998MAE/NOPB ACTIVE SOIC D 8 250 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP2998 & no Sb/Br) MA LP2998MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LP2998 & no Sb/Br) MA LP2998MR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LP2998 & no Sb/Br) MR LP2998MRE/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LP2998 & no Sb/Br) MR LP2998MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LP2998 & no Sb/Br) MR LP2998QMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LP2998 & no Sb/Br) Q1MR LP2998QMRE/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LP2998 & no Sb/Br) Q1MR LP2998QMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 125 LP2998 & no Sb/Br) Q1MR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LP2998, LP2998-Q1 : •Catalog: LP2998 •Automotive: LP2998-Q1 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP2998MAE/NOPB SOIC D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2998MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2998MRE/NOPB SO DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Power PAD LP2998MRX/NOPB SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Power PAD LP2998QMRE/NOPB SO DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Power PAD LP2998QMRX/NOPB SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Power PAD PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP2998MAE/NOPB SOIC D 8 250 210.0 185.0 35.0 LP2998MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2998MRE/NOPB SOPowerPAD DDA 8 250 210.0 185.0 35.0 LP2998MRX/NOPB SOPowerPAD DDA 8 2500 367.0 367.0 35.0 LP2998QMRE/NOPB SOPowerPAD DDA 8 250 210.0 185.0 35.0 LP2998QMRX/NOPB SOPowerPAD DDA 8 2500 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DDA0008A PowerPAD T M SOIC - 1.7 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.2 TYP 5.8 SEATING PLANE A PIN 1 ID 0.1 C AREA 6X 1.27 8 1 5.0 2X 4.8 3.81 NOTE 3 4 5 0.51 8X 0.31 B 4.0 1.7 MAX 3.8 0.25 C A B NOTE 4 0.25 TYP 0.10 SEE DETAIL A 4 5 EXPOSED THERMAL PAD 0.25 2.34 2.24 GAGE PLANE 0.15 0 - 8 1.27 0.00 1 8 0.40 DETAIL A 2.34 TYPICAL 2.24 4218825/A 05/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012. www.ti.com

EXAMPLE BOARD LAYOUT DDA0008A PowerPAD T M SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.95) NOTE 9 SOLDER MASK (2.34) DEFINED PAD SOLDER MASK OPENING SEE DETAILS 8X (1.55) 1 8 8X (0.6) SYMM (2.34) (1.3) SOLDER MASK TYP OPENING (4.9) NOTE 9 6X (1.27) 5 4 (R0.05) TYP SYMM METAL COVERED ( 0.2) TYP BY SOLDER MASK VIA (1.3) TYP (5.4) LAND PATTERN EXAMPLE SCALE:10X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL SOLDER MASK METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4218825/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DDA0008A PowerPAD T M SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE (2.34) BASED ON 0.125 THICK STENCIL 8X (1.55) (R0.05) TYP 1 8 8X (0.6) SYMM (2.34) BASED ON 0.125 THICK STENCIL 6X (1.27) 5 4 METAL COVERED BY SOLDER MASK SYMM SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL (5.4) THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.62 X 2.62 0.125 2.34 X 2.34 (SHOWN) 0.150 2.14 X 2.14 0.175 1.98 X 1.98 4218825/A 05/2016 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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