DATASHEET ISL85033 FN6676 Wide V Dual Standard Buck Regulator With 3A/3A Continuous Output Current Rev 8.00 IN February 17, 2015 The ISL85033 is a dual standard buck regulator capable of 3A Features per channel continuous output current. With an input range of 4.5V to 28V, it provides a high frequency power solution for a • Wide input voltage range from 4.5V to 28V variety of point of load applications. • Adjustable output voltage with continuous output current up to 3A The PWM controller in the ISL85033 drives an internal switching N-Channel power MOSFET and requires an external • Current mode control Schottky diode to generate the output voltage. The integrated • Adjustable switching frequency from 300kHz to 2MHz power switch is optimized for excellent thermal performance up to 3A of output current. The PWM regulator switches at a • Independent power-good detection default frequency of 500kHz and it can be user programmed • Selectable in-phase or out-of-phase PWM operation or synchronized from 300kHz to 2MHz. The ISL85033 utilizes • Independent, sequential, ratiometric or absolute tracking peak current mode control to provide flexibility in component between outputs selection and minimize solution size. The protection features • Internal 2ms soft-start time include overcurrent, UVLO and thermal overload protection. • Overcurrent/short circuit protection, thermal overload The ISL85033 is available in a small 4mmx4mm Thin Quad protection, UVLO Flat No-Lead (TQFN) Pb-free package. • Boot undervoltage detection Related Literature • Pb-free (RoHS compliant) •AN1574 “ISL85033DUALEVAL1Z Wide VIN Dual Standard Applications Buck Regulator With 3A/3A Output Current” • General purpose point-of-load DC/DC power conversion •AN1585 “ISL85033EVAL2Z (Small Form) Wide VIN Dual Standard Buck Regulator With 3A/3A Output Current - Short • Set-top boxes Form” • FPGA power and STB power •AN1584 “ISL85033EVAL2Z (Small Form) Wide VIN Dual • DVD and HDD drives Standard Buck Regulator With 3A/3A Output Current - Long • LCD panels, TV power Form” • Cable modems •AN1605 “ISL85033CRSHEVAL1Z Wide VIN Current sharing Standard Buck Regulator With 6A Output Current” 100 90 %) 80 12VOUT 1MHz Y ( C N 70 E CI FFI 60 E 50 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) FIGURE 1. EFFICIENCY vs LOAD, VIN = 28V, TA = +25°C FN6676 Rev 8.00 Page 1 of 26 February 17, 2015

ISL85033 Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-on Reset and Undervoltage Lockout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Tracking and Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Buck Regulator Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal Overload Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BOOT Undervoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current Sharing Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Loop Compensation Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Theory of Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM Comparator Gain Fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Rectifier Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power Derating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FN6676 Rev 8.00 Page 2 of 26 February 17, 2015

ISL85033 Pin Configuration ISL85033 (28 LD TQFN) TOP VIEW T 1 U 2 D N O D O D CI C O O N N N O G S C G Y Y G P F N S S S P 28 27 26 25 24 23 22 COMP1 1 21 COMP2 FB1 2 20 FB2 SS1 3 19 SS2 PGND1 4 PD 18 PGND2 BOOT1 5 17 BOOT2 PHASE1 6 16 PHASE2 PHASE1 7 15 PHASE2 8 9 10 11 12 13 14 1 1 1 C 2 2 2 N N N C N N N VI VI E V E VI VI Pin Descriptions PIN NUMBER SYMBOL PIN DESCRIPTION 1, 21 COMP1, COMP2 COMP1, COMP2 are the output of the error amplifier. 2, 20 FB1, FB2 Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In addition, the PWM regulator’s power-good and undervoltage protection circuits use FB1, FB2 to monitor the regulator output voltage. 3, 19 SS1, SS2 Soft-start pins for each controller. The SS1, SS2 pins control the soft-start and sequence of their respective outputs. A single capacitor from the SS pin to ground determines the output ramp rate. See the “Output Tracking and Sequencing” on page16 for soft-start and output tracking/sequencing details. If SS pins are tied to VCC, an internal soft-start of 2ms will be used. Maximum CSS value is 100nF. 4, 18 PGND1, PGND2 Power ground connections. Connect directly to the system GND plane. 5, 17 BOOT1, BOOT2 Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn on the internal N-Channel MOSFET. Connect an external capacitor from this pin to PHASE. 6, 7, 15, 16 PHASE1, PHASE2 Switch node output. It connects the source of the internal power MOSFET with the external output inductor and with the cathode of the external diode. 8, 9, 13, 14 VIN1, VIN2 The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from each VIN to GND and close to the IC for decoupling. 10, 12 EN1, EN2 PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to ground. When the voltage on this pin rises above 2V, the PWM controller is enabled. If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be: EN_T_off s = 10sC 2.2nF SS where CSS is the soft-start pin capacitor (nF). The ISL85033 does not have debouncing to EN1, EN2 external signals. 11 VCC Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7µF ceramic capacitor. This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA). FN6676 Rev 8.00 Page 3 of 26 February 17, 2015

ISL85033 Pin Descriptions (Continued) PIN NUMBER SYMBOL PIN DESCRIPTION 23 SYNCOUT Synchronization output. Provides a signal that is the inverse of the SYNCIN signal. 24 SYNCIN Connect to an external signal for synchronization from 300kHz to 2MHz (negative edge trigger). SYNCIN is not allowed to be floating. When SYNCIN = logic 0, PHASE1 and PHASE2 are running at 180° out-of-phase. When SYNCIN = logic 1, PHASE1 and PHASE2 are running at 0° in-phase. When SYNCIN = an external clock, PHASE1 and PHASE2 are running at 180° out-of-phase. External SYNC frequency applied to the SYNCIN pin should be at least 2.4 x the internal switching frequency setting. 25 SGND Signal ground connections. The exposed pad must be connected to SGND and soldered to the PCB. All voltage levels are measured with respect to this pin. 26 NC This is a no connection pin. 27 FS Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for adjustable frequency from 300kHz to 2MHz. 22, 28 PGOOD2, PGOOD1 Open-drain power-good output that is pulled to ground when the output voltage is below regulation limits or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor. PD The exposed pad must be connected to the system GND plane with as many vias as possible for proper electrical and thermal performance. FN6676 Rev 8.00 Page 4 of 26 February 17, 2015

ISL85033 Typical Application Schematics VOUT2 VOUT1 R5 R1 25.5k R6 R2 42.2k 8.06k 8.06k C4 C5 C2 C1 68pF 470pF 470pF 68pF MP2 R8 R4 MP1 B2 O 69.8k 69.8k O B1 F C C F 20 21 1 2 FS VIN1 VCC 27 8/9 SS2 VCC 19 VIN2 C71 VCC SS1 3 13/14 20µF PGOOD2 10µF C72 22 3VAOUT2 7Lµ2H PPGHOAOSDE21 28 ISL85033 6/7 PHASE1 7Lµ1H VOU3TA1 15/16 C471µ3F D2 C101n2F 5 BOOT1 1C0n8F D1 47CµF9 B340B 17 B340B BOOT2 24 23 4/18 12 26 10 25 11 N T 2 2 C 1 D C SYNCI NCOU GND1/ EN N EN SGN VC 4.7µF Y P S FIGURE 2. DUAL 3A OUTPUT (VIN RANGE FROM 4.5V TO 28V) FB2 VOUT1 R5 R6 42.2k 8.06k C4 R7 C5 COMP2 68pF 0 1nF FB2 P2 R8 P1 B2 OM 34k OM B1 F C C F 20 21 1 2 FS VIN1 VCC 27 8/9 SS2 19 C71 VIN2 20µF Css2 SS1 3 13/14 47nF Css1 PGOOD2 22 10µF C72 47nF PGOOD1 ISL85033 28 VOUT1 VOUT1 L2 PHASE2 15/16 6/7 PHASE1 L1 6A C471µ3F7µH D2 C101n2F 5 BOOT1 C108nF D1 7µH47CµF9 B340B 17 B340B BOOT2 24 23 4/18 12 26 10 25 11 N T 2 2 C 1 D C SYNCI NCOU GND1/ EN N EN SGN VC 4.7µF Y P S FIGURE 3. SINGLE 6A OUTPUT (VIN RANGE FROM 4.5V TO 28V) CURRENT SHARING FN6676 Rev 8.00 Page 5 of 26 February 17, 2015

ISL85033 Functional Block Diagram 2 D 2 2 O P T GO B2 OM OO P F C B VCC 5MΩ +- BOOT UV -10% DETECTION CC VIN2 SS2 SOFT-START V CONTROL VOLTAGE - CSA2 MONITOR + - EA + COMP2 0.8V REFERENCE FAULT MONITOR GATE PHASE2 EN2 DRIVE CSA2 BOOT REFRESH CONTROL PGND2 + SLOPE COMP VIN1 POWER-ON LDO VCC = 5V RESET MONITOR CSA2 VIN1 THERMAL MONITOR +150°C SYNCOUT C SA1 OSCILLATOR FS SYNCIN + SLOPE COMP CSA1 VIN1 CSA1 EN1 FAULT MONITOR 0.8V REFERENCE COMP1 DRIVE PHASE1 MONITOR + EA + GATE VOLTAGE - - SS1 CONTROL BOOT SOFT-START REFRESH CONTROL -10% + PGND1 - VCC 5MΩ BOOT UV VCC DETECTION C C V 1 1 1 D D 1 D B P N N T O F M G G O PGO CO PAD S BO E FN6676 Rev 8.00 Page 6 of 26 February 17, 2015

ISL85033 Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Notes1, 2, 3) MARKING (°C) (RoHS Compliant) DWG. # ISL85033IRTZ 850 33IRTZ -40 to +85 28 Ld TQFN L28.4x4 ISL85033-12VEVAL3Z Evaluation Board ISL85033DUALEVAL1Z Evaluation Board ISL85033EVAL2Z Evaluation Board ISL85033CRSHEVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85033. For more information on MSL please see techbrief TB363. FN6676 Rev 8.00 Page 7 of 26 February 17, 2015

ISL85033 Absolute Maximum Ratings Thermal Information VIN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V Thermal Resistance JA (°C/W) JC (°C/W) PHASE1/2 to GND . . . . . . . . . . . . . . . . . . . -7V (<10ns) /-0.3V (DC) to +33V QFN Package (Notes4, 5). . . . . . . . . . . . . . 38 3 BOOT1/2 to PHASE1/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C FS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C SYNCIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C FB1/2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C EN1/2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C PGOOD1/2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 COMP1/2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V VCC to GND Short Maximum Duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s Recommended Operating Conditions SYNCOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V SS1/2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C ESD Rating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 28V Human Body Model (Tested per JESD22-A114). . . . . . . . . . . . . . . . . 3kV Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .2.2kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . .300V Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications TA = -40°C to +85°C, VIN = 4.5V to 28V, unless otherwise noted. Typical values are at TA=+25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note8) TYP (Note8) UNITS SUPPLY VOLTAGE VIN Voltage Range VIN 4.5 28 V VIN Quiescent Supply Current IQ 1.2 2.2 mA VIN Shutdown Supply Current ISD EN1/2 = 0V 20 45 µA VCC Voltage VCC VIN = 12V; IOUT = 0mA 4.5 5.1 5.6 V POWER-ON RESET VIN POR Threshold Rising Edge 3.9 4.4 V Falling Edge 3.2 3.7 V OSCILLATOR Nominal Switching Frequency fSW FS pin = VCC 420 500 580 kHz Resistor from FS pin to GND = 383kΩ 300 kHz Resistor from FS pin to GND = 40.2kΩ 2000 kHz FS Voltage VFS FS = 100kΩ 780 800 820 mV Switching Frequency SYNCIN = 600kHz 300 kHz 1.2MHz ≤ SYNCIN ≤ 4MHz 600 2000 kHz Minimum Off-time tOFF 130 ns ERROR AMPLIFIER Error Amplifier Transconductance Gain gm 125 205 285 µA/V FB1, FB2 Leakage Current VFB = 0.8V 10 100 nA Current Sense Amplifier Gain RT 0.18 0.21 0.24 V/A Reference Voltage 0.792 0.8 0.808 V Soft-start Ramp Time SS1, SS2 = VDD 1.5 2.5 3.5 ms Soft-start Charging Current ISS 1.4 2 2.6 µA FN6676 Rev 8.00 Page 8 of 26 February 17, 2015

ISL85033 Electrical Specifications TA = -40°C to +85°C, VIN = 4.5V to 28V, unless otherwise noted. Typical values are at TA=+25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note8) TYP (Note8) UNITS POWER-GOOD PG1, PG2 Trip Level PG to PGOOD1, Rise 91 94 % PGOOD2 Fall 82.5 85.5 % PG1, PG2 Propagation Delay Percentage of the soft-start time 10 % PG1, PG2 Low Voltage ISINK = 3mA 100 300 mV ENABLE INPUT EN1, EN2 Leakage Current EN1/2 = 0V/5V -1 1 µA EN1, EN2 Input Threshold Voltage Low Level 0.8 V Float Level 1.0 1.4 V High Level 2 V SYNC INPUT/OUTPUT SYNCIN Input Threshold Falling Edge 1.1 1.4 V Rising Edge 1.6 1.9 V Hysteresis 200 mV SYNCIN Leakage Current SYNCIN = 0V/5V 10 1000 nA SYNCIN Pulse Width 100 ns SYNCOUT Phase-shift to SYNCIN Measured from rising edge to rising 180 Degree edge, if duty cycle is 50% SYNCOUT Frequency Range 600 4000 kHz SYNCOUT Output Voltage High ISYNCOUT = 3mA VCC - 0.3 VCC -0.08 V SYNCOUT Output Voltage Low 0.08 0.3 V FAULT PROTECTION Thermal Shutdown Temperature TSD Rising Threshold 150 °C THYS Hysteresis 20 °C Overcurrent Protection Threshold (Note7) 4.1 5.1 6.1 A OCP Blanking Time 60 ns POWER MOSFET High-side RHDS IPHASE = 100mA 75 150 mΩ Internal BOOT1, BOOT2 Refresh Low-side RLDS IPHASE = 100mA 1 Ω PHASE Leakage Current EN1/2 = PHASE1/2 = 0V 300 nA PHASE Rise Time tRISE VIN = 25V 10 ns NOTES: 6. Test Condition: VIN = 28V, FB forced above regulation point (0.8V), no switching, and power MOSFET gate charging current not included. 7. Established by both current sense amplifier gain test and current sense amplifier output test at IL = 0A. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN6676 Rev 8.00 Page 9 of 26 February 17, 2015

ISL85033 Typical Performance Curves Circuit of Figure2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. 100 100 90 90 %) 80 12VOUT 1MHz %) 80 CIENCY ( 70 5VOUT 500k9HVzOUT 1MHz CIENCY ( 70 3.3VOUT 5VOUT EFFI 60 3.3VOUT 500kHz EFFI 60 50 50 1.8VOUT 300kHz 40 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 4. EFFICIENCY vs LOAD, TA = +25°C, VIN = 28V FIGURE 5. EFFICIENCY vs LOAD, TA = +25°C, fSW = 500kHz, VIN= 12V 100 4.2 90 W) 3.5 %) 80 ON ( 2.8 ENCY ( 70 9VIN 12VIN 28VIN SSIPATI 2.1 CI DI EFFI 60 WER 1.4 12VIN O 28VIN 50 P 0.7 9VIN 40 0.0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 6. EFFICIENCY vs LOAD, TA = +25°C, CURRENT SHARING FIGURE 7. POWER DISSIPATION vs LOAD, TA = +25°C, 5VOUT, fSW=500kHz CURRENTSHARING 5VOUT, fSW = 500kHz 4.8 5.04 ON (W) 34..20 E (V) 55..0023 SIPATI 2.4 OLTAG 5.01 12VIN S V 9VIN DI T WER 1.6 12VIN UTPU 5.00 28VIN O 0.8 O 4.99 P 28VIN 9VIN 0.0 4.98 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 8. POWER DISSIPATION vs LOAD, TA = +85°C, FIGURE 9. VOUT REGULATION vs LOAD, CHANNEL 1, CURRENTSHARING 5VOUT, fSW = 500kHz TA = +25°C, 5VOUT, fSW = 500kHz FN6676 Rev 8.00 Page 10 of 26 February 17, 2015

ISL85033 Typical Performance Curves Circuit of Figure2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued) 5.04 3.329 V) 5.03 V) 3.328 28VIN GE ( 5.02 GE ( 3.326 18VIN A A T T T VOL 5.01 28VIN 9VIN 12VIN T VOL 3.325 PU 5.00 PU 3.323 T T U U O 4.99 O 3.322 12VIN 4.98 3.320 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 10. VOUT REGULATION vs LOAD, CURRENT SHARING, FIGURE 11. VOUT REGULATION vs LOAD, CHANNEL 2, TA = +25°C, TA=+25°C, 5VOUT, fSW = 500kHz 3.3VOUT, fSW = 500kHz 5.04 5.02 5.03 5.01 V) V) GE ( 5.02 GE ( 5.00 A A T T OL 5.01 OL 4.99 0A V V T T PU 5.00 3A 2A 0A PU 4.98 T T OU OU 4A 6A 4.99 4.97 4.98 4.96 0 5 10 15 20 25 30 0 5 10 15 20 25 30 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN, CHANNEL 1, FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN, CURRENT TA= +25°C, 5VOUT, fSW = 500kHz SHARING, TA = +25°C, 5VOUT, fSW = 500kHz 3.340 3.335 V) LX1 5V/DIV GE ( 3.330 A T L O 3.325 V VOUT1 RIPPLE 20mV/DIV T PU 3.320 T U O 0A 2A 3A 3.315 IL1 0.1A/DIV 3.310 0 5 10 15 20 25 30 INPUT VOLTAGE (V) FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN, CHANNEL 2, FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 TA= +25°C, 3.3VOUT, fSW = 500kHz FN6676 Rev 8.00 Page 11 of 26 February 17, 2015

ISL85033 Typical Performance Curves Circuit of Figure2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued) LX1 5V/DIV LX2 5V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.2A/DIV IL2 0.1A/DIV FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 1 FIGURE 17. STEADY STATE OPERATION AT NO LOAD CHANNEL 2 (VIN = 9V) LX1 5V/DIV LX2 5V/DIV VOUT1 RIPPLE 20mV/DIV IL1 1A/DIV VOUT2 RIPPLE 20mV/DIV IL2 1A/DIV FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1 FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2 LX2 10V/DIV VOUT RIPPLE 20mV/DIV VOUT1 RIPPLE 20mV/DIV LX1 10V/DIV IL1 2A/DIV FIGURE 20. STEADY STATE OPERATION WITH FULL LOAD CURRENT FIGURE 21. LOAD TRANSIENT CHANNEL 1 SHARING FN6676 Rev 8.00 Page 12 of 26 February 17, 2015

ISL85033 Typical Performance Curves Circuit of Figure2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued) EN1 5V/DIV VOUT1 2V/DIV VOUT2 RIPPLE 20mV/DIV IL1 0.5A/DIV PG1 5V/DIV IL2 2A/DIV FIGURE 22. LOAD TRANSIENT CHANNEL 2 FIGURE 23. SOFT-START WITH NO LOAD CHANNEL 1 EN2 5V/DIV EN1 5V/DIV VOUT2 2V/DIV VOUT1 2V/DIV IL2 0.5A/DIV IL1 2A/DIV PG2 5V/DIV PG1 5V/DIV FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 2 FIGURE 25. SOFT-START AT FULL LOAD CHANNEL 1 EN2 5V/DIV EN1 5V/DIV VOUT2 2V/DIV VOUT1 1V/DIV IL2 2A/DIV IILL11 00..55AA//DDIIVV PG2 5V/DIV PG 5V/DIV FIGURE 26. SOFT-START AT FULL LOAD CHANNEL 2 FIGURE 27. SOFT-DISCHARGE SHUTDOWN CHANNEL 1 FN6676 Rev 8.00 Page 13 of 26 February 17, 2015

ISL85033 Typical Performance Curves Circuit of Figure2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued) VOUT1 2V/DIV EN2 5V/DIV VOUT2 2V/DIV VOUT2 0.5V/DIV EN1, 2 2V/DIV IL2 0.5A/DIV PG 5V/DIV FIGURE 28. SOFT-DISCHARGE SHUTDOWN CHANNEL 2 FIGURE 29. INDEPENDENT START-UP SEQUENCING AT NO LOAD VOUT1 2V/DIV VOUT1 2V/DIV VOUT2 2V/DIV VOUT2 2V/DIV EN1, 2 2V/DIV EN1, 2 2V/DIV FIGURE 30. RATIOMETRIC START-UP SEQUENCING AT NO LOAD FIGURE 31. ABSOLUTE START-UP SEQUENCING AT NO LOAD LX1 10V/DIV LX1 10V/DIV VOUT1 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV LX2 10V/DIV LX2 10V/DIV SYNC 5V/DIV SYNC 5V/DIV FIGURE 32. STEADY STATE OPERATION CHANNEL 1 AT FULL LOAD WITH FIGURE 33. STEADY STATE OPERATION CHANNEL 2 AT FULL LOAD WITH SYNC FREQUENCY = 4MHz SYNC FREQUENCY = 4MHz FN6676 Rev 8.00 Page 14 of 26 February 17, 2015

ISL85033 Typical Performance Curves Circuit of Figure2. VIN = 12V, VOUT1 = 5V, VOUT2 = 3.3V, IOUT1 = 3A, IOUT2 = 3A, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. (Continued) PHASE1 10V/DIV PHASE1 10V/DIV VOUT1 2V/DIV IL1 2A/DIV VOUT1 2V/DIV IL1 2A/DIV PG1 5V/DIV PG1 5V/DIV FIGURE 34. OUTPUT SHORT CIRCUIT CHANNEL 1 FIGURE 35. OUTPUT SHORT CIRCUIT HICCUP AND RECOVERY FOR CHANNEL 1 PHASE2 10V/DIV PHASE2 10V/DIV IL2 2A/DIV VOUT2 2V/DIV VOUT2 2V/DIV IL2 2A/DIV PG2 5V/DIV PG2 5V/DIV FIGURE 36. OUTPUT SHORT CIRCUIT CHANNEL 2 FIGURE 37. OUTPUT SHORT CIRCUIT HICCUP AND RECOVERY FOR CHANNEL 2 FN6676 Rev 8.00 Page 15 of 26 February 17, 2015

ISL85033 Detailed Description pin. PG is actively held low when EN is low and during the buck regulator soft-start period. After the soft-start period terminates, The ISL85033 combines a standard buck PWM controller with PG becomes high impedance as long as the output voltage integrated switching MOSFETs. The buck controller drives an (monitored on the FB pin) is above 90% of the nominal regulation internal N-Channel MOSFET and requires an external diode to voltage set by FB. When VOUT drops 10% below the nominal deliver load current up to 3A. A Schottky diode is recommended regulation voltage, the ISL85033 pulls PG low. Any fault condition for improved efficiency and performance over a standard diode. forces PG low until the fault condition is cleared by attempts to The standard buck regulator can operate from an unregulated DC soft-start. There is an internal 5MΩ internal pull-up resistor. source, such as a battery, with a voltage ranging from +4.5V to Output Voltage Selection +28V. The converter output can be regulated to as low as 0.8V. These features make the ISL85033 ideally suited for FPGA, The regulator output voltage is easily programmed using an set-top boxes, LCD panels, DVD drives, and wireless chipset external resistor divider to scale VOUT relative to the internal power applications. reference voltage. The scaled voltage is applied to the inverting input of the error amplifier; refer to Figure38. The ISL85033 employs peak current-mode control loop, which simplifies feedback loop compensation and rejects input voltage The output voltage programming resistor, R2, depends on the variation. External feedback loop compensation allows flexibility value chosen for the feedback resistor, R3, and the desired in output filter component selection. The regulator switches at a output voltage, VOUT, of the regulator. Equation2 describes the default 500kHz and it can be adjusted from 300kHz to 2MHz relationship between VOUT and resistor values. R3 is often with a resistor from FS to GND. The ISL85033 is synchronizable chosen to be in the 1kΩ to 10kΩ range. from 300kHz to 2MHz. R = V –0.8R 0.8 (EQ. 2) 2 OUT 3 Operation Initialization If the desired output voltage is 0.8V, then R3 is left unpopulated The power-on reset circuitry and enable inputs prevent false and R2 is 0Ω. start-up of the PWM regulator output. Once all input criteria are met, the controller soft starts the output voltage to the VOUT programmed level. R2 FB Power-on Reset and Undervoltage Lockout - + The ISL85033 automatically initializes upon receipt of input EA R3 power supply. The power-on reset (POR) function continually 0.8V monitors VIN1 voltage. While below the POR threshold, the REFERENCE controller inhibits switching of the internal power MOSFET. Once exceeded, the controller initializes the internal soft-start circuitry. If VIN1 supply drops below their falling POR threshold during FIGURE 38. EXTERNAL RESISTOR DIVIDER soft-start or operation, the buck regulator is disabled until the input voltage returns. Output Tracking and Sequencing Enable and Disable The output tracking and sequencing between channels can be When EN1 and EN2 are pulled low, the device enters shutdown implemented by using the SS1 and SS2 pins. Figures39, 40 and mode and the supply current drops to a typical value of 20µA. All 41 show several configurations for output tracking/sequencing internal power devices are held in a high impedance state while for a 2.5V and 1.8V application. Independent soft-start for each in shutdown mode. channel is shown in Figure39 and measured in Figure29. The output ramp-time for each channel (tSS) is set by the soft-start The EN pin enables the controller of the ISL85033. When the capacitor (CSS) as shown by Equation3. voltage on the EN pin exceeds its logic rising threshold, the controller initiates the 2ms soft-start function for the PWM CSSF = 2.5*tSSs (EQ. 3) regulator. If the voltage on the EN pin drops below the falling threshold, the buck regulator shuts down. The maximum CSS value is recommended not to exceed 100nF. If EN1 and EN2 pins are driven by an external signal, the Ratiometric tracking is achieved in Figure40 by using the same minimum off-time for EN1 and EN2 should be: value for the soft-start capacitor on each channel; it is measured in Figure30. EN_T_off s = 10sC 2.2nF (EQ. 1) SS By connecting a feedback network from VOUT1 to the SS2 pin Where CSS is the soft-start pin capacitor (nF). The ISL85033 does with the same ratio that sets VOUT2 voltage, absolute tracking not have debouncing to the EN1 and EN2 external signals. shown in Figure41 is implemented. The measurement is shown in Figure31. If the output of Channel 1 is shorted to GND, it will Power-good enter overcurrent hiccup mode, SS2 will be pulled low through PG is the open-drain output of a window comparator that the added resistor between VOUT1 and SS2 and this will force continuously monitors the buck regulator output voltage via the FB Channel 2 into hiccup as well. If the output of Channel 2 is FN6676 Rev 8.00 Page 16 of 26 February 17, 2015

ISL85033 shorted to GND with VOUT1 in regulation, it will enter overcurrent hiccup mode with a very short hiccup waiting time. The reason is VOUT1 5.0V that VOUT1 is still in regulation and can pull up SS2 very quickly SS1 C3 via the resistor added between VOUT1 and SS2. C1 47nF Figure42 illustrates output sequencing. When EN1 is high and SS2 EN2 is floating, OUT1 comes up first and OUT2 will not start until ISL85033 OUT1>90% of its regulation point. If EN1 is floating and EN2 is VOUT2 3.3V high, OUT2 comes up first and OUT1 will not start until OUT2>90% of its regulation point. If EN1=EN2 = high, OUT1 C4 and OUT2 come up at the same time. Please refer to Table1 for conditions related to Figure42 (Output Sequencing). TABLE 1. OUTPUT SEQUENCING R2 R1 EN1 EN2 VOUT1 VOUT2 NOTE 8.06k 25.5k High Floating First After VOUT1>90% Floating High After VOUT2>90% First FIGURE 41. ABSOLUTE START-UP High High Same time Same time as VOUT2 as VOUT1 Floating Floating Not Allowed VOUT1 5.0V SS1 C1 C3 22nF SS1 VOUT1 5.0V SS2 ISL85033 C3 C1 C2 EN1 22nF 22nF VOUT2 3.3V SS2 ISL85033 EN2 C4 C2 47nF VOUT2 3.3V C4 FIGURE 42. OUTPUT SEQUENCING Protection Features FIGURE 39. INDEPENDENT START-UP The ISL85033 limits the current in all on-chip power devices. Overcurrent protection limits the current on the two buck regulators and internal LDO for VCC. VOUT1 5.0V SS1 Buck Regulator Overcurrent Protection C3 C1 22nF During PWM on-time, current through the internal switching SS2 MOSFET is sampled and scaled through an internal pilot device. ISL85033 The sampled current is compared to a nominal 5A overcurrent limit. If the sampled current exceeds the overcurrent limit VOUT2 3.3V reference level, an internal overcurrent fault counter is set to 1 C2 C4 and an internal flag is set. The internal power MOSFET is 22nF immediately turned off and will not be turned on again until the next switching cycle. The protection circuitry continues to monitor the current and FIGURE 40. RATIOMETRIC START-UP turns off the internal MOSFET as described. If the overcurrent condition persists for 17 sequential clock cycles, the overcurrent fault counter overflows indicating an overcurrent fault condition exists. The regulator is shutdown and power-good goes low. The buck controller attempts to recover from the overcurrent condition after waiting 8 soft-start cycles. The internal overcurrent flag and counter are reset. A normal soft-start cycle FN6676 Rev 8.00 Page 17 of 26 February 17, 2015

ISL85033 is attempted and normal operation continues if the fault Synchronization Control condition has cleared. If the overcurrent fault counter overflows The frequency of operation can be synchronized up to 2MHz by during soft-start, the converter shuts down and this hiccup mode an external signal applied to the SYNCIN pin. The falling edge on operation repeats. the SYNCIN triggers the rising edge of PHASE1/2. The switching Thermal Overload Protection frequency for each output is half of the SYNCIN frequency. Thermal overload protection limits maximum junction Output Inductor Selection temperature in the ISL85033. When the junction temperature The inductor value determines the converter’s ripple current. (TJ) exceeds +150°C, a thermal sensor sends a signal to the fault Choosing an inductor current requires a somewhat arbitrary monitor. choice of ripple current, I. A reasonable starting point is 30% of The fault monitor commands the buck regulator to shutdown. total load current. The inductor value can then be calculated When the junction temperature has decreased by 20°C, the using Equation5: regulator will attempt a normal soft-start sequence and return to V –V V normal operation. For continuous operation, the +125°C L = -----I--N--------------O----U----T--------O----U----T--- (EQ. 5) f I V junction temperature rating should not be exceeded. SW IN Increasing the value of inductance reduces the ripple current and BOOT Undervoltage Protection thus ripple voltage. However, the larger inductance value may If the BOOT capacitor voltage falls below 2.5V, the BOOT reduce the converter’s response time to a load transient. The undervoltage protection circuit will pull the phase pin low through inductor current rating should be such that it will not saturate in a 1Ω switch for 400ns to recharge the capacitor. This operation overcurrent conditions. may arise during long periods of no switching as in no load Buck Regulator Output Capacitor Selection situations. An output capacitor is required to filter the inductor current. The Application Guidelines Output ripple voltage and transient response are 2 critical factors when considering output capacitance choice. The current mode Operating Frequency control loop allows the usage of low ESR ceramic capacitors and The ISL85033 operates at a default switching frequency of thus smaller board layout. Electrolytic and polymer capacitors 500kHz if FS is tied to VCC. Tie a resistor from FS to GND to may also be used. program the switching frequency from 300kHz to 2MHz, as Additional consideration applies to ceramic capacitors. While shown in Equation4. [Minimum on-time of 150ns (typical) in they offer excellent overall performance and reliability, the actual conjunction with the input and output voltage should be in-circuit capacitance must be considered. Ceramic capacitors considered when selecting the maximum operating frequency]. are rated using large peak-to-peak voltage swings and with no DC R k = 122kt–0.17s (EQ. 4) bias. In the DC/DC converter application, these conditions do not FS reflect reality. As a result, the actual capacitance may be Where t is the switching period in µs. considerably lower than the advertised value. Consult the manufacturers data sheet to determine the actual in-application capacitance. Most manufacturers publish capacitance vs DC bias so that this effect can be easily accommodated. The effects of AC voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. The result of these 300 considerations can easily result in an effective capacitance 50% lower than the rated value. Nonetheless, they are a very good Ω) choice in many applications due to their reliability and extremely (kS 200 low ESR. F R The following equations allow calculation of the required capacitance to meet a desired ripple voltage level. Additional 100 capacitance may be used. For the ceramic capacitors (low ESR): 0 V = --------------------I----------------- (EQ. 6) 500 750 1000 1250 1500 1750 2000 OUTripple 8f C SW OUT fSW (kHz) Where I is the inductor’s peak-to-peak ripple current, fSW is the FIGURE 43. RFS SELECTION vs fSW switching frequency and COUT is the output capacitor. If using electrolytic capacitors then: V = I*ESR (EQ. 7) OUTripple FN6676 Rev 8.00 Page 18 of 26 February 17, 2015

ISL85033 Regarding transient response needs, a good starting point is to I determine the allowable overshoot in VOUT if the load is suddenly --R--I--M----S-- = D–D2 (EQ. 10) removed. In this case, energy stored in the inductor will be o transferred to COUT causing its voltage to rise. After calculating Where D = VO/VIN capacitance required for both ripple and transient needs, choose The input ripple current is graphically represented in Figure45. the larger of the calculated values. Equation8 determines the required output capacitor value in order to achieve a desired 0.6 overshoot relative to the regulated voltage. IOUT2*L 0.5 COUT = -V----O----U----T----2----*-----V----O-----U----T----M----A----X--------V----O-----U----T------2-----–----1----- (EQ. 8) 0.4 Wallhoewreed V dOuUrTiMngA Xth/VeO rUemT iosv tahle o rfe tlhaeti vloea md.a Fxoimr aunm o ovveersrshhoooot to f 5%, /IMSO 0.3 R the equation becomes Equation9: I 0.2 C = ---------------I--O-----U----T----2---*---L----------------- (EQ. 9) OUT 2 2 VOUT *1.05 –1 0.1 Figure44 shows the relationship of COUT and % overshoot at three 0 different output voltages. L is assumed to be 7µH and IOUT is 3A. 0 0.2 0.4 0.6 0.8 DUTY CYCLE (D) FIGURE 45. IRMS/IO vs DUTY CYCLE A minimum of 10µF ceramic capacitance is required on each VIN 80 pin. The capacitors must be as close to the IC as physically possible. Additional capacitance may be used. (µF)T 60 3.3VOUT Loop Compensation Design U O 40 The ISL85033 uses a constant frequency current mode control C 5VOUT architecture to achieve simplified loop compensation and fast loop transient response. 20 12VOUT The compensator schematic is shown in Figure47. As mentioned 0 in the COUT selection, ISL85033 allows the usage of low ESR 1.02 1.04 1.06 1.08 1.10 output capacitor. Choice of the loop bandwidth fc is somewhat VOUTMAX/VOUT arbitrary but should not exceed 1/4 of the switching frequency. As a starting point, the lower of 100kHz or 1/6 of the switching FIGURE 44. COUT vs OVERSHOOT VOUTMAX/VOUT frequency is reasonable. The following equations determine initial component values for the compensation, allowing the Current Sharing Configuration designer to make the selection with minimal effort. Further detail In current sharing configuration, FB1 is connected to FB2, EN1 to is provided in “Theory of Compensation” on page20 to allow fine EN2, COMP1 to COMP2 and VOUT1 to VOUT2 as shown in Figure3 tuning of the compensator. ochna pnangeel v5a. lAuse .a S rienscuel tt,h teh etw eoq cuhivaanlennetls g amr ed oouubt-loefs-p ihtsa ssein, gtlhee Compensation resistor R1 is given by Equation11: frequency will be 2x the channel switching frequency. Ripple R = 2--------f--c---V----o----C----o----R----T-- (EQ. 11) current cancellation will reduce the ripple current seen by the 1 g V m FB output capacitors and thus lower the ripple voltage. This results in the ability to use less capacitance than would be required by a Which, when applied to the ISL85033 becomes: single phase design of similar rating. Ripple current cancellation R k= 0.008247f V C (EQ. 12) 1 c o o also reduces the ripple current seen at the input capacitors. Input Capacitor Selection Where Co is the output capacitor value [µF], fc = loop bandwidth [kHz] and Vo is the output voltage [V]. To reduce the resulting input voltage ripple and to minimize EMI by forcing the very high frequency switching current into a tight Compensation capacitors C1 [nF], C2 [pF] are given by Equation13: local loop, an input capacitor is required. The input capacitor 3 6 must have adequate ripple current rating, which can be C V 10 C R 10 o o o c (EQ. 13) approximated by Equation10. If capacitors other than MLCC are C1 = ------------I-----------R------------------,C2= ------------------R----------------------- o 1 1 used, attention must be paid to ripple and surge current ratings. Where Io [A] is the output load current, R1 (Ω) and RC (Ω) is the ESR of the output capacitor Co. FN6676 Rev 8.00 Page 19 of 26 February 17, 2015

ISL85033 Example: Vo = 5V, Io = 3A, fSW = 500kHz, fc = 50kHz, Power Stage Transfer Functions Co=47µF/Rc= 5mΩ, then the compensation resistance R1=96kΩ. Transfer function F1(S) from control to output voltage is calculated in Equation17: The compensation capacitors are: S 1+------------ Cca1p =a c8i1ta5npcFe, Cfr2o m= 2V.C5OpMF P(T thoe GreN Dis; athpeprreofxoimrea, tCe2ly i s3 poFp tpioanraasl)i.t ic F1S = v-ˆ-d-ˆ-o-- = VIN--S--------2-------+----------------S------e--------s-----r--+-----1-- (EQ. 17) 2  Q  o p Theory of Compensation o 1 Co 1 The sensed current signal is injected into the voltage loop to Where  = ---------------,Q R ------- = --------------- achieve current mode control to simplify the loop compensation esr RcCo p o L o LCo design. The inductor is not considered as a state variable for Transfer function F2(S) from control to inductor current is given current mode control and the system becomes a single order by Equation18: system. It is much easier to design a compensator to stabilize the S voltage loop than voltage mode control. Figure46 shows the ˆIo VIN 1+-----z- small signal model of the synchronous buck regulator. F2S = -d-ˆ-- = R-----o-----+----R-----L-- -S----2---------------S------------------- (EQ. 18) -------+---------------+1 ^iIN ^iL LL V^O o2 oQp ++ 1 V^IN IILd^ 11::DD VINd^ Where z = R-----o----C----o-- RRcc ++ RT RRoo Current loop gain Ti(S) is expressed as Equation19: CCoo TiS = RTFmF2SHeS (EQ. 19) d^ TTi(S) The voltage loop gain with open current loop is calculated in K Equation20: FFmm T S = KF F SA S (EQ. 20) v m 1 v The voltage loop gain with current loop closed is given by + HHee((SS)) TTv((SS)) Equation21: ^ VCOMP --AAvv((SS)) TvS (EQ. 21) L S = ------------------------ v 1+TS i FIGURE 46. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK V REGULATOR K = -----F---B---, V Where V FB is the feedback voltage of the voltage o PWM Comparator Gain Fm error amplifier. If Ti(S)>>1, then Equation21 can be simplified as shown in Equation22: The PWM comparator gain Fm for peak current mode control is given by Equation14: 1+-----S------- dˆ 1 L S= V-----F---B---R-----o-----+----R-----L-----------------e---s----r-A----v------S-----,  -------1-------- (EQ. 22) Fm = v-ˆ------------------- = ---S---------+----S-----------T----- (EQ. 14) v Vo RT 1+--S----- HeS p RoCo COMP e n s  p Where Se is the slew rate of the slope compensation and Sn is Equation22 shows that the system is a single order system, given by Equation15. which has a single pole located at  before the half switching P VIN–Vo (EQ. 15) frequency. Therefore, a simple type II compensator can be easily S = R ----------------------- n T L used to stabilize the system. Where RT is transresistance and is the product of the current sensing resistance and gain of the current amplifier in current loop. CURRENT SAMPLING TRANSFER FUNCTION He(S) In current loop, the current signal is sampled every switching cycle. Equation16 shows the transfer function: 2 S S H S= -------+---------------+1 (EQ. 16) e 2  Q  n n n 2 Where Qn and n are given by Qn=–---= n= fS. FN6676 Rev 8.00 Page 20 of 26 February 17, 2015

ISL85033 VVoo Put the compensator zero at 6.6kHz (~1.5x CoRo), and put the compensator pole at ESR zero, which is 1.45MHz. The compensator capacitors are: R2 C3 VV C1 = 470pF, C2 = 3pF (There is approximately 3pF parasitic FFBB -- VVCCOOMMPP capacitance from VCOMP to GND; therefore, C2 is optional). GM VVRREEFF Figure48A shows the simulated voltage loop gain. It is shown R3 ++ that it has 80kHz loop bandwidth with 69° phase margin and R1 15dB gain margin. Optional addition phase boost can be added C2 to the overall loop response by usingC3. C1 60 45 FIGURE 47. TYPE II COMPENSATOR 30 GAIN (dB) Figure47 shows the type II compensator and its transfer function 15 is expressed as Equation23: 1+-----S--------1+-----S-------- 0 vˆ g      AvS= ----C-v-ˆ--O-F---BM-----P---= C-----1-----+-m---C-----2-- --------------S---c---z--1--1--+-------------S------------------c---z---2---- (EQ. 23) -15    cp -30100 1•103 1•104 1•105 1•106 Where: FIGURE 48A. 1 1 C1+C2 (EQ. 24)  = ---------------,  =--------------- = ----------------------- cz1 R C cz2 R C cp R C C 1 1 2 3 1 1 2 100 The compensator design goal is: 80 High DC gain Loop bandwidth fc: 14---to1--1--0--fSW 60 PHASE (°) Gain margin: >10dB 40 Phase margin: 40° 20 The compensator design procedure is shown in Equation25: 0 1 Put compensator zero  = 1to3--------------- (EQ. 25) cz1 R C o 0 -20 100 1•103 1•104 1•105 1•106 Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero FIGURE 48B. frequency or half switching frequency, whichever is lower. Rectifier Selection The loop gain Tv(S) at crossover frequency of fc has unity gain. Current circulates from ground to the junction of the external Therefore, the compensator resistance R1 is determined by Schottky diode and the inductor when the high-side switch is off. Equation26: As a consequence, the polarity of the switching node is negative 2f V C R with respect to ground. This voltage is approximately -0.5V (a R = ----------c-------o--------o--------T-- (EQ. 26) 1 g V Schottky diode drop) during the off-time. The rectifier's rated m FB reverse breakdown voltage must be at least equal to the Where gm is the transconductance of the voltage error amplifier, maximum input voltage, preferably with a 20% derating factor. typically 200µA/V. Compensator capacitor C1 is then given by The power dissipation when the Schottky diode conducts is Equation27: expressed in Equation28: C1 = R--------1---------,C2= 2--------R----1----f--------- (EQ. 27) P W = I V 1–V-----O----U----T--- (EQ. 28) 1 cz 1 esr D OUT D  VIN  Example: VIN = 12V, Vo = 5V, Io = 3A, fSW = 500kHz, Where: Co=22µF(derated value over voltage, temperature)/5mΩ, L=5.6µH, gm = 200µs, RT = 0.21, VFB=0.8V, Se = 1.1105V/s, The VD is the voltage drop of the Schottky diode. Selection of the Sn=3.4105V/s, fc=80kHz, then compensator resistance Schottky diode is critical in terms of the high temperature R1=72kΩ. reverse bias leakage current, which is very dependent on VIN and exponentially increasing with temperature. Due to the nature of FN6676 Rev 8.00 Page 21 of 26 February 17, 2015

ISL85033 reverse bias leakage vs temperature, the diode should be Layout Considerations carefully selected to operate in the worst case circuit conditions. Layout is very important in high frequency switching converter Catastrophic failure is possible if the diode chosen experiences designs. With power devices switching efficiently between thermal runaway at elevated temperatures. Refer to Application 100kHz and 600kHz, the resulting current transitions from one Notes for AN1574, AN1605, AN1584 diode selection listed on device to another cause voltage spikes across the page1. interconnecting impedances and parasitic circuit elements. Power Derating Characteristics These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful To prevent the ISL85033 from exceeding the maximum junction component layout and printed circuit board design minimizes temperature, some thermal analysis is required. The these voltage spikes. temperature rise is given by Equation29: As an example, consider the turn-off transition of the upper T = PD  (EQ. 29) RISE JA MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and Where PD is the power dissipated by the regulator and θJA is the is picked up by the Schottky diode. Any parasitic inductance in thermal resistance from the junction of the die to the ambient the switched current path generates a large voltage spike during temperature. The junction temperature, TJ, is given by the switching interval. Careful component selection, tight layout Equation30: of the critical components and short, wide traces minimizes the T = T +T  (EQ. 30) magnitude of voltage spikes. J A RISE There are two sets of critical components in the ISL85033 Where TA is the ambient temperature. For the QFN package, the switching converter. The switching components are the most θJA is +38°C/W. critical because they switch large amounts of energy and The actual junction temperature should not exceed the absolute therefore tend to generate large amounts of noise. Next are the maximum junction temperature of +125°C When considering small signal components which connect to sensitive nodes or the thermal design, (consider the thermal needs of the rectifier supply critical bypass current and signal coupling. diode). A multilayer printed circuit board is recommended. Figure50 The ISL85033 delivers full current at ambient temperatures up shows the connections of the critical components in the to +85°C if the thermal impedance from the thermal pad converter. Note that capacitors CIN and COUT could each maintains the junction temperature below the thermal shutdown represent numerous physical capacitors. Dedicate one solid level, depending on the Input Voltage/Output Voltage layer, (usually a middle layer of the PC board) for a ground plane combination and the switching frequency. The device power and make all critical component ground connections with vias to dissipation must be reduced to maintain the junction this layer. Dedicate another solid layer as a power plane and temperature at or below the thermal shutdown level. Figure49 break this plane into smaller islands of common voltage levels. illustrates the power derating versus ambient temperature for Keep the metal runs from the PHASE terminals to the output the ISL85033 evaluation kit. Note that the evaluation kit derating inductor short. The power plane should support the input power curve is based on total circuit dissipation, not IC dissipation and output power nodes. Use copper filled polygons on the top alone. and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. 120 In order to dissipate heat generated by the internal LDO and 110 MOSFET, the ground pad should be connected to the internal 100 ground plane through at least four vias. This allows the heat to T C) 90 BIENRE (° 7800 JA = +38°C/W mthroovueg ahw aa ylo fwro imm ptheed aICn caen dp aatlhs.o ties the pad to the ground plane AMTU 60 M RA 50 The switching components should be placed close to the MUPE 40 ISL85033 first. Minimize the length of the connections between AXIEM 30 the input capacitors, CIN, and the power switches by placing MT 20 them nearby. Position both the ceramic and bulk input capacitors 10 as close to the upper MOSFET drain as possible. Position the 0 0 1 2 3 4 5 6 7 8 9 10 11 12 output inductor and output capacitors between the upper and ISL85033EVAL1ZB EVALUATION BOARD Schottky diode and the load. TOTAL POWER DISSIPATION (W) The critical small signal components include any bypass FIGURE 49. POWER DERATING CURVE capacitors, feedback components, and compensation components. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required. FN6676 Rev 8.00 Page 22 of 26 February 17, 2015

ISL85033 1 2 p p m m Fb1 Fb2 o o C C L1 ISSLL8855003333 L2 LX1 trace LX2 trace .. .. .. .... .... .... t vias t D1 o o D2 o o b b C C Cin1 Cin2 VOUT2 Cout1 Cout2 VOUT1 VOUT2 1 2 N N I I V V FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN6676 Rev 8.00 Page 23 of 26 February 17, 2015

ISL85033 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE February 17, 2015 FN6676.8 Page21, paragraph below Equation 27, changed “Co = 220µF/5mΩ...” to "Co = 22µF (derated value over voltage, temperature)/5mΩ... April 17, 2014 FN6676.7 On page16 in the "Output Tracking and Sequencing" changed the sentence "Maximum CSS value is 50nF" to "The maximum CSS value is recommended not to exceed 100nF". Figure39 on page17, changed C1 from 0.1µF to 22nF and C2 from 0.2µF to 47nF. Figure40 on page17, changed the value of both C1 and C2 to 22nF each. Figure41 on page17, changed C1 value to 47nF. Figure42 on page17, changed C1 and C2 value to 22nF each. On page18 in the Operating Frequency chapter, after the sentence "Tie a resistor from FS to GND to program the switching frequency from 300kHz to 2MHz, as shown in Equation 4." Added : "Minimum on-time of 150ns (typical) in conjunction with input and output voltage should be considered when selecting the maximum operating frequency". November 2, 2011 FN6676.6 In the “Pin Descriptions” on page3, added the following to end of EN1, EN2 description: "If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be: EN_T_off s = 10sC 2.2nF SS where CSS is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external signals." In “Enable and Disable” on page16, adding the following: "If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be: EN_T_off s = 10sC 2.2nF SS where CSS is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external signals." Adding the following after Equation 3 on page16: "Maximum Css value is 50nF". In the “Pin Descriptions” on page3, added the following to the end of SS1, SS2 description: "Maximum Css value is 50nF". October 7, 2011 FN6676.5 In “Absolute Maximum Ratings” on page8, changed: PHASE1/2 to GND . . . . .-0.3V to +33V to: PHASE1/2 to GND . . . . .-7V (<10ns) /-0.3V (DC) to +33V September 14, 2011 FN6676.4 In the “Pin Descriptions” on page4, for “SYNCIN”, replaced “Set the internal switching frequency 20% lower than the external SYNC frequency applied to the SYNCIN pin" with "External SYNC frequency applied to the SYNCIN pin should be at least 2.4 times the internal switching frequency setting" August 9, 2011 On page8, changed parameter name from “Syncronization Frequency” to “Switching Frequency”. April 5, 2011 FN6676.3 Converted to new template Updated Intersil Trademark statement at bottom of page 1 per directive from Legal. Page 2 in the pin table definition, please add the following sentence to the Pin 11 (VCC) description after “Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7μF ceramic capacitor.” “This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).” Page 8 all Absolute Max Ratings that are “5.5” should be changed to “5.9” October 15, 2010 FN6676.2 Added the following sentence to the “SYNCIN” description in the “Pin Descriptions” table on page4: “Set the internal switching frequency 20% lower than the external SYNC frequency applied to the SYNCIN pin.” Added the following sentence to “Synchronization Control” on page18: “The switching frequency for each output is half of the SYNCIN frequency.” Revised tape and reel note in “Ordering Information” on page7 from: “Add “-T” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications” to: “Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications” This is in order to delineate all tape and reel options. FN6676 Rev 8.00 Page 24 of 26 February 17, 2015

ISL85033 Revision History (Continued) The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE September 14, 2010 Corrected Eq. 2 on page16 from: R x0.8V 2 R = ---------------------------------- 3 V –0.8V OUT to: R = V –0.8R 0.8 2 OUT 3 Revised preceding paragraph from: “The output voltage programming resistor, R3, depends on the value chosen for the feedback resistor, R2, and the desired output voltage, VOUT, of the regulator. Equation 2 describes the relationship between VOUT and resistor values. R2 is often chosen to be in the 1kΩ to 10kΩ range.” to: “The output voltage programming resistor, R2, depends on the value chosen for the feedback resistor, R3, and the desired output voltage, VOUT, of the regulator. Equation 2 describes the relationship between VOUT and resistor values. R3 is often chosen to be in the 1kΩ to 10kΩ range.” July 21, 2010 FN6676.1 Changed MIN/MAX for “Soft-start Charging Current” on page8 from 1.5/2.5µA to 1.4/2.6µA July 18, 2010 FN6676.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2010-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6676 Rev 8.00 Page 25 of 26 February 17, 2015

ISL85033 Package Outline Drawing L28.4x4 28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 9/06 4 . 00 A 2 . 50 PIN 1 B 0 . 40 PIN #1 INDEX AREA INDEX AREA CHAMFER 0 . 400 X 45° 22 28 21 1 F E R 4 . 00 2 . 50 0 . 40 x 6 = 2.40 3 . 20 4 0 . 15 7 0 . 10 2X 14 8 0 . 20 ±0 . 05 0 . 10M C A B 0 . 4 x 6 = 2 . 40 REF TOP VIEW 3 . 20 BOTTOM VIEW SEE DETAIL X'' 0 . 10C (3 . 20) C PACKAGE BOUNDARY MAX. 0 . 80 SEATING PLANE (28X 0 . 20) 0 . 00 - 0 . 05 0 . 20 REF 0 . 08C SIDE VIEW 0) 0) 5 2 2 . 3 . ( ( (0 . 40) 0 . 20 REF C 5 (0 . 40) 0 ~ 0 . 05 (2 . 50) (28X 0 . 60) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Controlling dimensions are in mm. Dimensions in ( ) for reference only. 2. Unless otherwise specified, tolerance : Decimal ±0.05 Angular ±2° 3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994. 4. Bottom side Pin#1 ID is diepad chamfer as shown. 5. Tiebar shown (if present) is a non-functional feature. FN6676 Rev 8.00 Page 26 of 26 February 17, 2015