DATASHEET ISL8120 FN6641 Dual/n-Phase Buck PWM Controller with Integrated Drivers Rev.3.00 July 20, 2016 The ISL8120 integrates two voltage-mode PWM leading-edge Features modulation control, with input feed-forward synchronous buck PWM controllers, to control a dual independent voltage • Wide VIN range operation: 3V to 22V regulator or a 2-phase single output regulator. It also - VCC operation from 3V to 5.60V integrates current sharing control for the power module to • Excellent output voltage regulation: 0.6V ±0.6%/±0.9% operate in parallel, which offers high system flexibility. internal reference over commercial/industrial temperature The ISL8120 integrates an internal linear regulator, which • Frequency synchronization generates VCC from input rail for applications with only one single supply rail. The internal oscillator is adjustable from • Programmable phase shift for 1-, 2-, 3-, 4-, 6-, up to 150kHz to 1.5MHz, and is able to synchronize to an external 12-phase applications clock signal for frequency synchronization and phase paralleling • Fault hand shake capability for high system reliability applications. Its PLL circuit can output a phase-shift •Digital soft-start with precharged output start-up capability programmable clock signal for the system to be expanded to 3-, 4-, 6-, 12- phases with desired interleaving phase shift. • Dual independent channel enable inputs with precision voltage monitor and voltage feed-forward capability The ISL8120’s Fault Hand Shake feature protects any channel - Programmable input voltage POR and its hysteresis with a from overloading/stressing due to system faults or phase resistor divider at EN input failure. The undervoltage fault protection features are also designed to prevent a negative transient on the output voltage • Extensive circuit protection functions: output overvoltage, during falling down. This eliminates the Schottky diode that is undervoltage, overcurrent protection, over temperature and used in some systems for protecting the load device from pre-power-on reset overvoltage protection option reversed output voltage damage. Applications Related Literature • Power supply for datacom/telecom and POL • Technical Brief TB389 “PCB Land Pattern Design and Surface • Paralleling power module Mount Guidelines for QFN (MLFP) Packages” • Wide and narrow input voltage range buck regulators •AN1528, “ISL8120EVAL3Z Evaluation Board Setup Procedure” • DDR I and II applications •AN1607, “ISL8120EVAL4Z Evaluation Board Setup • High current density power supplies Procedure” • Multiple outputs VRM and VRD CHANNELS 1 AND 2 GATE DRIVE PVCC 3Ω BOOTn UGATEn PWMn 10kΩ GATE SHOOT- FAULT LOGIC CONTROL THROUGH PHASEn LOGIC PROTECTION 10kΩ LGATEn FIGURE 1. INTEGRATED DRIVER BLOCK DIAGRAM FN6641 Rev.3.00 Page 1 of 39 July 20, 2016

ISL8120 Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-Phase Operation with DCR Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2-Phase Operation with rDS(ON) Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Dual Regulators with DCR Sensing and Remote Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Double Data Rate I or II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3-Phase Regulator with Precision Resistor Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4-Phase Operation with DCR Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multiple Power Modules in Parallel with Current Sharing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3-Phase Regulator with Resistor Sensing and 1 Phase Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6-Phase Operation with DCR Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Voltage Feed-Forward. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Overvoltage and Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PRE-POR Overvoltage Protection (PRE-POR-OVP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Inductor Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Resistive Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Internal Series Linear and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Frequency Synchronization and Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Differential Amplifier for Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Internal Reference and System Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DDR and Dual Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FN6641 Rev.3.00 Page 2 of 39 July 20, 2016

ISL8120 Pin Configuration ISL8120 (32 LD QFN) TOP VIEW FB1 VMON1 VSEN1- VSEN1+ ISEN1B ISEN1A VCC BOOT1 32 31 30 29 28 27 26 25 COMP1 1 24 UGATE1 ISET 2 23 PHASE1 ISHARE 3 22 LGATE1 EN/VFF1 4 21 PVCC 33 GND FSYNC 5 20 LGATE2 EN/VFF2 6 19 PHASE2 CLKOUT/REFIN 7 18 UGATE2 PGOOD 8 17 BOOT2 9 10 11 12 13 14 15 16 COMP2 FB2 VMON2 VSEN2- VSEN2+ ISEN2B ISEN2A VIN Functional Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 COMP1 These pins are the error amplifier outputs. They should be connected to FB1, FB2 pins through desired compensation networks when both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the 9 COMP2 corresponding error amplifier is disabled and its output (COMP pin) is high impedance. Thus, in multiphase operations, all other SLAVE phases’ COMP pins can tie to the MASTER phase’s COMP1 pin (1st phase), which modulates each phase’s PWM pulse with a single voltage feedback loop. While the error amplifier is not disabled, an independent compensation network is required for each cascaded IC. 2 ISET This pin sources a 15µA offset current plus the average current of both channels in multiphase mode or only Channel 1’s current in independent mode. The voltage (VISET) set by an external resistor (RISET) represents the average current level of the local active channel(s). 3 ISHARE This pin is used for current sharing purposes and is configured to current share bus representing all modules’ average current. It sources 15µA offset current plus the average current of both channels in multiphase mode or Channel 1’s current in independent mode. The share bus (ISHARE pins connected together) voltage (VISHARE) set by an external resistor (RISHARE) represents the average current level of all ISL8120 controller connected to current share bus. The ISHARE bus voltage compares with ISET voltage to generates current share error signal for current correction block of each cascaded controller. The share bus impedance RISHARE should be set as RISET/NCTRL (RISET divided by number of ISL8120 in current sharing controllers). There is a 1.2V threshold for average overcurrent protection on this pin. VISHARE is compared with a 1.2V threshold for average overcurrent protections. For full-scale current, RISHARE should be 1.2V/123µA = ~10kΩ. Typically 10kΩ is used for RSHARE and RSET. 4 EN/VFF1 These pins have triple functions. The voltage on EN/FF_ pin is compared with a precision 0.8V threshold for system enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel can be disabled 6 EN/VFF2 independently. By connecting these pins to the input rail through a voltage resistor divider, the input voltage can be monitored for UVLO (Undervoltage Lockout) function. The undervoltage lockout and its hysteresis levels can be programmed by these resistor dividers. The voltages on these pins are also fed into the controller to adjust the sawtooth amplitude of each channel independently to realize the feed-forward function. Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins are pulled low to communicate the information to other cascaded ICs. FN6641 Rev.3.00 Page 3 of 39 July 20, 2016

ISL8120 Functional Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 5 FSYNC The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal oscillator will lock to an external frequency source if this pin is connected to a switching square pulse waveform, typically the CLKOUT input signal from another ISL8120 or an external clock. The internal oscillator synchronizes with the leading edge of the input signal. 7 CLKOUT/REFIN This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal to synchronize with other ISL8120(s) with its VSEN2- pulled within 400mV of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase) operation. When the VSEN2- pin is not within 400mV of VCC, ISL8120 is in dual mode (dual independent PWM output). The clockout signal of this pin is not available in this mode, however, the ISL8120 can be synchronized to external clock. In dual mode, this pin works as the following two functions: 1. An external reference (0.6V target only) can be in place of the Channel 2’s internal reference through this pin for DDR/tracking applications (see “DDR and Dual Mode Operation” on page35). 2. The ISL8120 operates as a dual-PWM controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on REFIN (see “DDR and Dual Mode Operation” on page35). 8 PGOOD Provides an open drain power-good signal when both channels are within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON1/2) of the internal differential amplifiers. 32 FB1 These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1, VMON2 with the compensation feedback network. No direct connection between FB and VMON pins is allowed. With VSEN2- pulled 10 FB2 within 400mV of VCC, the corresponding error amplifier is disabled and the amplifier’s output is high impedance. FB2 is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal. See Table1 on page22. 31 VMON1 These pins are outputs of the unity gain amplifiers. They are connected internally to the OV/UV/PGOOD comparators. These pins should be connected to the FB1, FB2 pins by a standard feedback network when both channels are operating 11 VMON2 independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding differential amplifier is disabled and its output (VMON pin) is high impedance. In such an event, the VMON pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for both of the UV/OV comparator and output voltage feedback. 30 VSEN1- These pins are the negative inputs of standard unity gain operational amplifier for differential remote sense for the corresponding regulator (Channels 1and 2), and should be connected to the negative rail of the load/processor. 12 VSEN2- When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier and differential amplifier are disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels determine the relative phases between the internal controllers as well as the CLKOUT signal. See Table1 on page22. When configured as multiple power modules (each module with independent voltage loop) operating in parallel, in order to implement the current sharing control, a resistor (100Ω typical) needs to be inserted between the VSEN1- pin and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor), as shown in the “Typical Application Circuits” “Multiple Power Modules in Parallel with Current Sharing Control” on page13. This introduces a correction voltage for the modules with lower load current to keep the current distribution balanced among modules. The module with the highest load current will automatically become the master module. The recommended value for the VSEN1- resistor is 100Ω and it should not be large in order to keep the unit gain amplifier input impedance compatibility. 29 VSEN1+ These pins are the positive inputs of the standard unity gain operational amplifier for differential remote sense for the corresponding channel (Channels 1 and 2), and should be connected to the positive rail of the load/processor. These 13 VSEN2+ pins can also provide precision output voltage trimming capability by pulling a resistor from this pin to the positive rail of the load (trimming down) or the return (typical VSEN1-, VSEN2- pins) of the load (trimming up). The typical input impedance of VSEN+ with respect to VSEN- is 600kΩ. By setting the resistor divider connected from the output voltage to the input of the differential amplifier, the desired output voltage can be programmed. To minimize the system accuracy error introduced by the input impedance of the differential amplifier, a resistor below 1k is recommended to be used for the lower leg (ROS) of the feedback resistor divider. With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and VSEN2+ is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal. See Table1 on page22 for details. 28 ISEN1B These pins are the inverting (-) inputs of the current sensing amplifiers to provide rDS(ON), DCR, or precision resistor current sensing together with the ISEN1A, ISEN2A pins. Refer to “Typical Application Circuits” “2-Phase Operation with 14 ISEN2B DCR Sensing” on page7 for DCR sensing set up and “2-Phase Operation with rDS(ON) Sensing” on page8 for rDS(ON) sensing set up. FN6641 Rev.3.00 Page 4 of 39 July 20, 2016

ISL8120 Functional Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 27 ISEN1A These pins are the noninverting (+) inputs of the current sensing amplifiers to provide rDS(ON), DCR, or precision resistor current sensing together with the ISEN1B, ISEN2B pins. 15 ISEN2A 16 VIN This pin is the input of the internal linear regulator. It should be tied directly to the input rail. The internal linear device is protected against reverse bias generated by the remaining charge of the decoupling capacitor at PVCC when losing the input rail. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC. 25 BOOT1 These pins provide the bootstrap biases for the high-side drivers. Internal bootstrap diodes connected to the PVCC pin provide the necessary bootstrap charge. Its typical operational voltage range is 2.5V to 5.6V. 17 BOOT2 24 UGATE1 These pins provide the gate signals to drive the high-side devices and should be connected to the MOSFETs’ gates. 18 UGATE2 23 PHASE1 Connect these pins to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. These pins represent the return path for the high-side gate drives. 19 PHASE2 22 LGATE1 These pins provide the drive for the low-side devices and should be connected to the MOSFETs’ gates. 20 LGATE2 21 PVCC This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side drives. Its operational voltage range is 3V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10µF. 26 VCC This pin provides bias power for the analog circuitry. An RC filter is recommended between the connection of this pin to a 3V to 5.6V bias (typically PVCC). R is suggested to be a 5Ω resistor. And in 3.3V applications, the R could be shorted to allow the low end input in concerns of the VCC falling threshold. The VCC decoupling capacitor is strongly recommended to be as large as a 10µF ceramic capacitor. This pin can be powered either by the internal linear regulator or by an external voltage source. 33 GND The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad provides a return path for the low-side MOSFET drives and internal power circuitries as well as all analog signals. Connect this pad to the circuit ground with the shortest possible path (more than 5 to 6 vias to the internal ground plane, placed on the soldering pad are recommended). Ordering Information PART NUMBER PART TEMP. RANGE PACKAGE PKG. (Notes3, 4) MARKING (°C) (RoHS COMPLIANT) DWG.# ISL8120CRZ (Note1) ISL8120 CRZ 0 to +70 32 Ld QFN L32.5x5B ISL8120IRZ (Note2) ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B 1. Add “-T” suffix for 6000 unit Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. Add “-T” suffix for 6000 unit or “-TK” suffix for 1000 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL8120. For more information on MSL please see techbrief TB363. FN6641 Rev.3.00 Page 5 of 39 July 20, 2016

ISL8120 Controller Block Diagram PGOOD VCC VIN 8 26 16 EN1 EN2 INTERNAL PGOOD VMON1 POWER-ON LINEAR REGULATOR VCC CIRCUIT VMON2 RESET CH1_FAULT 21 PVCC CH2_FAULT 400mV SAW1 25 BOOT1 ICSH_CORR 24 UGATE1 MOSFET VSEN1- 30 INT. VREF E/A Σ DRIVER SS1 PWM1 23 PHASE1 VSEN1+ 29 CURRENT 22 LGATE1 BALANCE Ch1 FAULT VMON1 31 CIRCUIT FB1 32 PWM1 IAVG_CSICS1ICSH_ERR CHANNEL 1 27 ISEN1A CURRENT COMP1 1 SAMPLING 28 ISEN1B OV/UV COMP1 CHANNEL 1 ICS1 INT. VREF CH1 EN_TH SOFT-START AND OCP 7-CYCLE EN1 FAULT LOGIC DELAY 108µA EN/VFF1 4 IEN_HYS AVG_OCP 1.2V EN/VFF1 EN/VFF2 SAW1 3 ISHARE FSYNC 5 MOASSCTEILRL ACTLOORCK ICSH_CORR CSUHRARREENT ICSH_ERR BLOCK 2 ISET GENERATOR CLKOUT/ INT. VREF M/D CONTROL 7 REFIN ICS1 AVERAGE VCC IAVG_CS+15µA RELATIVE ICS2 CURRENT PHASE 400mV M/D CONTROL CONTROL M/D = 1 (Multiphase operation) : IAVG_CS = (ICS1+ICS2) / 2 M/D = 0 (Dual-output Operation) : IAVG_CS = ICS1 PVCC VSEN2- 12 VSEN2+ FB2 SAW2 VSEN2+ 13 17 BOOT2 VMON2 11 E/A Σ 18 UGATE2 MOSFET PWM2 SS2 DRIVER FB2 10 CURRENT IAVG_CSCh2 FAULT 19 PHASE2 BALANCE ICS2 COMP2 9 CIRCUIT ICSH_ERR 20 LGATE2 INT. VREF OV/UV CHANNEL 2 CH2 EN_TH EN2 COMP2 SOFT-START AND OCP 7-CYCLE 108µA DELAY EN/VFF2 6 FAULT LOGIC ICS2 PWM1 IEN_HYS CHANNEL 2 15 ISEN2A CURRENT SAMPLING 14 ISEN2B AVG_OCP M/D CONTROL EP FIGURE 2. CONTROLLER BLOCK DIAGRAM FN6641 Rev.3.00 Page 6 of 39 July 20, 2016

ISL8120 Typical Application Circuits 2-Phase Operation with DCR Sensing VIN +3V TO +22V CHFIN CBIN CF1 RCC CF2 VCC PVCC BOOT1 CBOOT1 VIN UGATE1 Q1 LOUT1 CF3 PHASE1 VOUT < VCC - 1.8V COUT1 LGATE1 Q2 EN/VFF1, 2 ISEN1A Local sensing (secondary sensing point) ISEN1B RISEN1 10 10 ISL8120 COMP1/2 ZCOMP1 FB1 RSET ISET VMON1/2 ISHARE VSEN1+ RFB1 VSENSE+ VSEN1- ROS1 CSEN1 VSENSE- Remote sensing PGOOD VIN BOOT2 CBOOT2 RFS FSYNC UGATE2 Q3 LOUT2 PHASE2 LGATE2 Q4 CLKOUT ISEN2A ISEN2B RISEN2 VCC FB2 VCC OR GND VSEN2+ VSEN2- VCC OR GND GND FIGURE 3. 2-PHASE OPERATION WITH DCR SENSING FN6641 Rev.3.00 Page 7 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) 2-Phase Operation with r Sensing DS(ON) VIN +3V TO +22V CHFIN CBIN CF1 RCC CF2 VCC PVCC BOOT1 CBOOT1 VIN UGATE1 Q1 LOUT1 CF3 PHASE1 VOUT ISEN1B RISEN1 COUT1 LGATE1 Q2 EN/FF1, 2 ISEN1A Local sensing (secondary sensing point) 10Ω 10Ω ISL8120 COMP1/2 ZCOMP1 FB1 RSET ISET VMON1/2 ISHARE VSEN1+ RFB1 VSENSE+ VSEN1- ROS1 CSEN1 VSENSE- Remote sensing PGOOD VIN BOOT2 CBOOT2 RFS FSYNC UGATE2 Q3 LOUT2 PHASE2 ISEN2B RISEN2 LGATE2 Q4 ISEN2A CLKOUT/REFIN VCC FB2 VCC OR GND VSEN2+ VSEN2- VCC OR GND GND FIGURE 4. 2-PHASE OPERATION WITH rDS(ON) SENSING FN6641 Rev.3.00 Page 8 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) Dual Regulators with DCR Sensing and Remote Sense VIN +3.3 TO +22V RCC CHFIN CBIN CF2 CF1 VCC PVCC BOOT1 CBOOT1 VIN UGATE1 Q1 LOUT1 PHASE1 CF3 VOUT1 COUT1 LGATE1 VIN 2kΩ Q2 ISEN1A 10Ω RISEN1 EN/FF1 ISEN1B 10Ω COMP1 ISL8120 ZCOMP1 FB1 ZFB1 VMON1 VSEN1+ RFB1 VSENSE1+ VCC CLKOUT/REFIN VSEN1- ROS1 CSEN1 VSENSE1- PGOOD VIN BOOT2 CBOOT2 RFS FSYNC UGATE2 Q3 LOUT2 PHASE2 VOUT2 LGATE2 Q4 COUT2 2kΩ VIN ISEN2A 10Ω ISEN2B EN/FF2 RISEN2 10Ω COMP2 ZCOMP2 FB2 ZFB2 RSET ISET VMON2 VSEN2+ RFB2 VSENSE2+ ISHARE VSEN2- ROS2 CSEN2 VSENSE2- GND FIGURE 5. DUAL REGULATORS WITH DCR SENSING AND REMOTE SENSE FN6641 Rev.3.00 Page 9 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) Double Data Rate I or II VIN +3.3 TO +22V RCC CHFIN CBIN CF2 CF1 VCC PVCC BOOT1 CBOOT1 VIN UGATE1 Q1 LOUT1 12..85VV ((DDDDRR II)I) PHASE1 CF3 VDDQ COUT1 LGATE1 RFS FSYNC 2kΩ Q2 ISEN1A 10Ω RISEN1 ISEN1B 10Ω COMP1 ISL8120 ZCOMP1 FB1 ZFB1 VMON1 VDDQ VSEN1+ RFB1 VSENSE1+ VSEN1- ROS1 CSEN1 VSENSE1- R*(VTT/0.6-1) (Notes5, 6) CLKOUT/REFIN VDDQ Or VIN 1nF R BOOT2 CBOOT2 1.25V (DDR I) UGATE2 Q3 LOUT2 00..99VV (DDR II) (Or tie REFIN pin to VMON1 pin) PHASE2 VTT LGATE2 Q4 COUT2 (VDDQ/2) 2kΩ ISEN2A 10Ω ISEN2B RISEN2 10Ω COMP2 ZCOMP1 FB2 PGOOD ZFB1 VMON2 RSET ISET VSEN2+ RFB2 VSENSE2+ ISHARE VSEN2- ROS2 CSEN2 VSENSE2- GND NOTES: 5. Setting the upper resistor to be a little higher than R*(VDDQ/0.6 - 1) will set the final REFIN voltage (stead state voltage after soft-start) derived from the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start. The other way is to add more delay at EN/VFF1 pin to have Channel 2 tracking VDDQ (check Table1 on page22 for more details). 6. Another way to set REFIN voltage is to connect VMON1 directly to the REFIN pin. FIGURE 6. DOUBLE DATA RATE I OR II FN6641 Rev.3.00 Page 10 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) 3-Phase Regulator with Precision Resistor Sensing VIN +3V TO +22V CF2 CIN VCC RCC PVCC CF1 BOOT1 CBOOT2 VIN CF3 UGATE1 Q1 LOUT2 PHASE1 ISL8120 EN/FF1 PHASE 2 LGATE1 Q2 CLKOUT/REFIN ISEN1A PGOOD ISEN1B COMP1 RISEN2 FB1 BOOT2 VMON1 UGATE2 PHASE2 VSEN1+ LGATE2 VSEN1- VCC ISEN2A ISEN2B GND EN/FF2 FSYNC FB2 VMON2 ISHARE VSEN2+ ISET R VSEN2- R VOUT COUT CF2 VCC RCC PVCC VIN CF1 BOOT1 VIN CBOOT1 CF3 FSYNC UGATE1 Q1 LOUT1 10Ω 10Ω RFS PHASE1 EN/FF1,2 LGATE1 Q2 PGOOD ISL8120 VIN ISEN1A BOOT2 PHASE 1 AND 3 VSENSE+ ISEN1B RISEN1 CBOOT3 LOUT3 Q3 UGATE2 COMP1/2 VSENSE- PHASE2 ZCOMP1 FB1 ZFB1 VMON1/2 Q4 LGATE2 VSEN1+ RFB1 ISEN2A ROS1 CSEN1 VSEN1- ISEN2B ISHARE FB2 RISEN3 VCC GND VSEN2+ R VSEN2- VCC CLKOUT/REFIN GND ISET R FIGURE 7. 3-PHASE REGULATOR WITH PRECISION RESISTOR SENSING FN6641 Rev.3.00 Page 11 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) 4-Phase Operation with DCR Sensing VIN +3V TO +22V CIN VCC RCC PVCC CF2 CF1 BOOT1 CBOOT2 VIN CF3 UGATE1 Q1 LOUT2 CLKOUT/REFIN PHASE1 VOUT PGOOD LGATE1 Q2 COUT EN/FF BUS EN/FF1, 2 VSEN1, 2+ ISEN1A FB2 ISL8120 ISEN1B VCC VSEN1,2- PHASE 2 AND 4 COMP1/2 RISEN2 10Ω VIN BOOT2 10Ω FB1 LOUCTB4OOT4 Q3 UGATE2 VMON1/2 RFB1 PHASE2 ISET ROS1 COS VSENSE1+ R Q4 LGATE2 GND 2ND DIVIDER TO AVOID VSENSE1- SINGLE POINT FAILURE ISEN2A FSYNC ISEN2B ISHARE RISEN4 R CF2 VCC RCC PVCC VIN CF1 BOOT1 VIN CBOOT1 CF3 FSYNC UGATE1 Q1 LOUT1 RFS PHASE1 LGATE1 Q2 EN/FF BUS EN/FF1, 2 PGOOD ISL8120 VIN ISEN1A BOOT2 PHASE 1 AND 3 ISEN1B RISEN1 CBOOT3 LOUT3 Q3 UGATE2 COMP1/2 ZCOMP1 PHASE2 FB1 ZFB1 VMON1/2 Q4 LGATE2 VSEN1+ RFB1 ISEN2A VSEN1- ROS1 CSEN1 RISEN3 ISEN2B FB2 ISHARE VCC VSEN2+ VCC R VSEN2- VCC CLKOUT/REFIN GND ISET R FIGURE 8. 4-PHASE OPERATION WITH DCR SENSING FN6641 Rev.3.00 Page 12 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) Multiple Power Modules in Parallel with Current Sharing Control +3V to +22V VIN CIN VCC RCC2 PVCC CF5 CF4 BOOT1 CBOOT3 VIN CF6 UGATE1 Q5 LOUT3 PGOOD PHASE1 VOUT2 FSYNC LGATE1 Q6 COUT2 EN EN/FF1, 2 2kΩ ISEN1A VIN BOOT2 ISEN1B LOUCTB4OOT4 Q7 UGATE2 RISEN3 10Ω PHASE2 COMP1/2 10Ω ZCOMP2 ISL8120 FB1 ZFB2 Q8 LGATE2 VMON1/2 2kΩ VSEN1+ RFB2 RISEN4 IISSEENN22BA VSEN1- ROS2 CSEN2 VVSSEENNSSEE22-+ VCC VSEN2+ 2M-OPHDAUSLEE #1 CLKOUT/RRECFISNR2 VLOAD FB2 VCC VSEN2- ISHARE VCC GND ISET R R CF2 VCC RCC1 PVCC VIN CF1 BOOT1 VIN CBOOT1 CF3 UPHGAASTEE11 Q1 LOUT1 VOUT1 EN/FF1, 2 LGATE1 Q2 COUT1 EN PGOOD 2kΩ VIN ISEN1A BOOT2 ISEN1B RISEN1 CBOOT2 LOUT2 Q3 UGATE2 COMP1/2 ZCOMP1 10Ω PHASE2 FB1 ZFB1 10Ω ISL8120 VMON1/2 Q4 LGATE2 VSEN1+ RFB1 2kΩ ISEN2A VSEN1- ROS1 CSEN1 VVSSEENNSSEE11+- RISEN2 ISEN2B RCSR1 ISHARE 2-PHASE VSEN2+ VCC FB2 MODULE #2 R VCC FSYNC VSEN2- VCC GND ISET R FIGURE 9. MULTIPLE POWER MODULES IN PARALLEL WITH CURRENT SHARING CONTROL FN6641 Rev.3.00 Page 13 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) 3-Phase Regulator with Resistor Sensing and 1 Phase Regulator VIN +3V TO +22V CF2 CIN VCC RCC PVCC CF1 BOOT1 CBOOT2 VIN CF3 UGATE1 Q1 LOUT2 VOUT1 PHASE1 EN/FF1 LGATE1 Q2 EN VOUT1 COUT1 EN/FF2 EN VOUT2 PGOOD ISEN1A VIN ISEN1B RISEN2 BOOT2 10Ω COMP1 CBOOT4 VOUT2 LOUT4 Q3 PUHGAASTEE22 FVBM1ON1 10Ω ISL8120 COUT2 VSEN1+ Q4 LGATE2 VSEN1- VSENSE1+ ISEN2A VCC ISET 10Ω ISEN2B VSENSE1- R 10Ω RISEN4 ZFB2 ZCOMP2 FSYNC FB2 VMON2 ISHARE VSEN2+ GND R VSENSE2+ VSEN2- PHASE 2 VSENSE2- CF2 VCC RCC PVCC VIN CF1 BOOT1 VIN CBOOT1 CF3 FSYNC UGATE1 Q1 LOUT1 RFS PHASE1 EN/FF1, 2 LGATE1 Q2 EN VOUT1 PGOOD VIN ISL8120 ISEN1A BOOT2 ISEN1B RISEN1 CBOOT3 LOUT3 Q3 UGATE2 COMP1/2 PHASE2 ZCOMP1 FB1 ZFB1 VMON1/2 Q4 LGATE2 RFB1 VSEN1+ ISEN2A ROS1 CSEN1 VSEN1- ISEN2B ISHARE RISEN3 VCC FB2 GND VSEN2+ PHASE 1 AND 3 CLKOUT/REFIN R VSEN2- VCC ISET VSEN2+ GND R FIGURE 10. 3-PHASE REGULATOR WITH RESISTOR SENSING AND 1 PHASE REGULATOR FN6641 Rev.3.00 Page 14 of 39 July 20, 2016

ISL8120 Typical Application Circuits (Continued) 6-Phase Operation with DCR Sensing VIN +3V TO +22V CF1 VCC RCC PVCC CF2 CIN BOOT1 CF3 VCILNKOUT/REFIN UPHGAASTEE11 Q1 CBOOT3LOUT3 EN/FF1, 2 LGATE1 Q2 PGOOD FB2 ISEN1A GND VSEN2+ ISL8120 ISEN1B VCC VSEN2- COMP1/2 RISEN3 VIN PHASE 3 AND 6 BOOT2 FB1 CBOOT6 VMON1/2 LOUT6 Q3 UGATE2 VSEN1+ PHASE2 VSEN1- VCC ISET Q4 LGATE2 R ISEN2A FSYNC ISEN2B GND ISHARE RISEN6 R CF1 VCC RCC PVBCOCOT1 CF2 VIN CF3 VIN UGATE1 Q1 CBOOT2LOUT2 PHASE1 EN/FF1,2 LGATE1 Q2 PGOOD ISEN1A VIN BOOT2 ISEN1B LOUCTB5OOT5 Q3 UGATE2 COMP1/2 RISEN2 PHASE2 FB1 ISL8120 VMON1/2 Q4 LGATE2 VSEN1+ VSEN1- VCC ISEN2A CLKOUT/REFIN ISEN2B FSYNC RISEN5 GND FB2 PHASE 2 AND 5 ISHARE VCC OR GND VSEN2+ ISET R VCC VSEN2- GND R VIN CF1 VCC RCC PVBCOCOT1 CF2 CF3 FSYNC VIN UPHGAASTEE11 Q1 CBOOT1LOUT1 VOUT1 EN/FF1, 2 LGATE1 Q2 PGOOD COUT1 ISEN1A VIN BOOT2 ISEN1B RISEN1 CBOOT4 VMON1 10Ω LOUT4 Q3 UGATE2 FB1 ZFB1 PHASE2 COMP1/2 ZCOMP1 10Ω ISL8120 VMON2 Q4 LGATE2 VSEN1+ ROS1 RFB1 RFB1 ISEN2A ISEN2B VSEN1- ROS1 CSEN1 VSENSE1+ RISEN4 GND FB2 ISHARE VSENSE1- VCC OR GND VVSSEENN22+- PHASE 1 AND 4 CISLEKTOUT/REFIN R VCC GND R FIGURE 11. 6-PHASE OPERATION WITH DCR SENSING FN6641 Rev.3.00 Page 15 of 39 July 20, 2016

ISL8120 Absolute Maximum Ratings Thermal Information Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +27V Thermal Resistance (Typical Notes7, 8) JA(°C/W) JC(°C/W) Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V 32 Ld QFN Package . . . . . . . . . . . . . . . . . . 32 3.5 Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +36V Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Phase Voltage, VPHASE . . . . . . . . . . . . . . . . . .(VBOOT - 7V) to VBOOT + 0.3V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 BOOT to PHASE Voltage, (VBOOT - VPHASE) . . . . . . . . . . -0.3V to VCC +0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Recommended Operating Conditions Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 22V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.6V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.6V Boot to Phase Voltage (Overcharged), (VBOOT - VPHASE). . . . . . . . . . . . <6V Commercial Ambient Temperature Range. . . . . . . . . . . . . . 0°C to +70°C Industrial Ambient Temperature Range . . . . . . . . . . . . . . .-40°C to +85°C Maximum Junction Temperature Range. . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note10) TYP (Note10) UNIT VCC SUPPLY CURRENT Nominal Supply VIN Current IQ_VIN VIN = 20V; VCC = PVCC; fSW=500kHz; 11 15 20 mA UGATE, LGATE = open Nominal Supply VIN Current IQ_VIN VIN = 3.3V; VCC = PVCC; 8 12 14 mA fSW=500kHz; UGATE, LGATE = open Shutdown Supply PVCC Current IPVCC EN = 0V, PVCC = 5V 0.5 1.0 1.4 mA Shutdown Supply VCC Current IVCC EN = 0V, VCC = 3V 7 10 12 mA INTERNAL LINEAR REGULATOR Maximum Current (Note9) IPVCC PVCC = 4V to 5.6V 250 mA PVCC = 3V to 4V 150 mA Saturated Equivalent Impedance (Note9) RLDO P-Channel MOSFET (VIN = 5V) 1 Ω PVCC Voltage Level PVCC IPVCC = 0mA; 0°C < TA < +85°C; 5.15 5.40 5.65 V VIN=12V IPVCC = 0mA; -40°C < TA < +85°C; 5.15 5.40 5.95 V VIN=12V Equivalent LDO Output Resistance RLDO_OUT VIN = 12V 0.3 Ω POWER-ON RESET Rising VCC Threshold 2.85 2.97 V Falling VCC Threshold 2.65 2.75 V Rising PVCC Threshold 0°C < TA < +75°C 2.85 2.97 V -40°C < TA < +85°C 2.85 3.05 V Falling PVCC Threshold 2.65 2.75 V FN6641 Rev.3.00 Page 16 of 39 July 20, 2016

ISL8120 Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note10) TYP (Note10) UNIT System Soft-Start Delay (Note9) tSS_DLY After PLL, VCC, and PVCC PORs, and 384 Cycles EN(s) above their thresholds ENABLE Turn-On Threshold Voltage 0.75 0.8 0.86 V Hysteresis Sink Current IEN_HYS 0°C < TA < +85°C 25 30 35 µA -40°C < TA < +85°C 23 30 35 µA Undervoltage Lockout Hysteresis (Note9) VEN_HYS VEN_RTH = 10.6V; VEN_FTH = 9V 1.6 V RUP = 53.6kΩ, RDOWN = 5.23kΩ Sink Current IEN_SINK VENFF = 1V 15.4 mA Sink Impedance REN_SINK VENFF = 1V 64 Ω OSCILLATOR Oscillator Frequency Range 150 1500 kHz Oscillator Frequency RFS = 100k, Figure42 on page33 344 377 406 kHz Total Variation VCC = 5V; -40°C < TA < +85°C -9 +9 % Peak-to-Peak Ramp Amplitude VRAMP VCC = 5V, VEN = 0.8V 1 VP-P Linear Gain of Ramp Over VEN GRAMP GRAMP = VRAMP/VEN 1.25 Ramp Peak Voltage VRAMP_PEAK VEN = VCC VCC - 1.4 V Peak-to-Peak Ramp Amplitude VRAMP VEN = VCC = 5.4V, RUP = 2k 3 VP-P Peak-to-Peak Ramp Amplitude VRAMP VEN = VCC = 3V; RUP = 2k 0.6 VP-P Ramp Amplitude Upon Disable VRAMP VEN = 0V; VCC = 3.5V to 5.5V 1 VP-P Ramp Amplitude Upon Disable VRAMP VEN = 0V; VCC < 3.4V VCC - 2.4 VP-P Ramp DC Offset VRAMP_OS 1 V FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP Synchronization Frequency VCC = 5V 150 1500 kHz PLL Locking Time VCC = 5.4V; fSW = 400kHz 105 µs VCC = 2.97V; fSW = 400kHz 150 µs Input Signal Duty Cycle Range (Note9) 10 90 % PWM Minimum PWM OFF Time tMIN_OFF 310 345 410 ns Current Sampling Blanking Time (Note9) tBLANKING 175 ns REFERENCE Channel 1 Reference Voltage (Include Error VREF1 -0°C < TA < +70°C 0.6 V and Differential Amplifiers’ Offsets) -0.6 0.6 % -40°C < TA < +85°C 0.6 V -0.7 0.7 % Channel 2 Reference Voltage (Include Error VREF2 -0°C < TA < +70°C 0.6 V and Differential Amplifiers’ Offsets) -0.75 0.75 % -40°C < TA < +85°C 0.6 V -0.75 0.95 % FN6641 Rev.3.00 Page 17 of 39 July 20, 2016

ISL8120 Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note10) TYP (Note10) UNIT ERROR AMPLIFIER DC Gain (Note9) RL = 10k, CL = 100pF, at COMP Pin 98 dB Unity Gain-Bandwidth (Note9) UGBW_EA RL = 10k, CL = 100pF, at COMP Pin 80 MHz Input Common-Mode Range (Note9) -0.2 VCC - 1.8 V Output Voltage Swing VCC = 5V 0.85 VCC - 1.0 V Slew Rate (Note9) SR_EA RL = 10k, CL = 100pF, at COMP Pin 20 V/µs Input Current (Note9) IFB Positive direction Into the FB pin 100 nA Output Sink Current ICOMP 3 mA Output Source Current ICOMP 6 mA Disable Threshold (Note9) VVSEN- VCC - 0.4 V DIFFERENTIAL AMPLIFIER DC Gain (Note9) UG_DA Unity Gain Amplifier 0 dB Unity Gain Bandwidth (Note9) UGBW_DA 5 MHz VSEN+ pin Sourcing Current IVSEN+ 0.2 1 2.5 µA Maximum Source Current for Current IVSEN1- VSEN1- Source current for current 350 µA Sharing (See Figure7 on page11) (Note9) Sharing when parallel multiple modules each of which has its own voltage loop Input Impedance RVSEN+_to VVSEN+/IVSEN+, VVSEN+ = 0.6V -600 kΩ _VSEN- Output Voltage Swing (Note9) 0 VCC - 1.8 V Input Common-Mode Range (Note9) -0.2 VCC - 1.8 V Disable Threshold (Note9) VVSEN- VMON1, VMON2 = Tri-state VCC - 0.4 V GATE DRIVERS Upper Drive Source Resistance RUGATE 45mA source current 1.0 Ω Upper Drive Sink Resistance RUGATE 45mA sink current 1.0 Ω Lower Drive Source Resistance RLGATE 45mA source current 1.0 Ω Lower Drive Sink Resistance RLGATE 45mA sink current 0.4 Ω OVERCURRENT PROTECTION Channel Overcurrent Limit (Note9) ISOURCE VCC = 2.97V to 5.6V 108 µA Channel Overcurrent Limit ISOURCE VCC = 5V; 0°C < TA < +70°C 94 108 122 µA VCC = 5V; -40°C < TA < +85°C 89 108 122 µA Share Pin OC Threshold VOC_ISHARE VCC = 2.97V to 5.6V 1.20 V (comparator offset included) VCC = 5V 1.16 1.20 1.22 V (comparator offset included) CURRENT SHARE Internal Balance Accuracy (Note9) VCC = 2.97V and 5.6V, 1% resistor sense, ±5 % 10mV signal Internal Balance Accuracy (Note9) VCC = 4.5V and 5.6V, 1% resistor sense, ±5 % 10mV signal FN6641 Rev.3.00 Page 18 of 39 July 20, 2016

ISL8120 Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). (Continued) MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note10) TYP (Note10) UNIT External Current Share Accuracy (Note9) VCC = 2.97V and 5.6V, 1% resistor sense, ±20 % 10mV signal POWER-GOOD MONITOR Undervoltage Falling Trip Point VUVF Percentage below reference point -15 -13 -11 % Undervoltage Rising Hysteresis VUVR_HYS Percentage above UV trip point 4 % Overvoltage Rising Trip Point VOVR Percentage above reference point 11 13 15 % Overvoltage Falling Hysteresis VOVF_HYS Percentage below OV trip point 4 % PGOOD Low Output Voltage IPGOOD = 2mA 0.35 V Sinking Impedance IPGOOD = 2mA 70 Ω Maximum Sinking Current (Note9) VPGOOD < 0.8V 10 mA OVERVOLTAGE PROTECTION OV Latching Trip Point EN/FF = UGATE = LATCH low, 118 120 122 % LGATE=High OV Non-Latching Trip Point (Note9) EN/FF = Low, UGATE = Low, 113 % LGATE = High LGATE Release Trip Point EN/FF = Low/HIGH, UGATE = Low, 87 % LGATE=Low OVER-TEMPERATURE PROTECTION Over-Temperature Trip (Note9) 150 °C Over-Temperature Release Threshold 125 °C (Note9) NOTES: 9. Limits should be considered typical and are not production tested. 10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Typical Performance Curves 0.606 0.606 0.604 0.604 0.602 0.602 )V )V ( 1B 0.600 ( 2B 0.600 F F V V 0.598 0.598 0.596 0.596 0.594 0.594 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 12. CHANNEL 1 ACCURACY vs TEMPERATURE FIGURE 13. CHANNEL 2 ACCURACY vs TEMPERATURE FN6641 Rev.3.00 Page 19 of 39 July 20, 2016

ISL8120 Typical Performance Curves (Continued) 5.7 410 VIN = 12V; 100mA LOAD 5.6 400 5.5 ) V ( CCVP 55..34 ) zHk ( fWS 338900 5.2 370 5.1 5.0 360 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 14. PVCC vs TEMPERATURE FIGURE 15. SWITCHING FREQUENCY vs TEMPERATURE 0.810 0.810 0.808 0.808 0.806 0.806 0.804 0.804 )V )V ( 1 0.802 ( 1 0.802 F F FN 0.800 FN 0.800 E_ 0.798 E_ 0.798 h h tV 0.796 tV 0.796 0.794 0.794 0.792 0.792 0.790 0.790 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 16. VENFF1 ENABLE THRESHOLD vs TEMPERATURE FIGURE 17. VENFF2 ENABLE THRESHOLD vs TEMPERATURE 33 33 32 32 )Aµ 31 )Aµ 31 ( T ( T S S YH 30 YH 30 _ _ 1 2 F F FN 29 FN 29 E E I I 28 28 27 27 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 18. ENFF1 HYSTERESIS CURRENT vs TEMPERATURE FIGURE 19. ENFF2 HYSTERESIS CURRENT vs TEMPERATURE FN6641 Rev.3.00 Page 20 of 39 July 20, 2016

ISL8120 Modes of Operation MODE 6: With VSEN2- pulled within 400mV of VCC, FB2 pulled high and VSEN2+ pulled low, the internal channels (as 1st and There are 9 typical operation modes depending upon the signal 3rd Phase, respectively) are 240° out-of-phase and operate in levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-, FB2 and 3-phase single output mode, combined with another ISL8120 at CLKOUT/REFIN. MODE 2B. The CLKOUT/REFIN pin signals out 120° relative phases to the falling edge of Channel 1’s clock signal to MODE 1: The IC is completely disabled when EN1/FF1 and synchronize with the second ISL8120’s Channel 1 (as 2nd EN2/FF2 are pulled below 0.8V. Phase). MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high MODE 7: With VSEN2- pulled within 400mV of VCC and FB2 and (Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pulled low VSEN2+ pulled high, the internal channel is 180° out-of-phase. (Mode 2B), the ISL8120 operates as a single phase regulator. The CLKOUT/REFIN pin (rising edge) signals out 90° relative The current sourcing out from the ISHARE pin represents the first phase to the Channel 1’s clock signal (falling edge of PWM) to channel current plus 15µA offset current. synchronize with another ISL8120, which can operate at Mode 3, MODE 3: When VSEN2- is used as a negative sense line, both 4, 5A, or 7A. A 4-phase single output converter can be channels’ phase shift depends upon the voltage level of constructed with two ISL8120s operating in Mode 5A or 7A CLKOUT/REFIN. When the CLKOUT/REFIN pin is within 29% to (Mode 7A). If the share bus is not connected between ICs, each IC 45% of VCC, Channel 2 delays 0° over Channel 1 (Mode 3A); could generate an independent output (Mode 7B). When the when within 45% to 62% of VCC, 90° delay (Mode 3B); when second ISL8120 operates as two independent regulators greater than 62% to VCC, 180° delay (Mode 3C). Refer to the (Mode3) or in DDR mode (Mode 4), then a three independent “Internal Reference and System Accuracy” on page34. output system is generated (Mode7C). Both ICs can also be constructed as a 3-phase converter (0°, 90°, and 180°, not an MODE 4: When VSEN2- is used as a negative remote sense line, equal phase shift for 3-phase) with a single phase regulator and CLKOUT/REFIN is connected to an external voltage ramp (270°). lower than the internal soft-start ramp and lower than 0.6V, the external ramp signal will replace Channel 2’s internal soft-start MODE 8: The output CLKOUT signal allows expansion for ramp to be tracked at start-up, controller operating in DDR mode. 12-phase operation with the cascaded sequencing, as shown in The controller will use the lowest voltage among the internal 0.6V Table1 on page22. No external clock is required in this mode for reference, the external voltage in CLKOUT/REFIN pin and the the desired phase shift. soft-start ramp signal. Channel 1 is delayed 60° behind Channel MODE 9: With an external clock, the part can be expanded for 5-, 2. Refer to the “Internal Reference and System Accuracy” on 7-, 8-, 9- 10- and 11-phase single output operation with the page34. desired phase shift. MODE 5: With VSEN2- pulled within 400mV of VCC and FB2 pulled to ground, the internal channels are 180° out-of-phase and operate in 2-phase single output mode (5A). The CLKOUT/REFIN pin (rising edge) also signals out clock with 60° phase shift relative to the Channel 1’s clock signal (falling edge of PWM) for 6-phase operation with two other ISL8120s (5B). When the share pins are not connected to each other for the three ICs in sync, two of which can operate in Mode 5A (3 independent outputs can be generated (Mode 5D) and Modes 3 and 4 (to generate 4 independent outputs (Mode 5C), respectively. FN6641 Rev.3.00 Page 21 of 39 July 20, 2016

JuFN TABLE 1. IS ly 266 1ST IC (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, BIDIRECTION) MODES OF OPERATION L81 04 2 , 21 2ND CHANNEL 0 0R EN1/ EN2/ CLKOUT/REFIN ISHARE (I/O) REPRESENTS WRT 1ST OPERATION OPERATION 1e 6v VFF1 VFF2 FB2 VSEN2+ WRT 1ST WHICH CHANNEL(S) (O) MODE MODE OUTPUT .3 .0 MODE (I) (I) VSEN2- (I) (I) (I) (IorO) CURRENT (Note11) of 2ND IC of 3RD IC (SEE DESCRIPTION FOR DETAILS) 0 1 <0.8V <0.8V - - - - - - - - DISABLED 2A <0.8V >0.8V ACTIVE ACTIVE ACTIVE - N/A - - - SINGLE PHASE 2B >0.8V <0.8V - - - - 1ST Channel - - - SINGLE PHASE 3A >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE 29% to 45% of 1ST Channel 0° - - DUAL REGULATOR VCC (I) 3B >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE 45% to 62% of 1ST Channel 90° - - DUAL REGULATOR VCC (I) 3C >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE > 62% of VCC (I) 1ST Channel 180° - - DUAL REGULATOR 4 >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE < 29% of VCC (I) 1ST Channel -60° - - DDR MODE 5A Note12 Note12 VCC GND VCC/GND 60° Average of Channel 1 and 2 180° - - 2-PHASE 5B Note12 Note12 VCC GND VCC/GND 60° Average of Channel 1 and 2 180° 5A 5A or 7A 6-PHASE 5C Note12 Note12 VCC GND VCC/GND 60° Average of Channel 1 and 2 180° 5A 5A or 7A 3 OUTPUTs 5D Note12 Note12 VCC GND VCC/GND 60° Average of Channel 1 and 2 180° 5A 3 or 4 4 OUTPUTs 6 Note12 Note12 VCC VCC GND 120° Average of Channel 1 and 2 240° 2B - 3-PHASE 7A Note12 Note12 VCC VCC VCC 90° Average of Channel 1 and 2 180° 5A or 7A - 4-PHASE 7B Note12 Note12 VCC VCC VCC 90° Average of Channel 1 and 2 180° 5A or 7A - 2 OUTPUTs (1st IC in Mode 7A) 7C Note12 Note12 VCC VCC VCC 90° Average of Channel 1 and 2 180° 3, 4 - 3 OUTPUTs (1st IC in Mode 7A) 8 Cascaded IC Operation MODEs 5A + 5A + 7A + 5A + 5A + 5A/7A, No External Clock Required 12-PHASE 9 External Clock or External Logic Circuits Required for Equal Phase Interval 5, 7, 8, 9, 10, 11, or (PHASE >12) NOTES: 11. “2ND CHANNEL WRT 1ST” is referred to as “Channel 2 lag Channel 1 by the degrees specified by the number in the corresponding table cells”. For example, 90° with 2ND CHANNEL WRT 1ST means Channel 2 lags Channel 1 by 90°; -60° with 2ND CHANNEL WRT 1ST means Channel 2 leads Channel 1 by 60°. 12. All EN/FF pins are tied together. P a g e 2 2 o f 3 9

ISL8120 Functional Description D 1-D CH1 UG (1ST IC) 180° CH2 UG (1ST IC) D 90° CLKOUT (1ST IC) 50% 90° D CH1 UG (2ND IC) 180° CH2 UG (2ND IC) D FIGURE 20. 4-PHASE TIMING DIAGRAM (MODE 7A) CH1 UG (1ST IC) D 1-D 240° CH2 UG (1ST IC) D 120° CLKOUT (1ST IC) 50% 120° CH1 UG (2ND IC) D 1-D CH2 UG(2ND IC, OFF, EN2/FF2 = 0) FIGURE 21. 3-PHASE TIMING DIAGRAM (MODE 6) VCC VSEN2- VSEN2+ VMON2 FB2 COMP2 CLKOUT/REFIN 400mV DIFF UV/OV ERROR AMP2 AMP2 COMP2 VREF2 = VREF CLOCK GENERATOR AND RELATIVE PHASES CONTROL CHANNEL 2 CHANNEL 1 PWM CONTROL PWM CONTROL BLOCK BLOCK FIGURE 22. SIMPLIFIED RELATIVE PHASES CONTROL FN6641 Rev.3.00 Page 23 of 39 July 20, 2016

ISL8120 Initialization VIN Initially, the ISL8120 Power-On Reset (POR) circuits continually ISL8120 ISL8120 monitor the bias voltages (PVCC and VCC) and the voltage at the RUP 2-PHASE 2-PHASE EN pin. The POR function initiates soft-start operation 384 clock EN/FF1 EN/FF1 cycles after the EN pin voltage is pulled to be above 0.8V, all EN/FF2 EN/FF2 input supplies exceed their POR thresholds and the PLL locking time expires, as shown in Figure23. During shutdown or fault conditions, the soft-start is reset quickly while UGATE and LGATE V RDOWN EN_HYS change states immediately (<100ns) upon the input drop below RUP = I--------------------------------N-------------------------- EN_HYS PHASE falling POR. FIGURE 24. TYPICAL 4-PHASE WITH FAULT HANDSHAKE HIGH = ABOVE POR; LOW = BELOW POR There is an internal transistor which will pull-down the EN/FF pin under fault conditions. The multiphase system can immediately VCC POR SOFT-START OF CHANNEL 1 turn off all ICs under fault conditions of one or more phases by PVCC POR 384 AND CYCLES pulling all EN/FF pins low. Thus, no bouncing occurs among EN1/FF1 POR channels at fault and no single phase could carry all current and be overstressed. The pull-up resistor (RUP) should be scaled to PLL LOCKING sink no more than 5mA current to the EN/VFF pin. Essentially, SOFT-START the EN/FF pins cannot be directly connected to VCC. OF CHANNEL 2 VCC POR 384 AND CYCLES Voltage Feed-Forward PVCC POR EN2/FF2 POR Other than used as a voltage monitor described in the previous section, the voltages applied to the EN/FF pins are also fed to FIGURE 23. SOFT-START INITIALIZATION LOGIC adjust the amplitude of each channel’s individual sawtooth. The The enable pin can be used as a voltage monitor and to set the amplitude of each channel’s sawtooth is set to 1.25 times the desired hysteresis with an internal 30µA sinking current going corresponding EN/FF voltage upon its enable (above 0.8V). This through an external resistor divider. The sinking current is helps to maintain a constant gain (G = VIND V ) M MAX RAMP disengaged after the system is enabled. This feature is especially contributed by the modulator and the input voltage to achieve designed for applications that require higher input rail POR for optimum loop response over a wide input voltage range. The better undervoltage protection. For example, in 12V applications, amplitude of each channel’s sawtooth is set to 1.25 times the RUP = 53.6k and RDOWN=5.23k will set the turn-on threshold corresponding EN/VFF voltage upon its enable (above 0.8V). The (VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with sawtooth ramp offset voltage is 1V, and the peak of the sawtooth 1.6V hysteresis (VEN_HYS). is limited to VCC- 1.4V. This allows a maximum peak-to-peak amplitude of sawtooth ramp to be VCC - 2.4V. A constant voltage The multiphase system can immediately turn off all ICs under (0.8V) is fed into the ramp generator to maintain a minimum fault conditions of one or more phases by pulling all EN/FF pins peak-to-peak ramp. low. Thus, no bouncing occurs among channels at fault and no single phase could carry all current and be over stressed. VCC RUP = N----V--x--E--I---N-----_---H----Y----S------- RDOWN = -V-------R-----U-----P---------V----–-E---V-N-----_---R----E----F----------- EN_HYS EN_FTH EN_REF Where N is number of EN/FF pins connected together GRAMP = 1.25 VCC - 1.4V V = V –V Σ UPPER LIMIT EN_FTH EN_RTH EN_HYS 0.8V VCC_FF LIMITER SAWTOOTH VRAMP = LIMIT(VCC_FFGRAMP, VCC - 1.4V - VRAMP_OFFSET AMPLITUDE (DVRAMP) VIN LOWER LIMIT VRAMP_OFFSET = 1.0V (RAMP OFFSET) RUP 0.8V EN/FF 384 Clock Cycles SOFT-START SYSTEM DELAY RDOWN IEN_HYS = 30µA OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1) FIGURE 25. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT FN6641 Rev.3.00 Page 24 of 39 July 20, 2016

ISL8120 With VCC = 5.4V, the ramp has an allowable maximum Power-Good peak-to-peak voltage of 3V and minimum of 1V. Therefore, the Both channels share the same PGOOD output. Either of the feed-forward voltage effective range is typically 3x. channels indicating out-of-regulation will pull-down the PGOOD A 384 cycle delay is added after the system reaches its rising pin. The power-good comparators monitor the voltage on the POR and prior to the soft-start. The RC timing at the EN/FF pin VMON pins. The trip points are shown in Figure29. PGOOD will should be sufficiently small to ensure that the input bus reaches not be asserted until after the completion of the soft-start cycle its static state and the internal ramp circuitry stabilizes before of both channels. States of both EN/FF1 and EN/FF2 have soft-start. A large RC could cause the internal ramp amplitude impact on the PGOOD signal. If one of the VMON pins’ voltage is not to synchronize with the input bus voltage during output out of the threshold window, PGOOD will not pull low until the start-up or when recovering from faults. It is recommended to fault presents for three consecutive clock cycles. use an open drain or open collector to gate this pin for any system delay, as shown in Figure25. ENFF1 + EN1 ENFF2 + EN2 0.8V - 0.8V - Soft-Start VMON1 + The ISL8120 has two independent digital soft-start circuitry with VREF - PGOOD1 fixed 1280 switching cycles. The soft-start time is inversely proportional to the switching frequency and is determined by the CH1 SOFT-START DONE 1280-cycle digital counter. Refer to Figure26. The full soft-start VMON2 + time from 0V to 0.6V can be estimated using Equation1. VREF - PGOOD2 tSS = 1--f--2---8---0--- (EQ. 1) CH2 SOFT-START DONE SW The ISL8120 has the ability to work under a precharged output EN1 (see Figure27). The output voltage would not be yanked down PGOOD1 during precharged start-up. If the precharged output voltage is PGOOD greater than the final target level but lowered to 120% setpoint, the switching will not start until the FB voltage reduces to the internal soft-start signal or the end of the soft-start is declared EN2 (see Figure28). PGOOD2 FIRST PWM PULSE SS SETTLING AT VREF + 100mV PGOOD1 PGOOD2 VMON +20% 0.0V -100mV 1280 tSS = -f------------ +13% SW VMON1, 2 +9% 384 t ª------------ SS_DLY fSW VREF -9% FIGURE 26. SOFT-START WITH VOUT = OV -13% FIRST PWM PULSE SS SETTLING AT VREF + 100mV PGOOD1,2 PGOOD LATCH OFF VMON AFTER 120% OV PRECHARGED LEVEL FIGURE 29. POWER-GOOD THRESHOLD WINDOW -100mV Overvoltage and Undervoltage Protection FIGURE 27. SOFT-START WITH VOUT = UV The Overvoltage (OV) and Undervoltage (UV) protection circuitry OV = 113% monitor the voltage on the VMON pins. FIRST PWM PULSE OV protection is active upon VCC POR. An OV condition (>120%) VOUT TARGET VOLTAGE would latch IC off (the high-side MOSFET to latch off permanently; the low-side MOSFET turns on immediately at the time of OV trip and then turns off after the VMON drops below 87%). The EN/FF and PGOOD are also latched low at OV event. FIGURE 28. SOFT-START WITH VOUT BELOW OV BUT ABOVE FINAL The latch condition can be reset only by recycling VCC. In TARGET VOLTAGE FN6641 Rev.3.00 Page 25 of 39 July 20, 2016

ISL8120 Dual/DDR mode, each channel is responsible for its own OV PRE-POR Overvoltage Protection event with the corresponding VMON as the monitor. In (PRE-POR-OVP) multiphase mode, both channels respond simultaneously when either triggers an OV event. When both the VCC and PVCC are below PORs (not including EN POR), the UGATE is low and LGATE is floating (high impedance). There is another non-latch OV protection (113% of target level). EN/VFF has no control on LGATE when VCC and PVCC are below At the condition of EN/FF low and the output over 113% OV, the their PORs. When VCC and PVCC are above their PORs, the LGATE lower side MOSFET will turn on until the output drops below 87%. would not be floating, however, toggling with its PWM pulses. An This is to protect the overall power trains in case of only one internal 10kΩ resistor, connected in between PHASE and LGATE channel of a multiphase system detecting OV. The low-side nodes, implements the PRE-POR-OVP circuit. The output of the MOSFET always turns on at the conditions of EN/FF = LOW and converter that is equal to phase node voltage via output the output voltage above 113% (all VMON pins and EN/FF pins inductors is then effectively clamped to the low-side MOSFET’s are tied together) and turns off after the output drops below 87%. gate threshold voltage, which provides some protection to the Thus, in a high phase count application (Multiphase Mode), all load if the upper MOSFET(s) is shorted during start-up, shutdown, cascaded ICs can latch off simultaneously via the EN/FF pins or normal operations. For complete protection, the low-side (EN/FF pins are tied together in multiphase mode), and each IC MOSFET should have a gate threshold that is much smaller than shares the same sink current to reduce the stress and eliminate the maximum voltage rating of the load. the bouncing among phases. The PRE-POR-OVP works against prebiased start-up when VMON1 precharged output voltage is higher than the threshold of the 113% low-side MOSFET, however, it can be disabled by placing a resistor from LGATE to ground. The resistor value can be 87% FORCE OR AND LGATE1 estimated from Equation2. HIGH EN/FF1 10k R------------------------------------------------------------ VMON1>120% V-----p---r--e----–----b----i-a----s---e---d-----m-----a---x----–1 (EQ. 2) OR Vthmin MULTIPHASE AND VMON2 MODE = HIGH The resistor value should be as large as possible to minimize 113% power dissipation, while providing sufficient margin for the internal 10kΩ and MOSFET’s Vth tolerances. For example, a 2kΩ 87% FORCE OR AND LGATE2 resistor is recommended for applications using logic-level HIGH EN/FF2 MOSFET with the maximum prebiased voltage less than 5V. VMON2 > 120% Over-Temperature Protection (OTP) FIGURE 30. FORCE LGATE HIGH LOGIC When the junction temperature of the IC is greater than +150°C (typically), both EN/FF pins pull low to inform other cascaded The UV functionality is not enabled until the end of soft-start. In a channels via their EN/FF pins. All connected EN/FFs stay low and UV event, if the output drops below -13% of the target level due to release after the IC’s junction temperature drops below +125°C some reason (cases when EN/FF is not pulled low) other than OV, (typically), with a +25°C hysteresis (typical). OC, OT, and PLL faults, the lower MOSFETs will turn off to avoid any negative voltage ringing. Inductor Current Sensing 120% The ISL8120 supports inductor DCR sensing, MOSFET’s rDS(ON) sensing, or resistive sensing techniques. The circuits shown in VOUT Figures32, 33, and 34 represent one channel of the controller. 3 CYCLES 3 CYCLES This circuitry is identical for both channels. Note that the common-mode input voltage range of the current sense amplifiers is VCC - 1.8V. Therefore, the rDS(ON) sensing UV must be used for applications with output voltage greater than PGOOD OV LATCH VCC - 1.8V. For example, when VCC=5.4V, the inductor DCR and the resistive sensing configurations can be used for output voltage less than 3V. For higher output voltage, rDS(ON) sensing UGATE AND EN/FF LATCH LOW configuration must be used. FIGURE 31. PGOOD TIMING UNDER UV AND OV FN6641 Rev.3.00 Page 26 of 39 July 20, 2016

ISL8120 INDUCTOR DCR SENSING temperature raise in the resistor package, recommend using 0.4. VIN Once Rmin has been calculated, solve for the maximum value of ILs C using Equation6 and choose the next-lowest readily available UGATE(n) value. Then substitute the chosen value into the same equation L DCR VOUT and recalculate the value of R. Choose the 1% resistor standard PHASE(n) INDUCTOR value closest to this recalculated value of R. LGATE(n) COUT + VL - C = ---------------L----------------- (EQ. 6) ISL8120 max R DCR +VC(s)- min INTERNAL CIRCUIT R C For example, when VIN_MAX = 14.4V, VOUT = 2.5V, L = 1µH and ICSn DCR = 1.5mΩ, with 0402 package Equation5 yields RMIN of RISEN(n) 1476Ω and Equation6 yields CMAX of 0.45µF. By choosing SAMPLE (PTC) 0.39µF and recalculating the resistor it yields 1.69kΩ. AND HOLD ISEN(n)A With the internal low-offset current amplifier, the capacitor + voltage VC is replicated across the sense resistor RISEN. - ISEN(n)B Therefore, the current out of ISEN(n)B pin, ISEN, is proportional to the inductor current. After 175ns blanking period with respect to the falling edge of the PWM pulse of each channel, the ISEN ISEN current is filtered and sampled for 175ns. The sampling current ICS then can be derived as shown by Equation7: FIGURE 32. DCR SENSING CONFIGURATION I +V-----O----U----T----1-----–----D----–t DCR An inductor’s winding is characteristic of a distributed resistance  L L 2fSW MIN_OFF (EQ. 7) ICS = -------------------------------------------------------------------------------------------------------------- as measured by the DCR (Direct Current Resistance) parameter. R ISEN Consider the inductor DCR as a separate lumped quantity, as shown in Figure32. The inductor current, IL; will also pass Where IL is the inductor DC current, fSW is the switching through the DCR. Equation3 shows the s-domain equivalent frequency, and tMIN_OFF is 350ns. voltage across the inductor VL. Resistive Sensing V = I sL+DCR (EQ. 3) L L For accurate current sense, a dedicated current-sense resistor RSENSE in series with the output inductor can serve as the A simple R-C network across the inductor extracts the DCR current sense element (see Figure33). This technique is more voltage, as shown in Figure32. The voltage on the capacitor VC, accurate, however, reduces overall converter efficiency due to the can be shown to be proportional to the inductor current IL, see additional power loss on the current sense element RSENSE. Equation4. sD-----C-L----R---+1DCRIL (EQ. 4) VIN IL V = --------------------------------------------------------------------- C sRC+1 UGATE(n) L RSENSE VOUT PHASE(n) If the R-C network components are selected such that the RC LGATE(n) COUT time constant (=R*C) matches the inductor time constant (=L/DCR), the voltage across the capacitor VC is equal to the ISL8120 voltage drop across the DCR, i.e., proportional to the inductor INTERNAL CIRCUIT current. The value of R should be as small as feasible for best signal-to-noise ratio. Make sure the resistor package size is ICSn appropriate for the power dissipated and include this loss in RISEN(n) efficiency calculations. In calculating the minimum value of R, SAMPLE the average voltage across C (which is the average ILDCR HAONLDD product) is small and can be neglected. Therefore, the minimum ISEN(n)A + value of R may be approximated using Equation5. - ISEN(n)B 2 2 R = D------------V----I--N-----–----m-----a---x----–-----V----O----U-----T----------+-------1-----–-----D-----------V----O----U-----T-- (EQ. 5) min kP  R–pkg P ISEN Where PR-pkg is the maximum power dissipation specification FIGURE 33. SENSE RESISTOR IN SERIES WITH INDUCTOR for the resistor package and P is the derating factor for the same parameter (eg.: PR-pkg = 0.063W for 0402 package, P=80% at +85°C). k is the margin factor, also to limit FN6641 Rev.3.00 Page 27 of 39 July 20, 2016

ISL8120 Equation8 shows the sampling current, ICS, when using sensing EN/VFF low again. The PGOOD signal will remain low and the resistor soft-start interval will be allowed to expire. Another soft-start interval will be initiated after the delay interval. If an overcurrent IL+V-----O----U----T----1-----–----D----–t RSENSE trip occurs again, this same cycle repeats until the fault is ICS = ----------------------L------------------2----f--S----W-------------M----I--N-----_--O-----F---F---------------------------------------- (EQ. 8) removed. R ISEN The OCP function is enabled at start-up. The ISL8120 monitors 2 Similar to DCR current sensing approach, the resistive sensing signals: sampled channel current, ICS and ISHARE voltage for approach can be used with output voltage less than VCC - 1.8V. over current protection. MOSFET r SENSING CHANNEL CURRENT OCP DS(ON) VIN Each sampled channel current, ICS, is compared to 108µA I CSn (typical) for the OCP trip point. The channel overcurrent trip point ISEN can be set by using RISEN value such that the overcurrent trip point corresponds to the channel sensing current, ICS, of 108µA. IL For DCR current sensing, Equation7, and rDS(ON) current SAMPLE AND ISEN(n)B sensing, Equation9, the RISEN can be estimated from HOLD Equations10 and 11, respectively. +- ISRE(PINST(ECnN))A +I-LxrDSON RISEN = ---I--O-----C------+-----V----------O----L----U--------T---------------2--1------f1---–-S---0-----WD--8--------–---A--t--M-----I-N-----_---O----F---F--------------D-----C-----R--- (EQ. 10) N-CHANNEL MOSFETs IOC+V-----O----U----T----1-----–----D----–t r ISL8120 INTERNAL CIRCUIT EXTERNAL CIRCUIT  L 2fSW MIN_OFF DSON R = ------------------------------------------------------------------------------------------------------------------------------ ISEN 108A (EQ. 11) FIGURE 34. MOSFET rDS(ON) CURRENT-SENSING CIRCUIT Without temperature compensation, the OCP trip point should be The controller can also sense the channel load current by evaluated based on the DCR or MOSFET rDS(ON) values at the sampling the voltage across the synchronous MOSFET rDS(ON) maximum device’s temperature. (see Figure34). The amplifier is ground-referenced by connecting the ISEN(n)A pin to the source of the synchronous MOSFET. While configured as multiphase operation ISEN(n)B pin is connected to the synchronous MOSFET’S drain (VSEN2->VCC-400mV), the channel OCP has 7 clock cycles through the current sense resistor RISEN. The voltage across delay before entering hiccup mode. RISEN is equivalent to the voltage drop across the rDS(ON) of the In dual-output operation, the 7-clock cycle delay on Channel 2 is lower MOSFET while it is conducting. The resulting current out of bypassed so the circuit responds to over current condition the ISEN(n)B pin is proportional to the channel current IL. immediately. In this mode, the 7-clock cycle delay in Channel 1 is Equation9 shows the sampling current, ICS, when using MOSFET still active. The fast OCP response on Channel 1 will rely on the rDS(ON) sensing. OCP on the ISHARE pin where the voltage on this pin represents the Channel 1 current. IL+V-----O--L--U----T---2-1---f--–S----WD----–tMIN_OFFrDSON (EQ. 9) ISHARE OCP I = ----------------------------------------------------------------------------------------------------------------------- CS R Refer to the block diagram, ISHARE pin sources out a current ISEN IAVG_CS with 15µA offset. In the 2-phase mode, IAVG_CS is the Both inductor DCR and MOSFET rDS(ON) value will increase as the average of both Channels 1 and 2 sampled currents as temperature increases. Therefore the sensed current will calculated in Equation12. increase as the temperature of the current sense element increases. In order to compensate the temperature effect on the IAVG_CS = I---C----S-----1-----+-----I--C-----S----2-- (EQ. 12) sensed current signal, a Positive Temperature Coefficient (PTC) 2 resistor can be selected for the sense resistor RISEN. While in the dual-output mode, IAVG_CS is a copy of Channel 1’s sampled current. Overcurrent Protection In multiphase operation, the VISHARE represents the average For overload and hard short condition, the overcurrent protection current of all ISL8120 and compares with the ISHARE pin reduces the regulator RMS output current much less than full precision 1.2V threshold to determine the overcurrent condition. load by putting the controller into hiccup mode. A delay time, At the same time, each channel has additional overcurrent trip equal to 3 soft-start intervals, is inserted to allow the disturbance point at 108µA with 7-cycle delay for channel overcurrent to be cleared out. After the delay time, the controller then protection. This scheme helps protect against loss of channel(s) initiates a soft-start interval. If the output voltage comes up and in multi-phase mode so that no single channel could carry returns to the regulation, PGOOD transitions high. If the OC trip is excessive current in such event. With RISHARE = 10kΩ, It would exceeded during the soft-start interval, the controller pulls FN6641 Rev.3.00 Page 28 of 39 July 20, 2016

ISL8120 make the channel current OCP and ISHARE OCP trip at the same Current Sharing Loop over current level; (108µA + 15µA) x 10kΩ = 1.23V. When the ISL8120 operates in 2-phase mode (VSEN2- is pulled Note that it is not necessary for the RISHARE to be scaled to trip at within VCC - 400mV), the current control loop keeps Channel 1 the same level as the 108µA OCP comparator if the application and Channel 2 currents in balance. The sensed currents from allows. For instance, when Channel 1 operates independently, the both channels are combined to create an average current OC trip set by 1.2V comparator can be lower than 108A trip point. reference (IAVG), which represents average current of both channel currents. The signal IAVG is then subtracted from the To set the ISHARE OCP in the multiphase configuration, the RISEN individual sensed current (ICS1 or ICS2) to produce a current must be determined first by using Equations10 or 11. The IOC in correction signal for each channel. The block diagram of current Equations10 or 11 is overcurrent for each phase, which is sharing control circuit is shown in Figure36. approximately IOC_total/number of phases. Upon determining RISET, Equations7, 8, 9 and 11 can be used to determine ISHARE When both channels operate independently, the average OCP, as shown in Equation12. function is disabled, and the current correction block of Channel2 is also disabled. The IAVG_CS is Channel 1 sensed R = ------------------------------1---.--2----V-------------------------------- current ICS1. Channel 1 makes any necessary current correction ISHARE N CNTL by comparing the voltages at ISET and ISHARE pins (for 3-phase,  I +15A twoISL8120s configuration). AVG_CS i (EQ. 13) i=1 When the share bus does not connect to other ICs, the ISET and RISET = RISHARENCNTL ISHARE pins can be shorted together and grounded via a single resistor to ensure zero share error. Where NCNTL is the number of the ISL8120 controllers in parallel or multiphase operations. For the RISEN chosen for OCP setting, the final value is usually higher than the number calculated from Equation9. The reason for which is practical, especially for low DCR applications since the PCB and inductor pad soldering resistance would have large effects in total impedance, affecting the DCR voltage to be sensed. FN6641 Rev.3.00 Page 29 of 39 July 20, 2016

ISL8120 IOUT1 DCR SENSING IOUT1 rDS(ON) SENSING IOUT2 VOUT PHASE1 VOUT PHASE1 PHASE2 VOUT L1 DCR1 L1 DCR1 DCR2 L2 C R R C LOW-SIDE RISEN1 MOSFET RISEN1 (PTC) RISEN2 (PTC) ISEN1B ISEN1A ISEN1B ISEN1A ISEN2A ISEN2B VCC DCR2 DCR1 AMP AMP ICS1 ICS2 400mV VSEN2- CHANNEL 1 CHANNEL 1  VSEN2+ PWM CONTROL CURRENT BLOCK CORRECTION + + 2 + BLOCK E/A - - IAVG + CHANNEL 2 CHANNEL 2 IAVG_CS +15µA ICSH_ERR - COCRURRERCETNITON PWM CONTROL ISHARE CURRENT - BLOCK BLOCK SHARE IAVG_CS BLOCK ISET IAVG_CS +15µA SCOHFATN-SNTEALR 1T ITRIP = 108µA 7 CYCLES SCOHFATN-SNTEALR 2T RISET AVG_OC FAULAT N LDOGIC OC2 DELAY FAULATN LDOGIC 1.2V COMP COMP VISHARE 7 CYCLES IAVG = (ICS1 + ICS2) / 2 DELAY ITRIP = 108µA IAVG_CS = IAVG or ICS1 OC1 ICSH_ERR = (VISARE - VISET)/GCS COMP FIGURE 35. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION FN6641 Rev.3.00 Page 30 of 39 July 20, 2016

ISL8120 IAVG = (ICS1 + ICS2) / 2 IAVG_CS = IAVG or ICS1 ERROR ERROR ISHARE = IAVG_CS + 15µA AMP 1 AMP 2 ISET = IAVG_CS + 15µA ICS1 IAVG_CS - + CURRENT - + VERROR1 - + CORRECTION BLOCK VERROR2 - ICS2 CURRENT + MIRROR VCC BLOCK ICSH_ERR CURRENT ICSH_ERR-  CURRENT MIRROR CORRECTION 400mV IAVG_CS+15µA BLOCK - BLOCK SHARE BUS ICSH_ERR ICSH_ERR ISHARE IAVG_CS RISHARE CURRENT SHARING ERROR VSEN2- CURRENT IAVG_CS+15µA BLOCK CORRECTION BLOCK ISET RISET RISHARE = RISET/NCTRL VSEN1- VSEN1+ VMON1 FIGURE 36. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION VIN REN/VFF_up REN/VFF_low EN/FF1,2 COM1/2 EN/FF1,2 COM1/2 EN/FF1,2 COM1/2 With VSEN1+ CLKOUT FSYNC FSYNC voltage VSEN1/2- VSEN1/2- loop VSEN1- ISL81201 VCCISL81202 VCC ISL81203 ISHARE ISET ISHARE ISET CLKOUT ISHARE ISET RISET1 RISET2 RISET3 RISHARE1 RISHARE2 RISHARE3 SHARE BUS RISHARE_ = RISET_ FIGURE 37. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION FN6641 Rev.3.00 Page 31 of 39 July 20, 2016

ISL8120 CURRENT SHARE CONTROL IN MULTIPHASE SINGLE bypass ceramic capacitors (10µF) connected to GND for proper OUTPUT WITH SHARED COMP VOLTAGE operation. The internal linear regulator’s input (VIN) can range between 3V to 22V. The PVCC pin is the output of the internal In multiphase/multi-IC implementation with one single error linear regulator and it provides power for both the internal amplifier for the voltage loop, all COMP pins must be tied MOSFET drivers through the PVCC pin. The VCC pin is the bias together. Therefore, all other channels’ error amplifiers that are input for the IC small signal analog circuitry. By connecting PVCC not used in voltage loop should be disabled with their to the VCC pin, the internal linear regulator supplies bias power to corresponding VSEN- pulled to VCC, as shown in Figure37 on VCC. The VCC pin should be connected to the PVCC pin with an RC page31. filter to prevent high frequency driver switching noise from the For current sharing purposes, all ISHARE pins must also be tied analog circuitry. When VIN drops below 5.0V, the pass element together. The share bus (VISHARE) represents the average current will saturate; PVCC will track VIN with a dropout of the linear of all ISL8120s connected to the same ISHARE bus. The ISHARE regulator. When used with an external 5V supply, the VIN pin is pin sources a copy of the IAVG_CS with 15µA offset (IAVG_CS recommended to be tied directly to PVCC. equals to IAVG or ICS1 depending upon the configuration). The ISET pin also sources out a copy of IAVG_CS with 15µA offset. The 2.65V TO 5.6V 3V TO 22V voltage on ISET pin represents individual current for each IC. The 2Ω 10µF current share error signal (ICSH_ERR) is then fed into the current correction block to adjust each channel’s PWM pulse 1µF accordingly. VCC PVCC VIN If one single external resistor is used as RISHARE connecting the ISHARE bus to ground for all the ICs in parallel, RISHARE should be set equal to RISET/NCTRL (where NCNTL is the number of the Z1 ISL8120 controllers in parallel or multiphase operations), and the share bus voltage (VISHARE) set by the RISHARE, represents Z2 the average current of all channels. RISHARE can also be set by putting one resistor in each IC’ s ISHARE pin and using the same value with RISET (RISHARE = RISET), which results in the total 5V equivalent resistance value as RISET/NCTRL. FIGURE 38. INTERNAL REGULATOR IMPLEMENTATION CURRENT SHARE CONTROL LOOP IN MULTI-MODULE WITH INDEPENDENT VOLTAGE LOOP The LDO is capable of supplying 250mA with regulated 5.4V The power module controlled by ISL8120 with its own voltage output. In 3.3V input applications, when the VIN pin voltage is 3V, loop can be paralleled to supply one common output load with its the LDO can still supply 150mA while maintaining LDO output integrated master-slave current sharing control, as shown in the voltage higher than VCC falling threshold to keep IC operating. Figure9 on page13. A resistor RCSR need to be inserted Figure39 shows the LDO voltage drop under different load between VSEN1- pin and the lower resistor of the voltage sense current. However, its thermal capability should not be exceeded. resistor divider for each module. With this resistor, the correction The power dissipation inside the IC could be estimated with current sourcing from the VSEN1- pin will create a voltage offset Equation14. to maintain even current sharing among modules. The recommended value for the VSEN1- resistor RCSR is 100Ω and it PIC= VIN–PVCCIVIN+PDR should not be large in order to keep the unity gain amplifier input (EQ. 14) pin impedance compatibility. The maximum source current from tdheete VrSmEiNne1 -t hpein c ius r3re5n0tµ sAh,a wrihnigc hre igsu cloamtiobnin readn gwei.t hT hReC gSeRn teor ated IVIN = Q-----G---V--1--G----S---N-1---Q-----1--+Q-----G---V--2--G----S---N-2---Q-----2--PVCCfSW+IQ_VIN correction voltage on RCSR is suggested to be within 5% of VREF (0.6V) to avoid fault triggering of UV/OV and PGOOD during 6.0 dynamic events. 5.5 It is recommended to have 3 analog signals: CLKOUT-SYNC, ISHARE and EN/FF for communication among the paralleled 5.0 modules. All the modules are synchronized and the phase shift )V 4.5 can also be configured to optimal to reduce the input current (C ripple by interleaving effects. The connections of these three CV 4.0 PVCC AT (250mA + IQ) P wires allows the system to be started at the same time and achieve good current balance in start-up without overcurrent trip. 3.5 PVCC AT (100mA + IQ) 3.0 Internal Series Linear and Power PVCC AT (140mA + IQ) Dissipation 2.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 The VIN pin is connected to PVCC with an internal series linear VIN PIN VOLTAGE (V) regulator. The PVCC and VIN pins should have the recommended FIGURE 39. PVCC vs VIN VOLTAGE FN6641 Rev.3.00 Page 32 of 39 July 20, 2016

ISL8120 Frequency Synchronization and Phase Lock P = P +P DR DR_UP DR_LOW Loop  RHI1 RLO1  PQg_Q1 PDR_UP = R-----H----I--1-----+----R-----E----X----T---1--+R-----L---O-----1----+-----R-----E----X----T---1------------2----------- The FSYNC pin has two primary capabilities: fixed frequency operation and synchronized frequency operation. By tying a  RHI2 RLO2  PQg_Q2 resistor (RFSYNC) to GND from the FSYNC pin, the switching P = --------------------------------------+------------------------------------------------------------- DR_LOW RHI2+REXT2 RLO2+REXT2 2 frequency can be set at any frequency between 150kHz and 1.5MHz. The value of RFSYNC can be estimated using Equation16. Q PVCC2 (EQ. 15) The frequency setting curve shown in Figure42 is also provided to G1 P = ---------------------------------------f N Qg_Q1 VGS1 SW Q1 assist in selecting the correct value for RFSYNC. Q PVCC2 1,600 G2 P = ---------------------------------------f N Qg_Q2 V SW Q2 z) 1,400 GS2 H k REXT2 = RG1+R-N----G-Q----I-11-- REXT2 = RG2+R-N----G-Q----I2-2-- ENCY ( 11,,020000 U Q Where the gate charge (QG1 and QG2) is defined at a particular E 800 R gate to source voltage (VGS1and VGS2) in the corresponding G F 600 MOSFET datasheet; IQ_VIN is the driver’s total quiescent current N with no load at drive outputs; NQ1 and NQ2 are number of upper CHI 400 T and lower MOSFETs, respectively. WI 200 S To keep the IC within its operating temperature range, an 0 20 40 60 80 100 120 140 160 180 200 220 240 260 external power resistor could be used in series with VIN pin to R_FS (kΩ) bring the heat out of the IC, or and external LDO could be used when necessary. FIGURE 42. RFS vs SWITCHING FREQUENCY . PVCC BOOT R k = 4.671104f kHz–1.04 (EQ. 16) FSYNC SW D By connecting the FSYNC pin to an external square pulse CGD waveform (such as the CLOCK signal, typically 50% duty cycle RHI1 G from another ISL8120), the ISL8120 will synchronize its CDS switching frequency to the fundamental frequency of the input RLO1 UGATE RG1 RGI1 waveform. The maximum voltage to the FSYNC pin is VCC+ 0.3V. CGS Q1 The frequency synchronization feature will synchronize the S leading edge of CLKOUT signal with the falling edge of PHASE Channel1’s PWM clock signal. The CLKOUT is not available until the PLL locks. FIGURE 40. TYPICAL UPPER-GATE DRIVE TURN-ON PATH The locking time is typically 130µs for fSW = 500kHz. EN/FF1 is released for a soft-start cycle until the FSYNC stabilized and the PVCC PLL is in locking. The PLL circuits control only EN/FF1, and control Channel 2’s soft-start instead of EN/FF2. Therefore, it is D recommended to connect all EN/FF pins together in multiphase CGD configuration. LGATE RHI2 G CDS The loss of a synchronization signal for 13 clock cycles causes RLO2 RG2 RGI2 the IC to be disabled until the PLL returns locking, at which point a soft-start cycle is initiated and normal operation resumes. CGS Q2 Holding FSYNC low will disable the IC. GND S Differential Amplifier for Remote Sense The differential remote sense buffers help compensate the droop FIGURE 41. TYPICAL LOWER-GATE DRIVE TURN-ON PATH due to load on the positive and negative rails and maintain the Oscillator high system accuracy of ±0.6%. They have precision unity gain resistor matching networks, which has a ultra low offset of 1mV. The Oscillator is a sawtooth waveform, providing for leading edge modulation with 350ns minimum PWM off-time. The oscillator (Sawtooth) waveform has a DC offset of 1.0V. Each channel’s peak-to-peak of the ramp amplitude is set proportional the voltage applied to its corresponding EN/FF pin. See “Voltage Feed-Forward” on page24. FN6641 Rev.3.00 Page 33 of 39 July 20, 2016

ISL8120 VSENSE- (REMOTE) VOUT (LOCAL) 10Ω VSENSE+ (REMOTE) GND (LOCAL) CSEN RFB 10Ω ROS ZFB ZCOMP PGOOD VCC VSEN- VSEN+ VMON FB COMP 400mV GAIN = 1 OV/UV ERROR AMP VREF COMP PGOOD FIGURE 43. SIMPLIFIED REMOTE SENSING IMPLEMENTATION The output of the remote sense buffer is connected directly to the In such an event, the VMON pin can be used as an additional internal OV/UV comparator. As a result, a resistor divider should monitor of the output voltage with a resistor divider to protect the be placed on the input of the buffer for proper regulation, as system against single point of failure, which occurs in the system shown in Figure43. The VMON pin should be connected to the FB using the same resistor divider for the UV/OV comparator and the pin by a standard feedback network. The output voltage can be output regulation. The resistor divider ratio should be the same set by using Equation17: as the one for the output regulation so that the correct voltage information is provided to the OV/UV comparator. Figure45 V = V 1+-R-----F---B--- (EQ. 17) shows the differential sense amplifier can be directly used as a OUT ref  ROS monitor without pulling VSEN- high. To optimize system accuracy, it is highly recommended to Internal Reference and System Accuracy include this impedance into calculation and use resistor with The internal reference is set to 0.6V. Including bandgap variation resistance as low as possible for the lower leg (ROS) of the and offset of differential and error amplifiers, it has an accuracy feedback resistor divider. Note that any RC filter at the inputs of of ±0.6% over commercial temperature range, and 0.9% over the differential amplifier, will contribute as a pole to the overall industrial temperature range. While the remote sense is not loop compensation. used, its offset (VOS_DA) should be included in the tolerance VCC calculation. Equations18 and 19 show the worst case of system I = VSEN+ + 1µA accuracy calculation. VOS_DA should set to zero when the 40k differential amplifier is in the loop, the differential amplifier’s input impedance (RDIF) is typically -600kΩ with a tolerance of 20k VSEN+ 20% (RDIF%) and can be neglected when ROS is less than 100Ω. To set a precision setpoint, ROS can be scaled by two paralleled 1µA resistors. 20k RDIF = -600k Figure46 shows the tolerance of various output voltage regulation for 1%, 0.5%, and 0.1% feedback resistor dividers. Note that the farther the output voltage setpoint away from the internal reference voltage, the larger the tolerance; the lower the VSEN- 20k 20k resistor tolerance (R%), the tighter the regulation. FIGURE 44. EQUIVALENT DIFFERENTIAL AMPLIFER  RFB1–R% The differential remote sense buffer has a precision unity gain %min= Vref1–Ref%–V 1+---------------------------------------- resistor matching network, which has a ultra low offset of 1mV. OS_DA  ROSMAX  This true remote sensing scheme helps compensate the droop (EQ. 18) due to load on the positive and negative rails and maintain the 1 high system accuracy of ±0.6%. ROSMAX= --------------------1------------------------------------------------------1--------------------------- -----------------------------------------+---------------------------------------------------- R 1+R% R 1+R % As some applications will not need the differential remote sense, OS DIF DIF the output of the remote sense buffer can be disabled and be placed in high impedance by pulling VSEN- within 400mV of VCC. FN6641 Rev.3.00 Page 34 of 39 July 20, 2016

ISL8120 VOUT RFB RFB ROS ROS ZCOMP GND VCC VSEN+ VSEN- VMON FB COMP PGOOD 400mV GAIN = 1 OV/UV ERROR AMP VREF COMP PGOOD FIGURE 45. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION reference signal (ramp and 0.6V), the one with the lowest voltage %max= Vref1–Ref%–V 1+R-----F----B----------1-----–----R-----%------- will be the one to be used as the reference comparing with FB OS_DA  ROSMIN  signal. So in DDR configuration, VTT channel should start-up later after its internal soft-start ramp in which way the VTT will track (EQ. 19) the voltage on REFIN pin derived from VDDQ. This can be 1 achieved by adding more filtering at EN//FF1 compared with R = ----------------------------------------------------------------------------------------------- OSMIN 1 1 EN/FF2. ---------------------------------------+------------------------------------------------- R 1–R% R 1–R % OS DIF DIF Since the UV/OV comparator uses the same internal reference 0.6V, to guarantee UV/OV and precharged start-up functions of 2.5 Channel2, the target voltage derived from Channel 1 (VDDQ) R% = 1% 2.0 should be scaled close to 0.6V, and it is suggested to be slightly above (+2%) 0.6V with an external resistor divider, which will 1.5 %) 0.5% have Channel 2 use the internal 0.6V reference after soft-start. N ( 1.0 Any capacitive load at the REFIN pin should not slow down the TIO 0.5 0.1% ramping of this input 150mV lower than the Channel 2’ internal A ramp. Otherwise, the UV protection could be fault triggered prior L U 0.0 G to the end of the soft-start. The start-up of Channel 2 can be E R -0.5 delayed to avoid such situation happening, if high capacitive load T 0.1% U presents at the REFIN pin for noise decoupling. During shutdown, P -1.0 T Channel 2 will follow Channel 1 until both channels drops below U 0.5% O -1.5 87%, at which point both channels enter UV protection zone. Depending on the loading, Channel 1 might drop faster than -2.0 1% Channel 2. To solve this race condition, Channel 2 can either -2.5 power up from Channel 1 or bridge the Channel 1 with a high 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 current Schottky diode. If the system requires to shutdown both OUTPUT VOLTAGE (V) channels when either has a fault, tying EN/FF1 and EN/FF2 will FIGURE 46. OUTPUT REGULATION WITH DIFFERENT RESISTOR do the job. In DDR mode, Channel 1 delays 60° over Channel 2. TOLERANCE FOR Ref% = ±0.6% In Dual mode, depending upon the resistor divider level of REFIN DDR and Dual Mode Operation from VCC, the ISL8120 operates as a dual-PWM controller for two independent regulators with a phase shift, as shown in Table2 If the CLKOUT/REFIN is less than 29% of VCC, an external soft-start ramp (0.6V) can be in parallel with the Channel 2’s on page36. The phase shift is latched as VCC raises above POR and cannot be changed on the fly. internal soft-start ramp for DDR/tracking applications (DDR Mode). The output voltage (typical VTT output) of Channel 2 tracks with the input voltage (typical VDDQ*(1+k) from Channel 1) at the CLKOUT/REFIN pin. As for the external input signal and internal FN6641 Rev.3.00 Page 35 of 39 July 20, 2016

ISL8120 TABLE 2. keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all sets of MOSFETs. DECODING PHASE FOR CHANNEL 2 REQUIRED MODE REFIN RANGE WRT CHANNEL 1 REFIN When placing the MOSFETs, try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally DDR <29% of VCC -60° 0.6V possible. Input high-frequency capacitors, CHF, should be placed Dual 29% to 45% of VCC 0° 37% VCC close to the drain of the upper FETs and the source of the lower Dual 45% to 62% of VCC 90° 53% VCC FETs. Input bulk capacitors, CBULK, case size typically limits following the same rule as the high-frequency input capacitors. Dual 62% to VCC 180° VCC Place the input bulk capacitors as close to the drain of the upper FETs as possible and minimize the distance to the source of the lower FETs. VCC VSEN2- Locate the output inductors and output capacitors between the PHASE-SHIFTED VDDQ MOSFETs and the load. The high-frequency output decoupling CLOCK capacitors (ceramic) should be placed as close as practicable to ISL8120 the decoupling target, making use of the shortest connection k*R STATE paths to any internal planes, such as vias to GND next or on the MACHINE CLKOUT/REFIN capacitor solder pad. The critical small components include the bypass capacitors R 400mV (CFILTER) for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC bypass VTT k = ------------–1 capacitors as close to the ISL8120 as possible. It is especially 0.6V important to locate the components associated with the INTERNAL SS 0.6V feedback circuit close to their respective controller pins, since FB2 E/A2 they belong to a high-impedance circuit loop, sensitive to EMI pick-up. FIGURE 47. SIMPLIFIED DDR IMPLEMENTATION A multi-layer printed circuit board is recommended. Dedicate one solid layer, usually the one underneath the component side of the Layout Considerations board, for a ground plane and make all critical component MOSFETs switch very fast and efficiently. The speed at which the ground connections with vias to this layer. Dedicate another solid current transitions from one device to another causes voltage layer as a power plane and break this plane into smaller islands spikes across the interconnecting impedances and parasitic of common voltage levels. Keep the metal runs from the PHASE circuit elements. These voltage spikes can degrade efficiency, terminal to output inductors short. The power plane should radiate noise into the circuit and lead to device overvoltage support the input power and output power nodes. Use copper stress. Careful component selection, layout and placement filled polygons on the top and bottom circuit layers for the phase minimizes these voltage spikes. Consider, as an example, the nodes. Use the remaining printed circuit layers for small signal turnoff transition of the upper PWM MOSFET. Prior to turnoff, the wiring. upper MOSFET was carrying current. During the turnoff, current ROUTING UGATE, LGATE AND PHASE TRACES stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates Special attention should be paid to routing the UGATE, LGATE and a large voltage spike during the switching interval. Careful PHASE traces since they drive the power train MOSFETs using component selection, tight layout of the critical components, and short, high current pulses. It is important to size them as large short, wide circuit traces minimize the magnitude of voltage and as short as possible to reduce their overall impedance and spikes. inductance. They should be sized to carry at least one ampere of current (0.02” to 0.05”). Going between layers with vias should There are two sets of critical components in a DC/DC converter also be avoided, however, if so, use two vias for interconnection using a ISL8120 controller. The power components are the most when possible. critical because they switch large amounts of energy. Next, are small signal components that connect to sensitive nodes or Extra care should be given to the LGATE traces in particular since supply critical bypassing current and signal coupling. keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. It is also The power components should be placed first, which include the important to route each channels UGATE and PHASE traces in as MOSFETs, input and output capacitors, and the inductors. It is close proximity as possible to reduce their inductances. important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains. Equidistant placement of the controller to the power trains (it controls through the integrated drivers), helps FN6641 Rev.3.00 Page 36 of 39 July 20, 2016

ISL8120 CURRENT SENSE COMPONENT PLACEMENT AND GENERAL POWERPAD DESIGN CONSIDERATIONS TRACE ROUTING The following is an example of how to use vias to remove heat One of the most critical aspects of the ISL8120 regulator layout is from the IC. the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISENA and ISENB pins on the ISL8120 as possible. The sense traces that connect the R-C sense components to each side of the output inductors should be routed away from the noisy switching components. These traces should be routed side by side, and they should be very thin traces. It is important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible. These traces should also originate from the geometric FIGURE 48. PCB VIA PATTERN center of the inductor pin pads and that location should be the single point of contact the trace makes with its respective net. It is recommended to fill the thermal pad area with vias. A typical via array fills the thermal pad foot print such that their centers are 3x the radius apart from each other. Keep the vias small, however, not so small that their inside diameter prevents solder wicking through during reflow. Connect all vias to the ground plane. It is important the vias have a low thermal resistance for efficient heat transfer. It is important to have a complete connection of the plated-through hole to each plane. © Copyright Intersil Americas LLC 2008-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6641 Rev.3.00 Page 37 of 39 July 20, 2016

ISL8120 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE July 20, 2016 FN6641.3 Applied Intersil Standards throughout datasheet. Updated Related Literature section. Updated Note1. Added Note2. Added Units to Rising PVCC Threshold on page 16 and PLL Locking Time on page 16. Updated Column header of Table 1(second column) from EN1/FF1 to EN1/VFF1. Corrected typo on page 25 changed 0V to OV. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN6641 Rev.3.00 Page 38 of 39 July 20, 2016

ISL8120 Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 5/10 4X 3.5 5.00 A 28X 0.50 6 B 25 32 PIN #1 INDEX AREA 6 PIN 1 24 1 INDEX AREA 0 5.0 3 .30 ± 0 . 15 17 8 (4X) 0.15 16 9 0.10MC AB + 0.07 32X 0.40 ± 0.10 4 32X 0.23 - 0.05 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( 28X 0 . 5 ) SIDE VIEW ( 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN6641 Rev.3.00 Page 39 of 39 July 20, 2016