DATASHEET ISL55001 FN6200 High Supply Voltage 220MHz Unity-Gain Stable Operational Amplifier Rev 3.00 Nov 3, 2009 The ISL55001 is a high speed, low power, low cost Features monolithic operational amplifier. The ISL55001 is unity-gain stable and features a 300V/µs slew rate and • 220MHz -3dB Bandwidth 220MHz bandwidth while requiring only 9mA of supply • Unity-gain Stable current. • Low Supply Current: 9mA @ VS = ±15V The power supply operating range of the ISL55001 is • Wide Supply Range: ±2.5V to ±15V Dual-Supply from ±15V down to ±2.5V. For single-supply operation, and 5V to 30V Single-Supply the ISL55001 operates from 30V down to 5V. • High Slew Rate: 300V/µs The ISL55001 also features an extremely wide output • Fast Settling: 75ns to 0.1% for a 10V Step voltage swing of -12.75V/+13.4V with VS = ±15V and • Wide Output Voltage Swing: -12.75V/+13.6V with RL=1k. VS= ±15V, RL = 1k At a gain of +1, the ISL55001 has a -3dB bandwidth of • Low Cost, Enhanced Replacement for the EL2044 220MHz with a phase margin of 50°. Because of its • Pb-free (RoHS compliant) conventional voltage-feedback topology, the ISL55001 allows the use of reactive or non-linear elements in its Applications feedback network. This versatility combined with low cost and 140mA of output-current drive makes the • Video Amplifiers ISL55001 an ideal choice for price-sensitive • Single-supply Amplifiers applications requiring low power and high speed. • Active Filters/Integrators The ISL55001 is available in an 8 Ld SO package and • High Speed Sample-and-Hold specified for operation over the full -40°C to +85°C • High Speed Signal Processing temperature range. • ADC/DAC Buffers Ordering Information • Pulse/RF Amplifiers • Pin Diode Receivers PART PACKAGE PKG. • Log Amplifiers PART NUMBER MARKING (Pb-free) DWG. # • Photo Multiplier Amplifiers ISL55001IBZ 55001 IBZ 8 Ld SO M8.15E (Note 2) • Difference Amplifier ISL55001IBZ-T7 55001 IBZ 8 Ld SO M8.15E Pin Configuration (Note 1, 2) ISL55001IBZ-T13 55001 IBZ 8 Ld SO M8.15E ISL55001 (Notes 1, 2) (8 LD SO) TOP VIEW NOTES: NC 1 8 NC 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ IN- 2 7 VS+ - special Pb-free material sets, molding compounds/die + attach materials, and 100% matte tin plate plus anneal IN+ 3 6 OUT (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering VS- 4 5 NC operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55001. For more information on MSL please see techbrief TB363. FN6200 Rev 3.00 Page 1 of 12 Nov 3, 2009

ISL55001 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS) . . . . . . . . . . . . . . . . . . ±16.5V or 33V Continuous Output Current . . . . . . . . . . . . . . . . . . . 60mA Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . . . . .±VS Power Dissipation (PD). . . . . . . . . . . . . . . . . . . .see Curves Differential Input Voltage (dVIN) . . . . . . . . . . . . . . . . ±10V Operating Temperature Range (TA). . . . . . . -40°C to +85°C ESD Rating Operating Junction Temperature (TJ). . . . . . . . . . . .+150°C Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 3kV Storage Temperature (TST) . . . . . . . . . . . -65°C to +150°C Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. DC Electrical Specifications VS = ±15V, RL = 1k, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT VOS Input Offset Voltage 0.06 3 mV TCVOS Average Offset Voltage Drift 18 µV/°C IB Input Bias Current 1.72 3.5 µA IOS Input Offset Current 0.27 1.5 µA TC-IOS Average Offset Current Drift 0.8 nA/°C (Note 4) AVOL Open-loop Gain VOUT = ±10V, RL = 1k 10 17 kV/V PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 75 90 dB CMRR Common-mode Rejection Ratio VCM = ±10V, VOUT = 0V 70 90 dB CMIR Common-mode Input Range VS = ±15V ±14 V VOUT Output Voltage Swing VO+, RL = 1k 13.25 13.5 V VO-, RL = 1k -12.6 -12.8 V VO+, RL = 150 10.7 11.5 V VO-, RL = 150 -8.8 -9.9 V ISC Output Short Circuit Current 120 145 mA IS Supply Current No load 8.3 9.25 mA RIN Input Resistance 2.0 2.75 M CIN Input Capacitance AV = +1 1 pF ROUT Output Resistance AV = +1 50 m PSOR Power Supply Operating Range Dual supply ±2.25 ±15 V Single supply 4.5 30 V NOTE: 4. Measured from TMIN to TMAX. AC Electrical SpecificationsVS = ±15V, AV = +1, RL = 1k, unless otherwise specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT BW -3dB Bandwidth (VOUT = 0.4VP-P) AV = +1 220 MHz AV = -1 55 MHz AV = +2 53 MHz AV = +5 17 MHz GBWP Gain Bandwidth Product 70 MHz PM Phase Margin RL = 1k, CL = 5pF 55 ° SR Slew Rate (Note 5) RL = 100 250 280 V/µs FN6200 Rev 3.00 Page 2 of 12 Nov 3, 2009

ISL55001 AC Electrical SpecificationsVS = ±15V, AV = +1, RL = 1k, unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT FPBW Full-power Bandwidth (Note 6) VS = ±15V 9.5 MHz tS Settling to +0.1% (AV = +1) VS = ±15V, 10V step 75 ns dG Differential Gain (Note 7) NTSC/PAL 0.01 % dP Differential Phase NTSC/PAL 0.05 ° eN Input Noise Voltage 10kHz 12 nV/H z iN Input Noise Current 10kHz 1.5 pA/H z NOTES: 5. Slew rate is measured on rising edge. 6. For VS = ±15V, VOUT = 10VP-P, for VS = ±5V, VOUT = 5VP-P. Full-power bandwidth is based on slew rate measurement using FPBW=SR/(2*VPEAK). 7. Video performance measured at VS = ±15V, AV = +2 with two times normal video level across RL = 150. This corresponds to standard video levels across a back-terminated 75 load. For other values or RL, see “Typical Performance Curves” on page4. FN6200 Rev 3.00 Page 3 of 12 Nov 3, 2009

ISL55001 Typical Performance Curves Vs=+/-15V RVLS= =1K ±15V SRoLu =rc 1ek Power=-20dBm SOURCE POWER = -20dBm VS = ±15V RL = 1k SOURCE POWER = -20dBm FIGURE 1. OPEN-LOOP GAIN vs FREQUENCY FIGURE 2. OPEN-LOOP PHASE vs FREQUENCY VS = ±15V VS = ±15V CL = 5pF CL = 5pF SOURCE POWER = -20dBm SOURCE POWER = -20dBm RL = 1k RL = 1k RL = 500 RL = 500 RL = 150 RL = 150 RL = 75 RL = 75 RL = -50 RL = 50 FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS RLOAD RLOAD (AV = +1) (AV = +2) VS = ±15V CL = 82pF CL = 82pF RL = 1k SOURCE POWER = -20dBm CL = 39pF CL = 39pF CL = 10pF CL = 5pF CL = 10pF VS = ±15V RL = 1k CL = 5pF SOURCE POWER = -20dBm FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS FIGURE 6. FREQUENCYRESPONSE FOR VARIOUS CLOAD CLOAD (AV = +1) (AV = +2) FN6200 Rev 3.00 Page 4 of 12 Nov 3, 2009

ISL55001 Typical Performance Curves (Continued) 270 360 VS = ±15V VS = ±15V RF = 500 315 RF = 500 180 RL= 500 RL= 500 270 90 (°) AV = +1 °)225 AV = -1 SE 0 E (180 A S H A P-90 PH135 AV = +5 90 AV = -5 -180 AV = +2 45 AV = -2 NOTE: FOR AV = +1, RF = 0 -270 0 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 7. PHASE vs FREQUENCY FOR VARIOUS FIGURE 8. PHASE vs FREQUENCY FOR VARIOUS NON-INVERTING GAIN SETTINGS INVERTING GAIN SETTINGS 100 350 CT (MHz) 80 RL = 500 300 ARRCARRCVFLLVFLL ======== +555 +555p002p20000F00F POPOSSITITIVIVEE SSLLEEWW RRAATTEE U s) D µ PRO 60 E (V/ 250 NNEEGGAATTIIVVEE SSLLEEWW R RAATETE H AT T R WID 40 W 200 E D L N S A N B 20 150 AI G 0 100 0 3 6 9 12 15 0 3 6 9 12 15 SUPPLY VOLTAGES (±V) SUPPLY VOLTAGES (±V) FIGURE 9. GAIN BANDWIDTH PRODUCT vs SUPPLY FIGURE 10. SLEW RATE vs SUPPLY 5 5 VS = ±15V VS = ±15V N (dB) 3 ARCVLL === +55p010F RF = 250 RF = 500 N (dB) 3 ARCVLL === +550p20F RFR =F 5=0 10k MALIZED GAI-11 RF = 100 RF = 0 MALIZED GAI-11 RF = 250 OR OR N-3 N-3 RF = 100 -5 -5 100k 1M 10M 100M 100k 1M 10M 100M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS RFEEDBACK (AV = +1) RFEEDBACK (AV = +2) FN6200 Rev 3.00 Page 5 of 12 Nov 3, 2009

ISL55001 Typical Performance Curves (Continued) 5 5 VS = ±15V AV = +1 AIN (dB) 3 ARRCVFLL ==== +555p00200F CCIINN == 46..78ppFF CIN = 10pF N (dB) 3 RRCFLL === 055p00F VS = ±5V VS = ±2.5V G 1 AI 1 D G E D Z E RMALI -1 CIN = 2.2CpINF = 0pF RMALIZ -1 VS = ±1V5SV = ±10V O O N -3 N -3 -5 -5 100k 1M 10M 100M 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS SUPPLY INVERTING INPUT CAPACITANCE (CIN) SETTINGS -10 -10 VS = ±15V VS = ±15V -20 -20 -30 -30 NEG_PSRR -40 -40 ) ) B B d -50 d-50 ( ( R R R -60 R-60 POS_PSRR M S C P -70 -70 -80 -80 -90 -90 -100 -100 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 15. COMMON-MODE REJECTION RATIO (CMRR) FIGURE 16. POWER SUPPLY REJECTION RATIO (PSRR) -30 c) VS = ±15V N (dB) VRVSOL U==T ±5 =10 502VVP-P THD ION (dB --5400 ARRCVFLL ==== +555p00200F THD TIO ORT FIN = 2MHz OR ST -60 ST DI C DI IC -70 2nd HD ONI 3rd HD ON -80 3rd HD M M R R HA 2nd HD HA -90 -100 0 2 4 6 8 10 12 14 16 18 20 22 24 26 OUTPUT VOLTAGE (V) FIGURE 17. HARMONIC DISTORTION vs FREQUENCY FIGURE 18. HARMONIC DISTORTION vs OUTPUT (AV = +1) VOLTAGE(AV = +2) FN6200 Rev 3.00 Page 6 of 12 Nov 3, 2009

ISL55001 Typical Performance Curves (Continued) 30 25 E SWING (V) 2205 ARVF == +01 VRCSLL === ±5510p50FV SWING (V)P-P 2105 RCLL ==RC 55LLp0 ==0F 55p00F AAVV ==RR +A+FAF1 V1= V= = 5 = 50+ 00+202 VOLTAG 15 OLTAGE 10 UTPUT 150 ARVF == +5010 UTPUT V 5 O O 0 0 1M 10M 100M 0 3 6 9 12 15 FREQUENCY (Hz) SUPPLY VOLTAGES (±V) FIGURE 19. OUTPUT SWING vs FREQUENCY FOR VARIOUS GAIN SETTINGS FIGURE 20. OUTPUT SWING vs SUPPLY VOLTAGE FOR VARIOUS GAIN SETTINGS VS = ±15V VS = ±15V AV = +1 AV = +1 RF = 0 RF = 0 RL = 500 RL = 500 CL = 5pF CL = 5pF VOUT = 4V tRISE = tFALL = VOUT = 400mV 2ns 2.2ns 20% to 80% 80% to 20% tRISE = 8.4ns tFALL = 7.2ns 20% to 80% 80% to 20% FIGURE 22. SMALL SIGNAL RISE AND FALL TIMES FIGURE 21. LARGE SIGNAL RISE AND FALL TIMES JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 12.5 1.8 1.6 A) m 10.0 T ( W) 1.4 REN ON ( 1.2 R 75 TI CU PA 1.0 1.136W Y SI UPPL 5.0 R DIS 0.8 SO8 AL S AAVV = = + 1+1 OWE 0.6 JA = +120°C/W OT 2.5 RRFF = = 0 0 P 0.4 T RRLL = = 5 05000 CCLL = = 5 p5FpF 0.2 0 0 0 3 6 9 12 15 0 25 50 75 85 100 125 150 SUPPLY VOLTAGES (±V) AMBIENT TEMPERATURE (°C) FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6200 Rev 3.00 Page 7 of 12 Nov 3, 2009

ISL55001 Product Description setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be The ISL55001 is a wide bandwidth, low power, and low created by the additional series resistor at the output. offset voltage feedback operational amplifier. This device is internally compensated for closed loop gain of +1 or When used as a cable driver, double termination is greater. Connected in voltage follower mode and driving always recommended for reflection-free performance. a 500 load, the -3dB bandwidth is around a 220MHz. For those applications, a back-termination series resistor Driving a 150 load and a gain of 2, the bandwidth is at the amplifier's output will isolate the amplifier from the about 90MHz while maintaining a 300V/µs slew rate. cable and allow extensive capacitive drive. However, other applications may have high capacitive loads The ISL55001 is designed to operate with supply voltage without a back-termination resistor. Again, a small series from +15V to -15V. That means for single supply resistor at the output can help to reduce peaking. application, the supply voltage is from 0V to 30V. For split supplies application, the supply voltage is from ±15V. Output Drive Capability The amplifier has an input common-mode voltage range The ISL55001 does not have internal short circuit from 1.5V above the negative supply (VS- pin) to 1.5V protection circuitry. It has a typical short circuit current of below the positive supply (VS+ pin). If the input signal is 140mA. If the output is shorted indefinitely, the power outside the above specified range, it will cause the output dissipation could easily overheat the die or the current signal to be distorted. could eventually compromise metal integrity. Maximum The outputs of the ISL55001 can swing from -12.75V to reliability is maintained if the output current never +13.4V for VS = ±15V. As the load resistance becomes exceeds ±60mA. This limit is set by the design of the lower, the output swing is lower. internal metal interconnect. Note that in transient applications, the part is robust. Choice of Feedback Resistor and Gain Bandwidth Product Short circuit protection can be provided externally with a back match resistor in series with the output placed close For applications that require a gain of +1, no feedback as possible to the output pin. In video applications this resistor is required. Just short the output pin to the would be a 75 resistor and will provide adequate short inverting input pin. For gains greater than +1, the circuit protection to the device. Care should still be taken feedback resistor forms a pole with the parasitic not to stress the device with a short at the output. capacitance at the inverting input. As this pole becomes Power Dissipation smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the With the high output drive capability of the ISL55001, it frequency domain. Therefore, RF can't be very big for is possible to exceed the +150°C absolute maximum optimum performance. If a large value of RF must be junction temperature under certain load current used, a small capacitor in the few Pico Farad range in conditions. Therefore, it is important to calculate the parallel with RF can help to reduce the ringing and maximum junction temperature for an application to peaking at the expense of reducing the bandwidth. For determine if load conditions or package types need to be gain of +1, RF = 0 is optimum. For the gains other than modified to assure operation of the amplifier in a safe +1, optimum response is obtained with RF with proper operating area. selection of RF and RG (see Figures 15 and 16 for The maximum power dissipation allowed in a package is selection). determined according to Equation 1: Video Performance T –T PD = ----J---M-----A----X--------------A---M-----A----X--- (EQ. 1) For good video performance, an amplifier is required to MAX  JA maintain the same output impedance and the same frequency response as DC levels are changed at the Where: output. This is especially difficult when driving a standard video load of 150, because of the change in output • TJMAX = Maximum junction temperature current with DC level. The dG and dP of this device is • TAMAX = Maximum ambient temperature about 0.01% and 0.05°, while driving 150 at a gain of2. Driving high impedance loads would give a similar • JA = Thermal resistance of the package or better dG and dP performance. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total Driving Capacitive Loads and Cables power supply voltage, plus the power in the IC due to the The ISL55001 can drive 47pF loads in parallel with 500 load, or: For sourcing use Equation 2: with less than 3dB of peaking at gain of +1 and as much n as 100pF at a gain of +2 with under 3db of peaking. If V less peaking is desired in applications, a small series PDMAX = (VS+ –VS-ISMAX+  VS+ –VOUTi R-------O----U----T----i-- resistor (usually between 5 to 50) can be placed in i=1 LOADi series with the output to eliminate most peaking. (EQ. 2) However, this will reduce the gain slightly. If the gain FN6200 Rev 3.00 Page 8 of 12 Nov 3, 2009

ISL55001 For sinking use Equation 3: capacitor from VS+ to GND will suffice. This same n capacitor combination should be placed at each supply V PDMAX = (VS+ –VS-ISMAX+  VOUTi–VS- R-------O----U----T----i-- pin to ground if split supplies are to be used. In this case, i=1 LOADi the VS- pin becomes the negative supply rail. (EQ. 3) Printed Circuit Board Layout Where: For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should • VS+ = Positive supply voltage be avoided because of their additional series inductance. • VS- = Negative supply voltage Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result • ISMAX = Maximum quiescent supply current in compromised performance. Minimizing parasitic • VOUT = Average output voltage of the application capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very • RLOAD = Load resistance tied to ground close to the inverting input pin. Strip line design • ILOAD = Load current techniques are recommended for the signal traces. • n = number of amplifiers (n = 1 for ISL55001) Application Circuits By setting the two PDMAX equations (Equations 1, 2 or 3) Sallen-Key Low Pass Filter equal to each other, we can solve the output current and RLOAD to avoid the device overheat. A common and easy to implement filter taking advantage of the wide bandwidth, low offset and low power Power Supply Bypassing Printed Circuit demands of the ISL55001. A derivation of the transfer Board Layout function is provided for convenience (see Figure 25). As with any high frequency device, a good printed circuit Sallen-Key High Pass Filter board layout is necessary for optimum performance. Again this useful filter benefits from the characteristics of Lead lengths should be as short as possible. The power the ISL55001. The transfer function is very similar to the supply pin must be well bypassed to reduce the risk of low pass so only the results are presented (see oscillation. For normal single supply operation, where the Figure26). VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic Holp  K V2 1 5V wo  C5 R C R C 1 1 2 2 1nF 1 C1 Q  R C R C R C 1 1 1 2 2 2 1nF (1 K )   R1 R2 R2C 2 R2C1 R1C1 V1 1k 1k1nCF2 +- VV+- VOUT R1k7 RB 1k 1RkA C5 Holp  K 4  K 1nF 2 V3 wo  5V RC 2 Q  4  K FIGURE 25. SALLEN-KEY LOW PASS FILTER FN6200 Rev 3.00 Page 9 of 12 Nov 3, 2009

ISL55001 V2 Holp  K 5V 1 C5 wo  R C R C 1 1 2 2 1nF R1 Q  1 R C R C R C C2 1k (1 K ) 1 1  1 2  2 2 C1 1nF R2C 2 R2C1 R1C1 V1 1nF 1Rk2 +- VV+- VOUT R1k7 Equations simplify if we let all components be equal R = C RB K 1k Holp  RA C5 4  K 1k 2 wo  1nF RC V3 Q  2 5V 4  K FIGURE 26. SALLEN-KEY HIGH PASS FILTER Differential Output Instrumentation coupled noise and ground potential errors inherent in Amplifier remote transmission. This configuration also provides enhanced bandwidth, wider output swing and faster slew The addition of a third amplifier to the conventional three rate than conventional three amplifier solutions with only amplifier instrumentation amplifier introduces the the cost of an additional amplifier and few resistors (see benefits of differential signal realization, specifically the Figure 27). advantage of using common-mode rejection to remove e1 +A1 R3 R3 - R2 A3 eo - e = –1+2R R e –e  e = 1+2R R e –e  + o3 2 G 1 2 o4 2 G 1 2 + e = –21+2R R e –e  o 2 G 1 2 R3 R3 2f RE BW = ------C----1------2-- ADi = –21+2R2RG RG R3 R3 eo ADi R2 A4 - + - eo A2 - R3 R3 e2 + FIGURE 27. DIFFERENTIAL OUTPUT INSTRUMENTATION AMPLIFIER FN6200 Rev 3.00 Page 10 of 12 Nov 3, 2009

ISL55001 Strain Gauge to increasing strain, its resistance changes, resulting in an imbalance in the bridge. A voltage variation from The strain gauge is an ideal application to take the referenced high accuracy source is generated and advantage of the moderate bandwidth and high translated to the difference amplifier through the buffer accuracy of the ISL55001. The operation of the circuit stage. This voltage difference as a function of the strain is very straightforward. As the strain variable is converted into an output voltage (see Figure 28). component resistor in the balanced bridge is subjected +V2 5V - C6 VARIABLE SUBJECT TO 1nF 1k V5+ R15 R16 R17 1k + V+ 0V 1k 1k - 1k R18 1k - V- R1kLV(VO1U+TV2+V3+V4) RF 1k C12 1nF + V4 - 5V FIGURE 28. STRAIN GAUGE AMPLIFIER © Copyright Intersil Americas LLC 2005-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6200 Rev 3.00 Page 11 of 12 Nov 3, 2009

ISL55001 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25MC AB SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C 0.175 ± 0.075 SEATING PLANE 0.10C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN6200 Rev 3.00 Page 12 of 12 Nov 3, 2009