DATASHEET ISL24021 FN6637 1A Rail-to-Rail Input-Output Operational Amplifier Rev 1.00 October 18, 2011 The ISL24021 is a high output current, high voltage, rail-to-rail Features voltage feedback amplifier. The ISL24021 is capable of ±1A peak output short circuit current. The amplifier exhibits beyond • ±1A Output Short Circuit Current the rail input capability, rail-to-rail output capability and is unity • 4.5V to 19V Maximum Supply Voltage Range gain stable. • 2.0mA Supply Current The operating supply voltage range is from 4.5V to 19V • 18V/µs Slew Rate maximum and the ISL24021 can be configured for single or dual supply operation. The ISL24021 has the ability to quickly • 25MHz -3dB Bandwidth source and sink large peak currents up to ±1A and to drive • ±300mA Continuous Output Current large continuous currents of ±300mA. • Unity-Gain Stable The ISL24021 features fast slewing and settling times. Also, the • Beyond the Rails Input Capability device provides common mode input capability beyond the • Rail-to-Rail Output Swing supply rails, and rail-to-rail output capability. This enables the amplifier to offer maximum dynamic range at any supply • Built-in Thermal Protection voltage. These features make the ISL24021 an ideal solution as • -40°C to +85°C Ambient Temperature Range a VCOM driver in TFT-LCD panel applications. Other applications may include battery power and portable devices, and especially • Pb-Free (RoHS Compliant) where low power consumption is important. Applications The ISL24021 is available in a 8 Ld 3mmx3mm TDFN package • TFT-LCD Panels featuring a standard operational amplifier pinout with a lead pitch of 0.65mm. The device utilizes a thermally enhanced • VCOM Driver package and has a built-in thermal protection circuit. It is • Video Processing specified for operation over an ambient temperature range of -40°C to +85°C. • Audio Processing • Active Filters Pin Configuration • Test Equipment ISL24021 (8 LD TDFN) • Battery-Powered Applications TOP VIEW • Portable Equipment NC 1 8 NC Ordering Information THERMAL INN 2 PAD 7 VDD PART LEAD PACKAGE INP 3 6 OUT NUMBER PITCH PART Tape & Reel PKG. VSS 4 5 NC (Notes 1, 2, 3) (mm) MARKING (Pb-Free) DWG.# ISL24021IRT065Z-T7A 0.65 P021 8 Ld TDFN L8.3x3K THERMAL PAD IS ELECTRICALLY ISL24021IRT065Z-T13 0.65 P021 8 Ld TDFN L8.3x3K ISOLATED, OR CONNECTED TO VSS NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb- free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL24021. For more information on MSL please see techbrief TB363. FN6637 Rev 1.00 Page 1 of 13 October 18, 2011

ISL24021 Absolute Maximum Ratings (T = +25°C) Thermal Information A Supply Voltage Range (VDD -VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Input Voltage Range (INN, INP). . . . . . . . . . . . . . . . . VSS - 0.5V, VDD + 0.5V 8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 50 17 Input Differential Voltage (INP - INN). . . . . . . . . .(VDD + 0.5V) - (VSS - 0.5V) Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C ESD Rating Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7500V Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see Figure 28 Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the ceramic on the package underside. Electrical Specifications VDD = 5V, VSS = -5V, RL = 1k to 0V, TA = +25°C, Unless Otherwise Specified. MIN MAX PARAMETER DESCRIPTION CONDITIONS (Note 6) TYP (Note 6) UNIT POWER SUPPLY PERFORMANCE VDD - VSS Supply Voltage Range 4.5 19 V IS Supply Current No load 2.1 2.8 mA PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±9.5V 60 80 dB INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 1.4 15 mV TCVOS Average Offset Voltage Drift (Note 7) 1 µV/°C ILEAK Input Leakage Current VCM = 0V 2 10 nA RIN Input Resistance 1 G CIN Input Capacitance 2 pF CMIR Common-Mode Input Range VSS- VDD+ V 0.5 0.5 CMRR Common-Mode Rejection Ratio For VIN from -5.5V to 5.5V 50 70 dB AVOL Open-Loop Gain -4.5V VOUT 4.5V 75 100 dB OUTPUT CHARACTERISTICS VOH Output Swing High IL= 5mA, VIN = VDD VDD- VDD- V 0.15 0.025 VOL Output Swing Low IL= -5mA,VIN = VSS VSS+ VSS+ V 0.025 0.15 ISC Short-Circuit Current ±1.0 A IOUT Continuous Output Current (Note 10) ±300 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) -4.0V VOUT 4.0V 18 V/µs tS Settling to 0.1% (Note 9) AV = +1, VO = 2V step 80 ns BW -3dB Bandwidth AV = +1, RL = 1kCL= 8pF 25 MHz PM Phase Margin RL = 1kCL= 8pF 44 ° THERMAL PERFORMANCE TTS Thermal Shutdown Temperature Die temperature at which the device will +165 °C shutdown until it cools by TTSH °C TTSH Thermal Shutdown Hysteresis Die temperature below TTS °C when the 15 °C device will become operational after shutdown FN6637 Rev 1.00 Page 2 of 13 October 18, 2011

ISL24021 . Electrical Specifications VDD = 5V, VSS = GND = 0V, RL = 1kto 2.5V, TA = +25°C, Unless Otherwise Specified. MIN MAX PARAMETER DESCRIPTION CONDITION (Note 6) TYP (Note 6) UNIT POWER SUPPLY PERFORMANCE VDD - VSS Supply Voltage Range 4.5 19 V IS Supply Current No load 2.0 2.8 mA PSRR Power Supply Rejection Ratio VS is moved from +4.5V to +19V 60 80 dB INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 1.4 15 mV TCVOS Average Offset Voltage Drift (Note 7) 1 µV/°C ILEAK Input Leakage Current VCM = 2.5V 2 10 nA RIN Input Resistance 1 G CIN Input Capacitance 2 pF CMIR Common-Mode Input Range VSS- VDD+ V 0.5 0.5 CMRR Common-Mode Rejection Ratio For VIN from -0.5V to 5.5V 45 70 dB AVOL Open-Loop Gain 0.5V VOUT 4.5V 70 100 dB OUTPUT CHARACTERISTICS VOH Output Swing High IL= 5mA, VIN = VDD VDD- VDD- V 0.15 0.025 VOL Output Swing Low IL= -5mA,VIN = VSS VSS+ VSS+ V 0.025 0.15 ISC Short-Circuit Current ±0.5 A IOUT Continuous Output Current (Note 10) ±300 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) 1V VOUT 4V 15 V/µs tS Settling to 0.1% (Note 9) AV = +1, VO = 2V step 80 ns BW -3dB Bandwidth AV = +1, RL = 1kCL= 8pF 22 MHz PM Phase Margin RL = 1kCL= 8pF 46 ° THERMAL PERFORMANCE TTS Thermal Shutdown Temperature Die temperature at which the device will +165 °C shutdown until it cools by TTSH °C TTSH Thermal Shutdown Hysteresis Die temperature below TTS °C when the 15 °C device will become operational after shutdown Electrical Specifications VDD = 15V, VSS = GND = 0V, RL = 1k to 7.5V, TA = +25°C, Unless Otherwise Specified. MIN MAX PARAMETER DESCRIPTION CONDITION (Note 6) TYP (Note 6) UNIT POWER SUPPLY PERFORMANCE VDD - VSS Supply Voltage Range 4.5 19 V IS Supply Current No load 2.2 2.8 mA PSRR Power Supply Rejection Ratio VS is moved from +4.5V to +19V 60 80 dB INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 1.4 15 mV TCVOS Average Offset Voltage Drift (Note 7) 1 µV/°C FN6637 Rev 1.00 Page 3 of 13 October 18, 2011

ISL24021 Electrical Specifications VDD = 15V, VSS = GND = 0V, RL = 1k to 7.5V, TA = +25°C, Unless Otherwise Specified. (Continued) MIN MAX PARAMETER DESCRIPTION CONDITION (Note 6) TYP (Note 6) UNIT ILEAK Input Leakage Current VCM = 7.5V 2 10 nA RIN Input Resistance 1 G CIN Input Capacitance 2 pF CMIR Common-Mode Input Range VSS- VDD+ V 0.5 0.5 CMRR Common-Mode Rejection Ratio For VIN from -0.5V to 15.5V 50 70 dB AVOL Open-Loop Gain 0.5V VOUT 14.5V 75 95 dB OUTPUT CHARACTERISTICS VOH Output Swing High IL= 100mA, VIN = VDD VDD - V 0.4 IL= 7.5mA, VIN = VDD VDD - VDD - V 0.15 0.025 VOL Output Swing Low IL= -100mA,VIN = VSS VSS + V 0.4 IL= -7.5mA,VIN = VSS VSS + VSS + V 0.025 0.15 ISC Short-Circuit Current ±1.0 A IOUT Continuous Output Current (Note 10) ±300 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) 1V VOUT 14V 19 V/µs tS Settling to 0.1% (Note 9) AV = +1, VO = 2V step 80 ns BW -3dB Bandwidth AV = +1, RL = 1kCL= 8pF 27 MHz PM Phase Margin RL = 1kCL= 8pF 42 ° THERMAL PERFORMANCE TTS Thermal Shutdown Temperature Die temperature at which the device will +165 °C shutdown until it cools by TTSH °C TTSH Thermal Shutdown Hysteresis Die temperature below TTS °C when the 15 °C device will become operational after shutdown NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Measured over the -40°C to +85°C ambient operating temperature range. 8. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal. 9. Settling time measured from [Full Scale - (0.1%*StepSize)] on the rising edge to when the output is bounded within ±0.1% of full scale. 10. Continuous output current with a typical of ±300mA. Care should be taken to ensure the maximum package power dissipation is not exceeded, refer to “Power Dissipation” on page10. Pin Descriptions PIN NUMBER PIN NAME PIN TYPE PIN FUNCTION 1, 5, 8 NC No Connection 2 INN Analog Input Amplifier negative input 3 INP Analog Input Amplifier positive input 4 VSS Analog Power Negative power supply (connect to GND for single supply operation) 6 OUT Analog Output Amplifier output 7 VDD Analog Power Positive power supply FN6637 Rev 1.00 Page 4 of 13 October 18, 2011

ISL24021 Typical Performance Curves 500 1.0 450 VS = ±5V TPYRPOIDCUALC TION V) 0.8 VS = ±5V ES 400 TA = +25°C DISTRIBUTION E (m 0.6 C 350 G 0.4 VI TA E 300 L 0.2 D O OF 250 T V 0.0 MBER 125000 OFFSE --00..42 NU 100 UT -0.6 P 50 N -0.8 I 0 -1.0 -6 -4 -2 0 2 4 6 -50 0 50 100 150 INPUT OFFSET VOLTAGE (mV) TEMPERATURE (°C) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE vs TEMPERATURE 2.0 4.972 NT (nA) 11..05 VS = ±5V E (V) 4.970 VARVSL === 1±15kV E G R A 4.968 UR 0.5 OLT GE C 0.0 GH V 4.966 KA -0.5 HI A T 4.964 E U L -1.0 P UT UT 4.962 P -1.5 O N I -2.0 4.960 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 3. INPUT LEAKAGE CURRENT vs TEMPERATURE FIGURE 4. OUTPUT HIGH VOLTAGE vs TEMPERATURE -4.980 120 VS = ±5V VS = ±5V V) -4.982 AV = 1 E ( RL = 1k B) 110 G d TA -4.984 N ( L AI 100 O G W V -4.986 OP O O 90 L L T -4.988 N U E P P T O 80 U -4.990 O -4.992 70 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 5. OUTPUT LOW VOLTAGE vs TEMPERATURE FIGURE 6. OPEN-LOOP GAIN vs TEMPERATURE FN6637 Rev 1.00 Page 5 of 13 October 18, 2011

ISL24021 Typical Performance Curves (Continued) 100 100 VS = ±5V VS = ±5V 95 90 90 B) B) 80 d d R ( 85 R ( R R S M 70 P 80 C 60 75 70 50 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. PSRR vs TEMPERATURE FIGURE 8. CMRR vs TEMPERATURE 22 2.6 VS = ±5V VS = ±5V V/µs) 20 AV = 2 NT (mA) 2.4 E ( RE 2.2 W RAT 18 Y CUR 2.0 E L L P S 16 P U S 1.8 14 1.6 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. SLEW RATE vs TEMPERATURE FIGURE 10. SUPPLY CURRENT vs TEMPERATURE 140 4.0 TA = +25°C 3.5 TA = +25°C 120 mA) 3.0 RL = OPEN GAIN (dB) 10800 Y CURRENT ( 22..05 L P 1.5 P U 60 S 1.0 40 0.5 4 8 12 16 20 4 8 12 16 20 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 11. OPEN-LOOP GAIN vs SUPPLY VOLTAGE FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE FN6637 Rev 1.00 Page 6 of 13 October 18, 2011

ISL24021 Typical Performance Curves (Continued) 5 10 4 VS = ±5V 8 VS = ±5V 3 AV = 1 1k 6 AV = 1 2 4 47pF 560 B) 1 B) 2 d d N ( 0 N ( 0 GAI -1 GAI -2 100pF 10pF -2 -4 -3 150 -6 -4 -8 -5 -10 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS RL FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS CL 5 120 180 4 VS = ±5V 100 160 3 AV = 1 80 GAIN (dB) 140 V) 2 60 120 ZE ( 1 dB)40 100E(°) TEP SI -01 0.1% GAIN (200 PHASE (°) 6800 PHAS S -2 -20 40 -3 -40 VS = ±5V 20 -4 -60 0 TA = +25°C -5 -80 -20 50 60 70 80 90 100 110 10 100 1k 10k 100k 1M 10M 100M SETTLING TIME (ns) FREQUENCY (Hz) FIGURE 15. STEP SIZE vs SETTLING TIME FIGURE 16. OPEN LOOP GAIN AND PHASE -10 10 VS = ±5V 0 VS = ±5V -20 RL = 1k -10 RL = 1k -30 -20 CMRR (dB) ---456000 PSRR (dB) ---345000 PSRR- -60 -70 -70 PSRR+ -80 -80 -90 -90 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 17. CMRR vs FREQUENCY FIGURE 18. PSRR vs FREQUENCY FN6637 Rev 1.00 Page 7 of 13 October 18, 2011

ISL24021 Typical Performance Curves (Continued) VS = ±5V 1000 AV = 1 z) H  V/ 100 n E ( S OI N E G 10 A 6V STEP T L 200ns/DIV O V 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 19. INPUT VOLTAGE NOISE SPECTRAL DENSITY FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE VS = ±5V AV = 1 INN VDD INP ISL24021 0.1µF 4.7µF VSS OUT 200mV STEP 200ns/DIV 4.7µF 0.1µF RL CL THERMAL PAD CONNECTED TO VSS FIGURE 21. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 22. TEST CIRCUIT FN6637 Rev 1.00 Page 8 of 13 October 18, 2011

ISL24021 Applications Information VS = ±2.5V, TA = +25°C, AV = 1, VIN = 6VP-P Product Description 1V 10µs The ISL24021 is a high output current, high voltage, rail-to-rail voltage feedback amplifier. The ISL24021 is capable of ±1A peak output short circuit current. The amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. Other features include fast slew rate and settling time which is important in many applications, such as TFT-LCD panels. The ISL24021 is available in a 8 Ld 3mmx3mm TDFN package 1V featuring a standard operational amplifier pinout and a lead pitch of 0.65mm. The device utilizes a thermally enhanced package and FIGURE 23. OPERATION WITH BEYOND-THE-RAILS INPUT has a built-in thermal protection circuit. It is specified for operation . over an ambient temperature range of -40°C to +85°C. Operating Voltage, Input and Output VS = ±5V, TA = +25°C, AV = 1, VIN = 10VP-P Capability 5V 10µs The ISL24021 can operate on a single supply or dual supply configuration. The ISL24021 operating voltage ranges from a minimum of 4.5V to a maximum of 19V. This range allows for a T standard 5V (or ±2.5V) supply voltage to dip to -10%, or a PU N standard 18V (or ±9V) to rise by +5.5% without affecting I performance or reliability. T U The input common mode voltage range extends 0.5V beyond the P T supply rails. For this range, the ISL24021 amplifier is immune to 5V OU phase reversal. If the common mode input voltage exceeds the supply voltage by more than 0.5V, electrostatic protection diodes FIGURE 24. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT in the input stage of the device begin to conduct. It is suggested to not overdrive the inputs. Figure 23 shows the input voltage Output Current Limit driven beyond the supply rails and the device output swinging The ISL24021 is capable of ±1A peak output short circuit between the supply rails. current. The device will limit the current to ±1A. Maximum The output swings of the ISL24021 typically extend to within reliability is maintained if the output continuous current never 25mV of positive and negative supply rails with load currents of exceeds ±300mA. This limit is set by the characteristics of the ±5mA. Decreasing load currents will extend the output voltage internal metal interconnects. See “Power Dissipation” on range even closer to the supply rails. Figure 24 shows the input page10 for detailed information about ensuring device and output waveforms for the device in a unity-gain operation with temperature and load conditions. configuration. Operation is from ±5V supply with a 1k load Driving Capacitive Loads connected to GND. The input is a 10VP-P sinusoid and the output voltage is approximately 9.95VP-P. As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be Refer to the “Electrical Specifications” tables beginning on necessary to reduce peaking and to improve device stability. To page2 for specific device parameters. Parameter variations with improve device stability a snubber circuit or a series resistor may operating voltage, loading and/or temperature are shown in the be added to the output of the ISL24021. “Typical Performance Curves” on page5. A snubber is a shunt load consisting of a resistor in series with a capacitor, see Figure 25. An optimized snubber can improve the phase margin and the stability of the ISL24021. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between 1 to 10; see Figure 26). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. FN6637 Rev 1.00 Page 9 of 13 October 18, 2011

ISL24021 . Power Dissipation With a 300mA maximum continuous output drive capability, it is INN VDD possible to exceed the rated +150°C maximum junction 4.7µF temperature. It is important to calculate the maximum power INP ISL24021 0.1µF dissipation of the ISL24021 for the application. Proper load conditions will ensure that the ISL24021 junction temperature VSS OUT RSNUBBER stays within a safe operating region. 4.7µF 0.1µF ZL The ISL24021 has a built-in thermal protection, which THERMAL PAD automatically shuts the output OFF (high impedance) when the CONNECTED TO VSS CSNUBBER die temperature reaches +165°C. This ensures safe operation and prevents internal damage to the device. When the die cools FIGURE 25. OUTPUT SNUBBER CIRCUIT by +15°C the output will automatically turn ON. . The maximum power dissipation allowed in a package is determined according to Equation 1: INN VDD P = T----J--M-----A---X-----–----T---A----M-----A---X-- (EQ. 1) DMAX  4.7µF JA INP ISL24021 0.1µF where: VSS RSERIES OUT • TJMAX = Maximum junction temperature 4.7µF 0.1µF ZL • TAMAX = Maximum ambient temperature COTNHNEERCMTAELD PTAOD V SS •JA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package FIGURE 26. OUTPUT SERIES RESISTOR CIRCUIT The actual maximum power dissipation of the IC is the total Typical Application Circuit quiescent supply current, times the total power supply voltage, plus the power dissipation in the IC caused by the loading A typical application of the ISL24021 is as a TFT-LCD VCOM driver condition. (see Figure 27). A VCOM driver maintains the backplane common voltage of a TFT-LCD panel. Maintaining the VCOM voltage at a Sourcing: steady level is critical to panel performance. The ability of the ISL24021 to source/sink large peak short circuit currents make PDMAX = VSIS+VDD–VOUTILOAD (EQ. 2) it ideal as a VCOM driver. The ±1A short circuit current capability combined with a large bandwidth and fast settling time give the Sinking: ISL24021 ideal VCOM driver characteristics, and make it a great choice for TFT-LCD applications. P = V I +V –V I  (EQ. 3) DMAX S S OUT SS LOAD VDD = 15V • VS = Total supply voltage range (VDD - VSS) VCOM CARLEISBIRSATTOORR / ISL24021 0.1µF 4.7µF • IS = Device supply current LADDER INN - INP + TFT-LCD • VDD = Positive supply voltage • VSS = Negative supply voltage 0.1µF OUT + PANEL VSS CSTORAGE CAPACITANCE • VOUT = Output voltage THERMAL PAD CONNECTED • ILOAD = Load current TO VSS NOTE: CSTORAGE WILL VARY Device overheating can be avoided by calculating the minimum DEPENDING ON THE APPLICATION resistive load condition, RLOAD, resulting in the highest power dissipation. To find RLOAD, set the two PDMAX equations equal to FIGURE 27. TYPICAL APPLICATION CIRCUIT: TFT-LCD VCOM each other and solve for VOUT/ILOAD. Reference the package power dissipation curve, Figure 28, for further information. FN6637 Rev 1.00 Page 10 of 13 October 18, 2011

ISL24021 Printed Circuit Board Layout JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD - TDFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 As with any high-frequency device, good printed circuit board 3.0 layout is necessary for optimum performance. For the ISL24021 2.5W low impedance analog power and ground planes are W) 2.5 recommended, and trace lengths should be as short as possible. ON ( 2.0 TDFN8 The power supply pins must be well bypassed to reduce the risk ATI JA = +50 (°C/W) of oscillation. For optimal thermal and operating performance P the ISL24021 thermal pad should always be connected to the SI 1.5 DIS lowest potential, VSS. R 1.0 E For normal single supply operation (the VSS pin is connected to W PO 0.5 GND) a 4.7µF capacitor should be placed from VDD to GND, then a parallel 0.1µF capacitor should be connected as close to the amplifier as possible. For dual supply operation the same 0 0 25 50 75 100 125 150 bypassing techniques should be utilized by connecting capacitors AMBIENT TEMP (°C) from each supply to GND. FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6637 Rev 1.00 Page 11 of 13 October 18, 2011

ISL24021 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE 9/14/2011 FN6637.1 Updated Ordering Information by Removing bulk part ISL24021IRT065Z, added T7A part, PKG DWG# changed from L8.3x3A to L8.3x3K, added MSL Note Changed Human Body Model from "3000V" to "7500V" Added to Abs Max Rating - Charged Device Model Updated Tja Note to Non direct attached at High Thermal conductivity Added to Thermal Information Tjc "17" and respective note. Electrical Spec Table - Updated Note from: Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. To: Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Changed POD L8.3x3A to L8.3x3K. 06/03/2009 FN6637.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL24021 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php © Copyright Intersil Americas LLC 2009-2011. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6637 Rev 1.00 Page 12 of 13 October 18, 2011

ISL24021 Package Outline Drawing L8.3x3K 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 7/11 2X 1.95 3.00 A 6X 0.65 B PIN #1 1 INDEX AREA 6 6 00 1.50 ±0.10 3. PIN 1 INDEX AREA (4X) 0.15 8 TOP VIEW 8X 0.25 ±0.05 4 0.40 ± 0.05 0.10 M C A B 2.30 ±0.10 BOTTOM VIEW SEE DETAIL "X" C 0 . 203 REF 5 0.10 C C 0.75 ±0.05 0 . 02 NOM. 0.08 C 0 . 05 MAX. SIDE VIEW DETAIL "X" ( 2.30) ( 1.95) NOTES: ( 8X 0.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (1.50) 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. ( 2.90 ) 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. PIN 1 5. Tiebar shown (if present) is a non-functional feature. (6x 0.65) 6. The configuration of the pin #1 identifier is optional, but must be ( 8 X 0.25) located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. TYPICAL RECOMMENDED LAND PATTERN 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. FN6637 Rev 1.00 Page 13 of 13 October 18, 2011