DATASHEET ISL12022MA FN7575 Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Rev 5.00 Compensation and Auto Daylight Saving September 5, 2012 The ISL12022MA device is a low power real time clock (RTC) Features with an embedded temperature sensor and crystal. Device functions include oscillator compensation, clock/calendar, • Embedded 32.768kHz Quartz Crystal in the Package power fail and low battery monitors, brownout indicator, • 20 Ld SOIC Package (for DFN version, refer to the one-time, periodic or polled alarms, intelligent battery backup ISL12020M) switching, Battery Reseal™ function and 128 bytes of • Calendar battery-backed user SRAM. Backup battery current draw is less • On-chip Oscillator Temperature Compensation than 1.6µA over the temperature range. The device is offered in a 20Ld SOIC module that contains the RTC and an embedded • 10-bit Digital Temperature Sensor Output 32.768kHz quartz crystal. The calibrated oscillator provides less • 15 Selectable Frequency Outputs than ±5ppm drift over the full -40°C to +85°C temperature • Interrupt for Alarm or 15 Selectable Frequency Outputs range. • Automatic Backup to Battery or Supercapacitor The RTC tracks time with separate registers for hours, minutes, • VDD and Battery Status Monitors and seconds. The calendar registers track date, month, year and • Battery Reseal™ Function to Extend Battery Shelf Life day of the week and are accurate through 2099, with automatic leap year correction. • Power Status Brownout Monitor • Time Stamp for Battery Switchover Daylight Savings time adjustment is done automatically, using parameters entered by the user. Power fail and battery monitors • 128 Bytes Battery-Backed User SRAM offer user-selectable trip levels. The time stamp function records • 1.6µA Max Battery Current the time and date of switchover from VDD to VBAT power, and • I2C Bus™ also from VBAT to VDD power. • RoHS Compliant The ISL12022MA features enhanced immunity to ESD per the Applications IEC61000-4-2 standard, and also provides improved resistance to system leakage related to environmental moisture. • Utility Meters Related Literature • POS Equipment • Printers and Copiers • See TB484 “ISL12022MA Enhanced RTC Module” • Digital Cameras • See AN1549 “Addressing Power Issues in Real Time Clock Applications” 1 20 GND GND 2 19 GND GND 3 18 GND GND 3.3V 4 17 NC NC 5 16 SCHOTTKY DIODE NC NC C1 6 15 R1 R2 R3 BAT54 NC NC 0.1µF 7 14 10k 10k 10k VBAT VDD BATTERY C2 8 GND IRQ/FOUT 13 VDO 3.0V 0.1µF 9 12 NC SCL SCL MCU 10 NC SDA 11 SDA INTERFACE ISL12022MA GND IRQ/FOUT FIGURE 1. TYPICAL APPLICATION CIRCUIT FN7575 Rev 5.00 Page 1 of 31 September 5, 2012

ISL12022MA Block Diagram SDA SDA BUFFER I2C SECONDS SCL SCL INTERFACE COLNOTGRICOL MINUTES BUFFER REGISTERS HOURS DAY OF WEEK CRYSTAL RTC DATE OSCILLATOR DIVIDER MONTH VDD POR FREQUENCY YEAR OUT ALARM CONTROL VTRIP REGISTERS + SWITCH USER - SRAM VBAT INSTUEPRPNLAYL IRQ/FOUT GND TEMPERATURE FREQUENCY SENSOR CONTROL Pin Configuration ISL12022MA (20 LD SOIC) TOP VIEW GND 1 20 GND GND 2 19 GND GND 3 18 GND NC 4 17 NC NC 5 16 NC NC 6 15 NC VBAT 7 14 VDD GND 8 13 IRQ/FOUT NC 9 12 SCL NC 10 11 SDA Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 4, 5, 6, 9, 10, NC No Connection. Do not connect to a signal or supply voltage. 15, 16, 17 7 VBAT Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a supercapacitor or tied to ground if not used. See the Battery Monitor parameter in the “” table on page6. This pin should be tied to ground if not used. 11 SDA Serial Data. SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be OR’ed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. 12 SCL Serial Clock. The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. FN7575 Rev 5.00 Page 2 of 31 September 5, 2012

ISL12022MA Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 13 IRQ/FOUT Interrupt Output/Frequency Output (Default 32.768kHz frequency output). This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. Frequency Output Mode. The pin outputs a clock signal, which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain output. The output is open drain and requires a pull-up resistor. 14 VDD Power Supply. Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. 1, 2, 3, 8, 18, GND Ground Pin. 19, 20 Ordering Information PART NUMBER PART VDD RANGE TEMP RANGE PACKAGE PKG. (Notes 2, 3) MARKING (V) (°C) (RoHS Compliant) DWG. # ISL12022MAIBZ ISL12022MAIBZ 2.7 to 5.5 -40 to +85 20 Ld SOIC M20.3 ISL12022MAIBZ-T (Note 1) ISL12022MAIBZ 2.7 to 5.5 -40 to +85 20 Ld SOIC (Tape and Reel) M20.3 1. Please refer to TB347 for details on reel specifications. 2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (Pb in high melting temperature type solders, electronic ceramic parts (e.g. piezoelectronic devices)) and exemption 5 (Pb in glass of electronic components). These Intersil RoHS compliant products are compatible with both SnPb and Pb free soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12022MA. For more information on MSL please see Tech Brief TB363. FN7575 Rev 5.00 Page 3 of 31 September 5, 2012

ISL12022MA Table of Contents Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Operating Characteristics RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power-Down Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 I C Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SDA vs SCL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Symbol Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Normal Mode (V ) to Battery DD Backup Mode (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BAT Battery Backup Mode (V ) to BAT Normal Mode (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DD Power Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Brownout Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Battery Level Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Real Time Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single Event and Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Frequency Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General Purpose User SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 I C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Real Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Addresses [00h to 06h]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Control and Status Registers (CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Addresses [07h to 0Fh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Supply Control Register (PWR_VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery Voltage Trip Voltage Register (PWR_VBAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Initial AT and DT Setting Register (ITRO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ALPHA Register (ALPHA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BETA Register (BETA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Final Analog Trimming Register (FATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Final Digital Trimming Register (FDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ALARM Registers (10h to 15h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Time Stamp VDD to Battery Registers (TSV2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Time Stamp Battery to VDD Registers (TSB2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DST Control Registers (DSTCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TEMP Registers (TEMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 NPPM Registers (NPPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 XT0 Registers (XT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ALPHA Hot Register (ALPHAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 User Registers (Accessed by Using Slave Address 1010111x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Addresses [00h to 7Fh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Protocol Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FN7575 Rev 5.00 Page 4 of 31 September 5, 2012

ISL12022MA Device Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power Supply Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Battery Backup Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Measuring Oscillator Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Temperature Compensation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Daylight Savings Time (DST) Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Device Handling Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FN7575 Rev 5.00 Page 5 of 31 September 5, 2012

ISL12022MA Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT and IRQ/FOUT pins Thermal Resistance (Typical) JA (°C/W) JC (°C/W) (Respect to Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 20 Lead SOIC (Notes 4, 5). . . . . . . . . . . . . . 70 35 Voltage on SCL and SDA pins Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C (Respect to Ground). . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V Pb-Free Reflow Profile (Note 6). . . . . . . . . . . . . . . . . . . . . . . . see link below ESD Rating http://www.intersil.com/pbfree/Pb-FreeReflow.asp Human Body Model (Per JESD22-A114F) . . . . . . . . . . . . . . . . . . . . . . >3kV Machine Model (Per JESD22-A115B) . . . . . . . . . . . . . . . . . . . . . . . .>300V Charge Device Model (Per JESD22-C101D) . . . . . . . . . . . . . . . . . . . .2.2kV Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Shock Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . .5000g, 0.3ms, 1/2 sine Vibration (Ultrasound cleaning not advised). . . . . . . . . . .20g/10-2000Hz, CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is on top of the package and measured in the center of the package between pins 6 and 15. 6. The ISL12022MA Oscillator Initial Accuracy can change after solder reflow attachment. The amount of change will depend on the reflow temperature and length of exposure. A general rule is to use only one reflow cycle and keep the temperature and time as short as possible. Changes on the order of ±1ppm to ±3ppm can be expected with typical reflow profiles. DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note 7) (Note 8) (Note 7) UNITS NOTES VDD Main Power Supply (Note 15) 2.7 5.5 V VBAT Battery Supply Voltage (Note 15) 1.8 5.5 V 9 IDD1 Supply Current. (I2CNotActive, VDD = 5V 4.1 15 µA 10, 11 Temperature Conversion Not Active, FOUT Not Active) VDD = 3V 3.5 14 µA 10, 11 IDD2 Supply Current. (I2C Active, Temperature VDD = 5V 200 500 µA 10, 11 Conversion Not Active, Fout Not Active) IDD3 Supply Current. (I2CNotActive, VDD = 5V 120 400 µA 10, 11 Temperature Conversion Active, FOUT Not Active) IBAT Battery Supply Current VDD = 0V, VBAT = 3V, TA=+25°C 1.0 1.6 µA 10 VDD = 0V, VBAT = 3V 1.0 5.0 µA 10 IBATLKG Battery Input Leakage VDD = 5.5V, VBAT = 1.8V 100 nA ILI Input Leakage Current on SCL VIL = 0V, VIH = VDD -1.0 ±0.1 1.0 µA ILO I/O Leakage Current on SDA VIL = 0V, VIH = VDD -1.0 ±0.1 1.0 µA VBATM Battery Level Monitor Threshold -100 +100 mV VPBM Brownout Level Monitor Threshold -100 +100 mV VTRIP VBAT Mode Threshold (Note 15) 2.0 2.2 2.4 V VTRIPHYS VTRIP Hysteresis 30 mV 13 VBATHYS VBAT Hysteresis 50 mV 13 FN7575 Rev 5.00 Page 6 of 31 September 5, 2012

ISL12022MA DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note 7) (Note 8) (Note 7) UNITS NOTES OSCILLATOR ACCURACY FoutI Oscillator Initial Accuracy VDD  3.3V -2 +8 ppm 6, 17 FoutR Oscillator Accuracy after Reflow Cycle VDD  3.3V ±5 ppm 6, 17 FoutT Oscillator Stability vs Temperature VDD  3.3V ±2 ppm 6, 18 FoutV Oscillator Stability vs Voltage 2.7V  VDD  5.5V -3 +3 ppm 19 Temp Temperature Sensor Accuracy VDD = VBAT = 3.3V ±2 °C 13 IRQ/FOUT (OPEN DRAIN OUTPUT) VOL Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V VDD = 2.7V, IOL = 1mA 0.4 V Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note 7) (Note 8) (Note 7) UNITS NOTES VDDSR- VDD Negative Slew Rate 10 V/ms 12 VDDSR+ VDD Positive Slew Rate, minimum 0.05 V/ms 16 2 I C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 7) (Note 8) (Note 7) UNITS NOTES VIL SDA and SCL Input Buffer -0.3 0.3 x VDD V LOW Voltage VIH SDA and SCL Input Buffer 0.7 x VDD VDD + 0.3 V HIGH Voltage Hysteresis SDA and SCL Input Buffer 0.05 x VDD V 13, 14 Hysteresis VOL SDA Output Buffer LOW VDD = 5V, IOL = 3mA 0 0.02 0.4 V Voltage, Sinking 3mA CPIN SDA and SCL Pin TA = +25°C, f = 1MHz, 10 pF 13, 14 Capacitance VDD = 5V, VIN=0V, VOUT = 0V fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Any pulse narrower than the max spec is 50 ns Time at SDA and SCL suppressed. Inputs tAA SCL Falling Edge to SDA SCL falling edge crossing 30% of VDD, 900 ns Output Data Valid until SDA exits the 30% to 70% of VDD window. tBUF Time the Bus Must be Free SDA crossing 70% of VDD during a STOP 1300 ns Before the Start of a New condition, to SDA crossing 70% of VDD Transmission during the following START condition. tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns FN7575 Rev 5.00 Page 7 of 31 September 5, 2012

ISL12022MA 2 I C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 7) (Note 8) (Note 7) UNITS NOTES tSU:STA START Condition Setup SCL rising edge to SDA falling edge. Both 600 ns Time crossing 70% of VDD. tHD:STA START Condition Hold From SDA falling edge crossing 30% of 600 ns Time VDD to SCL falling edge crossing 70% of VDD. tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD 100 ns window, to SCL rising edge crossing 30% of VDD. tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of 20 900 ns VDD to SDA entering the 30% to 70% of VDD window. tSU:STO STOP Condition Setup From SCL rising edge crossing 70% of 600 ns Time VDD, to SDA rising edge crossing 30% of VDD. tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge. 600 ns Both crossing 70% of VDD. tDH Output Data Hold Time From SCL falling edge crossing 30% of 0 ns VDD, until SDA enters the 30% to 70% of VDD window. tR SDA and SCL Rise Time From 30% to 70% of VDD. 20 +0.1 x Cb 300 ns 13, 14 tF SDA and SCL Fall Time From 70% to 30% of VDD. 20 +0.1 x Cb 300 ns 13, 14 Cb Capacitive Loading of SDA Total on-chip and off-chip 10 400 pF 13, 14 or SCL RPU SDA and SCL Bus Pull-up Maximum is determined by tR and tF. 1 k 13, 14 Resistor Off-chip For Cb = 400pF, max is about 2k~2.5k. For Cb = 40pF, max is about 15k~20k NOTES: 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. Specified at +25°C. 9. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT <1.8V. 10. IRQ/FOUT inactive. 11. VDD > VBAT +VBATHYS 12. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 13. Limits should be considered typical and are not production tested. 14. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 15. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested. 16. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only. 17. Defined as the deviation from a target oscillator frequency of 32,768.0Hz at room temperature. 18. Defined as the deviation from the room temperature measured 1Hz frequency, VDD = 3.3V, at TA = -40°C to +85°C. 19. Defined as the deviation at room temperature from the measured 1Hz frequency (or equivalent) at VDD = 3.3, over the range of VDD = 2.7V to VDD=5.5V. FN7575 Rev 5.00 Page 8 of 31 September 5, 2012

ISL12022MA SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V WAVEFORM INPUTS OUTPUTS 1533Ω FOR VOL= 0.4V Must be steady Will be steady SDA AND IOL = 3mA AND IRQ/FOUT May change Will change 100pF from LOW from LOW to HIGH to HIGH FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE May change Will change from HIGH from HIGH WITH VDD = 5.0V to LOW to LOW Don’t Care: Changing: Changes Allowed State Not Known N/A Center Line is High Impedance FN7575 Rev 5.00 Page 9 of 31 September 5, 2012

ISL12022MA Typical Performance Curves Temperature is +25°C unless otherwise specified. 1050 1600 1000 1400 A) n NT ( 950 A) 1200 VBAT = 5.5V E n RR (T CUT 900 IBA 1000 VBAT = 3.0V A B V 850 800 VBAT = 1.8V 800 600 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 -40 -20 0 20 40 60 80 VBAT VOLTAGE (V) TEMPERATURE (°C) FIGURE 3. IBAT vs VBAT (VDD = 0V) FIGURE 4. IBAT vs TEMPERATURE (VDD = 0V) 6 4.4 4.2 5 4.0 VDD = 5.5V A) A) 3.8 µ 4 µ (D1 (D1 3.6 ID VDD = 2.7V ID 3.4 3 VDD = 3.3V 3.2 2 3.0 -40 -20 0 20 40 60 80 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE (°C) VDD (V) FIGURE 5. IDD1 vs TEMPERATURE FIGURE 6. IDD1 vs VDD 5 6 4 m) p 3 R (p 2 5 VBAT = 5.5V O R 1 CY ER 0 VBAT = 5.5V (µA)D 4 VDD = 3.3V EN -1 VDD = 2.7V ID QU -2 E 3 VDD = 2.7V FR -3 VDD = 3.3V UT -4 O F -5 2 -40 -20 0 20 40 60 80 0.01 0.1 1 10 100 1k 10k 1M TEMPERATURE (°C) FREQUENCY OUTPUT (Hz) FIGURE 7. OSCILLATOR ERROR vs TEMPERATURE FIGURE 8. FOUT vs IDD FN7575 Rev 5.00 Page 10 of 31 September 5, 2012

ISL12022MA Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued) 5.5 110 100 5.0 90 VBAT = 5.5V FOUT = 32kHz µA) 4.5 80 T ( RREN 4.0 (µA)T 6700 U A Y C 3.5 FOUT = 64Hz IB 50 VDD = 3.0V L PP FOUT = 1Hz 40 U 3.0 S 30 VDD = 1.8V 2.5 20 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. IDD vs TEMPERATURE, 3 DIFFERENT FOUT FIGURE 10. IBAT WITH TSE = 1, BTSE = 1 vs TEMPERATURE 110 80 100 VBAT = 5.5V m) 60 32ppm 90 pp 40 62.5ppm E ( 20 G 0ppm (µA)D 7800 VDD = 3.3V CHAN 0 D Y -20 I C 60 VDD = 2.7V QUEN -40 -61.5ppm -31ppm 50 RE -60 F 40 -80 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 11. IDD WITH TSE = 1 vs TEMPERATURE FIGURE 12. OSCILLATOR CHANGE vs TEMPERATURE AT DIFFERENT AGING SETTINGS (IATR) (BETA SET FOR 1ppm STEPS) General Description the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The ISL12022MA device is a low power real time clock (RTC) with embedded temperature sensor and crystal. It contains crystal The device also offers a backup power input pin. This VBAT pin frequency compensation circuitry over the operating temperature allows the device to be backed up by battery or supercapacitor range good to ±5ppm accuracy. It also contains a clock/calendar with automatic switchover from VDD to VBAT. The ISL12022MA with Daylight Savings Time (DST) adjustment, power fail and low device is specified for VDD=2.7V to 5.5V and the clock/calendar portion of the device remains fully operational in battery backup battery monitors, brownout indicator, 1 periodic or polled alarm, intelligent battery backup switching and 128 Bytes of battery- mode down to 1.8V (Standby Mode). The VBAT level is monitored and reported against preselected levels. The first report is backed user SRAM. registered when the VBAT level falls below 85% of nominal level; The oscillator uses an internal 32.768kHz crystal. The real time the second level is set for 75%. Battery levels are stored in clock tracks time with separate registers for hours, minutes and PWR_VBAT registers. seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, The ISL12022MA offers a “Brownout” alarm once the VDD falls below a pre-selected trip level. This allows system Micro to save with automatic leap year correction. In addition, the vital information to memory before complete power loss. There ISL12022MA can be programmed for automatic Daylight Saving Time (DST) adjustment by entering local DST information. are six VDD levels that could be selected for initiation of the Brownout alarm. The ISL12022MA’s alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ/FOUT pin. There is a repeat mode for FN7575 Rev 5.00 Page 11 of 31 September 5, 2012

ISL12022MA Functional Description BATTERY BACKUP Power Control Operation MODE VDD The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For VBAT 3.0V example, 3.0V or 3.6V Lithium batteries are appropriate, and battery VTRIP 2.2V sizes are available that can power the ISL12022MA for up to 10 years. Another option is to use a supercapacitor for applications where VDD is interrupted for up to a month. See the “Application VTRIP VTRIP + VTRIPHYS Section” on page27 for more information. Normal Mode (V ) to Battery FIGURE 14. BATTERY SWITCHOVER WHEN VBAT > VTRIP DD Backup Mode (V ) BAT The device Time Stamps the switchover from VDD to VBAT and To transition from the VDD to VBAT mode, both of the following VBAT to VDD, and the time is stored in tSV2B and tSB2V registers conditions must be met: respectively. If multiple VDD power-down sequences occur before Condition 1: the status is read, the earliest VDD to VBAT power-down time is VDD < VBAT - VBATHYS stored and the most recent VBAT to VDD time is stored. where VBATHYS  50mV Temperature conversion and compensation can be enabled in battery backup mode. Bit BTSE in the BETA register controls this Condition 2: operation, as described in “BETA Register (BETA)” on page20. VDD < VTRIP where VTRIP  2.2V Power Failure Detection The ISL12022MA provides a Real Time Clock Failure Bit (RTCF) Battery Backup Mode (V ) to BAT to detect total power failure. It allows users to determine if the Normal Mode (V ) DD device has powered up after having lost all power to the device The ISL12022MA device will switch from the VBAT to VDD mode (both VDD and VBAT). when one of the following conditions occurs: Brownout Detection Condition 1: The ISL12022MA monitors the VDD level continuously and VDD > VBAT + VBATHYS provides warning if the VDD level drops below prescribed levels. where VBATHYS 50mV There are six (6) levels that can be selected for the trip level. Condition 2: These values are 85% below popular VDD levels. The LVDD bit in the Status Register will be set to “1” when brownout is detected. VDD > VTRIP + VTRIPHYS Note that the I2C serial bus remains active unless the Battery where VTRIPHYS  30mV VTRIP levels are reached. These power control situations are illustrated in Figures13 and Battery Level Monitor 14. The I2C bus is deactivated in battery backup mode to reduce The ISL12022MA has a built-in warning feature once the backup battery level drops first to 85% and then to 75% of the battery’s power consumption. Aside from this, all RTC functions are operational during battery backup mode. Except for SCL and SDA, nominal VBAT level. When the battery voltage drops to between 85% and 75%, the LBAT85 bit is set in the status register. When all the inputs and outputs of the ISL12022MA are active during the level drops below 75%, both LBAT85 and LBAT75 bits are set battery backup mode unless disabled via the control register. in the status register. The battery level monitor is not functional in battery backup BATTERY BACKUP mode. In order to read the monitor bits after powering up VDD, MODE instigate a battery level measurement by setting the TSE bit to VDD "1" (BETA register), and then read the bits. VTRIP 2.2V There is a Battery Time Stamp Function available. Once the VDD is VBAT 1.8V low enough to enable switchover to the battery, the RTC time/date are written into the TSV2B register. This information can be read VBAT - VBATHYS VBAT + VBATHYS from the TSV2B registers to discover the point in time of the VDD power-down. If there are multiple power-down cycles before reading these registers, the first values stored in these registers FIGURE 13. BATTERY SWITCHOVER WHEN VBAT < VTRIP will be retained. These registers will hold the original power-down value until they are cleared by setting CLRTS = 1 to clear the registers. FN7575 Rev 5.00 Page 12 of 31 September 5, 2012

ISL12022MA The normal power switching of the ISL12022MA is designed to should be noted that the I2C bus is disabled in battery backup switch into battery backup mode only if the VDD power is lost. mode. This will ensure that the device can accept a wide range of 2 I C Serial Interface backup voltages from many types of sources while reliably switching into backup mode. The ISL12022MA has an I2C serial bus interface that provides N< o1t.e8 tVh. aIft tthhee bISaLtt1e2ry0 2vo2lMtaAg eis i sn oetx pgeucatreadn tteoe ddr otop olopweerar tteh wanit hth VisB AT aThccee Is2sC t soe trhiael cinotnetrrfoal caen ids sctoamtupsa rteibglies tweritsh a ontdh ethr ein udsuesrt rSyR I2ACM . minimum, correct operation of the device, (especially after a VDD serial bus protocols using a bi-directional data signal (SDA) and a power-down cycle) is not guaranteed. clock signal (SCL). The minimum VBAT to insure SRAM is stable is 1.0V. Below that, Oscillator Compensation the SRAM may be corrupted when VDD power resumes. The ISL12022MA provides both initial timing correction and temperature correction due to variation of the crystal oscillator. Real Time Clock Operation Analog and digital trimming control is provided for initial The Real Time Clock (RTC) uses an integrated 32.768kHz quartz adjustment, and a temperature compensation function is provided crystal to maintain an accurate internal representation of to automatically correct for temperature drift of the crystal. Initial second, minute, hour, day of week, date, month, and year. The values for the initial AT and DT settings (ITR0), temperature RTC also has leap-year correction. The clock also corrects for coefficient (ALPHA), crystal capacitance (BETA), as well as the months having fewer than 31 days and has a bit that controls 24- crystal turn-over temperature (XTO), are preset internally and hour or AM/PM format. When the ISL12022MA powers up after recalled to RAM registers on power-up. The compensation function the loss of both VDD and VBAT, the clock will not begin can be enabled/disabled at any time and can be used in battery incrementing until at least one byte is written to the clock mode as well. register. Register Descriptions Single Event and Interrupt The battery-backed registers are accessible following a slave The alarm mode is enabled via the MSB bit. Choosing single byte of “1101111x” and reads or writes to addresses [00h:2Fh]. event or interrupt alarm mode is selected via the IM bit. Note that The defined addresses and default values are described in the when the frequency output function is enabled, the alarm Table 1. The battery backed general purpose SRAM has a function is disabled. different slave address (1010111x), so it is not possible to read/write that section of memory while accessing the registers. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single REGISTER ACCESS event mode, the IRQ/FOUT pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The pulsed interrupt mode allows for repetitive or recurring alarm The registers are divided into 8 sections. They are: functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and 1. Real Time Clock (7 bytes): Address 00h to 06h. present time. Thus, it will alarm as often as every minute (if only 2. Control and Status (9 bytes): Address 07h to 0Fh. the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the 3. Alarm (6 bytes): Address 10h to 15h. IRQ/FOUT pin will be pulled low for 250ms and the alarm status 4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah. bit (ALM) will be set to “1”. 5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh. The ALM bit can be reset by the user or cleared automatically 6. Day Light Saving Time (8 bytes): 20h to 27h. using the auto reset mode (see ARST bit). The alarm function can 7. TEMP (2 bytes): 28h to 29h. be enabled/disabled during battery backup mode using the 8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh. FOBATB bit. For more information on the alarm, please see “ALARM Registers (10h to 15h)” on page21. 9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch. 10.Crystal ALPHA at high temperature, ALPHA_H (1byte): 2Dh. Frequency Output Mode 11.Scratch Pad (2 bytes): Address 2Eh and 2Fh. The ISL12022MA has the option to provide a clock output signal Write capability is allowable into the RTC registers (00h to 06h) only using the IRQ/FOUT open drain output pin. The frequency output when the WRTC bit (bit 6 of address 08h) is set to “1”. A multi-byte mode is set by using the FO bits to select 15 possible output read or write operation should be limited to one section per frequency values from 1/32Hz to 32kHz. The frequency output operation for best RTC time keeping performance. can be enabled/disabled during Battery Backup mode using the FOBATB bit. A register can be read by performing a random read at any address at any time. This returns the contents of that register General Purpose User SRAM location. Additional registers are read by performing a sequential The ISL12022MA provides 128 bytes of user SRAM. The SRAM read. For the RTC and Alarm registers, the read instruction will continue to operate in battery backup mode. However, it latches all clock registers into a buffer, so an update of the clock FN7575 Rev 5.00 Page 13 of 31 September 5, 2012

ISL12022MA does not change the time being read. At the end of a read, the It is not necessary to set the WRTC bit prior to writing into the master supplies a stop condition to end the operation and free control and status, alarm, and user SRAM registers. the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. When the previous address is 2Fh, the next address will wrap around to 00h. TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS) BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 00h RTC SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h 01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 00h 02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h 03h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 01h 04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 01h 05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h 06h DW 0 0 0 0 0 DW2 DW1 DW0 0 to 6 00h 07h CSR SR BUSY OSCF DSTADJ ALM LVDD LBAT85 LBAT75 RTCF N/A 01h 08h INT ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 N/A 01h 09h PWR_VD CLRTS D D D D VDDTrip2 VDDTrip1 VDDTrip0 N/A 00h D 0Ah PWR_VBA D RESEAL VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 N/A 00h T B 0Bh ITRO IDTR0 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 N/A XXh 1 0Ch ALPHA D ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 N/A XXh 0Dh BETA TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 N/A XXh 0Eh FATR 0 0 FFATR5 FATR4 FATR3 FATR2 FATR1 FATR0 N/A 00h 0Fh FDTR 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 N/A 00h 10h ALARM SCA0 ESCA0 SCA022 SCA021 SCA020 SCA013 SCA012 SCA011 SCA010 00 to 59 00h 11h MNA0 EMNA MNA022 MNA021 MNA020 MNA013 MNA012 MNA011 MNA010 00 to 59 00h 0 12h HRA0 EHRA0 D HRA021 HRA020 HRA013 HRA012 HRA011 HRA010 0 to 23 00h 13h DTA0 EDTA0 D DTA021 DTA020 DTA013 DTA012 DTA011 DTA010 01 to 31 00h 14h MOA0 EMOA0 D D MOA020 MOA013 MOA012 MOA011 MOA010 01 to 12 00h 0 15h DWA0 EDWA D D D D DWA02 DWA01 DWA00 0 to 6 00h 0 16h TSV2B VSC 0 VSC22 VSC21 VSC20 VSC13 VSC12 VSC11 VSC10 0 to 59 00h 17h VMN 0 VMN22 VMN21 VMN20 VMN13 VMN12 VMN11 VMN10 0 to 59 00h 18h VHR VMIL 0 VHR21 VHR20 VHR13 VHR12 VHR11 VHR10 0 to 23 00h 19h VDT 0 0 VDT21 VDT20 VDT13 VDT12 VDT11 VDT10 1 to 31 00h 1Ah VMO 0 0 0 VMO20 VMO13 VMO12 VMO11 VMO10 1 to 12 00h FN7575 Rev 5.00 Page 14 of 31 September 5, 2012

ISL12022MA TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS) (Continued) BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 1Bh TSB2V BSC 0 BSC22 BSC21 BSC20 BSC13 BSC12 BSC11 BSC10 0 to 59 00h 1Ch BMN 0 BMN22 BMN21 BMN20 BMN13 BMN12 BMN11 BMN10 0 to 59 00h 1Dh BHR BMIL 0 BHR21 BHR20 BHR13 BHR12 BHR11 BHR10 0 to 23 00h 1Eh BDT 0 0 BDT21 BDT20 BDT13 BDT12 BDT11 BDT10 1 to 31 00h 1Fh BMO 0 0 0 BMO20 BMO13 BMO12 BMO11 BMO10 1 to 12 00h 20h DSTCR DstMoFd DSTE D D DstMoFd DstMoFd DstMoFd DstMoFd DstMoFd 1 to 12 00h 20 13 12 11 10 21h DstDwFd D DstDwFd DstWkFd DstWkFd DstWkFd DstDwFd DstDwFd DstDwFd 0 to 6 00h E 12 11 10 12 11 10 22h DstDtFd D D DstDtFd2 DstDtFd2 DstDtFd1 DstDtFd1 DstDtFd1 DstDtFd1 1 to 31 00h 1 0 3 2 1 0 23h DstHrFd D D DstHrFd2 DstHrFd2 DstHrFd1 DstHrFd1 DstHrFd1 DstHrFd1 0 to 23 00h 1 0 3 2 1 0 24h DstMoRv D D D DstMoRv DstMoRv DstMoR1 DstMoRv DstMoRv 01 to 12 00h 20 13 2v 11 10 25h DstDwRv D DstDwR DstWkrv1 DstWkRv DstWkRv DstDwRv DstDwRv DstDwRv 0 to 6 00h vE 2 11 10 12 11 10 26h DstDtRv D D DstDtRv2 DstDtRv2 DstDtRv1 DstDtRv1 DstDtRv1 DstDtRv1 01 to 31 00h 1 0 3 2 1 0 27h DstHrRv D D DstHrRv2 DstHrRv2 DstHrRv1 DstHrRv1 DstHrRv1 DstHrRv1 0 to 23 00h 1 0 3 2 1 0 28h TEMP TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 00 to FF 00h 29h TK0M 0 0 0 0 0 0 TK09 TK08 00 to 03 00h 2Ah NPPM NPPML NPPM NPPM6 NPPM5 NPPM4 NPPM3 NPPM2 NPPM1 NPPM0 00 to FF 00h 7 2Bh NPPMH 0 0 0 0 0 NPPM10 NPPM9 NPPM8 00 to 07 00h 2Ch XT0 XT0 D D D XT4 XT3 XT2 XT1 XT0 00 to FF XXh 2Dh ALPHAH ALPHAH D ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0 00 to 7F XXh 2Eh GPM GPM1 GPM17 GPM16 GPM15 GPM14 GPM13 GPM12 GPM11 GPM10 00 to FF 00h 2Fh GPM2 GPM2 GPM26 GPM25 GPM24 GPM23 GPM22 GPM21 GPM20 00 to FF 00h 7 Real Time Clock Registers week is arbitrary and may be decided by the system software designer. The default value is defined as “0”. Addresses [00h to 06h] 24-HOUR TIME RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) If the MIL bit of the HR register is “1”, the RTC uses a 24-hour These registers depict BCD representations of the time. As such, format. If the MIL bit is “0”, the RTC uses a 12-hour format and SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) HR21 bit functions as an AM/PM indicator with a “1” can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, representing PM. The clock defaults to 12-hour format time with MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the HR21 = “0”. Week) is 0 to 6. LEAP YEARS The DW register provides a Day of the Week status and uses three Leap years add the day February 29 and are defined as those years bits (DW2 to DW0) to represent the seven days of the week. The that are divisible by 4. Years divisible by 100 are not leap years, counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… unless they are also divisible by 400. This means that the year 2000 Theassignment of a numerical value to a specific day of the is a leap year and the year 2100 is not. The ISL12022MA does not correct for the leap year in the year 2100. FN7575 Rev 5.00 Page 15 of 31 September 5, 2012

ISL12022MA Control and Status Registers are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in (CSR) PWR_ VDD registers. The LVDD detection is only enabled in VDD mode and the detection happens in real time. The LVDD bit is set Addresses [07h to 0Fh] whenever the VDD has dropped below the pre-selected trip level, and self clears whenever the VDD is above the pre-selected trip The Control and Status Registers consist of the Status Register, level. Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers. LOW BATTERY INDICATOR 85% BIT (LBAT85) STATUS REGISTER (SR) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are The Status Register is located in the memory map at address selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the 07h. This is a volatile register that provides either control or PWR_VBAT registers. The LBAT85 detection happens automatically status of RTC failure (RTCF), Battery Level Monitor (LBAT85, once every minute when seconds register reaches 59. The detection LBAT75), alarm trigger, Daylight Saving Time, crystal oscillator can also be manually triggered by setting the TSE bit in BETA enable and temperature conversion in progress bit. register to “1”. The LBAT85 bit is set when the VBAT has dropped TABLE 2. STATUS REGISTER (SR) below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by ADDR 7 6 5 4 3 2 1 0 manual or automatic trigger. 07h BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 BUSY BIT (BUSY) detection happens automatically once when the minute register reaches x9h or x0h minutes. Busy Bit indicates temperature sensing is in progress. In this mode, Alpha, Beta and ITRO registers are disabled and cannot be Example - When the LBAT85 is Set To “1” In Battery Mode accessed. The minute the register changes to 19h when the device is in OSCILLATOR FAIL BIT (OSCF) battery mode, the LBAT85 is set to “1” the next time the device switches back to Normal Mode. Oscillator Fail Bit indicates that the oscillator has failed. The oscillator frequency is either zero or very far from the desired Example - When the LBAT85 Remains at “0” In Battery 32.768kHz due to failure, PC board contamination or mechanical Mode issues. If the device enters into battery mode after the minute register reaches 20h and switches back to Normal Mode before the DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ) minute register reaches 29h, then the LBAT85 bit will remain at DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the “0” the next time the device switches back to Normal Mode. daylight saving time forward adjustment has happened. If a DST Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit LOW BATTERY INDICATOR 75% BIT (LBAT75) will stay high when DSTFD event happens, and will be reset to “0” In Normal Mode (VDD), this bit indicates when the battery level has when the DST Reverse event happens. It is read-only and cannot be dropped below the pre-selected trip levels. The trip points are written. Setting time during a DST forward period will not set this bit selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the to “1”. PWR_VBAT registers. The LBAT75 detection happens automatically The DSTE bit must be enabled when the RTC time is more than once every minute when seconds register reaches 59. The detection one hour before the DST Forward or DST Reverse event time can also be manually triggered by setting the TSE bit in BETA setting, or the DST event correction will not happen. register to “1”. The LBAT75 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is DSTADJ is reset to “0” upon power-up. It will reset to “0” when the above the pre-selected trip level at the next detection cycle either by DSTE bit in Register 15h is set to “0” (DST disabled), but no time manual or automatic trigger. adjustment will happen. In Battery Mode (VBAT), this bit indicates the device has entered into ALARM BIT (ALM) battery mode by polling once every 10minutes. The LBAT85 This bit announces if the alarm matches the real time clock. If detection happens automatically once when the minute register there is a match, the respective bit is set to “1”. This bit can be reaches x9h or x0h minutes. manually reset to “0” by the user or automatically reset by Example - When the LBAT75 is Set to “1” in Battery Mode enabling the auto-reset bit (see ARST bit). A write to this bit in the The minute register changes to 30h when the device is in battery SR can only set it to “0”, not “1”. An alarm bit that is set by an mode, the LBAT75 is set to “1” the next time the device switches alarm occurring during an SR read operation will remain set after back to Normal Mode. the read operation is complete. Example - When the LBAT75 Remains at “0” in Battery Mode LOW V INDICATOR BIT (LV ) DD DD If the device enters into battery mode after the minute register This bit indicates when VDD has dropped below the pre-selected reaches 49h and switches back to Normal Mode before minute trip level (Brownout Mode). The trip points for the brownout levels FN7575 Rev 5.00 Page 16 of 31 September 5, 2012

ISL12022MA register reaches 50h, then the LBAT75 bit will remain at “0” the Note that the open drain IRQ/FOUT pin will need a pull-up to the next time the device switches back to Normal Mode. battery voltage to operate in battery backup mode. REAL TIME CLOCK FAIL BIT (RTCF) FREQUENCY OUT CONTROL BITS (FO <3:0>) This bit is set to a “1” after a total power failure. This is a read These bits enable/disable the frequency output function and only bit that is set by hardware (ISL12022MA internally) when select the output frequency at the IRQ/FOUT pin. See Table5 for the device powers up after having lost all power (defined as VDD frequency selection. Default for the ISL12022MA is FO<3:0> = 1h, = 0V and VBAT = 0V). The bit is set regardless of whether VDD or or 32.768kHz output (FOUT is ON). When the frequency mode is VBAT is applied first. The loss of only one of the supplies does not enabled, it will override the alarm mode at the IRQ/FOUT pin. set the RTCF bit to “1”. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN one byte is sufficient). FREQUENCYFOU Interrupt Control Register (INT) T UNITS FO3 FO2 FO1 FO0 0 Hz 0 0 0 0 TABLE 3. INTERRUPT CONTROL REGISTER (INT) 32768 Hz 0 0 0 1 ADDR 7 6 5 4 3 2 1 0 4096 Hz 0 0 1 0 08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 1024 Hz 0 0 1 1 AUTOMATIC RESET BIT (ARST) 64 Hz 0 1 0 0 This bit enables/disables the automatic reset of the ALM, LVDD, 32 Hz 0 1 0 1 LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”, 16 Hz 0 1 1 0 these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the 8 Hz 0 1 1 1 ARST is cleared to “0”, the user must manually reset the ALM, 4 Hz 1 0 0 0 LVDD, LBAT85, and LBAT75 bits. 2 Hz 1 0 0 1 WRITE RTC ENABLE BIT (WRTC) 1 Hz 1 0 1 0 The WRTC bit enables or disables write capability into the RTC 1/2 Hz 1 0 1 1 Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to 1/4 Hz 1 1 0 0 enable the RTC. Upon the completion of a valid write (STOP), the 1/8 Hz 1 1 0 1 RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. 1/16 Hz 1 1 1 0 INTERRUPT/ALARM MODE BIT (IM) 1/32 Hz 1 1 1 1 This bit enables/disables the interrupt mode of the alarm Power Supply Control Register (PWR_VDD) function. When the IM bit is set to “1”, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms CLEAR TIME STAMP BIT (CLRTS) will appear at the IRQ/FOUT pin when the RTC is triggered by the alarm, as defined by the alarm registers (0Ch to 11h). When the TABLE 6. IM bit is cleared to “0”, the alarm will operate in standard mode, where the IRQ/FOUT pin will be set low until the ALM status bit is ADDR 7 6 5 4 3 2 1 0 cleared to “0”. 09h CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0 TABLE 4. IM BIT INTERRUPT/ALARM FREQUENCY This bit clears Time Stamp VDD to Battery (TSV2B) and Time Stamp Battery to VDD Registers (TSB2V). The default setting is 0 0 Single Time Event Set By Alarm (CLRTS=0) and the Enabled setting is 1 (CLRTS= 1). 1 Repetitive/Recurring Time Event Set By Alarm V BROWNOUT TRIP VOLTAGE BITS (V TRIP<2:0>) DD DD These bits set the trip level for the VDD alarm, indicating that VDD FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) has dropped below a preset level. In this event, the LVDD bit in This bit enables/disables the IRQ/FOUT pin during battery the Status Register is set to “1”. See Table 7. backup mode (i.e. VBAT power source active). When the FOBATB is set to “1”, the IRQ/FOUT pin is disabled during battery backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to “0”, the IRQ/FOUT pin is enabled during battery backup mode. FN7575 Rev 5.00 Page 17 of 31 September 5, 2012

ISL12022MA TABLE 7. VDD TRIP LEVELS BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>) TRIP VOLTAGE VDDTrip2 VDDTrip1 VDDTrip0 (V) Three bits select the second alarm (75% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be 0 0 0 2.295 selected for the second alarm. Any of the of levels could be selected 0 0 1 2.550 as the second alarm with no reference as to nominal Battery voltage level. See Table 10. 0 1 0 2.805 TABLE 10. BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>) 0 1 1 3.060 BATTERY ALARM TRIP 1 0 0 4.250 LEVEL 1 0 1 4.675 VB75Tp2 VB75Tp1 VB75Tp0 (V) 0 0 0 1.875 Battery Voltage Trip Voltage Register 0 0 1 2.025 (PWR_VBAT) 0 1 0 2.250 This register controls the trip points for the two VBAT alarms, with levels set to approximately 85% and 75% of the nominal battery 0 1 1 2.475 level. 1 0 0 2.700 TABLE 8. 1 0 1 3.750 ADDR 7 6 5 4 3 2 1 0 1 1 0 4.125 0Ah D RESEALB VB85 VB85 VB85 VB75 VB75T VB75 Tp2 Tp1 Tp0 Tp2 p1 Tp0 Initial AT and DT Setting Register (ITRO) These bits are used to trim the initial error (at room temperature) RESEAL BIT (RESEALB) of the crystal. Both Digital Trimming (DT) and Analog Trimming This is the Reseal bit for actively disconnecting the VBAT pin from the (AT) methods are available. The digital trimming uses clock pulse internal circuitry. Setting this bit allows the device to disconnect the skipping and insertion for frequency adjustment. Analog battery and eliminate standby current drain while the device is trimming uses load capacitance adjustment to pull the oscillator unused. Once VDD is powered up, this bit is reset and the VBAT pin is frequency. A range of +62.5ppm to -61.5ppm is possible with then connected to the internal circuitry. combined digital and analog trimming. The application for this bit involves placing the chip on a board Initial values for the ITR0 register are preset internally and with a battery and testing the board. Once the board is tested recalled to RAM registers on power-up. These values are pre-set and ready to ship, it is desirable to disconnect the battery to keep in device production and are READ-ONLY. They cannot be it fresh until the board or unit is placed into final use. Setting overwritten by the user. If an application requires adjustment of RESEALB = “1” initiates the battery disconnect, and after VDD the IATR bits outside the preset values, the user should contact power is cycled down and up again, the RESEAL bit is cleared Intersil. to“0”. AGING AND INITIAL TRIM DIGITAL TRIMMING BITS BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>) (IDTR0<1:0>) Three bits select the first alarm (85% of Nominal VBAT) level for the These bits allow ±30.5ppm initial trimming range for the crystal battery voltage monitor. There are total of 7levels that could be frequency. This is meant to be a coarse adjustment if the range selected for the first alarm. Any of the of levels could be selected as needed is outside that of the IATR control. See Table 11. The the first alarm with no reference as to nominal Battery voltage level. IDTR0 register should only be changed while the TSE (Temp See Table9. Sense Enable) bit is “0”. TABLE 9. VB85T ALARM LEVEL The ISL12022MA has a preset Initial Digital Trimming value BATTERY ALARM TRIP corresponding to the crystal in the module. This value is recalled LEVEL on initial power-up and is READ-ONLY. It cannot be overwritten by VB85Tp2 VB85Tp1 VB85Tp0 (V) the user. 0 0 0 2.125 TABLE 11. IDTR0 TRIMMING RANGE 0 0 1 2.295 IDTR01 IDTR00 TRIMMING RANGE 0 1 0 2.550 0 0 Default/Disabled 0 1 1 2.805 0 1 +30.5ppm 1 0 0 3.060 1 0 1 4.250 1 0 0ppm 1 1 0 4.675 1 1 -30.5ppm FN7575 Rev 5.00 Page 18 of 31 September 5, 2012

ISL12022MA AGING AND INITIAL ANALOG TRIMMING BITS TABLE 13. IATRO TRIMMING RANGE (Continued) (IATR0<5:0>) TRIMMING The Initial Analog Trimming Register allows +32ppm to -31ppm IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE adjustment in 1ppm/bit increments. This enables fine frequency 1 0 0 1 0 1 -5 adjustment for trimming initial crystal accuracy error or to 1 0 0 1 1 0 -6 correct for aging drift. 1 0 0 1 1 1 -7 The ISL12022MA has a preset Initial Analog Trimming value 1 0 1 0 0 0 -8 corresponding to the crystal in the module. This value is recalled on 1 0 1 0 0 1 -9 initial power-up, is preset in device production and is READ-ONLY. It 1 0 1 0 1 0 -10 cannot be overwritten by the user. 1 0 1 0 1 1 -11 1 0 1 1 0 0 -12 TABLE 12. INITIAL AT AND DT SETTING REGISTER 1 0 1 1 0 1 -13 ADDR 7 6 5 4 3 2 1 0 1 0 1 1 1 0 -14 0Bh IDTR01 IDTR00 IATR0 IATR0 IATR03 IATR0 IATR0 IATR0 1 0 1 1 1 1 -15 5 4 2 1 0 1 1 0 0 0 0 -16 1 1 0 0 0 1 -17 TABLE 13. IATRO TRIMMING RANGE 1 1 0 0 1 0 -18 TRIMMING 1 1 0 0 1 1 -19 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE 1 1 0 1 0 0 -20 0 0 0 0 0 0 +32 1 1 0 1 0 1 -21 0 0 0 0 0 1 +31 1 1 0 1 1 0 -22 0 0 0 0 1 0 +30 1 1 0 1 1 1 -23 0 0 0 0 1 1 +29 1 1 1 0 0 0 -24 0 0 0 1 0 0 +28 1 1 1 0 0 1 -25 0 0 0 1 0 1 +27 1 1 1 0 1 0 -26 0 0 0 1 1 0 +26 1 1 1 0 1 1 -27 0 0 0 1 1 1 +25 1 1 1 1 0 0 -28 0 0 1 0 0 0 +24 1 1 1 1 0 1 -29 0 0 1 0 0 1 +23 1 1 1 1 1 0 -30 0 0 1 0 1 0 +22 1 1 1 1 1 1 -31 0 0 1 0 1 1 +21 ALPHA Register (ALPHA) 0 0 1 1 0 0 +20 0 0 1 1 0 1 +19 TABLE 14. ALPHA REGISTER 0 0 1 1 1 0 +18 ADDR 7 6 5 4 3 2 1 0 0 0 1 1 1 1 +17 0 1 0 0 0 0 +16 0Ch D ALPHA ALPHA ALPHA ALPHA ALPHA ALPHA ALPHA 6 5 4 3 2 1 0 0 1 0 0 0 1 +15 0 1 0 0 1 0 +14 0 1 0 0 1 1 +13 The ALPHA variable is 8 bits and is defined as the temperature coefficient of crystal from -40°C to T0, or the ALPHA Cold (there is 0 1 0 1 0 0 +12 an Alpha Hot register that must be programmed as well). It is 0 1 0 1 0 1 +11 normally given in units of ppm/°C2, with a typical value of -0.034. 0 1 0 1 1 0 +10 The ISL12022MA device uses a scaled version of the absolute 0 1 0 1 1 1 +9 value of this coefficient in order to get an integer value. Therefore, 0 1 1 0 0 0 +8 ALPHA <7:0> is defined as the (|Actual ALPHA Value| x 2048) and 0 1 1 0 0 1 +7 converted to binary. For example, a crystal with Alpha of - 0 1 1 0 1 0 +6 0.034ppm/°C2 is first scaled (|2048*(-0.034)| =70d) and then 0 1 1 0 1 1 +5 converted to a binary number of 01000110b. 0 1 1 1 0 0 +4 The practical range of Actual ALPHA values is from -0.020 to -0.060. 0 1 1 1 0 1 +3 0 1 1 1 1 0 +2 The ISL12022MA has a preset ALPHA value corresponding to the 0 1 1 1 1 1 +1 crystal in the module. This value is recalled on initial power-up and is preset in device production. It is READ ONLY and cannot be 1 0 0 0 0 0 0 overwritten by the user. 1 0 0 0 0 1 -1 1 0 0 0 1 0 -2 1 0 0 0 1 1 -3 1 0 0 1 0 0 -4 FN7575 Rev 5.00 Page 19 of 31 September 5, 2012

ISL12022MA BETA Register (BETA) temperature period, the average current is expressed in Equation1: TABLE 15. 0.022s I =------------------68A= 250nA (EQ. 1) BAT 60s ADDR 7 6 5 4 3 2 1 0 0Dh TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 For the 10 minute temperature period the average current is expressed in Equation 2: The BETA register has special Write properties. Only the TSE, 0.022s I =------------------68A= 25nA (EQ. 2) BTSE and BTSR bits can be written; the BETA bits are READ-ONLY. BAT 600s A write to both bytes in this register will only change the 3 MSB’s If the application has a stable temperature environment that (TSE, BTSE, BTSR), and the 5LSB’s will remain the same as set doesn’t change quickly, the 10 minute option will work well and at the factory. the backup battery lifetime impact is minimized. If quick TEMPERATURE SENSOR ENABLED BIT (TSE) temperature variations are expected (multiple cycles of more than 10° within an hour), then the 1 minute option should be This bit enables the Temperature Sensing operation, including the considered and the slightly higher battery current figured into temperature sensor, A/D converter and FATR/FDTR register overall battery life. adjustment. The default mode after power-up is disabled: (TSE = 0). To enable the operation, TSE should be set to 1. (TSE = 1). When GAIN FACTOR OF AT BIT (BETA<4:0>) temp sense is disabled, the initial values for IATR and IDTR registers are used for frequency control. Beta is specified to take care of the Cm variations of the crystal. Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF, When TSE is set to 1, the temperature conversion cycle begins and the actual AT steps may reduce from 1ppm/step to approximately will end when two temperature conversions are completed. The 0.80ppm/step. Beta is then used to adjust for this variation and average of the two conversions is in the TEMP registers. restore the step size to 1ppm/step. TEMP SENSOR CONVERSION IN BATTERY MODE BIT BETA values are limited in the range from 01000 to 11111, as shown in Table 17. To use Table 17, the device is tested at two AT (BTSE) settings as follows: This bit enables the Temperature Sensing and Correction in battery mode. BTSE = 0 (default) no conversion, Temp Sensing or BETA VALUES = (AT(max) - AT (min))/63, where: Compensation in battery mode. BTSE = 1 indicates Temp Sensing AT(max) = FOUT in ppm (at AT = 00H) and and Compensation enabled in battery mode. The BTSE is disabled when the battery voltage is lower than 2.7V. No temperature AT(min) = FOUT in ppm (at AT = 3FH). compensation will take place with VBAT<2.7V. The BETA VALUES result is indexed in the right hand column and FREQUENCY OF TEMPERATURE SENSING AND the resulting Beta factor (for the register) is in the same row in the left column. CORRECTION BIT (BTSR) This bit controls the frequency of Temp Sensing and Correction. The ISL12022MA has a preset BETA value corresponding to the BTSR = 0 default mode is every 10 minutes, BTSR = 1 is every crystal in the module. This value is recalled on initial power-up 1.0 minute. Note that BTSE has to be enabled in both cases. See and is preset in device production. It is READ ONLY and cannot Table 16. be overwritten by the user. TABLE 16. FREQUENCY OF TEMPERATURE SENSING AND TABLE 17. BETA VALUES CORRECTION BIT BETA<4:0> AT STEP ADJUSTMENT TC PERIOD IN 01000 0.5000 BTSE BTSR BATTERY MODE 00111 0.5625 0 0 Off 00110 0.6250 0 1 Off 00101 0.6875 1 0 10 Minutes 00100 0.7500 1 1 1 Minute 00011 0.8125 The temperature measurement conversion time is the same for 00010 0.8750 battery mode as for VDD mode, approximately 22ms. The battery 00001 0.9375 mode current will increase during this conversion time to typically 68µA. The average increase in battery current is much 00000 1.0000 lower than this due to the small duty cycle of the ON-time versus 10000 1.0625 OFF-time for the conversion. 10001 1.1250 To figure the average increase in battery current, we take the change in current times the duty cycle. For the 1minute 10010 1.1875 FN7575 Rev 5.00 Page 20 of 31 September 5, 2012

ISL12022MA TABLE 17. BETA VALUES (Continued) TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL TRIMMING REGISTER (Continued) BETA<4:0> AT STEP ADJUSTMENT FDTR<4:0> DECIMAL ppm ADJUSTMENT 10011 1.2500 00110 6 183 10100 1.3125 00111 7 213.5 10101 1.3750 01000 8 244 10110 1.4375 01001 9 274.5 10111 1.5000 01010 10 305 11000 1.5625 10000 0 0 11001 1.6250 10001 -1 -30.5 11010 1.6875 10010 -2 -61 11011 1.7500 10011 -3 -91.5 11100 1.8125 10100 -4 -122 11101 1.8750 10101 -5 -152.5 11110 1.9375 10110 -6 -183 11111 2.0000 10111 -7 -213.5 Final Analog Trimming Register (FATR) 11000 -8 -244 This register shows the final setting of AT after temperature 11001 -9 -274.5 correction. It is read-only; the user cannot overwrite a value to this 11010 -10 -305 register. This value is accessible as a means of monitoring the temperature compensation function. See Table 18 and Table 19 (for ALARM Registers (10h to 15h) values). The alarm register bytes are set up identical to the RTC register TABLE 18. FINAL ANALOG TRIMMING REGISTER bytes, except that the MSB of each byte functions as an enable ADDR 7 6 5 4 3 2 1 0 bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the 0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0 comparison. Note that there is no alarm byte for year. Final Digital Trimming Register (FDTR) The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm This Register shows the final setting of DT after temperature will be triggered once a match occurs between the alarm registers correction. It is read-only; the user cannot overwrite a value to and the RTC registers. Any one alarm register, multiple registers, or this register. The value is accessible as a means of monitoring all registers can be enabled for a match. the temperature compensation function. The corresponding clock adjustment values are shown in Table20. The FDTR setting There are two alarm operation modes: Single Event and periodic has both positive and negative settings to adjust for any offset in Interrupt Mode: the crystal.. •Single Event Mode is enabled by setting the Bit 7 on any of the TABLE 19. FINAL DIGITAL TRIMMING REGISTER Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time ADDR 7 6 5 4 3 2 1 0 match between the Alarm registers and the RTC registers. 0Fh 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 Once this match occurs, the ALM bit is set to “1” and the IRQ/FOUT output will be pulled low and will remain low until TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL the ALM bit is reset. This can be done manually or by using the TRIMMING REGISTER auto-reset feature. FDTR<4:0> DECIMAL ppm ADJUSTMENT •Interrupt Mode is enabled by setting the Bit 7 on any of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and 00000 0 0 disabling the frequency output. The IRQ/FOUT output will now 00001 1 30.5 be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for 00010 2 61 each occurring match of the alarm and present time. This 00011 3 91.5 mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility 00100 4 122 meter reading. 00101 5 152.5 FN7575 Rev 5.00 Page 21 of 31 September 5, 2012

ISL12022MA To clear a single event alarm, the ALM bit in the status register TABLE 21. must be set to “0” with a write. Note that if the ARST bit is set to BIT 1 (address 08h, Bit 7), the ALM bit will automatically be cleared ALARM when the status register is read. REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION Following are examples of both Single Event and periodic SCA0 1 0 1 1 0 0 0 0 B0h Seconds set to 30, Interrupt Mode alarms. enabled Example 1 MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled • Alarm set with single interrupt (IM = “0”) HRA0 0 0 0 0 0 0 0 0 00h Hours disabled • A single alarm will occur on January 1 at 11:30 a.m. DTA0 0 0 0 0 0 0 0 0 00h Date disabled • Set Alarm registers as follows: MOA0 0 0 0 0 0 0 0 0 00h Month disabled DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled BIT ALARM Once the registers are set, the following waveform will be seen at REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION IRQ/FOUT: SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled RTC AND ALARM REGISTERS ARE BOTH “30s” MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, enabled HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, 60s enabled FIGURE 15. IRQ/FOUT WAVEFORM MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared. DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled Time Stamp V to Battery Registers (TSV2B) DD The TSV2B Register bytes are identical to the RTC register bytes, After these registers are set, an alarm will be generated when the except they do not extend beyond the Month. The Time Stamp RTC advances to exactly 11:30 a.m. on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register captures the FIRST VDD to Battery Voltage transition time, and will not update upon subsequent events until cleared (only the first event to “1” and also bringing the IRQ/FOUT output low. is captured before clearing). Set CLRTS = 1 to clear this register (Add Example 2 09h, PWR_VDD register). • Pulsed interrupt once per minute (IM = “1”) Note that the time stamp registers are cleared to all “0”, • Interrupts at one minute intervals when the seconds register is including the month and day, which is different from the RTC and at 30 seconds. alarm registers (those registers default to 01h). This is the indicator that no time stamping has occurred since the last clear • Set Alarm registers as follows: or initial power-up. Once a time stamp occurs, there will be a non- zero time stamp. Time Stamp Battery to V Registers (TSB2V) DD The Time Stamp Battery to VDD Register bytes are identical to the RTC register bytes, except they do not extend beyond Month. The Time Stamp captures the LAST transition of VBAT to VDD (only the last event of a series of power-up/power-down events is retained). Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD register). TABLE 22. DST FORWARD REGISTERS ADDRESS FUNCTION 7 6 5 4 3 2 1 0 20h Month Forward DSTE 0 0 MoFd20 MoFd13 MoFd12 MoFd11 MoFd10 21h Day Forward 0 DwFdE WkFd12 WkFd11 WkFd10 DwFd12 DwFd11 DwFd10 22h Date Forward 0 0 DtFd21 DtFd20 DtFd13 DtFd12 DtFd11 DtFd10 23h Hour Forward 0 0 HrFd21 HrFd20 HrFd13 HrFd12 HrFd11 HrFd10 FN7575 Rev 5.00 Page 22 of 31 September 5, 2012

ISL12022MA TABLE 23. DST REVERSE REGISTERS ADDRESS NAME 7 6 5 4 3 2 1 0 24h Month Reverse 0 0 0 MoRv20 MoRv13 MoRv12 MoRv11 MoRv10 25h Day Reverse 0 DwRvE WkRv12 WkRv11 WkRv10 DwRv12 DwRv11 DwRv10 26h Date Reverse 0 0 DtRv21 DtRv20 DtRv13 DtRv12 DtRv11 DtRv10 27h Hour Reverse 0 0 HrRv21 HrRv20 HrRv13 HrRv12 HrRv11 HrRv10 DST Control Registers (DSTCR) DST Hour Forward 8 bytes of control registers have been assigned for the Daylight DstHrFd controls the hour that DST begins. The RTC hour and Savings Time (DST) functions. DST beginning (set Forward) time DstHrFd registers have the same formats except there is no Military is controlled by the registers DstMoFd, DstDwFd, DstDtFd, and bit for DST hour. The user sets the DST hour with the same format as DstHrFd. DST ending time (set Backward or Reverse) is controlled used for the RTC hour (AM/PM or MIL) but without the MIL bit, and by DstMoRv, DstDwRv, DstDtRv and DstHrRv. the DST will still advance as if the MIL bit were there. The default value for DST hour Forward is 00h. Tables 22 and 23 describe the structure and functions of the DSTCR. DST REVERSE REGISTERS (24H TO 27H) DST FORWARD REGISTERS (20H TO 23H) DST end (reverse) is controlled by the following DST Registers: DST forward is controlled by the following DST Registers: DST Month Reverse DST Enable DstMoRv sets the Month that DST ends. The format is the same DSTE is the DST Enabling Bit located in Bit 7 of register 20h as for the RTC register month, from 1 to 12. The default value for (DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon the DST end month is October (10h). powering up for the first time (including battery), the DSTE bit defaults to “0”. When DSTE is set to “1” the RTC time must be at DST Day/Week Reverse least one hour before the scheduled DST time change for the DstDwRv contains both the Day of the Week and the Week of the correction to take place. When DSTE is set to “0”, the DSTADJ bit Month data for DST Reverse control. DST can be controlled either by in the Status Register automatically resets to “0”. actual date or by setting both the Week of the month and the Day of the Week. DstDwRvE sets the priority of the Day/Week over the DST Month Forward Date. For DstDwRvE = 1, Day/Week is the priority. You must have DstMoFd sets the Month that DST starts. The format is the same the correct Day of Week entered in the RTC registers for the as for the RTC register month, from 1 to 12. The default value for Day/Week correction to work properly. the DST begin month is 00h. • Bits 0, 1, 2 contain the Day of the week information which sets DST Day/Week Forward the Day of the Week that DST ends. Note that Day of the week DstDwFd contains both the Day of the Week and the Week of the counts from 0 to 6, like the RTC registers. The default for the Month data for DST Forward control. DST can be controlled either DST Reverse Day of the Week is 00h (normally Sunday). by actual date or by setting both the Week of the month and the • Bits 3, 4, 5 contain the Week of the Month information that sets Day of the Week. DstDwFdE sets the priority of the Day/Week the week that DST ends. The range is from 1to 5, and Week 7 is over the Date. For DstDwFdE = 1, Day/Week is the priority. You used to indicate the last week of the month. The default for the must have the correct Day of Week entered in the RTC registers DST Reverse Week of the Month is 00h. for the Day/Week correction to work properly. DST Date Reverse • Bits 0, 1, 2 contain the Day of the week information which sets DstDtRv controls which Date DST ends. The format for the Date is the Day of the Week that DST starts. Note that Day of the week the same as for the RTC register, from 1to31. The default value counts from 0 to 6, like the RTC registers. The default for the for DST Date Reverse is 00h. The DstDtRv is only effective if the DST Forward Day of the Week is 00h (normally Sunday). DwRvE = 0. • Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST starts. The range is from 1 to 5, and Week 7 DST Hour Reverse is used to indicate the last week of the month. The default for DstHrRv controls the hour that DST ends. The RTC hour and the DST Forward Week of the Month is 00h. DstHrFd registers have the same formats except there is no Military bit for DST hour. The user sets the DST hour with the DST Date Forward same format as used for the RTC hour (AM/PM or MIL) but DstDtfd controls which Date DST begins. The format for the Date without the MIL bit, and the DST will still advance as if the MIL bit is the same as for the RTC register, from 1 to 31. The default were there. The default value for DST hour Reverse is 00h. value for DST forward date is 00h. DstDtFd is only effective if DstDwFdE = 0. TEMP Registers (TEMP) The temperature sensor produces an analog voltage output which is input to an A/D converter and produces a 10-bit FN7575 Rev 5.00 Page 23 of 31 September 5, 2012

ISL12022MA temperature value in degrees Kelvin. TK07:00 are the LSBs of the XT0 Registers (XT0) code, and TK09:08 are the MSBs of the code. The temperature result is actually the average of two successive temperature TURNOVER TEMPERATURE (XT<3:0>) measurements to produce greater resolution for the temperature The apex of the Alpha curve occurs at a point called the turnover control. The output code can be converted to °C by first temperature, or XT0. Crystals normally have a turnover converting from binary to decimal, dividing by 2, and then temperature between +20°C and +30°C, with most occurring subtracting 273d. near +25°C. Temperature in °C = [(TK <9:0>)/2] - 273 (EQ. 3) TABLE 25. TURNOVER TEMPERATURE The practical range for the temp sensor register output is from 446d ADDR 7 6 5 4 3 2 1 0 to 726d, or -50°C to +90°C. The temperature compensation function is only guaranteed over -40°C to +85°C. The TSE bit must 2Ch 0 0 0 XT4 XT3 XT2 XT1 XT0 be set to “1” to enable temperature sensing. The ISL12022MA has a preset Turnover temperature TABLE 24. corresponding to the crystal in the module. This value is recalled TEMP 7 6 5 4 3 2 1 0 on initial power-up and is preset in device production. It is READ ONLY and cannot be overwritten by the user. TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 Table 26 shows the values available, with a range from +17.5°C TK0M 0 0 0 0 0 0 TK09 TK08 to +32.5°C in +0.5°C increments. The default value is 00000b or +25°C. NPPM Registers (NPPM) TABLE 26. XT0 VALUES The NPPM value is exactly 2x the net correction, in ppm, required to bring the oscillator to 0ppm error. The value is the combination XT<4:0> TURNOVER TEMPERATURE of oscillator Initial Correction (IPPM) and crystal temperature 01111 32.5 dependent correction (CPPM). 01110 32.0 IPPM is used to compensate the oscillator offset at room temperature and is controlled by the ITR0 and BETA registers. This 01101 31.5 value is normally set during room temperature testing. 01100 31 The CPPM compensates the oscillator frequency fluctuation over- 01011 30.5 temperature. It is determined by the temperature (T), crystal 01010 30 curvature parameter (ALPHA), and crystal turnover temperature (XT0). T is the result of the temp sensor/ADC conversion, whose 01001 29.5 decimal result is 2x the actual temperature in Kelvin. ALPHA is 01000 29.0 from either the ALPHA (cold) or ALPHAH (hot) register depending on T, and XT0 is from the XT0 register. 00111 28.5 NPPM is governed by Equations 4 and 5: 00110 28.0 NPPM = IPPM(ITR0, BETA) + ALPHA x (T-T0)2 00101 27.5 NPPM = IPPM+CPPM 00100 27.0 2 NPPM = IPPM+A-----L----P----H-----A------------T-----–-----T----0-------- (EQ. 4) 00011 26.5 4096 where 00010 26.0 ALPHA = 2048 00001 25.5 T is the reading of the ADC, result is 2 x temperature in degrees 00000 25.0 Kelvin. 10000 25.0 T = 2298+XT0 (EQ. 5) 10001 24.5 or T = 596+XT0 10010 24.0 Note that NPPM can also be predicted from the FATR and FDTR 10011 23.5 register by the relationship (all values in decimal): 10100 23.0 NPPM = 2*(BETA*FATR - (FDTR-16) 10101 22.5 10110 22.0 10111 21.5 11000 21.0 FN7575 Rev 5.00 Page 24 of 31 September 5, 2012

ISL12022MA TABLE 26. XT0 VALUES (Continued) User Registers (Accessed by XT<4:0> TURNOVER TEMPERATURE Using Slave Address 1010111x) 11001 20.5 Addresses [00h to 7Fh] 11010 20.0 These registers are 128 bytes of battery-backed user SRAM. The 11011 19.5 separate I2C slave address must be used to read and write to these registers. 11100 19.0 2 11101 18.5 I C Serial Interface 11110 18.0 The ISL12022MA supports a bi-directional bus oriented protocol. 11111 17.5 The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device ALPHA Hot Register (ALPHAH) controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers TABLE 27. ALPHAH REGISTER and provides the clock for both transmit and receive operations. Therefore, the ISL12022MA operates as a slave device in all ADDR 7 6 5 4 3 2 1 0 applications. 2Dh D ALP_H ALP_H ALP_H ALP_H ALP_H ALP_H ALP_H All communication over the I2C interface is conducted by sending 6 5 4 3 2 1 0 the MSB of each byte of data first. The ALPHA Hot variable is 7 bits and is defined as the temperature Protocol Conventions coefficient of Crystal from the XT0 value to +85°C (both Alpha Hot Data states on the SDA line can change only during SCL LOW and Alpha Cold must be programmed to provide full temperature compensation). It is normally given in units of ppm/°C2, with a periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power- typical value of -0.034. Like the ALPHA Cold version, a scaled up of the ISL12022MA, the SDA pin is in the input mode. version of the absolute value of this coefficient is used in order to get an integer value. Therefore, ALP_H <7:0> is defined as the All I2C interface operations must begin with a START condition, (|Actual Alpha Hot Value| x 2048) and converted to binary. For which is a HIGH to LOW transition of SDA while SCL is HIGH. The example, a crystal with Alpha Hot of -0.034ppm/°C2 is first scaled ISL12022MA continuously monitors the SDA and SCL lines for the (|2048*(-0.034)| = 70d) and then converted to a binary number START condition and does not respond to any command until this of 01000110b. condition is met (see Figure 16). A START condition is ignored during the power-up sequence. The practical range of Actual ALPHAH values is from -0.020 to - 0.060. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is The ISL12022MA has a preset ALPHAH value corresponding to HIGH (see Figure 16). A STOP condition at the end of a read the crystal in the module. This value is recalled on initial operation or at the end of a write operation to memory only power-up and is preset in device production. It is READ ONLY and places the device in its standby mode. cannot be overwritten by the user. SCL SDA DATA DATA DATA START STOP STABLE CHANGE STABLE FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS FN7575 Rev 5.00 Page 25 of 31 September 5, 2012

ISL12022MA SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE S MASTER T S A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 1 1 0 1 1 1 1 0 0 0 0 0 SIGNALS FROM A A A THE ISL12022MA C C C K K K FIGURE 18. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN) An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master SLAVE ADDRESS 1 1 0 1 1 1 1 R/W or slave, releases the SDA bus after transmitting eight bits. BYTE During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS 17). The ISL12022MA responds with an ACK after recognition of a D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE START condition followed by a valid Identification Byte, and once again, after successful receipt of an Address Byte. The ISL12022MA also responds with an ACK after receiving a Data FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES Byte of a write operation. The master must respond with an ACK Following the Slave Byte is a one byte word address. The word after receiving a Data Byte of a read operation. address is either supplied by the master device or obtained from Device Addressing an internal counter. On power-up, the internal address counter is set to address 00h, so a current address read starts at address Following a start condition, the master must output a Slave 00h. When required, as part of a random read, the master must Address Byte. The 7 MSBs are the device identifiers. These bits supply the 1 Word Address Bytes, as shown in Figure 20. are “1101111” for the RTC registers and “1010111” for the User In a random read operation, the slave byte in the “dummy write” SRAM. portion must match the slave byte in the “read” section. For a The last bit of the Slave Address Byte defines a read or write random read of the Control/Status Registers, the slave byte must operation to be performed. When this R/W bit is a “1”, a read be “1101111x” in both places. operation is selected. A “0” selects a write operation (refer to Figure 19). Write Operation After loading the entire Slave Address Byte from the SDA bus, the A Write operation requires a START condition, followed by a valid ISL12022MA compares the device identifier and device select Identification Byte, a valid Address Byte, a Data Byte, and a STOP bits with “1101111” or “1010111”. Upon a correct compare, the condition. After each of the three bytes, the ISL12022MA device outputs an acknowledge on the SDA line. responds with an ACK. At this time, the I2C interface enters a standby state. FN7575 Rev 5.00 Page 26 of 31 September 5, 2012

ISL12022MA SIGNALS S S FROM THE T IDENTIFICATION T IDENTIFICATION S MASTER A BYTE WITH ADDRESS A BYTE WITH A A T R R/W = 0 BYTE R R/W = 1 C C O T T K K P SIGNAL AT 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 SDA A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN) Read Operation Note that the device is not guaranteed to operate with a VBAT < 1.8V, so the battery should be changed before discharging to that A Read operation consists of a three byte instruction, followed by level. It is strongly advised to monitor the low battery indicators in one or more Data Bytes (see Figure 20). The master initiates the the status registers and take action to replace discharged operation issuing the following sequence: a START, the batteries. Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit If a supercapacitor is used, it is possible that it may discharge to set to “1”. After each of the three bytes, the ISL12022MA responds below 1.8V during prolonged power-down. Once powered up, the with an ACK. Then the ISL12022MA transmits Data Bytes as long device may lose serial bus communications until both VDD and as the master responds with an ACK during the SCL cycle following VBAT are powered down together. To avoid that situation, including the eighth bit of each byte. The master terminates the read situations where a battery may discharge deeply, the circuit in operation (issuing a STOP condition) following the last bit of the Figure 21 can be used. last Data Byte (see Figure 20). The Data Bytes are from the memory location indicated by an VDD = 2.7V ISL12022MA JBAT BADTB4A3TW internal pointer. This pointer’s initial value is determined by the TO 5.5V VDD VBAT +VBAT = 1.8V TO 3.2V Address Byte in the Read operation instruction, and increments CIN CBAT by one during transmission of each Data Byte. After reaching the 0.1µF 0.1µF memory location 2Fh, the pointer “rolls over” to 00h, and the GND device continues to output data for each ACK received. Application Section FIGURE 21. SUGGESTED BATTERY BACKUP CIRCUIT Power Supply Considerations The diode, DBAT will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. The ISL12022M contains programmed EEPROM registers which are The jumper is added as a safeguard should the battery ever need recalled to volatile RAM registers during initial power-up. These to be disconnected from the circuit. registers contain DC voltage, frequency and temperature calibration settings. Initial power-up can be either application of VBAT or VDD The VDD negative slew rate should be limited to below the data power, whichever is first. It is important that the initial power-up sheet spec (10V/ms) otherwise battery switchover can be meet the power supply slew rate specification to avoid faulty delayed, resulting in SRAM contents corruption and oscillator EEPROM power-up recall. Also, any glitches or low voltage DC operation interruption. pauses should be avoided, as these may activate recall at a low Some applications will require separate supplies for the RTC VDD voltage and load erroneous data into the calibration registers. Note and the I2C pull-ups. This is not advised, as it may compromise that a very slow VDD ramp rate (outside data sheet limits) will the operation of the I2C bus. For applications that do require almost always trigger erroneous recall and should be avoided serial bus communication with the RTC VDD powered down, the entirely. SDA pin must be pulled low during the time the RTC VDD ramps Battery Backup Details down to 0V. Otherwise, the device may lose serial bus communications once VDD is powered up, and will return to The ISL12022MA has automatic switchover to battery backup normal operation ONLY once VDD and VBAT are both powered when the VDD drops below the VBAT mode threshold. A wide down together. variety of backup sources can be used, including standard and rechargeable lithium, super-capacitors, or regulated secondary Layout Considerations sources. The serial interface is disabled in battery backup, while The ISL12020M contains a quartz crystal and requires special the oscillator and RTC registers are operational. The SRAM handling during PC board assembly. Excessive shock and vibrations register contents are powered to preserve their contents as well. should be avoided. Ultrasound cleaning is not advisable. See Note 6 The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind on page6 in the electrical specifications table pertaining to solder the temperature compensation only operates for VBAT>2.7V. reflow effects on oscillator accuracy. FN7575 Rev 5.00 Page 27 of 31 September 5, 2012

ISL12022MA The part of the package from pin 4 to 6 and from pin 15 to 17 Other frequencies may be used for measurement but the error contains the crystal. Low frequency RTC crystals are known to pick calculation becomes more complex. Use the FOUT output and a up noise very easily if layout precautions are not followed, even frequency counter for the most accurate results. Also, when the embedded within a plastic package. Most instances of erratic proper layout guidelines above are observed, the oscillator clocking or large accuracy errors can be traced to the susceptibility should start-up in most circuits in less than one second. of the oscillator circuit to interference from adjacent high speed Temperature Compensation Operation clock or data lines. Careful layout of the RTC circuit will avoid noise pickup and insure accurate clocking. The ISL12022MA temperature compensation feature needs to Figure 22 shows a suggested layout for the ISL12022MA device. be enabled by the user. This must be done in a specific order as The following main precautions should be followed: follows. • Do not run the serial bus lines or any high speed logic lines in • Read register 0Dh, the BETA register. This register contains the the vicinity of pins 1 and 20, or under the package. These logic 5-bit BETA trimmed value, which is automatically loaded on level lines can induce noise in the oscillator circuit, causing initial power-up. Mask off the 5 LSB’s of the value just read. misclocking. • Bit 7 of the BETA register is the master enable control for • Add a ground trace around the device with one end terminated at temperature sense operation. Set this to “1” to allow the chip ground. This guard ring will provide termination for continuous temperature frequency correction. Frequency emitted noise in the vicinity of the RTC device correction will then happen every 60 seconds with VDD applied. • Add a 0.1µF decoupling capacitor at the device VDD pin, especially when using the 32.768kHz FOUT function. • Bits 5 and 6 of the BETA register control temperature compensation in battery backup mode (see Table 16). Set the values for the operation desired. • Write back to register 0Dh making sure not to change the 5 LSB values, and include the desired compensation control bits. Note that every time the BETA register is written with the TSE bit GROUND = 1, a temperature compensation cycle is instigated and a new RING correction value will be loaded into the FATR/FDTR registers (if the temperature changed since the last conversion). Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA registers, are READ-ONLY, and cannot be written to. Also the value for BETA is SDA locked and cannot be changed with a write. However, It is still a good idea to do the bit masking when doing TSE bit changes. SCL Daylight Savings Time (DST) Example DST involves setting the forward and back times and allowing the FOUT RTC device to automatically advance the time or set the time back. This can be done for current year, and future years. Many regions have DST rules that use standard months, weeks and FIGURE 22. SUGGESTED LAYOUT FOR THE ISL12022MA time of the day, which permit a pre-programmed, permanent The best way to run clock lines around the RTC is to stay outside setting. of the ground ring by at least a few millimeters. Also, use the Table 28 shows an example setup for the ISL12022MA. VBAT and VDD as guard ring lines as well, they can isolate clock lines from the oscillator section. In addition, if the IRQ/FOUT pin is used as a clock, it should be routed away from the RTC device as well. Measuring Oscillator Accuracy The best way to analyze the ISL12022MA frequency accuracy is to set the IRQ/FOUT pin for a specific frequency, and look at the output of that pin on a high accuracy frequency counter (at least 7 digits accuracy). Note that the IRQ/FOUT is an drain output and will require a pull-up resistor. Using the 1.0Hz output frequency is the most convenient as the ppm error is expressed in Equation 6: ppm error = F –11e6 (EQ. 6) OUT FN7575 Rev 5.00 Page 28 of 31 September 5, 2012

ISL12022MA TABLE 28. DST EXAMPLE Note that the DSTADJ bit in the status register monitors whether the DST forward adjustment has happened. When it is “1”, DST VARIABLE VALUE REGISTER VALUE forward has taken place. When it is “0”, then either DST reverse Month Forward and DST April 15h 84h has happened, or it has been reset either by initial power-up or if Enable the DSTE bit has been set to “0”. Week and Day Forward and 1st Week and 16h 48h Device Handling Precautions select Day/Week, not Date Sunday Date Forward Not used 17h 00h The ISL12022MA contains a quartz crystal and requires special handling during PC board assembly. Excessive shock and vibrations Hour Forward 2am 18h 02h should be avoided, especially with automated handling equipment Month Reverse October 19h 10h (see “Absolute Maximum Ratings” on page6 for shock and vibration). Avoid dropping onto hard surfaces, placing rubber floor Week and Day Reverse and Last Week and 1Ah 78h mats in assembly areas will greatly reduce the risk of damage. select Day/Week, not Date Sunday PCB panel routing should be monitored to avoid generating Date Reverse Not used 1Bh 00h vibrations at harmonics of the crystal frequency (32kHz). If Hour Reverse 2am 1Ch 02h possible, router speed should be adjusted to mitigate this risk. The Enable bit (DSTE) is in the Month forward register, so the BCD Ultrasound cleaning is not advisable as it subjects the crystal to value for that register is altered with the additional bit. The Week resonance and possible failure. Units subject to shock, vibration or and Day values along with Week/Day vs Date select bit is in the ultrasound may sustain crystal failures in one of many modes, all Week/Day register, so that value is also not straight BCD. Hour and of which will affect oscillator frequency accuracy or cause Month are normal BCD, but the Hour doesn’t use the MIL bit since oscillator failure. Military time PM values are already discretely different from See also Note 6 on page6 in the specifications tables, which AM/PM time PM values. The DST reverse setting utilizes the option pertains to solder reflow effects on oscillator accuracy. Note that to select the last week of the month for October, which could have overheating the package, in excess of +260° for >30 sec, will cause 4 or 5 weeks but needs to have the time change on the last damage to the crystal seal and compromise oscillator accuracy. Sunday. © Copyright Intersil Americas LLC 2010-2012. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7575 Rev 5.00 Page 29 of 31 September 5, 2012

ISL12022MA Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE August 22, 2012 FN7575.5 Corrected Pin 4 in “TYPICAL APPLICATION CIRCUIT” on page1 from "GND" to "NC" to match “Pin Configuration” and “Pin Descriptions” on page2. August 7, 2012 FN7575.4 Changed Pin 1 from GNC to GND on page2. Removed bullet left column above Figure 22 on page28 which read: "Be sure to ground pins 6 and 15 as well as pin 8 as these all insure the integrity of the device ground". May 16, 2012 FN7575.3 Added new section header “OSCILLATOR ACCURACY” on page7 Removed Min/Max of -5/5ppm for “Oscillator Stability vs Temperature” on page7. Added typ of ±2ppm Changed Min/Max for “Oscillator Initial Accuracy” on page7 from -3/+3 ppm to -2/+8ppm Added “Oscillator Accuracy after Reflow Cycle” on page7. Added notes 17, 18 cross references where required to above specs. Added note 19 to “Oscillator Stability vs Voltage” on page7. Added notes 17, 18 and 19 to end of spec table on page8. “Layout Considerations” on page27. Changed 1st sentence of 2nd paragraph from: "The part of the package that has NC pins from pin 4 to 6 and from pin 15 to 17 contains the crystal." to "The part of the package from pin 4 to 6 and from pin 15 to 17 contains the crystal." October 24, 2011 FN7575.2 • On page 1, 1st paragraph, added “Backup battery current draw is less than 1.6µA over the temperature range.” Under Features, added bullet “1.6µA Max Battery Current” • On page6, DC Operating Characteristics: for IDD1 at 5V and 3V limits, changed MAX from 7µA and 6µA to 15µA and 14µA. • On page7, Power-Down Timing: added VDDSR+ with TYP value of 0.05V/ms, with reference to Note 16. • On page8, added Note 16 for VDDSR+ • On page13, Oscillator Compensation: text deleted: "These values can be overwritten by the user although this is not suggested as the resulting temperature compensation performance will be compromised." • On page16, Oscillator Fail Bit: changed text from "Oscillator Fail Bit indicates that the oscillator has stopped." to: "Oscillator Fail Bit indicates that the oscillator has failed. The oscillator frequency is either zero or very far from the desired 32.768kHz due to failure, PC board contamination or mechanical issues." • On page16, Daylight Saving Time Change Bit (DSTADJ): removed "DSTADJ can be set to "1" for instances where the RTC device is initialized during the DST Forward period." and added "It is read-only and cannot be written. Setting time during a DST forward period will not set this bit to "1"." • On page21, Table 20, FDTR column heading changed from <2:0> to <4:0> • On page27, added “Power Supply Considerations” section. • On page27, added paragraph at beginning of Layout Considerations for handling. • On page 31, Package Outline Drawing: replaced M20.3, Rev 2, 6/15, with M20.3, Rev 3, 2/11. July 1, 2010 FN7575.1 In the “Device Handling Precautions” on page29, changed the max reflow temperature from “+280°C” to “+260°C for >30 sec” June 1, 2010 FN7575.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL12022MA To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php FN7575 Rev 5.00 Page 30 of 31 September 5, 2012

ISL12022MA Package Outline Drawing M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 10.65 0.25 (0.10) M B M 10.00 7.60 3 7.40 1 2 3 TOP VIEW 2 SEATING PLANE 1132..0600 2.65 5 1.27 2.35 0.40 0.75 x 45° 1.27 7 0.49 0.30 0.25 BSC 0.35 MAX 8° 0.25 (0.10) M C A M B S MAX 0.10 (0.004) 0.32 SIDE VIEW DETAIL "X" 0.23 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 20 0.15mm (0.006 inch) per side. (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 9. Dimensions in ( ) for reference only. TYPICAL RECOMMENDED LAND PATTERN 10. JEDEC reference drawing number: MS-013-AC. FN7575 Rev 5.00 Page 31 of 31 September 5, 2012