GaAs, pHEMT, MMIC, Low Noise Amplifier, 6 GHz to 17 GHz Data Sheet HMC903LP3E FEATURES FUNCTIONAL BLOCK DIAGRAM Low noise figure: 1.7 dB typical at 6 GHz to 16 GHz HMC903LP3E High gain: 18.5 dB typical at 6 GHz to 16 GHz NIC VDD1 VDD2 NIC Output power for 1 dB compression (P1dB): 14.5 dBm typical 6 5 4 3 1 1 1 1 at 6 GHz to 16 GHz Single-supply voltage: 3.5 V at 80 mA typical NIC 1 12 NIC Output third-order intercept (IP3): 25 dBm typical 50 Ω matched input/output GND 2 11 GND Self biased with optional bias control for I reduction DQ RFIN 3 10 RFOUT 16-lead, 3 mm × 3 mm, LFCSP package APPLICATIONS NIC 4 9 NIC Point to point radios 5 6 7 8 PMoiliintta troy amnudl tsippaocinet radios NIC VGG1 VGG2 NIC PABGCAKNSADEGE 14479-001 Test instrumentation Figure 1. GENERAL DESCRIPTION The HMC903LP3E is a self biased, gallium arsenide (GaAs), The P1dB output power of 14.5 dBm enables the LNA to function monolithic microwave integrated circuit (MMIC), pseudomorphic as a local oscillator (LO) driver for balanced, I/Q or image reject (pHEMT), low noise amplifier (LNA) with an option bias mixers. The HMC903LP3E also features an input and an output control for I reduction. It is housed in a 16-lead, 3 mm × 3 mm, that are dc blocked and internally matched to 50 Ω, making it DQ LFCSP package. The HMC903LP3E amplifier operates from 6 GHz ideal for high capacity microwave radios and video satellite to 17 GHz, providing 18.5 dB of small signal gain and 1.7 dB noise (VSAT) applications. figure in the 6 GHz to 16 GHz band, and an output IP3 of 25 dBm full band 6 GHz to 17 GHz, while requiring only 80 mA from a 3.5 V supply. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

HMC903LP3E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................5 Applications ....................................................................................... 1 Interface Schematics .....................................................................5 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Theory of Operation .........................................................................9 Revision History ............................................................................... 2 Applications Information .............................................................. 10 Specifications ..................................................................................... 3 Recommended Bias Sequence During Power Up .................. 10 6 GHz to 16 GHz Frequency Range ........................................... 3 Recommended Bias Sequence During Power Down ............ 10 16 GHz to 17 GHz Frequency Range ......................................... 3 Evaluation PCB ........................................................................... 11 Absolute Maximum Ratings ............................................................ 4 Typical Application Circuits ..................................................... 12 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 13 REVISION HISTORY 7/2017—Rev. F to Rev. G This Hittite Microwave product data sheet has been reformatted Changed HMC903 to HMC903LP3E ......................... Throughout to the styles and standards of Analog Devices, Inc. Changes to Figure 1 .......................................................................... 1 1/2017—v06.0816 (HMC903LP3E) to Rev. F Changes to RF Input Parameter, Table 3 ....................................... 4 Updated Format .................................................................. Universal Changes to Features Section, Figure 1, and General Description Section .................................................................................................1 Add Thermal Resistance Section and Table 5; Renumbered Sequentially ........................................................................................4 Changes to Figure 2 and Table 5 ...................................................... 5 Added Theory of Operation Section .............................................. 9 Added Applications Information Section ................................... 10 Updated Outline Dimensions ....................................................... 13 Added Ordering Guide .................................................................. 13 Rev. G | Page 2 of 13

Data Sheet HMC903LP3E SPECIFICATIONS T = 25°C, V = V = 3.5 V, I = 80 mA (V = V = open for normal, self biased operation), unless otherwise noted. A DD1 DD2 DQ GG1 GG2 6 GHz TO 16 GHz FREQUENCY RANGE Table 1. Parameter Min Typ Max Unit GAIN 16.5 18.5 dB Gain Variation over Temperature 0.012 dB/°C NOISE FIGURE1 1.7 2.2 dB RETURN LOSS Input 12 dB Output 12 dB OUTPUT POWER For 1 dB Compression (P1dB)1 13 14.5 dBm Saturated (P )1 16.5 dBm SAT OUTPUT THIRD-ORDER INTERCEPT (IP3) 22 25 dBm SUPPLY CURRENT (I ) 80 110 mA DQ 1 Board loss removed from gain, power, and noise figure measurements. 16 GHz TO 17 GHz FREQUENCY RANGE Table 2. Parameter Min Typ Max Unit GAIN 15 18 dB Gain Variation over Temperature 0.012 dB/°C NOISE FIGURE1 2.2 2.5 dB RETURN LOSS Input 11 dB Output 14 dB OUTPUT POWER For 1 dB Compression (P1dB)1 12 13 dBm Saturated (P )1 16.5 dBm SAT OUTPUT THIRD-ORDER INTERCEPT (IP3) 22 25 dBm SUPPLY CURRENT (I ) 80 110 mA DQ 1 Board loss removed from gain, power, and noise figure measurements. Rev. G | Page 3 of 13

HMC903LP3E Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Thermal performance is directly linked to printed circuit board Parameter Rating (PCB) design and operating environment. Careful attention to Drain Bias Voltage 4.5 V PCB thermal design is required. RF Input Power 20 dBm Gate Bias Voltage Table 4. Thermal Resistance V −0.8 V to +0.2 V GG1 Package Type1 θ Unit JC V −0.8 V to +0.2 V GG2 HCP-16-1 144.8 °C/W Continuous Power Dissipation, P (T = 0.45 W DISS A 85°C, Derate 6.9 mW/°C Above 85°C) 1 Thermal impedance simulated values are based on JEDEC 2s2p thermal test board. See JEDEC JESD51. Channel Temperature 150°C Maximum Peak Reflow Temperature 260°C ESD CAUTION Storage Temperature −65°C to +85°C Operating Temperature −40°C to +85°C ESD Sensitivity (Human Body Model) Class 0, Passed 150 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. G | Page 4 of 13

Data Sheet HMC903LP3E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NIC VDD1 VDD2 NIC 6 5 4 3 1 1 1 1 NIC 1 12 NIC GND 2 HMC903LP3E 11 GND TOP VIEW (Not to Scale) RFIN 3 10 RFOUT NIC 4 9 NIC 5 6 7 8 NIC GG1 GG2 NIC PABCAKSAEGE V V GND NOTES 1.NIC = NOT INTERNALLY CONNECTED. 2.EATXHNPA EOTX SMPEOUDSS PTEA DCD OM. NETNTHAEECL P TGA TRCOOK AURGNFDE/D PBCAO GDTRDTOOLUEMN HDA.S 14479-002 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 4, 5, 8, 9, NIC Not Internally Connected. However, all data shown was measured with these pins connected to RF/dc ground 12, 13, 16 externally. 2, 11 GND Ground. Connect these pins to RF/dc ground. See Figure 3 for the interface schematic. 3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic. 6, 7 V , V Optional Gate Controls for the Amplifier. If left open, the amplifier runs self biased at the standard current. GG1 GG2 Applying a negative voltage reduces the drain current. External capacitors are required (see Figure 24). See Figure 5 for the interface schematic. 10 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 14, 15 V , V Power Supply Voltages for the Amplifier. See assembly for the required external components (see Figure 23 and DD1 DD2 Figure 24). See Figure 7 for the interface schematic. EPAD Exposed Pad. The package bottom has an exposed metal ground paddle that must connect to RF/dc ground. INTERFACE SCHEMATICS GND RFOUT 14479-003 14479-006 Figure 3. GND Interface Schematic Figure 6. RFOUT Interface Schematic RFIN 14479-004 VVDDDD12, 14479-007 Figure 4. RFIN Interface Schematic Figure 7. VDD1 and VDD2 Interface Schematic VGG1, VGG2 14479-005 Figure 5. VGG1 and VGG2 Interface Schematic Rev. G | Page 5 of 13

HMC903LP3E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 24 +85°C +25°C 22 –40°C 15 S11 S21 20 B) S22 ESPONSE (d –55 GAIN (dB) 1168 R 14 –15 12 –253 5 7 F9REQUE1N1CY (GH13z) 15 17 19 14479-008 106 8 10FREQUE1N2CY (GHz)14 16 18 14479-011 Figure 8. Broadband Gain and Return Loss (Board Loss Removed from Gain, Figure 11. Gain vs. Frequency for Various Temperatures (Board Loss Power, and Noise Figure Measurements) vs. Frequency Removed from Gain, Power, and Noise Figure Measurements) 0 0 +85°C +85°C +25°C +25°C –40°C –40°C INPUT RETURN LOSS (dB) –––112–0505 OUTPUT RETURN LOSS (dB) –––112–0505 –256 8 10FREQUE1N2CY (GHz)14 16 18 14479-009 –256 8 10FREQUE1N2CY (GHz)14 16 18 14479-012 Figure 9. Input Return Loss vs. Frequency for Various Temperatures Figure 12. Output Return Loss vs. Frequency for Various Temperatures 6 30 +85°C +25°C –40°C 5 25 B) 4 m) SE FIGURE (d 3 TPUT IP3 (dB 2105 NOI 2 OU 10 1 +85°C +25°C –40°C 06 8 10FREQUE1N2CY (GHz)14 16 18 14479-010 56 8 10FREQUE1N2CY (GHz)14 16 18 14479-013 Figure 10. Noise Figure vs. Frequency for Various Temperatures (Board Loss Figure 13. Output Third-Order Intercept (IP3) vs. Frequency for Various Removed from Gain, Power, and Noise Figure Measurements) Temperatures Rev. G | Page 6 of 13

Data Sheet HMC903LP3E 25 25 20 20 m) 15 m) 15 B B dB (d (dAT P1 10 PS 10 5 5 +85°C +85°C +25°C +25°C –40°C –40°C 06 8 10FREQUE1N2CY (GHz)14 16 18 14479-014 06 8 10FREQUE1N2CY (GHz)14 16 18 14479-017 Figure 14. Output Power for 1 dB Compression (P1dB) vs. Frequency for Figure 17. Saturated Output Power (PSAT) vs. Frequency for Various Temperatures (Board Loss Removed from Gain, Power, and Various Temperatures (Board Loss Removed from Gain, Power, and Noise Figure Measurements) Noise Figure Measurements) 0 24 +85°C +25°C –10 –40°C 20 %) N (dB) –20 PAE ( 16 SOLATIO –30 AIN (dB), 12 RSE I m), G 8 E –40 B V d RE (UT 4 O –50 P 0 GAIN POUT PAE –606 8 10FREQUE1N2CY (GHz)14 16 18 14479-015 –4–20 –17 –14 IN–P11UT PO–W8ER (d–B5m) –2 1 4 14479-018 Figure 15. Reverse Isolation vs. Frequency for Various Temperatures Figure 18. Output Power (POUT), Gain, and Power Added Efficiency (PAE) vs. Input Power (Board Loss Removed from Gain, Power, and Noise Figure Measurements) 22 7 94 20 6 92 Bm) 18 5 B) 90 d d 1dB ( 16 4 URE ( A) 88 P GAIN G m AIN (dB), 14 NP1OdISBE FIGURE 3 NOISE FI I (DD 8864 G 12 2 82 10 1 80 8 0 3.0 VD3D.5 (V) 4.0 14479-016 78–30 –27 –24 –21 I–N1P8UT– P15OW–E1R2 (dB–m9) –6 –3 0 3 14479-019 Figure 16. Gain, Output Power for 1 dB Compression (P1dB), and Noise Figure 19. Supply Current (IDD) vs. Input Power (Board Loss Removed from Figure vs. Supply Voltage (VDD) at 12 GHz (Board Loss Removed from Gain, Gain Measurement and Data Taken at VDD1 = VDD2 = 3 V) Power, and Noise Figure Measurements) Rev. G | Page 7 of 13

HMC903LP3E Data Sheet 30 120 25 100 Bm) 20 80 d B), IP3 ( 15 60 (mA)D N (d ID AI 10 40 G 5 20 IP3 GAIN IDD 0 0 –0.7 –0.6 VG–G0.15, VGG2– G0.A4TE V–O0L.3TAGE –(0V. 2dc) –0.1 0 14479-020 Figure 20. Gain, Output Third-Order Intercept (IP3), and Supply Current (IDD) vs. VGG1, VGG2 Gate Voltage Rev. G | Page 8 of 13

Data Sheet HMC903LP3E THEORY OF OPERATION The HMC903LP3E is a gallium arsenide (GaAs), monolithic The HMC903LP3E has single-ended input and output ports microwave integrated circuit (MMIC), pseudomorphic (pHEMT), whose impedances are nominally equal to 50 Ω over the 6 GHz low noise amplifier. The HMC903LP3E amplifier uses two gain to 17 GHz frequency range. Consequently, it can directly insert stages in series, and the basic schematic of the amplifier is shown in into a 50 Ω system with no required impedance matching Figure 21, which forms a low noise amplifier operating from 6 GHz circuitry, which also means that multiple HMC903LP3E to 17 GHz with excellent noise figure performance. amplifiers can be cascaded back to back without the need for VDD1 VDD2 external matching circuitry. The input and output impedances are sufficiently stable vs. RFIN RFOUT variations in temperature and supply voltage that no impedance VGG1 VGG2 14479-021 mNoattec hthinagt icto ims cpreintiscaatli oton sius prpeqlyu vireerdy. low inductance ground Figure 21. Basic Schematic of the Amplifier connections to the GND pins and to the package base exposed pad to ensure stable operation. To achieve optimal performance from the HMC903LP3E and to prevent damage to the device, do not exceed the absolute maximum ratings. Rev. G | Page 9 of 13

HMC903LP3E Data Sheet APPLICATIONS INFORMATION Figure 22 shows the basic connections for operating the RECOMMENDED BIAS SEQUENCE DURING POWER HMC903LP3E. Both the RFIN and RFOUT ports have on-chip DOWN dc block capacitors that eliminate the need for external ac The recommended bias sequence to power down the coupling capacitors. HMC903LP3E is as follows: The HMC903LP3E has V and V optional gate bias pins. GG1 GG2 1. Turn off the RF signal. When these pins are left open, the amplifier runs in self biased 2. Decrease V and V to −2 V to achieve a typical I = GG1 GG2 DQ operation with a typical I = 80 mA, when V /V = 3.5 V. DQ DD1 DD2 0 mA. When using the V and V gate bias pins, follow the GG1 GG2 3. Decrease V and V to 0 V. DD1 DD2 recommended bias sequencing so that the amplifier is not 4. Increase V and V to 0 V. GG1 GG2 damaged. Unless otherwise noted, all measurements and data shown were RECOMMENDED BIAS SEQUENCE DURING taken using the typical application circuit (see Figure 23), with POWER UP the evaluation board (see Figure 22) and biased per the conditions The recommended bias sequence to power up the in this section. The V and V pins are connected together, DD1 DD2 HMC903LP3E is as follows: similarly the V and V pins are also connected together. GG1 GG2 1. Connect to GND. The bias conditions shown in this section are the operating 2. Set V and V to −2 V. points recommended to optimize the overall performance. GG1 GG2 3. Set V and V to 3.5 V. Operation using other bias conditions may provide DD1 DD2 4. Increase V and V to achieve a typical I = 80 mA. performance that differs from what is shown in this data sheet. GG1 GG2 DQ 5. Apply the RF signal. Decreasing the V and V levels has negligible effect on the DD1 DD2 gain and noise figure performance; however, they reduce the P1dB. This behavior is shown in Figure 8 thru Figure 20. For applications where the P1dB requirement is not stringent, the HMC903LP3E can be down biased to reduce power consumption. Rev. G | Page 10 of 13

Data Sheet HMC903LP3E EVALUATION PCB Use a sufficient number of via holes to connect the top and bottom ground planes. Mount the evaluation PCB to an The circuit board used in this application must use RF circuit appropriate heat sink. The evaluation PCB shown is available design techniques. Signal lines must have 50 Ω impedance, and from Analog Devices, Inc., upon request. the package ground leads and exposed paddle must be connected directly to the ground plane similar to that shown in Figure 22. 14479-022 Figure 22. Evaluation PCB (128395-1) Table 6. List of Materials for the Evaluation PCB Component Description J1, J2 SMA connectors J3, J4, J6 to J8 DC pins C1, C4, C7, C10 100 pF capacitors, 0402 package C2, C5, C8, C11 0.01 μF capacitors, 0402 package C3, C6, C9, C12 4.7 μF tantalum capacitors U1 HMC903LP3E amplifier PCB 128395-1 evaluation PCB; circuit board material: Rogers 4350 or Arlon 25FR Rev. G | Page 11 of 13

HMC903LP3E Data Sheet TYPICAL APPLICATION CIRCUITS VDD1 + C9 C8 C7 C10 C11 + C12 VDD2 4.7µF 0.01µF 100pF 100pF 0.01µF 4.7µF 6 5 4 3 1 1 1 1 1 12 2 11 RFIN 3 10 RFOUT 4 9 5 6 7 8 100CpF4 C1010pF 14479-023 Figure 23. Standard (Self Biased) Operation Typical Application Circuit VDD1 + C9 C8 C7 C10 C11 + C12 VDD2 4.7µF 0.01µF 100pF 100pF 0.01µF 4.7µF 6 5 4 3 1 1 1 1 1 12 2 11 RFIN 3 10 RFOUT 4 9 5 6 7 8 VGG1 + C4.67µF C0.501µF C1040pF C1010pF C0.201µF + C4.37µF VGG2 14479-024 Figure 24. Gate Control, Reduced Current Operation Typical Application Circuit Rev. G | Page 12 of 13

Data Sheet HMC903LP3E OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 3.10 0.30 3.00 SQ 0.25 PIN 1 2.90 0.20 INDICATOR PIN 1 0.50 13 16 I(NSDEEIC DAETTAOIRL AAR)EA OPTIONS BSC 12 1 EXPOSED 1.95 PAD 1.70 SQ 1.50 9 4 0.45 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.35 0.90 FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.80 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF PKG-004863 COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4. 03-15-2017-B Figure 25. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.85 mm Package Height (HCP-16-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Lead Finish Package Description Package Option Branding2 HMC903LP3E −40°C to +85°C 100% Matte Sn 16-Lead LFCSP HCP-16-1 903 XXXX HMC903LP3ETR −40°C to +85°C 100% Matte Sn 16-Lead LFCSP HCP-16-1 903 XXXX 129798-HMC903LP3E Evaluation Board 1 The HMC903LP3E is a RoHS Compliant Part. 2 The four digital lot number for the HMC903LP3E is XXXX. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14479-0-7/17(G) Rev. G | Page 13 of 13

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