3-Axis, ±2 g/±4 g/±8 g/±16 g Ultralow Power Digital MEMS Accelerometer Data Sheet ADXL344 FEATURES GENERAL DESCRIPTION Multipurpose accelerometer with 10- to 13-bit resolution for The ADXL344 is a versatile 3-axis, digital-output, low g MEMS use in a wide variety of applications accelerometer. Selectable measurement range and bandwidth and Digital output accessible via SPI (3- and 4-wire) and I2C configurable, built-in motion detection make it suitable for sensing Built-in motion detection features make tap, double-tap, acceleration in a wide variety of applications. Robustness to activity, inactivity, orientation, and free-fall detection 10,000 g of shock and a wide temperature range (−40°C to +85°C) trivial enable use of the accelerometer even in harsh environments. User-adjustable thresholds The ADXL344 measures acceleration with high resolution (13-bit) Interrupts independently mappable to two interrupt pins measurement at up to ±16 g. Digital output data is formatted as Low power operation down to 23 µA and embedded FIFO for 16-bit twos complement and is accessible through either a SPI reducing overall system power (3- or 4-wire) or I2C digital interface. The ADXL344 can Wide supply and I/O voltage range: 1.7 V to 2.75 V measure the static acceleration of gravity in tilt-sensing appli- Wide operating temperature range (−40°C to +85°C) cations, as well as dynamic acceleration resulting from motion 10,000 g shock survival or shock. Its high resolution (3.9 mg/LSB) enables measurement Small, thin Pb free, RoHS compliant 3 mm × 3 mm × 0.95 mm of inclination changes less than 1.0°. LGA package Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion. Tap APPLICATIONS sensing detects single and double taps in any direction. Free-fall Handsets sensing detects if the device is falling. Orientation detection Gaming and pointing devices reports four- and six-position orientation and can trigger an Hard disk drive (HDD) protection interrupt upon change in orientation. These functions can be mapped individually to either of two interrupt output pins. An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. The ADXL344 is supplied in a small, thin, 3 mm × 3 mm × 0.95 mm, 16-terminal, plastic package. FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL344 POWER MANAGEMENT CONTROL INT1 SENSE ADC AND ELECTRONICS DIGITAL INTERRUPT 3-AXIS FILTER LOGIC INT2 SENSOR SDA/SDI/SDIO 32-FLIEFVOEL SERIAL I/O SDO/ALT ADDRESS SCL/SCLK GND CS 10628-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.

ADXL344 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Definitions ................................................................... 21 Applications Information .............................................................. 27 Applications ....................................................................................... 1 General Description ......................................................................... 1 Power Supply Decoupling ......................................................... 27 Mechanical Considerations for Mounting .............................. 27 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Tap Detection .............................................................................. 27 Specifications ..................................................................................... 3 Improved Tap Detection............................................................ 28 Tap Sign ....................................................................................... 28 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 Threshold .................................................................................... 29 Link Mode ................................................................................... 29 Package Information .................................................................... 5 ESD Caution .................................................................................. 5 Sleep Mode vs. Low Power Mode............................................. 29 Offset Calibration ....................................................................... 29 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Using Self-Test ............................................................................ 30 Theory of Operation ...................................................................... 10 Orientation Sensing ................................................................... 31 Data Formatting of Upper Data Rates ..................................... 32 Power Sequencing ...................................................................... 10 Power Savings.............................................................................. 11 Noise Performance ..................................................................... 33 Operation at Voltages Other Than 2.6 V ................................ 33 Serial Communications ................................................................. 12 SPI ................................................................................................. 12 Offset Performance at Lowest Data Rates ............................... 34 Axes of Acceleration Sensitivity ............................................... 35 I2C ................................................................................................. 15 Interrupts ..................................................................................... 17 Layout and Design Recommendations ................................... 36 FIFO ............................................................................................. 18 Outline Dimensions ....................................................................... 37 Ordering Guide .......................................................................... 37 Self-Test ........................................................................................ 19 Register Map .................................................................................... 20 REVISION HISTORY 4/12—Revision 0: Initial Version Rev. 0 | Page 2 of 40

Data Sheet ADXL344 SPECIFICATIONS T = 25°C, V = 2.6 V, V = 1.8 V, acceleration = 0 g, C = 10 μF tantalum, C = 0.1 μF, output data rate (ODR) = 800 Hz, unless A S DD I/O S I/O otherwise noted. Table 1. Parameter Test Conditions/Comments Min1 Typ2 Max1 Unit SENSOR INPUT Each axis Measurement Range User selectable ±2, ±4, ±8, ±16 g Nonlinearity Percentage of full scale ±0.5 % Inter-Axis Alignment Error ±0.1 Degrees Cross-Axis Sensitivity3 ±1 % OUTPUT RESOLUTION Each axis All g Ranges 10-bit resolution 10 Bits ±2 g Range Full resolution 10 Bits ±4 g Range Full resolution 11 Bits ±8 g Range Full resolution 12 Bits ±16 g Range Full resolution 13 Bits SENSITIVITY Each axis Sensitivity at X , Y , Z All g ranges, full resolution 256 LSB/g OUT OUT OUT ±2 g, 10-bit resolution 256 LSB/g ±4 g, 10-bit resolution 128 LSB/g ±8 g, 10-bit resolution 64 LSB/g ±16 g, 10-bit resolution 32 LSB/g Sensitivity Deviation from Ideal All g ranges ±1.0 % Scale Factor at X , Y , Z All g ranges, full resolution 3.9 mg/LSB OUT OUT OUT ±2 g, 10-bit resolution 3.9 mg/LSB ±4 g, 10-bit resolution 7.8 mg/LSB ±8 g, 10-bit resolution 15.6 mg/LSB ±16 g, 10-bit resolution 31.2 mg/LSB Sensitivity Change Due to Temperature ±0.02 %/°C 0 g OFFSET Each axis 0 g Output Deviation from Ideal for X-, Y-, Z-Axes ±35 mg 0 g Offset vs. Temperature for X-, Y-, Z-Axes ±1.0 mg/°C NOISE X-, Y-, Z-Axes ODR = 100 Hz for ±2 g, 10-bit 1.5 LSB rms resolution or all g ranges, full resolution OUTPUT DATA RATE AND BANDWIDTH User selectable Output Data Rate (ODR)4, 5, 6, 7 0.10 3200 Hz SELF-TEST8 Output Change in X-Axis 0.27 1.55 g Output Change in Y-Axis −1.55 −0.27 g Output Change in Z-Axis 0.40 1.95 g POWER SUPPLY Operating Voltage Range (V) 1.7 2.6 2.75 V S Interface Voltage Range (V ) 1.7 1.8 V V DD I/O S Measurement Mode Supply Current ODR ≥ 100 Hz 140 µA ODR < 10 Hz 30 µA Standby Mode Supply Current 0.2 µA Turn-On and Wake-Up Time9 ODR = 3200 Hz 1.4 ms Rev. 0 | Page 3 of 40

ADXL344 Data Sheet Parameter Test Conditions/Comments Min1 Typ2 Max1 Unit TEMPERATURE Operating Temperature Range −40 +85 °C WEIGHT Device Weight 18 mg 1 All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. 2 The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean ±1 σ except for 0 g output and sensitivity, which represents the target value. For 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean ±1 σ. 3 Cross-axis sensitivity is defined as coupling between any two axes. 4 Bandwidth is the −3 dB frequency and is half the output data rate bandwidth = ODR/2. 5 The output format for the 3200 Hz and 1600 Hz ODRs is different from the output format for the remaining ODRs. This difference is described in the Data Formatting of Upper Data Rates section. 6 Output data rates below 6.25 Hz exhibit additional offset shift with increased temperature, depending on selected output data rate. Refer to the Offset Performance at Lowest Data Rates section for details. 7 These are typical values for the lowest and highest output data rate settings. 8 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit = 0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). The part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) for self-test to operate correctly. 9 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate). Rev. 0 | Page 4 of 40

Data Sheet ADXL344 ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Table 2. Parameter Rating The information in Figure 2 and Table 4 provide details about Acceleration the package branding for the ADXL344. For a complete listing Any Axis, Unpowered 10,000 g of product availability, see the Ordering Guide section. Any Axis, Powered 10,000 g V −0.3 V to +3.0 V S V −0.3 V to +3.0 V Y4S DD I/O Digital Pins −0.3 V to V + 0.3 V or DD I/O 3.0 V, whichever is less All Other Pins −0.3 V to +3.0 V vvvv Output Short-Circuit Duration Indefinite Tem(Apneyr aPtinu rteo R Garnoguen d) 10628-047 Figure 2. Product Information on Package (Top View) Powered −40°C to +105°C Storage −40°C to +105°C Table 4. Package Branding Information Branding Key Field Description Y4S Part identifier for the ADXL344 Stresses above those listed under Absolute Maximum Ratings vvvv Factory lot code may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational ESD CAUTION section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 3. Package Characteristics Package Type θ θ Device Weight JA JC 16-Terminal LGA 150°C/W 85°C/W 18 mg Rev. 0 | Page 5 of 40

ADXL344 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D E V R D ES NG ER VS 16 15 14 VDD I/O 1 13 GND ADXL344 NC 2 12 GND +X NC 3 11 INT1 SCL/SCLK 4 +Y 10 NC +Z NC 5 9 INT2 6 7 8 ODISI/DS/ADS /ODSSSERDDA TLA SC TOP VIEW N1.O NTCE S= NO INTERNAL(N CoOt NtoN SEcCaTleIO)N. 10628-002 Figure 3. Pin Configuration (Top View) Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 V Digital Interface Supply Voltage. DD I/O 2 NC Not Internally Connected. 3 NC Not Internally Connected. 4 SCL/SCLK Serial Communications Clock. 5 NC Not Internally Connected. 6 SDA/SDI/SDIO Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire). 7 SDO/ALT ADDRESS Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C). 8 CS Chip Select. 9 INT2 Interrupt 2 Output. 10 NC Not Internally Connected. 11 INT1 Interrupt 1 Output. 12 GND Must be connected to ground. 13 GND Must be connected to ground. 14 V Supply Voltage. S 15 RESERVED Reserved. This pin must be connected to V. S 16 GND Must be connected to ground. Rev. 0 | Page 6 of 40

Data Sheet ADXL344 TYPICAL PERFORMANCE CHARACTERISTICS 30 250 200 25 %) 150 TION ( 20 T (mg) 100 A E L S 50 U F P F F PO 15 Og O 0 T O ER –50 CEN 10 Z –100 R E P –150 5 –200 0–150 –100 –5Z0EROgOF0FSET (mg50) 100 150 10628-006 –250–40 –20 0 TEM2P0ERATUR4E0 (°C) 60 80 100 10628-013 Figure 4. Zero g Offset at 25°C, VS = 2.6 V, All Axes Figure 7. X-Axis Zero g Offset vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V 30 250 200 25 %) 150 TION ( 20 T (mg) 100 A E L S 50 U F P F F PO 15 Og O 0 T O ER –50 CEN 10 Z –100 R E P –150 5 –200 0–150 –100 –5Z0EROgOF0FSET (mg50) 100 150 10628-105 –250–40 –20 0 TEM2P0ERATUR4E0 (°C) 60 80 100 10628-014 Figure 5. Zero g Offset at 25°C, VS = 1.8 V, All Axes Figure 8. Y-Axis Zero g Offset vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V 60 250 200 50 %) 150 TION ( 40 T (mg) 100 A E L S 50 U F P F T OF PO 30 EROg O –500 CEN 20 Z –100 R E P –150 10 –200 0 –3 ZEROg OFF–S2ET TEMPERA–T1URE COEFFIC0IENT (mg/°C) 1 10628-012 –250–40 –20 0 TEM2P0ERATUR4E0 (°C) 60 80 100 10628-015 Figure 6. Zero g Offset Temperature Coefficient, VS = 2.6 V, All Axes Figure 9. Z-Axis Zero g Offset vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V Rev. 0 | Page 7 of 40

ADXL344 Data Sheet 60 280 275 50 %) 270 N ( CENT OF POPULATIO 342000 SENSITIVITY (LSB/g) 222224556650505 R E P 240 10 235 0230 240 SE25N0SITIVITY 2(L6S0B/g) 270 280 10628-018 230–40 –20 0 TEM2P0ERATUR4E0 (°C) 60 80 100 10628-025 Figure 10. Sensitivity at 25°C, VS = 2.6 V, Full Resolution, All Axes Figure 13. X-Axis Sensitivity vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution 60 280 275 50 %) 270 N ( CENT OF POPULATIO 342000 SENSITIVITY (LSB/g) 222224556650505 R E P 240 10 235 0230 240 SE25N0SITIVITY 2(L6S0B/g) 270 280 10628-116 230–40 –20 0 TEM2P0ERATUR4E0 (°C) 60 80 100 10628-026 Figure 11. Sensitivity at 25°C, VS = 1.8 V, Full Resolution, All Axes Figure 14. Y-Axis Sensitivity vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution 100 280 90 275 %)80 270 ON (70 g) 265 TI B/ PULA60 Y (LS 260 PO50 VIT 255 T OF 40 NSITI 250 N E CE30 S 245 R E P20 240 10 235 0–0.10SENSITIVI–T0Y. 0T5EMPERATUR0E COEFFICIE0N.T05 (%/°C) 0.10 10628-024 230–40 –20 0 TEM2P0ERATUR4E0 (°C) 60 80 100 10628-127 Figure 12. Sensitivity Temperature Coefficient, VS = 2.6 V, All Axes Figure 15. Z-Axis Sensitivity vs. Temperature— Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution Rev. 0 | Page 8 of 40

Data Sheet ADXL344 40 40 35 35 %) %) N ( 30 N (30 O O TI TI A 25 A25 L L U U P P PO 20 PO20 F F O O T 15 T 15 N N E E C C ER 10 ER10 P P 5 5 0 0.5 0.6 SEL0F.7-TEST SHI0F.8T (g) 0.9 1.0 10628-007 0 90 100 110 O12U0TPU1T3 0CUR1R4E0NT (1µ5A0) 160 170 180 10628-019 Figure 16. X-Axis Self-Test Response at 25°C, VS = 2.6 V Figure 19. Supply Current at 25°C, 100 Hz Output Data Rate, VS = 2.6 V 40 160 35 140 %) LATION ( 2350 NT (µA)110200 U E P R PO 20 UR 80 OF Y C ERCENT 1105 SUPPL 4600 P 5 20 0–1.0 –0.9 SE–L0F.8-TEST SH–I0F.T7 (g) –0.6 –0.5 10628-008 0 3.13 6.25 12.50 O25UTPU50T DA1T00A R2A0T0E (4H0z0) 800 1600 3200 10628-020 Figure 17. Y-Axis Self-Test Response at 25°C, VS = 2.6 V Figure 20. Supply Current vs. Output Data Rate at 25°C—10 Parts, VS = 2.6 V 40 150 35 A) %) N (µ140 N ( 30 TIO O P ATI 25 UM130 L S U N P O F PO 20 NT C120 O E CENT 15 CURR110 ER 10 LY P P UP100 5 S 0 1.0 1.1 SEL1.F2-TEST SHI1F.3T (g) 1.4 1.5 10628-009 901.6 1.8 S2U.P0PLY VO2L.T2AGE, VS2 .(4V) 2.6 2.8 10628-021 Figure 18. Z-Axis Self-Test Response at 25°C, VS = 2.6 V Figure 21. Supply Current vs. Supply Voltage at 25°C Rev. 0 | Page 9 of 40

ADXL344 Data Sheet THEORY OF OPERATION The ADXL344 is a complete 3-axis acceleration measurement POWER SEQUENCING system with a selectable measurement range of ±2 g, ±4 g, ±8 g, Power can be applied to V or V in any sequence without S DD I/O or ±16 g. It measures both dynamic acceleration resulting from damaging the ADXL344. All possible power-on modes are motion or shock and static acceleration, such as gravity, which summarized in Table 6. The interface voltage level is set with allows the device to be used as a tilt sensor. the interface supply voltage, V , which must be present to DD I/O The sensor is a polysilicon surface-micromachined structure ensure that the ADXL344 does not create a conflict on the built on top of a silicon wafer. Polysilicon springs suspend the communication bus. For single-supply operation, V can be DD I/O structure over the surface of the wafer and provide a resistance the same as the main supply, V. In a dual-supply application, S against forces due to applied acceleration. however, V can differ from V to accommodate the desired DD I/O S interface voltage, as long as V is greater than or equal to V . Deflection of the structure is measured using differential capacitors S DD I/O that consist of independent fixed plates and plates attached to the After V is applied, the device enters standby mode, where power S moving mass. Acceleration deflects the proof mass and unbalances consumption is minimized and the device waits for V to be DD I/O the differential capacitor, resulting in a sensor output with an applied and for the command to enter measurement mode to be amplitude proportional to acceleration. Phase-sensitive de- received. (This command can be initiated by setting the measure modulation is used to determine the magnitude and polarity bit (Bit D3) in the POWER_CTL register (Address 0x2D).) In of the acceleration. addition, any register can be written to or read from to configure the part while the device is in standby mode. It is recommended to configure the device in standby mode and then to enable measurement mode. Clearing the measure bit returns the device to the standby mode. Table 6. Power Sequencing Condition V V Description S DD I/O Power Off Off Off The device is completely off, but there is a potential for a communication bus conflict. Bus Disabled On Off The device is on in standby mode, but communication is unavailable and will create a conflict on the communication bus. The duration of this state should be minimized during power-up to prevent a conflict. Bus Enabled Off On No functions are available, but the device will not create a conflict on the communication bus. Standby or On On At power-up, the device is in standby mode, awaiting a command to Measurement Mode enter measurement mode, and all sensor functions are off. After the device is instructed to enter measurement mode, all sensor functions are available. Rev. 0 | Page 10 of 40

Data Sheet ADXL344 POWER SAVINGS Table 8. Typical Current Consumption vs. Data Rate, Low Power Modes Power Mode (T = 25°C, V = 2.6 V, V = 1.8 V) A S DD I/O The ADXL344 automatically modulates its power consumption Output Data Rate (Hz) Bandwidth (Hz) Rate Code I (µA) in proportion to its output data rate, as outlined in Table 7. If DD 400 200 1100 90 additional power savings is desired, a lower power mode is 200 100 1011 55 available. In this mode, the internal sampling rate is reduced, 100 50 1010 40 allowing for power savings in the 12.5 Hz to 400 Hz data rate 50 25 1001 31 range at the expense of slightly greater noise. To enter low 25 12.5 1000 27 power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE 12.5 6.25 0111 23 register (Address 0x2C). The current consumption in low power mode is shown in Table 8 for cases where there is an advantage to using low power mode. Use of low power mode for a data Autosleep Mode rate not shown in Table 8 does not provide any advantage over Additional power can be saved if the ADXL344 automatically the same data rate in normal power mode. Therefore, it is switches to sleep mode during periods of inactivity. To enable recommended that only data rates listed in Table 8 be used in this feature, set the THRESH_INACT register (Address 0x25) low power mode. The current consumption values shown in and the TIME_INACT register (Address 0x26) each to a value Table 7 and Table 8 are for a V of 2.6 V. S that signifies inactivity (the appropriate value depends on the application), and then set the AUTO_SLEEP bit (Bit D4) and the Table 7. Typical Current Consumption vs. Data Rate link bit (Bit D5) in the POWER_CTL register (Address 0x2D). (T = 25°C, V = 2.6 V, V = 1.8 V) A S DD I/O Current consumption at the sub-8 Hz data rates used in this Output Data mode is typically 23 µA for a V of 2.6 V. Rate (Hz) Bandwidth (Hz) Rate Code IDD (µA) S 3200 1600 1111 140 Standby Mode 1600 800 1110 90 For even lower power operation, standby mode can be used. 800 400 1101 140 In standby mode, current consumption is reduced to 0.2 µA 400 200 1100 140 (typical). In this mode, no measurements are made. Standby mode 200 100 1011 140 is entered by clearing the measure bit (Bit D3) in the 100 50 1010 140 POWER_CTL register (Address 0x2D). Placing the device into 50 25 1001 90 standby mode preserves the contents of FIFO. 25 12.5 1000 55 12.5 6.25 0111 40 6.25 3.13 0110 31 3.13 1.56 0101 27 1.56 0.78 0100 23 0.78 0.39 0011 23 0.39 0.20 0010 23 0.20 0.10 0001 23 0.10 0.05 0000 23 Rev. 0 | Page 11 of 40

ADXL344 Data Sheet SERIAL COMMUNICATIONS I2C and SPI digital communications are available. In both cases, (MB in Figure 25 to Figure 27), must be set. After the register the ADXL344 operates as a slave. I2C mode is enabled if the CS pin addressing and the first byte of data, each subsequent set of is tied high to V . The CS pin should always be tied high to clock pulses (eight clock pulses) causes the ADXL344 to point DD I/O V or be driven by an external controller because there is no to the next register for a read or write. This shifting continues DD I/O default mode if the CS pin is left unconnected. Therefore, not until the clock pulses cease and CS is deasserted. To perform reads taking these precautions may result in an inability to communicate or writes on different, nonsequential registers, CS must be with the part. In SPI mode, the CS pin is controlled by the bus deasserted between transmissions and the new register must be master. In both SPI and I2C modes of operation, data transmitted addressed separately. from the ADXL344 to the master device should be ignored during The timing diagram for 3-wire SPI reads or writes is shown in writes to the ADXL344. Figure 27. The 4-wire equivalents for SPI writes and reads are SPI shown in Figure 25 and Figure 26, respectively. For correct operation of the part, the logic thresholds and timing parameters For SPI, either 3- or 4-wire configuration is possible, as shown in in Table 9 and Table 10 must be met at all times. the connection diagrams in Figure 22 and Figure 23. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) Use of the 3200 Hz and 1600 Hz output data rates is only selects 4-wire mode, whereas setting the SPI bit selects 3-wire recommended with SPI communication rates greater than or mode. The maximum SPI clock speed is 5 MHz with 100 pF equal to 2 MHz. The 800 Hz output data rate is recommended maximum loading, and the timing scheme follows clock polarity only for communication speeds greater than or equal to 400 kHz, (CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to and the remaining data rates scale proportionally. For example, the ADXL344 before the clock polarity and phase of the host the minimum recommended communication speed for a 200 Hz processor are configured, the CS pin should be brought high output data rate is 100 kHz. Operation at an output data rate above the recommended maximum may result in undesirable before changing the clock polarity and phase. When using 3-wire effects on the acceleration data, including missing samples or SPI, it is recommended that the SDO pin be either pulled up to additional noise. V or pulled down to GND via a 10 kΩ resistor. DD I/O Preventing Bus Traffic Errors ADXL344 PROCESSOR The ADXL344 CS pin is used both for initiating SPI CS CS transactions and for enabling I2C mode. When the ADXL344 SDIO MOSI SSCDLOK MSCISLOK 10628-027 hisi guhse wdh oinle at hSeP Im bausste wr ictohm mmuultnipiclea tdeesv wicieths, tihtse CoSth peirn d ies vhiceelds. Figure 22. 3-Wire SPI Connection Diagram There may be conditions where a SPI command transmitted to another device looks like a valid I2C command. In this case, the ADXL344 interprets this as an attempt to communicate in I2C mode, and may interfere with other bus traffic. Unless bus ADXL344 PROCESSOR traffic can be adequately controlled to assure such a condition CS CS never occurs, it is recommended to add a logic gate in front of SDI MOSI SSCDLOK MSCISLOK 10628-028 tlihnee ShDigIh p iwnh aesn s ChoSw isn h iing hF itgou prer e2v4e.n Tt hSiPs IO bRu sg tartaef fhioc ladts t thhee SDI Figure 23. 4-Wire SPI Connection Diagram ADXL344 from appearing as an I2C start command. Note that this recommendation applies only in cases where the ADXL344 CS is the serial port enable line and is controlled by the SPI is used on a SPI bus with multiple devices. master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 25. SCLK ADXL344 PROCESSOR is the serial port clock and is supplied by the SPI master. SCLK CS CS should idle high during a period of no transmission. SDI and SDI MOSI SuDpdOa taerde othne t hseer fiaalll dinagta e idngpeu ot fa SnCdL oKu tapnudt, srheospueldc tbivee slya.m Dpaltead ios n SSCDLOK MSCISLOK 10628-236 the rising edge of SCLK. Figure 24. Recommended SPI Connection Diagram when Using Multiple SPI Devices on a Single Bus To read or write multiple bytes in a single transmission, the multiple-byte bit, located after the R/W bit in the first byte transfer Rev. 0 | Page 12 of 40

Data Sheet ADXL344 CS tDELAY tSCLK tM tS tQUIET tCS,DIS SCLK tSETUP tHOLD SDI W MB A5 A0 D7 D0 tSDO ADDRESS BITS DATA BITS tDIS SDO X X X X X X 10628-129 Figure 25. SPI 4-Wire Write CS tDELAY tSCLK tM tS tQUIET tCS,DIS SCLK tSETUP tHOLD SDI R MB A5 A0 X X tSDO ADDRESS BITS tDIS SDO X X X X D7 D0 DATA BITS 10628-130 Figure 26. SPI 4-Wire Read CS tDELAY tSCLK tM tS tQUIET tCS,DIS SCLK tSETUP tHOLD tSDO SDIO R/W MB A5 A0 D7 D0 ADDRESS BITS DATA BITS SDO N1.OtTSDEOS IS ONLY PRESENT DURING READS. 10628-131 Figure 27. SPI 3-Wire Read/Write Rev. 0 | Page 13 of 40

ADXL344 Data Sheet Table 9. SPI Digital Input/Output Limit1 Parameter Test Conditions Min Max Unit Digital Input Low Level Input Voltage (V ) 0.3 × V V IL DD I/O High Level Input Voltage (V ) 0.7 × V V IH DD I/O Low Level Input Current (I ) V = V 0.1 µA IL IN DD I/O High Level Input Current (I ) V = 0 V −0.1 µA IH IN Digital Output Low Level Output Voltage (V ) I = 10 mA 0.2 × V V OL OL DD I/O High Level Output Voltage (V ) I = −4 mA 0.8 × V V OH OH DD I/O Low Level Output Current (I ) V = V 10 mA OL OL OL, max High Level Output Current (I ) V = V −4 mA OH OH OH, min Pin Capacitance f = 1 MHz, V = 2.6 V 8 pF IN IN 1 Limits are based on characterization results; not production tested. Table 10. SPI Timing (T = 25°C, V = 2.6 V, V = 1.8 V)1 A S DD I/O Limit2, 3 Parameter Min Max Unit Description f 5 MHz SPI clock frequency SCLK t 200 ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40 SCLK tDELAY 5 ns CS falling edge to SCLK falling edge tQUIET 5 ns SCLK rising edge to CS rising edge tDIS 10 ns CS rising edge to SDO disabled tCS,DIS 150 ns CS deassertion between SPI communications t 0.3 × t ns SCLK low pulse width (space) S SCLK t 0.3 × t ns SCLK high pulse width (mark) M SCLK t 5 ns SDI valid before SCLK rising edge SETUP t 5 ns SDI valid after SCLK rising edge HOLD t 40 ns SCLK falling edge to SDO/SDIO output transition SDO t 4 20 ns SDO/SDIO output low to output high transition R t4 20 ns SDO/SDIO output high to output low transition F 1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. 2 Limits are based on characterization results; not production tested. 3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9. 4 Output rise and fall times are measured with a capacitive load of 150 pF. Rev. 0 | Page 14 of 40

Data Sheet ADXL344 I2C Due to communication speed limitations, the maximum output data rate when using 400 kHz I2C is 800 Hz and scales linearly with With CS tied high to V , the ADXL344 is in I2C mode, DD I/O a change in the I2C communication speed. For example, using I2C requiring a simple 2-wire connection as shown in Figure 28. at 100 kHz limits the maximum ODR to 200 Hz. Operation at an The ADXL344 conforms to the UM10204 I2C-Bus Specification output data rate above the recommended maximum may result and User Manual, Rev. 03—19 June 2007, available from NXP in an undesirable effect on the acceleration data, including Semiconductor. It supports standard (100 kHz) and fast (400 kHz) missing samples or additional noise. data transfer modes if the bus parameters given in Table 11 and Table 12 are met. Single- or multiple-byte reads/writes are sup- VDD I/O ported, as shown in Figure 29. With the ALT ADDRESS pin (Pin 7) high, the 7-bit I2C address for the device is 0x1D, followed ADXL344 RP RP PROCESSOR by the R/W bit. This translates to 0x3A for a write and 0x3B for CS a read. An alternate I2C address of 0x53 (followed by the R/W SDA D IN/OUT bit) can be chosen by grounding the ALT ADDRESS pin. This ALT ADDRESS tTrhanersela ateres tnoo 0 ixnAte6r nfoalr pau wllr-iutep aonrd p 0uxllA-d7o fworn ar erseiasdto. r s for any SCL D OUT 10628-032 Figure 28. I2C Connection Diagram (Address 0x53) unused pins; therefore, there is no known state or default state for the CS or ALT ADDRESS pin if left floating or unconnected. If other devices are connected to the same I2C bus, the nominal It is required that the CS pin be connected to VDD I/O and that operating voltage level of these other devices cannot exceed VDD I/O the ALT ADDRESS pin be connected to either VDD I/O or GND by more than 0.3 V. External pull-up resistors, RP, are necessary for when using I2C. proper I2C operation. Refer to the UM10204 I2C-Bus Specification and User Manual, Rev. 03—19 June 2007, when selecting pull-up resistor values to ensure proper operation. Table 11. I2C Digital Input/Output Limit1 Parameter Test Conditions Min Max Unit Digital Input Low Level Input Voltage (V ) 0.3 × V V IL DD I/O High Level Input Voltage (V ) 0.7 × V V IH DD I/O Low Level Input Current (I ) V = V 0.1 µA IL IN DD I/O High Level Input Current (I ) V = 0 V −0.1 µA IH IN Digital Output Low Level Output Voltage (V ) V < 2 V, I = 3 mA 0.2 × V V OL DD I/O OL DD I/O V ≥ 2 V, I = 3 mA 400 mV DD I/O OL Low Level Output Current (I ) V = V 3 mA OL OL OL, max Pin Capacitance f = 1 MHz, V = 2.6 V 8 pF IN IN 1 Limits are based on characterization results; not production tested. SINGLE-BYTE WRITE MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA STOP SLAVE ACK ACK ACK MULTIPLE-BYTE WRITE MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA DATA STOP SLAVE ACK ACK ACK ACK SINGLE-BYTE READ MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START1 SLAVE ADDRESS + READ NACK STOP SLAVE ACK ACK ACK DATA MULTIPLE-BYTE READ MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START1 SLAVE ADDRESS + READ ACK NACK STOP SLAVE ACK ACK ACK DATA DATA 1THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START. N1.O TTHEES SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. 10628-033 Figure 29. I2C Device Addressing Rev. 0 | Page 15 of 40

ADXL344 Data Sheet Table 12. I2C Timing (T = 25°C, V = 2.6 V, V = 1.8 V) A S DD I/O Limit1, 2 Parameter Min Max Unit Description f 400 kHz SCL clock frequency SCL t 2.5 µs SCL cycle time 1 t 0.6 µs t , SCL high time 2 HIGH t 1.3 µs t , SCL low time 3 LOW t 0.6 µs t , start/repeated start condition hold time 4 HD, STA t 100 ns t , data setup time 5 SU, DAT t 3, 4, 5, 6 0 0.9 µs t , data hold time 6 HD, DAT t 0.6 µs t , setup time for repeated start 7 SU, STA t 0.6 µs t , stop condition setup time 8 SU, STO t 1.3 µs t , bus-free time between a stop condition and a start condition 9 BUF t 300 ns t , rise time of both SCL and SDA when receiving 10 R 0 ns t , rise time of both SCL and SDA when receiving or transmitting R t 300 ns t, fall time of SDA when receiving 11 F 250 ns t, fall time of both SCL and SDA when transmitting F C 400 pF Capacitive load for each bus line B 1 Limits are based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. 2 All values referred to the VIH and the VIL levels given in Table 11. 3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge. 4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH,min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min). SDA t9 t3 t10 t11 t4 SCL t4 t6 t2 t5 t7 t1 t8 COSNTDAIRTTION CROESPNTEDAAIRTTTIEODN COSNTDOITPION 10628-034 Figure 30. I2C Timing Diagram Rev. 0 | Page 16 of 40

Data Sheet ADXL344 DOUBLE_TAP Bit INTERRUPTS The DOUBLE_TAP bit is set when two acceleration events The ADXL344 provides two output pins for driving interrupts: that are greater than the value in the THRESH_TAP register INT1 and INT2. Both interrupt pins are push-pull, low impedance (Address 0x1D) occur for less time than is specified in the DUR pins with the output specifications listed in Table 13. The default register (Address 0x21). The second tap starts after the time configuration of the interrupt pins is active high. This can be specified by the latent register (Address 0x22) but within the changed to active low by setting the INT_INVERT bit (Bit D5) time specified in the window register (Address 0x23). See the Tap in the DATA_FORMAT (Address 0x31) register. All functions Detection section for more details. can be used simultaneously, with the only limiting feature being that some functions may need to share interrupt pins. Activity Bit Interrupts are enabled by setting the appropriate bit in the The activity bit is set when acceleration greater than the value stored INT_ENABLE register (Address 0x2E) and are mapped to either in the THRESH_ACT register (Address 0x24) is experienced on the INT1 or INT2 pin based on the contents of the INT_MAP any participating axis, as set by the ACT_INACT_CTL register register (Address 0x2F). When initially configuring the interrupt (Address 0x27). pins, it is recommended that the functions and interrupt mapping Inactivity Bit be done before enabling the interrupts. When changing the con- The inactivity bit is set when acceleration of less than the figuration of an interrupt, it is recommended that the interrupt be value stored in the THRESH_INACT register (Address 0x25) is disabled first, by clearing the bit corresponding to that function in experienced for more time than is specified in the TIME_INACT the INT_ENABLE register, and then the function be reconfigured register (Address 0x26) on all participating axes, as set by the before enabling the interrupt again. Configuration of the functions ACT_INACT_CTL register (Address 0x27). The maximum value while the interrupts are disabled helps to prevent the accidental for TIME_INACT is 255 sec. generation of an interrupt before it is desired. FREE_FALL Bit The interrupt functions are latched and cleared by either reading the DATAX, DATAY, and DATAZ registers (Address 0x32 to The FREE_FALL bit is set when acceleration of less than the Address 0x37) until the interrupt condition is no longer valid value stored in the THRESH_FF register (Address 0x28) is for the data-related interrupts or by reading the INT_SOURCE experienced for more time than is specified in the TIME_FF register (Address 0x30) for the remaining interrupts. This section register (Address 0x29) on all axes (logical AND). The FREE_FALL describes the interrupts that can be set in the INT_ENABLE interrupt differs from the inactivity interrupt as follows: all axes register and monitored in the INT_SOURCE register. always participate and are logically AND’ed, the timer period is much smaller (1.28 sec maximum), and the mode of operation is DATA_READY Bit always dc-coupled. The DATA_READY bit is set when new data is available and is Watermark Bit cleared when no new data is available. The watermark bit is set when the number of samples in FIFO SINGLE_TAP Bit equals the value stored in the samples bits (Register FIFO_CTL, The SINGLE_TAP bit is set when a single acceleration event Address 0x38). The watermark bit is cleared automatically when that is greater than the value in the THRESH_TAP register FIFO is read, and the content returns to a value below the value (Address 0x1D) occurs for less time than is specified in stored in the samples bits. the DUR register (Address 0x21). Table 13. Interrupt Pin Digital Output Limit1 Parameter Test Conditions Min Max Unit Digital Output Low Level Output Voltage (V ) I = 300 µA 0.2 × V V OL OL DD I/O High Level Output Voltage (V ) I = −150 µA 0.8 × V V OH OH DD I/O Low Level Output Current (I ) V = V 300 µA OL OL OL, max High Level Output Current (I ) V = V −150 µA OH OH OH, min Pin Capacitance f = 1 MHz, V = 2.6 V 8 pF IN IN Rise/Fall Time Rise Time (t )2 C = 150 pF 210 ns R LOAD Fall Time (t)3 C = 150 pF 150 ns F LOAD 1 Limits are based on characterization results; not production tested. 2 Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin. 3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin. Rev. 0 | Page 17 of 40

ADXL344 Data Sheet Overrun Bit Stream Mode The overrun bit is set when new data replaces unread data. The In stream mode, data from measurements of the x-, y-, and z- precise operation of the overrun function depends on the FIFO axes are stored in FIFO. When the number of samples in FIFO mode. In bypass mode, the overrun bit is set when new data equals the level specified in the samples bits of the FIFO_CTL replaces unread data in the DATAX, DATAY, and DATAZ registers register (Address 0x38), the watermark interrupt is set. FIFO (Address 0x32 to Address 0x37). In all other modes, the overrun continues accumulating samples and holds the latest 32 samples bit is set when FIFO is filled. The overrun bit is automatically from measurements of the x-, y-, and z-axes, discarding older cleared when the contents of FIFO are read. data as new data arrives. The watermark interrupt continues occurring until the number of samples in FIFO is less than the Orientation Bit value stored in the samples bits of the FIFO_CTL register. The orientation bit is set when the orientation of the accelerometer Trigger Mode changes from a valid orientation to a different valid orientation. An interrupt is not generated, however, if the orientation of the In trigger mode, FIFO accumulates samples, holding the latest accelerometer changes from a valid orientation to an invalid 32 samples from measurements of the x-, y-, and z-axes. After orientation, or from a valid orientation to an invalid orientation a trigger event occurs and an interrupt is sent to the INT1 or and then back to the same valid orientation. An invalid orientation INT2 pin (determined by the trigger bit in the FIFO_CTL register), is defined as an orientation within the dead zone, or the region of FIFO keeps the last n samples (where n is the value specified by hysteresis. This region helps to prevent rapid orientation change the samples bits in the FIFO_CTL register) and then operates in due to noise when the accelerometer orientation is close to the FIFO mode, collecting new samples only when FIFO is not full. boundary between two valid orientations. A delay of at least 5 μs should be present between the trigger event occurring and the start of reading data from the FIFO to allow The orientations that are valid for the interrupt depend on which the FIFO to discard and retain the necessary samples. Additional mode, 2D or 3D, is linked to the orientation interrupt. The mode is trigger events cannot be recognized until the trigger mode is selected with the INT_3D bit (Bit D3) in the ORIENT_CONF reset. To reset the trigger mode, set the device to bypass mode register (Address 0x3B). See the Register 0x3B—ORIENT_CONF and then set the device back to trigger mode. Note that the FIFO (Read/Write) section for more details on how to enable the data should be read first because placing the device into bypass orientation interrupt. mode clears FIFO. FIFO Retrieving Data from FIFO The ADXL344 contains an embedded memory management The FIFO data is read through the DATAX, DATAY, and DATAZ system with a 32-level FIFO memory buffer that can be used to registers (Address 0x32 to Address 0x37). When the FIFO is in minimize host processor burden. This buffer has four modes: FIFO, stream, or trigger mode, reads to the DATAX, DATAY, bypass, FIFO, stream, and trigger (see Table 22). Each mode is and DATAZ registers read data stored in the FIFO. Each time selected by the settings of the FIFO_MODE bits (Bits[D7:D6]) data is read from the FIFO, the oldest x-, y-, and z-axes data are in the FIFO_CTL register (Address 0x38). placed into the DATAX, DATAY, and DATAZ registers. If use of the FIFO is not desired, the FIFO should be placed in If a single-byte read operation is performed, the remaining bytes of bypass mode. data for the current FIFO sample are lost. Therefore, all axes of Bypass Mode interest should be read in a burst (or multiple-byte) read operation. In bypass mode, FIFO is not operational and, therefore, To ensure that the FIFO has completely popped (that is, that new remains empty. data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 μs between the end of reading FIFO Mode the data registers and the start of a new read of the FIFO or a In FIFO mode, data from measurements of the x-, y-, and z-axes read of the FIFO_STATUS register (Address 0x39). The end of are stored in FIFO. When the number of samples in FIFO reading a data register is signified by the transition of data from equals the level specified in the samples bits of the FIFO_CTL Register 0x37 to Register 0x38 or by the CS pin going high. register (Address 0x38), the watermark interrupt is set. FIFO For SPI operation at 1.6 MHz or less, the register addressing continues accumulating samples until it is full (32 samples from portion of the transmission is a sufficient delay to ensure that measurements of the x-, y-, and z-axes) and then stops collecting the FIFO has completely popped. For SPI operation greater than data. After FIFO stops collecting data, the device continues to 1.6 MHz, it is necessary to deassert the CS pin to ensure a total operate; therefore, features such as tap detection can be used delay of 5 μs; otherwise, the delay is not be sufficient. The total after FIFO is full. The watermark interrupt continues to occur delay necessary for 5 MHz operation is at most 3.4 μs. This is until the number of samples in FIFO is less than the value not a concern when using I2C mode because the communication stored in the samples bits of the FIFO_CTL register. rate is low enough to ensure a sufficient delay between FIFO reads. Rev. 0 | Page 18 of 40

Data Sheet ADXL344 SELF-TEST Table 14. Self-Test Output Scale Factors for Different Supply The ADXL344 incorporates a self-test feature that effectively Voltages, VS tests its mechanical and electronic systems simultaneously. Supply Voltage, VS X-, Y-Axes Z-Axis When the self-test function is enabled (via the SELF_TEST bit 1.70 V 0.43 0.38 (Bit D7 in the DATA_FORMAT register, Address 0x31), an 1.80 V 0.48 0.47 electrostatic force is exerted on the mechanical sensor. This 2.00 V 0.59 0.58 electrostatic force moves the mechanical sensing element in the 2.60 V 1.00 1.00 same manner as acceleration would, and it is additive to the 2.75 V 1.13 1.11 acceleration experienced by the device. This added electrostatic Table 15. Self-Test Output in LSB for ±2 g, 10-Bit or Full force results in an output change in the x-, y-, and z-axes. Because Resolution (T = 25°C, V = 2.6 V, V = 1.8 V) the electrostatic force is proportional to V2, the output change A S DD I/O S Axis Min Max Unit varies with V. This effect is shown in Figure 31. S X 70 400 LSB The scale factors listed in Table 14 can be used to adjust the Y −400 −70 LSB expected self-test output limits for different supply voltages, V. S Z 100 500 LSB The self-test feature of the ADXL344 also exhibits a bimodal behavior. However, the limits listed in Table 1 and Table 15 to Table 16. Self-Test Output in LSB for ±4 g, 10-Bit Resolution Table 18 are valid for both potential self-test values due to bi- (T = 25°C, V = 2.6 V, V = 1.8 V) A S DD I/O modality. Use of the self-test feature at data rates less than 100 Hz Axis Min Max Unit or at 1600 Hz may yield values outside these limits. Therefore, X 35 200 LSB the part must be in normal power operation (LOW_POWER Y −200 −35 LSB bit = 0 in the BW_RATE register, Address 0x2C) and be placed Z 50 250 LSB into a data rate of 100 Hz through 800 Hz or 3200 Hz for the self-test function to operate correctly. Table 17. Self-Test Output in LSB for ±8 g, 10-Bit Resolution (T = 25°C, V = 2.6 V, V = 1.8 V) 3 A S DD I/O X-AXIS SELF-TEST HIGH LIMIT Axis Min Max Unit Y-AXIS SELF-TEST HIGH LIMIT Z-AXIS SELF-TEST HIGH LIMIT X 17 100 LSB 2 X-AXIS SELF-TEST LOW LIMIT S (g) YZ--AAXXIISS SSEELLFF--TTEESSTT LLOOWW LLIIMMIITT Y −100 −17 LSB MIT 1 Z 25 125 LSB LI T F Table 18. Self-Test Output in LSB for ±16 g, 10-Bit Resolution HI 0 T S (TA = 25°C, VS = 2.6 V, VDD I/O = 1.8 V) S F-TE –1 Axis Min Max Unit L X 8 50 LSB E S Y −50 −8 LSB –2 Z 12 63 LSB –31.6 1.8 SUP2.P0LY VOLT2A.2GE, VS (2V.)4 2.6 2.8 10628-136 Figure 31. Self-Test Output Change Limits vs. Supply Voltage Rev. 0 | Page 19 of 40

ADXL344 Data Sheet REGISTER MAP Table 19. Register Map Address Hex Dec Name Type Reset Value Description 0x00 0 DEVID R 11100110 Device ID. 0x01 to 0x1C 1 to 28 Reserved Reserved. Do not access. 0x1D 29 THRESH_TAP R/W 00000000 Tap threshold. 0x1E 30 OFSX R/W 00000000 X-axis offset. 0x1F 31 OFSY R/W 00000000 Y-axis offset. 0x20 32 OFSZ R/W 00000000 Z-axis offset. 0x21 33 DUR R/W 00000000 Tap duration. 0x22 34 Latent R/W 00000000 Tap latency. 0x23 35 Window R/W 00000000 Tap window. 0x24 36 THRESH_ACT R/W 00000000 Activity threshold. 0x25 37 THRESH_INACT R/W 00000000 Inactivity threshold. 0x26 38 TIME_INACT R/W 00000000 Inactivity time. 0x27 39 ACT_INACT_CTL R/W 00000000 Axis enable control for activity and inactivity detection. 0x28 40 THRESH_FF R/W 00000000 Free-fall threshold. 0x29 41 TIME_FF R/W 00000000 Free-fall time. 0x2A 42 TAP_AXES R/W 00000000 Axis control for single tap/double tap. 0x2B 43 ACT_TAP_STATUS R 00000000 Source of single tap/double tap. 0x2C 44 BW_RATE R/W 00001010 Data rate and power mode control. 0x2D 45 POWER_CTL R/W 00000000 Power-saving features control. 0x2E 46 INT_ENABLE R/W 00000000 Interrupt enable control. 0x2F 47 INT_MAP R/W 00000000 Interrupt mapping control. 0x30 48 INT_SOURCE R 00000010 Source of interrupts. 0x31 49 DATA_FORMAT R/W 00000000 Data format control. 0x32 50 DATAX0 R 00000000 X-Axis Data 0. 0x33 51 DATAX1 R 00000000 X-Axis Data 1. 0x34 52 DATAY0 R 00000000 Y-Axis Data 0. 0x35 53 DATAY1 R 00000000 Y-Axis Data 1. 0x36 54 DATAZ0 R 00000000 Z-Axis Data 0. 0x37 55 DATAZ1 R 00000000 Z-Axis Data 1. 0x38 56 FIFO_CTL R/W 00000000 FIFO control. 0x39 57 FIFO_STATUS R 00000000 FIFO status. 0x3A 58 TAP_SIGN R 00000000 Sign and source for single tap/double tap. 0x3B 59 ORIENT_CONF R/W 00100101 Orientation configuration. 0x3C 60 Orient R 00000000 Orientation status. Rev. 0 | Page 20 of 40

Data Sheet ADXL344 REGISTER DEFINITIONS Register 0x24—THRESH_ACT (Read/Write) Register 0x00—DEVID (Read Only) The THRESH_ACT register is eight bits and holds the threshold D7 D6 D5 D4 D3 D2 D1 D0 value for detecting activity. The data format is unsigned, 1 1 1 0 0 1 1 0 therefore, the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor The DEVID register holds a fixed device ID code of 0xE6 is 62.5 mg/LSB. A value of 0 may result in undesirable behavior (346 octal). if the activity interrupt is enabled. Register 0x1D—THRESH_TAP (Read/Write) Register 0x25—THRESH_INACT (Read/Write) The THRESH_TAP register is eight bits and holds the threshold The THRESH_INACT register is eight bits and holds the threshold value for tap interrupts. The data format is unsigned, therefore, value for detecting inactivity. The data format is unsigned, the magnitude of the tap event is compared with the value in therefore, the magnitude of the inactivity event is compared THRESH_TAP for normal tap detection. For information on with the value in the THRESH_INACT register. The scale factor improved tap detection, refer to the Improved Tap Detection is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if section. The scale factor is 62.5 mg/LSB (that is, 0xFF = +16 g). the inactivity interrupt is enabled. A value of 0 may result in undesirable behavior if single-tap/ Register 0x26—TIME_INACT (Read/Write) double-tap interrupts are enabled. The TIME_INACT register is eight bits and contains an unsigned Register 0x1E, Register 0x1F, Register 0x20—OFSX, time value representing the amount of time that acceleration OFSY, OFSZ (Read/Write) must be less than the value in the THRESH_INACT register for The OFSX, OFSY, and OFSZ registers are each eight bits and inactivity to be declared. The scale factor is 1 sec/LSB. Unlike offer user-set offset adjustments in twos complement format the other interrupt functions, which use unfiltered data (see the with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The Threshold section), the inactivity function uses filtered output values stored in the offset registers are automatically added to data. At least one output sample must be generated for the the acceleration data, and the resulting value is stored in the inactivity interrupt to be triggered. This results in the function output data registers. For additional information regarding appearing unresponsive if the TIME_INACT register is set to a offset calibration and the use of the offset registers, refer to the value less than the time constant of the output data rate. A value Offset Calibration section. of 0 results in an interrupt when the output data is less than the Register 0x21—DUR (Read/Write) value in the THRESH_INACT register. The DUR register is eight bits and contains an unsigned time Register 0x27—ACT_INACT_CTL (Read/Write) value representing the maximum time that an event must be D7 D6 D5 D4 above the THRESH_TAP threshold to qualify as a tap event. For ACT ac/dc ACT_X enable ACT_Y enable ACT_Z enable information on improved tap detection, refer to the Improved Tap D3 D2 D1 D0 Detection section. The scale factor is 625 µs/LSB. A value of 0 INACT ac/dc INACT_X enable INACT_Y enable INACT_Z enable disables the single-tap/double-tap functions. ACT AC/DC and INACT AC/DC Bits Register 0x22—Latent (Read/Write) A setting of 0 selects dc-coupled operation, and a setting of 1 The latent register is eight bits and contains an unsigned time enables ac-coupled operation. In dc-coupled operation, the value representing the wait time from the detection of a tap current acceleration magnitude is compared directly with event to the start of the time window (defined by the window THRESH_ACT and THRESH_INACT to determine whether register) during which a possible second tap event can be detected. activity or inactivity is detected. For information on improved tap detection, refer to the Improved In ac-coupled operation for activity detection, the acceleration Tap Detection section. The scale factor is 1.25 ms/LSB. A value of 0 value at the start of activity detection is taken as a reference disables the double-tap function. value. New samples of acceleration are then compared to this Register 0x23—Window (Read/Write) reference value, and if the magnitude of the difference exceeds The window register is eight bits and contains an unsigned time the THRESH_ACT value, the device triggers an activity interrupt. value representing the amount of time after the expiration of the Similarly, in ac-coupled operation for inactivity detection, a latency time (determined by the latent register) during which a reference value is used for comparison and is updated whenever second valid tap can begin. For information on improved tap the device exceeds the inactivity threshold. After the reference detection, refer to the Improved Tap Detection section. The scale value is selected, the device compares the magnitude of the factor is 1.25 ms/LSB. A value of 0 disables the double-tap difference between the reference value and the current acceleration function. with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered. Rev. 0 | Page 21 of 40

ADXL344 Data Sheet ACT_x Enable Bits and INACT_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 A setting of 1 enables x-, y-, or z-axis participation in detecting 0 ACT_X ACT_Y ACT_Z Asleep TAP_X TAP_Y TAP_Z activity or inactivity. A setting of 0 excludes the selected axis from source source source source source source participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR’ed, ACT_x Source and TAP_x Source Bits causing the activity function to trigger when any of the partici- These bits indicate the first axis involved in a tap or activity pating axes exceeds the threshold. For inactivity detection, all event. A setting of 1 corresponds to involvement in the event, participating axes are logically AND’ed, causing the inactivity and a setting of 0 corresponds to no involvement. When new function to trigger only if all participating axes are below the data is available, these bits are not cleared but are overwritten by threshold for the specified period of time. the new data. The ACT_TAP_STATUS register should be read Register 0x28—THRESH_FF (Read/Write) before clearing the interrupt. Disabling an axis from participation clears the corresponding source bit when the next activity or The THRESH_FF register is eight bits and holds the threshold single-tap/double-tap event occurs. value, in unsigned format, for free-fall detection. The acceleration on all axes is compared with the value in THRESH_FF to deter- Asleep Bit mine if a free-fall event occurred. The scale factor is 62.5 mg/LSB. A setting of 1 in the asleep bit indicates that the part is asleep, Note that a value of 0 mg may result in undesirable behavior if and a setting of 0 indicates that the part is not asleep. This bit the free-fall interrupt is enabled. Values between 300 mg and toggles only if the device is configured for autosleep. See the 600 mg (0x05 to 0x09) are recommended. Register 0x2D—POWER_CTL (Read/Write) section for more Register 0x29—TIME_FF (Read/Write) information on autosleep mode. The TIME_FF register is eight bits and stores an unsigned time Register 0x2C—BW_RATE (Read/Write) value representing the minimum time that the value of all axes D7 D6 D5 D4 D3 D2 D1 D0 must be less than THRESH_FF to generate a free-fall interrupt. 0 0 0 LOW_POWER Rate The scale factor is 5 ms/LSB. A value of 0 may result in undesirable LOW_POWER Bit behavior if the free-fall interrupt is enabled. Values between 100 ms and 350 ms (0x14 to 0x46) are recommended. A setting of 0 in the LOW_POWER bit selects normal operation, Register 0x2A—TAP_AXES (Read/Write) and a setting of 1 selects reduced power operation, which is associated with somewhat higher noise (see the Power Modes D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Improved Suppress TAP_X TAP_Y TAP_Z section for details). tap enable enable enable Rate Bits Improved Tap Bit These bits select the device bandwidth and output data rate (see The improved tap bit is used to enable improved tap detection. Table 7 and Table 8 for details). The default value is 0x0A, which This mode of operation improves tap detection by performing translates to a 100 Hz output data rate. An output data rate should an ac-coupled differential comparison of the output acceleration be selected that is appropriate for the communication protocol and data. The improved tap detection is performed on the same output frequency selected. Selecting too high of an output data rate with a data available in the DATAX, DATAY, and DATAZ registers. Due low communication speed results in samples being discarded. to the dependency on the output data rate and the ac-coupled Register 0x2D—POWER_CTL (Read/Write) differential measurement, the threshold and timing values for D7 D6 D5 D4 D3 D2 D1 D0 single taps and double taps must be adjusted for improved tap 0 0 Link AUTO_SLEEP Measure Sleep Wakeup detection. For further explanation of improved tap detection, see the Improved Tap Detection section. Improved tap is enabled Link Bit by setting the improved tap bit to a value of 1 and is disabled A setting of 1 in the link bit with both the activity and inactivity by clearing the bit to a value of 0. functions enabled delays the start of the activity function until Suppress Bit inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links Setting the suppress bit suppresses double-tap detection if the activity and inactivity functions. When this bit is set to 0, acceleration greater than the value in THRESH_TAP is present the inactivity and activity functions are concurrent. Additional between taps. See the Tap Detection section for more details. information can be found in the Link Mode section. TAP_x Enable Bits A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection. Rev. 0 | Page 22 of 40

Data Sheet ADXL344 When clearing the link bit, it is recommended that the part be Wakeup Bits placed into standby mode and then set back to measurement These bits control the frequency of readings in sleep mode as mode with a subsequent write. This is done to ensure that the described in Table 20. device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared Table 20. Frequency of Readings in Sleep Mode may have additional noise, especially if the device was asleep Setting when the bit was cleared. D1 D0 Frequency (Hz) AUTO_SLEEP Bit 0 0 8 0 1 4 If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables 1 0 2 the autosleep functionality. In this mode, the ADXL344 auto- 1 1 1 matically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, when acceleration is Register 0x2E—INT_ENABLE (Read/Write) below the THRESH_INACT value for at least the time indicated D7 D6 D5 D4 by TIME_INACT). If activity is also enabled, the ADXL344 DATA_READY SINGLE_TAP DOUBLE_TAP Activity automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW_RATE D3 D2 D1 D0 register. A setting of 0 in the AUTO_SLEEP bit disables automatic Inactivity FREE_FALL Watermark Overrun/ orientation switching to sleep mode. See the description of the sleep bit in this section for more information on sleep mode. Setting bits in this register to a value of 1 enables their respective If the link bit is not set, the AUTO_SLEEP feature is disabled, functions to generate interrupts, whereas a value of 0 prevents and setting the AUTO_SLEEP bit does not have any impact on the functions from generating interrupts. The DATA_READY, device operation. Refer to the Link Bit section or the Link Mode watermark, and overrun/orientation bits enable only the interrupt section for more information about using the link feature. output; the functions are always enabled. It is recommended that interrupts be configured before enabling their outputs. When clearing the AUTO_SLEEP bit, it is recommended that the part be placed into standby mode and then set back to measure- Register 0x2F—INT_MAP (Read/Write) ment mode with a subsequent write. This is done to ensure that D7 D6 D5 D4 the device is properly biased if sleep mode is manually disabled; DATA_READY SINGLE_TAP DOUBLE_TAP Activity otherwise, the first few samples of data after the AUTO_SLEEP D3 D2 D1 D0 bit is cleared may have additional noise, especially if the device Inactivity FREE_FALL Watermark Overrun/ was asleep when the bit was cleared. orientation Measure Bit Bits set to 0 in this register send their respective interrupts to the A setting of 0 in the measure bit places the part into standby mode, INT1 pin, whereas bits set to 1 send their respective interrupts to and a setting of 1 places the part into measurement mode. The the INT2 pin. All selected interrupts for a given pin are OR’ed. ADXL344 powers up in standby mode with minimum power Register 0x30—INT_SOURCE (Read Only) consumption. D7 D6 D5 D4 Sleep Bit DATA_READY SINGLE_TAP DOUBLE_TAP Activity D3 D2 D1 D0 A setting of 0 in the sleep bit puts the part into the normal mode Inactivity FREE_FALL Watermark Overrun/ of operation, and a setting of 1 places the part into sleep mode. orientation Sleep mode suppresses DATA_READY, stops transmission of data to FIFO, and switches the sampling rate to one specified by the Bits set to 1 in this register indicate that their respective functions wakeup bits. In sleep mode, only the activity function can be used. have triggered an event, whereas bits set to 0 indicate that the While the DATA_READY interrupt is suppressed, the output corresponding events have not occurred. The DATA_READY, data registers are still updated at the sampling rate set by the watermark, and overrun/orientation bits are always set if the wakeup bits. corresponding events occur, regardless of the INT_ENABLE When clearing the sleep bit, it is recommended that the part be register settings, and are cleared by reading data from the placed into standby mode and then set back to measurement DATAX, DATAY, and DATAZ registers. The DATA_READY and mode with a subsequent write. This is done to ensure that the watermark bits may require multiple reads, as indicated in the device is properly biased if sleep mode is manually disabled; FIFO mode descriptions in the FIFO section. Other bits, and the otherwise, the first few samples of data after the sleep bit is corresponding interrupts, including orientation if enabled, are cleared may have additional noise, especially if the device was cleared by reading the INT_SOURCE register. asleep when the bit was cleared. Rev. 0 | Page 23 of 40

ADXL344 Data Sheet Register 0x31—DATA_FORMAT (Read/Write) and DATAx1 as the most significant byte, where x represents X, D7 D6 D5 D4 D3 D2 D1 D0 Y, or Z. The DATA_FORMAT register (Address 0x31) controls SELF_TEST SPI INT_INVERT 0 FULL_RES Justify Range the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data The DATA_FORMAT register controls the presentation of data between reads of sequential registers. to Register 0x32 through Register 0x37. All data, except that for Register 0x38—FIFO_CTL (Read/Write) the ±16 g range, must be clipped to avoid rollover. D7 D6 D5 D4 D3 D2 D1 D0 SELF_TEST Bit FIFO_MODE Trigger Samples A setting of 1 in the SELF_TEST bit applies a self-test force to FIFO_MODE Bits the sensor, causing a shift in the output data. A value of 0 disables the self-test force. These bits set the FIFO mode, as described in Table 22. SPI Bit Table 22. FIFO Modes A value of 1 in the SPI bit sets the device to 3-wire SPI mode, Setting and a value of 0 sets the device to 4-wire SPI mode. D7 D6 Mode Function INT_INVERT Bit 0 0 Bypass FIFO is bypassed. 0 1 FIFO FIFO collects up to 32 values and then A value of 0 in the INT_INVERT bit sets the interrupts to active stops collecting data, collecting new high, and a value of 1 sets the interrupts to active low. data only when FIFO is not full. FULL_RES Bit 1 0 Stream FIFO holds the last 32 data values. When FIFO is full, the oldest data is When this bit is set to a value of 1, the device is in full resolution overwritten with newer data. mode, where the output resolution increases with the g range 1 1 Trigger When triggered by the trigger bit, set by the range bits to maintain a 4 mg/LSB scale factor. When FIFO holds the last data samples the FULL_RES bit is set to 0, the device is in 10-bit mode, and before the trigger event and then continues to collect data until FIFO is the range bits determine the maximum g range and scale factor. full. New data is collected only when Justify Bit FIFO is not full. A setting of 1 in the justify bit selects left-justified (MSB) mode, Trigger Bit and a setting of 0 selects right-justified mode with sign extension. A value of 0 in the trigger bit links the trigger event of trigger mode Range Bits to INT1, and a value of 1 links the trigger event to INT2. These bits set the g range as described in Table 21. Samples Bits Table 21. g Range Setting The function of these bits depends on the FIFO mode selected (see Setting Table 23). Entering a value of 0 in the samples bits immediately D1 D0 g Range sets the watermark bit in the INT_SOURCE register (Address 0 0 ±2 g 0x30), regardless of which FIFO mode is selected. Undesirable 0 1 ±4 g operation may occur if a value of 0 is used for the samples bits 1 0 ±8 g when trigger mode is used. 1 1 ±16 g Table 23. Samples Bits Functions Register 0x32 to Register 0x37—DATAX0, DATAX1, FIFO Mode Samples Bits Function DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Bypass None. FIFO Specifies how many FIFO entries are needed to These six bytes (Register 0x32 to Register 0x37) are eight bits trigger a watermark interrupt. each and hold the output data for each axis. Register 0x32 and Stream Specifies how many FIFO entries are needed to Register 0x33 hold the output data for the x-axis, Register 0x34 and trigger a watermark interrupt. Register 0x35 hold the output data for the y-axis, and Register 0x36 Trigger Specifies how many FIFO samples are retained in and Register 0x37 hold the output data for the z-axis. The output the FIFO buffer before a trigger event. data is twos complement, with DATAx0 as the least significant byte Rev. 0 | Page 24 of 40

Data Sheet ADXL344 Register 0x39—FIFO_STATUS (Read Only) An orientation interrupt is generated whenever the orientation D7 D6 D5 D4 D3 D2 D1 D0 status for the mode selected by the INT_3D bit changes in the FIFO_TRIG 0 Entries orient register (Address 0x3C). The orientation interrupt is cleared by reading the INT_SOURCE register. Clearing the FIFO_TRIG Bit INT_ORIENT bit or the orientation bit in the INT_ENABLE A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, register (Address 0x2E) disables and clears the interrupt. and a 0 means that a FIFO trigger event has not occurred. Writing to the BW_RATE register (Address 0x2C) or placing Entries Bits the part into standby mode resets the orientation feature, clearing the orientation filter and the interrupt. However, resetting the These bits report how many data values are stored in FIFO. orientation feature also resets the orientation status in the orient Access to collect the data from FIFO is provided through the register (Address 0x3C) and, therefore, causes an interrupt to be DATAX, DATAY, and DATAZ registers. FIFO reads must be generated when the next output sample is available if the present done in burst or multiple-byte mode because each FIFO level is orientation is not the default orientation. A value of 0 for the cleared after any read (single- or multiple-byte) of FIFO. FIFO INT_ORIENT bit disables generation of the orientation interrupt stores a maximum of 32 entries, which equates to a maximum and permits the use of the overrun function. of 33 entries available at any given time because an additional entry is available at the output filter of the device. Dead Zone Bits Register 0x3A—TAP_SIGN (Read Only) These bits determine the region between two adjacent orientations, D7 D6 D5 D4 D3 D2 D1 D0 where the orientation is considered invalid and is not updated. A 0 XSIGN YSIGN ZSIGN 0 XTAP YTAP ZTAP value of 0 may result in undesirable behavior when the orientation is close to the bisector between two adjacent regions. The dead zone xSIGN Bits angle is determined by these bits, as described in Table 24. See the These bits indicate the sign of the first axis involved in a tap Orientation Sensing section for more details. event. A setting of 1 corresponds to acceleration in the negative Table 24. Dead Zone and Divisor Codes direction, and a setting of 0 corresponds to acceleration in the Dead Zone Angle Divisor positive direction. These bits update only when a new single- Decimal Binary (Degrees) Bandwidth (Hz) tap/double-tap event is detected, and only the axes enabled in the 0 000 5.1 ODR/9 TAP_AXES register (Address 0x2A) are updated. The TAP_SIGN 1 001 10.2 ODR/22 register should be read before clearing the interrupt. See the Tap 2 010 15.2 ODR/50 Sign section for more details. 3 011 20.4 ODR/100 xTAP Bits 4 100 25.5 ODR/200 These bits indicate the first axis involved in a tap event. A 5 101 30.8 ODR/400 setting of 1 corresponds to involvement in the event, and a 6 110 36.1 ODR/800 setting of 0 corresponds to no involvement. When new data is 7 111 41.4 ODR/1600 available, these bits are not cleared but are overwritten by the new data. The TAP_SIGN register should be read before clearing INT_3D Bit the interrupt. Disabling an axis from participation clears the If the orientation interrupt is enabled, the INT_3D bit determines corresponding source bit when the next single-tap/double-tap whether 2D or 3D orientation detection generates an interrupt. event occurs. A value of 0 generates an interrupt only if the 2D orientation Register 0x3B—ORIENT_CONF (Read/Write) changes from a valid 2D orientation to a different valid 2D D7 D6 D5 D4 D3 D2 D1 D0 orientation. A value of 1 generates an interrupt only if the 3D INT_ Dead zone INT_ Divisor orientation changes from a valid 3D orientation to a different ORIENT 3D valid 3D orientation. INT_ORIENT Bit Divisor Bits Setting the INT_ORIENT bit enables the orientation interrupt. These bits set the bandwidth of the filter used to low-pass filter the A value of 1 overrides the overrun function of the device and measured acceleration for stable orientation sensing. The divisor replaces overrun in the INT_MAP (Address 0x2F), INT_ENABLE bandwidth is determined by these bits, as detailed in Table 24, (Address 0x2E), and INT_SOURCE (Address 0x30) registers with where ODR is the output data rate set in the BW_RATE register the orientation function. After setting the INT_ORIENT bit, the (Address 0x2C). See the Orientation Sensing section for more orientation bits in the INT_MAP and INT_ENABLE registers must details. be configured to map the orientation interrupt to INT1 or INT2 and to enable generation of the interrupt to the pin. Rev. 0 | Page 25 of 40

ADXL344 Data Sheet Register 0x3C—Orient (Read Only) Writing to the BW_RATE register (Address 0x2C) or placing D7 D6 D5 D4 D3 D2 D1 D0 the part into standby mode resets the orientation feature, clearing 0 V2 2D_ORIENT V3 3D_ORIENT the orientation filter and the orientation status. An orientation interrupt (if enabled) results from these actions if the orientation Vx Bits during the next output sample is different from the default These bits show the validity of the 2D (V2) and 3D (V3) orienta- value (+X for 2D orientation detection and undefined for 3D tions. A value of 1 corresponds to the orientation being valid. A orientation). value of 0 means that the orientation is invalid because the current Table 25. 2D Orientation Codes orientation is in the dead zone. Decimal Binary Orientation Dominant Axis xD_ORIENT Bits 0 00 Portrait positive +X These bits represent the current 2D (2D_ORIENT) and 3D 1 01 Portrait negative −X (3D_ORIENT) orientations of the accelerometer. If the orien- 2 10 Landscape positive +Y tation interrupt is enabled, this register is read to determine the 3 11 Landscape negative −Y orientation of the device when the interrupt occurs. Because this register updates with each new sample of acceleration data, it Table 26. 3D Orientation Codes should be read at the time of the orientation interrupt to ensure Decimal Binary Orientation Dominant Axis that the orientation change that caused the interrupt has been 3 011 Front +X identified. Orientation values are shown in Table 25 and Table 26. 4 100 Back −X See the Orientation Sensing section for more details. 2 010 Left +Y 5 101 Right −Y 1 001 Top +Z 6 110 Bottom −Z Rev. 0 | Page 26 of 40

Data Sheet ADXL344 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING TAP DETECTION A 1 μF tantalum capacitor (C) at V and a 0.1 μF ceramic capacitor The tap interrupt function is capable of detecting either single S S (C ) at V placed close to the ADXL344 supply pins is or double taps. The following parameters are shown in Figure 34 I/O DD I/O for a valid single-tap event and a valid double-tap event: recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, • The tap detection threshold is defined by the THRESH_TAP a resistor or ferrite bead, no larger than 100 Ω, in series with VS register (Address 0x1D). may be helpful. Additionally, increasing the bypass capacitance • The maximum tap duration time is defined by the DUR on VS to a 10 μF tantalum capacitor in parallel with a 0.1 μF register (Address 0x21). ceramic capacitor may also improve noise. • The tap latency time is defined by the latent register Care should be taken to ensure that the connection from the (Address 0x22) and is the waiting period from the end of ADXL344 ground to the power supply ground has low impedance the first tap until the start of the time window when a because noise transmitted through ground has an effect similar second tap can be detected, which is determined by the to noise transmitted through V. It is recommended that V and value in the window register (Address 0x23). S S VDD I/O be separate supplies to minimize digital clock noise on • The interval after the latency time (set by the latent register) is the VS supply. If this is not possible, additional filtering of the defined by the window register. Although a second tap must supplies as previously mentioned may be necessary. begin after the latency time has expired, it need not finish VS VDD I/O before the end of the time defined by the window register. CS CI/O FIRST TAP SECOND TAP VS VDD I/O ADXL344 W INTERRUPT INT1 SDO/ASLDTA A/SDDDI/RSEDSIOS 34--WWIIRREE OSPRI XHI B T(THHRREESSHHO_LTDAP) CONTROL INT2 SCL/SCLK OR I2C GND CS INTERFACE 10628-035 TIMTAEP LSI M(DITU RFO)R Figure 32. Applications Diagram LATENCY TIME WINDOW FOR TIME SECOND TAP (WINDOW) MECHANICAL CONSIDERATIONS FOR MOUNTING (LATENT) S T Tcthlhoese eA A tDoD XaX LhL3a34r4d44 ma stho auonnu utlidnn sgbu epp ompinootru tonefdt te hPde Co PBnC tlBoh cetoa Pt tiChoenB ,c iaanss e as. hlMoocowauntni oitninn g INTERRUP SININTGELRER-UTPATP DIONTUEBRLREU-TPATP 10628-037 Figure 34. Tap Interrupt Function with Valid Single and Double Taps Figure 33, may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near If only the single-tap function is in use, the single-tap interrupt a hard mounting point ensures that any PCB vibration at the is triggered when the acceleration goes below the threshold, as accelerometer is above the accelerometer’s mechanical sensor long as DUR has not been exceeded. If both single and double- resonant frequency and, therefore, effectively invisible to the tap functions are in use, the single-tap interrupt is triggered accelerometer. Multiple mounting points close to the sensor when the double-tap event has been either validated or and/or a thicker PCB also help to reduce the effect of system invalidated. resonance on the performance of the sensor. Several events can occur to invalidate the second tap of a ACCELEROMETERS double-tap event. First, if the suppress bit in the TAP_AXES PCB register (Address 0x2A) is set, any acceleration spike above the threshold during the latency time (set by the latent register) MOUNTING POINTS 10628-036 invalidates the double-tap detection, as shown in Figure 35. Figure 33. Incorrectly Placed Accelerometers Rev. 0 | Page 27 of 40

ADXL344 Data Sheet INVALIDATES DOUBLE TAP IF DUR, latent, window, and THRESH_TAP registers is required. SUPRESS BIT IS SET In general, a good starting point is to set the DUR register to a value greater than 0x10 (10 ms), the latent register to a value greater BW than 0x10 (20 ms), the window register to a value greater than HI X 0x40 (80 ms), and the THRESH_TAP register to a value greater than 0x30 (3 g). Setting a very low value in the latent, window, or THRESH_TAP register may result in an unpredictable response TFIOM(RDE U TLRAIM)PIST TIMLEA T(LEANTCEYNT) TIME WTINADP O(WWI NFDOORW S)ECOND 10628-038 dAuftee tro a t thaep aicncteelrerruopmt ehtaesr bpeicekni nregc euipv eedc,h tohees foirf stth aex tias pto i nepxucetse.d Figure 35. Double-Tap Event Invalid Due to High g Event the THRESH_TAP level is reported in the ACT_TAP_STATUS When the Suppress Bit Is Set register (Address 0x2B). This register is never cleared but is A double-tap event can also be invalidated if acceleration above overwritten with new data. the threshold is detected at the start of the time window for the IMPROVED TAP DETECTION second tap (set by the window register (Address 0x23)). This results in an invalid double tap at the start of this window, as shown in Improved tap detection is enabled by setting the improved tap Figure 36. Additionally, a double-tap event can be invalidated if bit of the TAP_AXES register (Address 0x2A). When improved an acceleration exceeds the time limit for taps (set by the DUR tap detection is enabled, the filtered output data corresponding to register (Address 0x21)), resulting in an invalid double tap at the output data rate set in the BW_RATE register (Address 0x2C) the end of the DUR time limit for the second tap event, also is processed to determine if a tap event occurred. In addition, an shown in Figure 36. ac-coupled differential measurement is used. This results in the timing values and threshold values for improved tap detection INVALIDATES DOUBLE TAP being different from those used for normal tap detection. AT START OF WINDOW When improved tap detection is used, new values must be determined based on test results. In general, no timing values W (in the DUR, latent, or window registers) should be set that are B XHI less than the time step resolution set by the output data rate. The threshold value for improved tap detection can typically be set much lower than the threshold for normal tap detection. TIME LIMIT The value used depends on the value in the BW_RATE register FOR TAPS (DUR) and should be determined through system testing. Refer to the TIME LIMIT Threshold section for more details. FO(RD UTRA)PS LATTIEMNECY SETCIMOEN DW TINADPO (WWI NFODORW) TAP SIGN (LATENT) TIME LIMIT A negative sign is produced by experiencing a negative accel- FOR TAPS (DUR) eration, which corresponds to tapping on the positive face of the device for the desired axis. The positive face of the device is the face such that movement in that direction is positive acceleration. W For example, tapping on the face that corresponds to the +X B XHI direction, labeled as front in Figure 37, results in a negative sign INVALIDATES DOUBLE TAP AT for the x-axis. Tapping on the face labeled as left in Figure 37 END OF DUR 10628-039 rlaebsuelletsd i tno ap nreesgualttisv ein s iag nne fgoart itvhee syi-ganx ifso,r a tnhde tza-papxiisn.g C oonn vtheers fealcye, Figure 36. Tap Interrupt Function with Invalid Double Taps tapping on the back, right, or bottom side results in positive Single taps, double taps, or both can be detected by setting the signs for the corresponding axes. respective bits in the INT_ENABLE register (Address 0x2E). +z Control over participation of each of the three axes in single-tap/ double-tap detection is exerted by setting the appropriate bits in TOP (+Z) the TAP_AXES register (Address 0x2A). For the double-tap function to operate, both the latent and window registers must +y be set to a nonzero value. LEFT (+Y) dEoveurbyl em-teacph raensipcoanl sseyss tbeamse hda os nso tmhee wmheacth danififcearle ncht asrinacgtleer-tisatpic/ s of +x FR(+OXN)T 10628-046 Figure 37. 3D Orientation with Coordinate System the system. Therefore, some experimentation with values for the Rev. 0 | Page 28 of 40

Data Sheet ADXL344 THRESHOLD and application of any compounds on or over the component. If calibration is deemed necessary, it is recommended that calibration The lower output data rates are achieved by decimating a be performed after system assembly to compensate for these effects. common sampling frequency inside the device. The activity, free-fall, and single-tap/double-tap detection functions without A simple method of calibration is to measure the offset while improved tap enabled are performed using undecimated data. assuming that the sensitivity of the ADXL344 is as specified in As the bandwidth of the output data varies with the data rate Table 1. The offset can then be automatically accounted for by and is lower than the bandwidth of the undecimated data, the using the built-in offset registers (Register 0x1E, Register 0x1F, and high frequency and high g data that is used to determine activity, Register 0x20). This results in the data acquired from the DATAX, free-fall, and single-tap/double-tap events may not be present if DATAY, and DATAZ registers (Address 0x32 to Address 0x37) the output of the accelerometer is examined. This may result in already compensating for any offset. functions triggering when acceleration data does not appear to In a no-turn or single-point calibration scheme, the part is oriented meet the conditions set by the user for the corresponding function. such that one axis, typically the z-axis, is in the 1 g field of gravity LINK MODE and the remaining axes, typically the x- and y-axes, are in a 0 g field. The output is then measured by taking the average of a The function of the link bit is to reduce the number of activity series of samples. The number of samples averaged is a choice of interrupts that the processor must service by setting the device the system designer, but a recommended starting point is 0.1 sec to look for activity only after inactivity. For proper operation of worth of data for data rates of 100 Hz or greater. This corresponds this feature, the processor must still respond to the activity and to 10 samples at the 100 Hz data rate. For data rates of less than inactivity interrupts by reading the INT_SOURCE register 100 Hz, it is recommended that at least 10 samples be averaged (Address 0x30) and, therefore, clearing the interrupts. If an activity together. These values are stored as X , Y , and Z for the 0 g interrupt is not cleared, the part cannot go into autosleep mode. 0g 0g +1g measurements on the x- and y-axes and the 1 g measurement The asleep bit in the ACT_TAP_STATUS register (Address 0x2B) on the z-axis, respectively. indicates whether the part is asleep. The values measured for X and Y correspond to the offset of SLEEP MODE VS. LOW POWER MODE 0g 0g the x- and y-axes, and compensation is done by subtracting those In applications where a low data rate and low power consumption values from the output of the accelerometer to obtain the actual are desired (at the expense of noise performance), it is recom- acceleration: mended that low power mode be used. The use of low power X = X − X mode preserves the functionality of the DATA_READY interrupt ACTUAL MEAS 0g and FIFO for postprocessing of the acceleration data. Sleep YACTUAL = YMEAS − Y0g mode, while offering a low data rate and power consumption, is Because the z-axis measurement is done in a 1 g field, a no-turn or not intended for data acquisition. single-point calibration scheme assumes an ideal sensitivity, S , Z However, when sleep mode is used in conjunction with the for the z-axis. This is subtracted from Z+1g to attain the z-axis AUTO_SLEEP mode and the link mode, the part can automatically offset, which is then subtracted from future measured values to switch to a low power, low sampling rate mode when inactivity obtain the actual value: is detected. To prevent the generation of redundant inactivity Z = Z − S 0g 1g Z interrupts, the inactivity interrupt is automatically disabled Z = Z − Z and activity is enabled. When the ADXL344 is in sleep mode, the ACTUAL MEAS 0g host processor can also be placed into sleep mode or low power The ADXL344 can automatically compensate the output for offset mode to save significant system power. Once activity is detected, by using the offset registers (Register 0x1E, Register 0x1F, and the accelerometer automatically switches back to the original Register 0x20). These registers contain an 8-bit, twos complement data rate of the application and provides an activity interrupt value that is automatically added to all measured acceleration that can be used to wake up the host processor. Similar to when values, and the result is then placed into the DATAX, DATAY, inactivity occurs, detection of activity events is disabled and and DATAZ registers. Because the value placed in an offset register inactivity is enabled. is additive, a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset. The register OFFSET CALIBRATION has a scale factor of 15.6 mg/LSB and is independent of the Accelerometers are mechanical structures containing elements selected g range. that are free to move. These moving parts can be very sensitive As an example, assume that the ADXL344 is placed into full- to mechanical stresses, much more so than solid-state electronics. resolution mode with a sensitivity of typically 256 LSB/g. The The 0 g bias or offset is an important accelerometer metric because part is oriented such that the z-axis is in the field of gravity and it defines the baseline for measuring acceleration. Additional the outputs of the x-, y-, and z-axes are measured as +10 LSB, stresses can be applied during assembly of a system containing −13 LSB, and +9 LSB, respectively. Using the previous equations, an accelerometer. These stresses can come from, but are not X is +10 LSB, Y is −13 LSB, and Z is +9 LSB. Each LSB of limited to, component soldering, board stress during mounting, 0g 0g 0g Rev. 0 | Page 29 of 40

ADXL344 Data Sheet output in full-resolution is 3.9 mg or one-quarter of an LSB of recommended that at least 10 samples be averaged together. The the offset register. averaged values should be stored and labeled appropriately as the self-test disabled data, that is, X , Y , and Z . Because the offset register is additive, the 0 g values are negated ST_OFF ST_OFF ST_OFF and rounded to the nearest LSB of the offset register: Next, self-test should be enabled by setting Bit D7 of the DATA_FORMAT register (Address 0x31). The output needs some X = −Round(10/4) = −3 LSB OFFSET time (about four samples) to settle once self-test is enabled. After Y = −Round(−13/4) = 3 LSB OFFSET allowing the output to settle, several samples of acceleration data ZOFFSET = −Round(9/4) = −2 LSB for the x-, y-, and z-axes should be taken again and averaged. It is recommended that the same number of samples be taken for These values are programmed into the OFSX, OFSY, and OFXZ this average as was previously taken. These averaged values should registers, respectively, as 0xFD, 0x03, and 0xFE. As with all again be stored and labeled appropriately as the value with self- registers in the ADXL344, the offset registers do not retain the test enabled, that is, X , Y , and Z . Self-test can then value written into them when power is removed from the part. ST_ON ST_ON ST_ON be disabled by clearing Bit D7 of the DATA_FORMAT register Power-cycling the ADXL344 returns the offset registers to their (Address 0x31). default value of 0x00. With the stored values for self-test enabled and disabled, the Because the no-turn or single-point calibration method assumes an self-test change is as follows: ideal sensitivity in the z-axis, any error in the sensitivity results in offset error. For instance, if the actual sensitivity was 250 LSB/g X = X − X ST ST_ON ST_OFF in the previous example, the offset would be 15 LSB, not 9 LSB. Y = Y − Y ST ST_ON ST_OFF To help minimize this error, an additional measurement point Z = Z − Z can be used with the z-axis in a 0 g field, and the 0 g measurement ST ST_ON ST_OFF can be used in the Z equation. Because the measured output for each axis is expressed in LSBs, ACTUAL USING SELF-TEST XST, YST, and ZST are also expressed in LSBs. These values can be converted to g’s of acceleration by multiplying each value by the The self-test change is defined as the difference between the 3.9 mg/LSB scale factor, if configured for full-resolution mode. acceleration output of an axis with self-test enabled and the Additionally, Table 15 through Table 18 correspond to the self-test acceleration output of the same axis with self-test disabled (see range converted to LSBs and can be compared with the measured Endnote 8 of Table 1). This definition assumes that the sensor self-test change when operating at a V of 2.6 V. For other voltages, S does not move between these two measurements. If the sensor the minimum and maximum self-test output values should be moves, the additional shift, which is unrelated to self-test, adjusted based on (multiplied by) the scale factors shown in corrupts the test. Table 14. If the part was placed into ±2 g, 10-bit or full-resolution Proper configuration of the ADXL344 is also necessary for mode, the values listed in Table 15 should be used. Although an accurate self-test measurement. The part should be set with the fixed 10-bit mode or a range other than 16 g can be used, a a data rate of 100 Hz through 800 Hz, or 3200 Hz. This is done different set of values, as indicated in Table 16 through Table 18, by ensuring that a value of 0x0A through 0x0D, or 0x0F is would need to be used. Using a range below 8 g may result in written into the rate bits (Bit D3 through Bit D0) in the insufficient dynamic range and should be considered when BW_RATE register (Address 0x2C). The part also must be selecting the range of operation for measuring self-test. placed into normal power operation by ensuring that the If the self-test change is within the valid range, the test is considered LOW_POWER bit (Bit D4) in the BW_RATE register is cleared successful. Generally, a part is considered to pass if the minimum (LOW_POWER bit = 0) for accurate self-test measurements. It magnitude of change is achieved. However, a part that changes is recommended that the part be set to full-resolution 16 g by more than the maximum magnitude is not necessarily a failure. mode to ensure that there is sufficient dynamic range for the Another effective method for using the self-test to verify accel- entire self-test shift. This is done by setting the FULL_RES bit erometer functionality is to toggle the self-test at a certain rate (Bit D3) and writing a value of 0x03 to the range bits (Bit D1 and then perform an FFT on the output. The FFT should have a and Bit D0) of the DATA_FORMAT register (Address 0x31). corresponding tone at the frequency the self-test was toggled. This results in a high dynamic range for measurement and a This methodology removes the dependency of the test on supply 3.9 mg/LSB scale factor. voltage and on self-test magnitude, which can vary within a rather After the part is configured for accurate self-test measurement, wide range. several samples of acceleration data for the x-, y-, and z-axes should be retrieved from the sensor and averaged together. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater. This corresponds to 10 samples at the 100 Hz data rate. For data rates of less than 100 Hz, it is Rev. 0 | Page 30 of 40

Data Sheet ADXL344 ORIENTATION SENSING To eliminate most human motion, such as walking or shaking, the value in the divisor bits (Bits[D2:D0]) of the ORIENT_CONF The orientation function of the ADXL344 reports both 2D register (Address 0x3B) should be selected to effectively limit the and 3D orientation concurrently through the orient register orientation bandwidth to 1 Hz or 2 Hz. For example, with an (Address 0x3C). The V2 and V3 bits (Bit D6 and Bit D3 in the output data rate of 100 Hz, a divisor selection of 3 (ODR/100) orient register) report the validity of the 2D and 3D orientation results in a 1 Hz bandwidth for orientation detection. For best codes. If V2 or V3 are set, their respective code is a valid results, it is recommended that an output data rate of ≥25 Hz in orientation. If V2 or V3 are cleared, the orientation of the normal power mode and ≥200 Hz in low power operation be used. accelerometer is unknown, such as when the orientation is within the dead zone between valid regions. PORTRAIT POSITIVE (00) NEGATIVE (01) For 2D orientation sensing, the relation of the x- and y-axes to gravity is used to determine the accelerometer orientation (see +X DEADZONES Figure 38 and Table 25). Portrait positive corresponds to the x-axis being most closely aligned to the gravity vector and directed +Y +Y upwards, opposite the gravity vector. Portrait negative is the +g +g opposite of portrait positive, with the x-axis pointing downwards along the gravity vector. Landscape positive corresponds to the +X y-axis being most closely aligned with the gravity vector and directed upwards, away from the gravity vector. Landscape LANDSCAPE negative is the orientation opposite landscape positive. The POSITIVE (10) NEGATIVE (11) +Y dead zone regions are shown in the orientations for portrait positive (+X) and portrait negative (−X) of Figure 38. These regions also exist for landscape positive (+Y) and landscape +g +X +X +g negative (−Y), as shown in Figure 38. Ipnla 3cDed o irnie an Ctaatirotnes, itahne czo-aoxridsi insa atles osy isntcelmud, eads .s Ihf othwen a icnc eFleigroumree 3te7r iins +Y 10628-040 Figure 38. 2D Orientation with Corresponding Codes the Tap Sign section, the top of the device corresponds to the positive z-axis direction, the front of the device corresponds to The width of the dead zone region between two orientation the positive x-axis direction, and the right side of the device positions is determined by setting the value of the dead zone bits corresponds to the positive y-axis direction. (Bits[D6:D4]) in the ORIENT_CONF register (Address 0x3B). The dead zone region size can be specified as per the values The states shown in Table 26 correspond to which side of the shown in Table 24. The dead zone angle represents the total accelerometer is directed upwards, opposite the gravity vector. angle where the orientation is considered invalid. Therefore, a As shown in Figure 37, the accelerometer is oriented in the top dead zone of 15.4° corresponds to 7.7° in either direction away state. If the device is flipped over such that the top of the device from the bisector of two bordering regions. An example with a is facing down, toward gravity, the orientation is reported as the dead zone region of 15.4° is shown in Figure 39. It should be bottom state. If the device is adjusted such that the positive x-axis noted that the values shown in Table 24 correspond to the or positive y-axis direction is pointing upwards, away from the typical dead zone angle when the gravity vector is completely gravity vector, the accelerometer reports the orientation as front contained in only two axes (xy, xz, or yz) and should be used or left, respectively. only as a starting point. If the device is oriented such that the The algorithm to detect orientation change is performed after projection of gravity onto all three axes is nonzero, the effective filtering the output acceleration data to eliminate the effects of sensitivity is reduced, causing an increase in the dead zone angle. high frequency motion. This is performed by using a low-pass Therefore, evaluation needs to be performed for specific appli- filter with a bandwidth set by the divisor bits (ORIENT_CONF cation uses to determine the optimal setting for the dead zone. register, Address 0x3B). The orientation filter uses the same PORTRAIT output data available in the output data registers (Address 0x32 POSITIVE to Address 0x37); therefore, the orient register (Address 0x3C) 52.7° DEADZONE is updated at the same rate as the data rate that is set in the 45° +X BW_RATE register (Address 0x2C). Because the output data 37.3° is used, the bandwidth of the orientation filter depends on the LANDSCAPE POSITIVE vvaalluuees s ient Tinab tlhee 2 B4 Ware_ RreAfeTrEen rceegdi sttoe rt,h aen sdel ethctee dd iovuistopru tb daantdaw raidtet.h +Y +g 10628-041 Figure 39. Orientation Showing a 15.4° Dead Zone Region Rev. 0 | Page 31 of 40

ADXL344 Data Sheet By setting the INT_ORIENT bit (Bit D7) of the ORIENT_CONF When using the 3200 Hz or 1600 Hz output data rates in register (Address 0x3B), an interrupt can be generated when the full-resolution or ±2 g, 10-bit operation, the LSB of the output device is placed into a new valid orientation. Only one mode of data-word is always 0. When data is right justified, this corresponds orientation detection, 2D or 3D, can generate an interrupt at a to Bit D0 of the DATAx0 register, as shown in Figure 40. When time. The orientation detection mode is selected by setting or data is left justified and the part is operating in ±2 g, 10-bit mode, clearing the INT_3D bit (Bit D3) of the ORIENT_CONF register the LSB of the output data-word is Bit D6 of the DATAx0 register. (Address 0x3B). For more details, refer to the Register 0x3B— In full-resolution operation when data is left justified, the location ORIENT_CONF (Read/Write) section. of the LSB changes according to the selected output range. For a range of ±2 g, the LSB is Bit D6 of the DATAx0 register; for ±4 g, Writing to the BW_RATE register or placing the part into standby Bit D5 of the DATAx0 register; for ±8 g, Bit D4 of the DATAx0 mode resets the orientation feature, clearing the orientation filter register; and for ±16 g, Bit D3 of the DATAx0 register. This is and the orientation status. These actions cause an orientation shown in Figure 41. interrupt (if enabled), however, if the orientation during the next output sample is different from the default value (+X for The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit 2D orientation detection and undefined for 3D orientation). operation in the ±4 g, ±8 g, and ±16 g output ranges provides an DATA FORMATTING OF UPPER DATA RATES LSB that is valid and that changes according to the applied accel- eration. Therefore, in these modes of operation, Bit D0 is not Formatting of output data at the 3200 Hz and 1600 Hz output always 0 when output data is right justified, and Bit D6 is not data rates changes depending on the mode of operation (full- always 0 when output data is left justified. Operation at any data resolution or fixed 10-bit) and the selected output range. rate of 800 Hz or lower also provides a valid LSB in all ranges and modes that change according to the applied acceleration. DATAx1 REGISTER DATAx0 REGISTER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 OUTPUT DATA-WORD FOR OUTPUT DATA-WORD FOR THE ±2g, ±16g, FULL-RESOLUTION MODE. FULL-RESOLUTION AND ALL 10-BIT MODES. TABHNITED D ±±341 gO6 gFA NFTUDHL E±L 8D-gRA EFTSUAOLxL1L -URRTEEIGOSOINSL TMUEOTRDI OFENOS R,M B O±U4DgTE ATSHN HEDA M±V8SEgB ,T RHLEOES CSPAAETMCIOET NILV SECBLH YAL.NOGCEAST ITOON BAIST TDH2E A±N2Dg 10628-145 Figure 40. Data Formatting When Output Data Is Right Justified DATAx1 REGISTER DATAx0 REGISTER D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 LSB FOR ±2g, FULL-RESOLUTION AND ALL 10-BIT MODES. MSB FOR ALL MODES OF OPERATION WHEN LSB FOR ±4g, FULL-RESOLUTION MODE. LEFT JUSTIFIED. LSB FOR ±8g, FULL-RESOLUTION MODE. LSB FOR ±16g, FULL-RESOLUTION MODE. FADODADTRAI T3 2IIOS0 0NLHAEzLF ALTYN J,DU A S1N6TY0IF 0BIHEIzTD SO. UTOTP TUHTE D RAITGAH TR AOTFE TSH, ET HLES BL SABR EIN A TLHWEASYES M 0O WDEHSE NIS T AHLEW OAUYTSP 0U.T 10628-146 Figure 41. Data Formatting When Output Data Is Left Justified Rev. 0 | Page 32 of 40

Data Sheet ADXL344 NOISE PERFORMANCE 10k X-AXIS The specification of noise shown in Table 1 corresponds to the Y-AXIS Z-AXIS typical noise performance of the ADXL344 in normal power opera- g) tion with an output data rate of 100 Hz (LOW_POWER bit = 0, N (µ 1k rate = 0x0A in the BW_RATE register, Address 0x2C). For TIO A normal power operation at data rates below 100 Hz, the noise of VI E D the ADXL344 is equivalent to the noise at 100 Hz ODR in LSBs. N A For data rates greater than 100 Hz, the noise increases approxi- LL100 A mately by a factor of √2 per doubling of the data rate. For example, at 400 Hz ODR, the noise on the x- and y-axes is typically less than 2 LSB rms, and the noise on the z-axis is typically less than 3 LSB rms. 100.01 0.1 AV1ERAGING10 PERIOD1,00 (s) 1k 10k 10628-148 For low power operation (LOW_POWER bit = 1 in the BW_RATE Figure 43. Allan Deviation register, Address 0x2C), the noise of the ADXL344 is constant 150 for all valid data rates shown in Table 8. This value is typically %) X-AXIS less than 2.83 LSB rms for the x- and y-axes and typically less SE (140 Y-AXIS than 4.25 LSB rms for the z-axis. NOI Z-AXIS D The trend of noise performance for both normal power and low ZE130 LI A power modes of operation of the ADXL344 is shown in Figure 42. M OR120 Figure 43 shows the typical Allan deviation for the ADXL344. F N O The 1/f corner of the device, as shown in this figure, is very low, GE 110 A allowing absolute resolution of approximately 100 µg (assuming T N E that there is sufficient integration time). The figure also shows C100 R E that the noise density is 420 µg/√Hz for the x- and y-axes and P 5F3ig0u µreg /4√4H szh ofowrs tthhee zty-apxicisa.l noise performance trend of the 901.6 1.8 S2U.0PPLY VO2L.T2AGE, VS2 (.V4) 2.6 2.8 10628-149 ADXL344 over supply voltage. The performance is normalized Figure 44. Normalized Noise vs. Supply Voltage to the tested and specified supply voltage, VS = 2.6 V. The x-axis OPERATION AT VOLTAGES OTHER THAN 2.6 V offers the best noise performance over supply voltage, increasing by The ADXL344 is tested and specified at a supply voltage of typically less than 25% from nominal at a supply voltage of 1.8 V. V = 2.6 V; however, it can be powered with a V as high as 2.75 V The performance of the y- and z-axes is comparable, with both S S or as low as 1.7 V. Some performance parameters change as the axes increasing by typically less than 35% when operating with a supply voltage changes, including the offset, sensitivity, noise, supply voltage of 1.8 V. It should be noted, as shown in Figure 42, self-test, and supply current. that the noise on the z-axis is typically higher than that on the y-axis; therefore, although the noise on the z- and y-axes change Due to minuscule changes in the electrostatic forces as supply roughly the same in percentage over supply voltage, the magnitude voltage is varied, the offset and sensitivity change slightly. When of change on the z-axis is greater than the magnitude of change operating at a supply voltage of VS = 1.8 V, the offset of the x- and on the y-axis. y-axes is typically 25 mg higher than at VS = 2.6 V operation. The z-axis is typically 20 mg lower when operating at a supply voltage 7 X-AXIS, NORMAL POWER of 1.8 V than when operating at VS = 2.6 V. Sensitivity on the 6 Y-AXIS, NORMAL POWER x- and y-axes typically shifts from a nominal 256 LSB/g (full- Z-AXIS, NORMAL POWER SB rms)5 XYZ---AAAXXXIIISSS,,, LLLOOOWWW PPPOOOWWWEEERRR r2e5s0o LluStBio/gn w ohr e±n2 o gp, e1r0at-ibnigt owpitehr aat isounp)p layt vVoSl t=ag 2e. 6o fV 1 .o8 pVe. rTathieo nz- taox is E (L4 sensitivity is unaffected by a change in supply voltage and is the OIS same at VS = 1.8 V operation as it is at VS = 2.6 V operation. Simple T N3 linear interpolation can be used to determine typical shifts in U P T offset and sensitivity at other supply voltages. U2 O 1 0 3.13 6.2512.50 O25UTPU50T DA1T00A R2A0T0E (H40z0) 800 1600 3200 10628-147 Figure 42. Noise vs. Output Data Rate for Normal and Low Power Modes, Full Resolution (256 LSB/g) Rev. 0 | Page 33 of 40

ADXL344 Data Sheet Changes in noise performance, self-test response, and supply 140 current are discussed elsewhere throughout the data sheet. For 120 more information about noise performance, review the Noise B) Performance section. The Self-Test section discusses both the S L100 operation of self-test over voltage (a square relationship with the T ( U P supply voltage) and the conversion of the self-test response in T 80 U O 0.10Hz g’s to LSBs. Finally, Figure 21 shows the impact of supply voltage D 0.20Hz on typical current consumption at a 100 Hz output data rate, ALIZE 60 00..3798HHzz with all other output data rates following the same trend. M 1.56Hz OR 40 3.13Hz OFFSET PERFORMANCE AT LOWEST DATA RATES N 6.25Hz 20 The ADXL344 offers several output data rates and bandwidths ddeastaig rnaeteds ,f odre asc wriibdeed r aasn gtheo osfe a dpaptlaic raattieosn bs.e Hlowow 6e.2ve5r ,H azt ,t thhee l oowffseestt 0 25 35 4T5EMPERA55TURE (°6C5) 75 85 10628-056 performance over temperature can vary significantly from the Figure 45. Typical X-Axis Output vs. Temperature at Lower Data Rates, remaining data rates. Figure 45, Figure 46, and Figure 47 show Normalized to 100 Hz Output Data Rate, VS = 2.6 V the typical offset performance of the ADXL344 over temperature for data rates of 6.25 Hz and lower. All plots are normalized to 140 the offset at 100 Hz output data rate; therefore, a nonzero value corresponds to additional offset shift due to the temperature for 120 that data rate. B) S When using the lowest data rates, it is recommended that the T (L100 U operating temperature range of the device be limited to provide P T 80 U minimal offset shift across the operating temperature range. O 0.10Hz D 0.20Hz Due to variability between parts, it is also recommended that ZE 60 0.39Hz calibration over temperature be performed if any data rates ALI 0.78Hz M 1.56Hz below 6.25 Hz are in use. OR 40 3.13Hz N 6.25Hz 20 0 25 35 4T5EMPERA55TURE (°6C5) 75 85 10628-057 Figure 46. Typical Y-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.6 V 140 120 SB)100 L T ( U 80 P T U D O 60 00..1200HHzz E Z 0.39Hz ALI 40 0.78Hz M 1.56Hz OR 20 3.13Hz N 6.25Hz 0 –20 25 35 4T5EMPERA55TURE (°6C5) 75 85 10628-058 Figure 47. Typical Z-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.6 V Rev. 0 | Page 34 of 40

Data Sheet ADXL344 AXES OF ACCELERATION SENSITIVITY AZ AY AX 10628-042 Figure 48. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis) XOUT = +1g YOUT = 0g ZOUT = 0g TOP GRAVITY XOUT = 0g XOUT = 0g YOUT = –1g OP TO YOUT = +1g ZOUT = 0g T P ZOUT = 0g POT XYZOOOUUUTTT === 0–0gg1g XYZOOOUUUTTT === +001ggg XYZOOOUUUTTT === –001ggg 10628-043 Figure 49. Output Response vs. Orientation to Gravity Rev. 0 | Page 35 of 40

ADXL344 Data Sheet LAYOUT AND DESIGN RECOMMENDATIONS Figure 50 shows the recommended printed wiring board land pattern. Figure 51 and Table 27 provide details about the recommended soldering profile. 0.8000 0.3000 3.3500 0.5000 3.3500 10628-044 Figure 50. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters) CRITICAL ZONE TP tP TL TO TP RAMP-UP URETL TSMAX tL T A R PE TSMIN M E T PREtHSEAT RAMP-DOWN t25°C TO PEAK TIME 10628-045 Figure 51. Recommended Soldering Profile Table 27. Recommended Soldering Profile1, 2 Condition Profile Feature Sn63/Pb37 Pb-Free Average Ramp Rate from Liquid Temperature (T) to Peak Temperature (T) 3°C/sec max 3°C/sec max L P Preheat Minimum Temperature (T ) 100°C 150°C SMIN Maximum Temperature (T ) 150°C 200°C SMAX Time from T to T (t) 60 sec to 120 sec 60 sec to 180 sec SMIN SMAX S T to T Ramp-Up Rate 3°C/sec max 3°C/sec max SMAX L Liquid Temperature (T) 183°C 217°C L Time Maintained Above T (t) 60 sec to 150 sec 60 sec to 150 sec L L Peak Temperature (T) 240 + 0/−5°C 260 + 0/−5°C P Time of Actual T − 5°C (t) 10 sec to 30 sec 20 sec to 40 sec P P Ramp-Down Rate 6°C/sec max 6°C/sec max Time 25°C to Peak Temperature 6 minutes max 8 minutes max 1 Based on JEDEC Standard J-STD-020D.1. 2 For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. Rev. 0 | Page 36 of 40

Data Sheet ADXL344 OUTLINE DIMENSIONS 3.10 3.00SQ PIN1 2.90 0.10 0.350 CORNER 0.50 1314 16 1 BSC 0.250 0.50 9 8 6 5 TOPVIEW BOTTOMVIEW 0.275 1.00 0.95 ENDVIEW 0.85 0.79 0.74 SEPALTAINNGE 0.69 01-13-2010-B Figure 52. 16-Terminal Land Grid Array [LGA] (CC-16-3) Solder Terminations Finish Is Au over Ni Dimensions shown in millimeters ORDERING GUIDE Measurement Specified Temperature Package Branding Model1 Range (g) Voltage (V) Range Package Description Option Code ADXL344ACCZ-RL ±2, ±4, ±8, ±16 2.6 −40°C to +85°C 16-Terminal Land Grid Array [LGA] CC-16-3 Y4S ADXL344ACCZ-RL7 ±2, ±4, ±8, ±16 2.6 −40°C to +85°C 16-Terminal Land Grid Array [LGA] CC-16-3 Y4S EVAL-ADXL344Z Breakout Board EVAL-ADXL344Z-DB Datalogger and Development Board EVAL-ADXL344Z-M Analog Devices Inertial Sensor Evaluation System, Includes ADXL344 Satellite EVAL-ADXL344Z-S ADXL344 Satellite Only 1 Z = RoHS Compliant Part. Rev. 0 | Page 37 of 40

ADXL344 Data Sheet NOTES Rev. 0 | Page 38 of 40

Data Sheet ADXL344 NOTES Rev. 0 | Page 39 of 40

ADXL344 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). Analog Devices offers specific products designated for automotive applications; please consult your local Analog Devices sales representative for details. Standard products sold by Analog Devices are not designed, intended, or approved for use in life support, implantable medical devices, transportation, nuclear, safety, or other equipment where malfunction of the product can reasonably be expected to result in personal injury, death, severe property damage, or severe environmental harm. Buyer uses or sells standard products for use in the above critical applications at Buyer's own risk and Buyer agrees to defend, indemnify, and hold harmless Analog Devices from any and all damages, claims, suits, or expenses resulting from such unintended use. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10628-0-4/12(0) Rev. 0 | Page 40 of 40